Signal testing system and testing method

Abstract

The application discloses a signal test system and a test method, which are used for testing an HRPWM signal. The signal test system comprises a frequency division module and an operation module. The frequency division module is used for dividing a reference PWM signal based on the period of the HRPWM signal to generate a frequency division signal. The operation module is connected with the frequency division module and is used for calculating the period ratio of the frequency division signal and the HRPWM signal and generating an operation result. The signal test system and the test method can test the parameters of the HRPWM signal by using simple hardware instruments, and have the advantages of high test precision, short test time and easy automatic test under various test conditions.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of signal testing, and particularly relates to a signal testing system and a testing method. BACKGROUND

[0002] In an MCU or DSP chip, there is an HRPWM (high resolution PWM) circuit module, the control precision of which reaches 100-200 pS or even dozens of pS. An ultra-high-speed oscilloscope is required to test the circuit performance. This testing method is not only high in testing cost and long in testing time, but also inconvenient to obtain testing data.

[0003] The information disclosed in the background section of this document is only intended to increase the understanding of the general background of the application and should not be considered as admitting or implying that the information constitutes prior art in any form. SUMMARY

[0004] The present application aims to provide a signal testing system and a testing method, which can test HRPWM simply.

[0005] In order to achieve the above-mentioned purpose, the technical scheme provided by one embodiment of the present application is as follows:

[0006] A signal testing system for testing HRPWM signal, the signal testing system comprising:

[0007] a frequency division module for frequency dividing a reference PWM signal based on the period of the HRPWM signal to generate a frequency division signal;

[0008] an operation module connected with the frequency division module, for calculating the period ratio of the frequency division signal and the HRPWM signal and generating an operation result.

[0009] In one or more embodiments of the present application, the operation module comprises a first logic unit, a counting unit and a reset unit, the first logic unit is connected with the frequency division module to perform logical operation on the HRPWM signal and the frequency division signal to generate a first logic signal, the reset unit is connected with the frequency division module to generate a reset signal based on the frequency division signal, and the counting unit is connected with the first logic unit and the reset unit to count the first logic signal to generate a counting signal representing the operation result and reset based on the control of the reset signal.

[0010] In one or more embodiments of the present application, the first logic unit comprises an AND gate, the first input end of the AND gate is used to receive the HRPWM signal, the second input end of the AND gate is connected with the frequency division module to receive the frequency division signal, and the output end of the AND gate is used to generate the first logic signal.

[0011] In one or more embodiments of the present application, the reset unit comprises a first delay unit and a second logic unit, the first delay unit is connected with the frequency division module to delay the frequency division signal once to generate a first delay signal and to delay the frequency division signal twice to generate a second delay signal, and the second logic unit is connected with the first delay unit to perform a logic operation on the first delay signal and the second delay signal to generate the reset signal.

[0012] In one or more embodiments of the present application, the second logic unit comprises a NOT gate and an OR gate, the NOT gate is connected with the first delay unit to generate a second delay NOT signal by taking the NOT of the second delay signal, the first input end of the OR gate is connected with the first delay unit to receive the first delay signal, the second input end of the OR gate is connected with the NOT gate to receive the second delay NOT signal, and the output end of the OR gate is used to generate the reset signal.

[0013] In one or more embodiments of the present application, the operation module further comprises a latch unit, the latch unit is connected with the counting unit to latch the counting signal.

[0014] In one or more embodiments of the present application, the operation module further comprises a second delay unit, the second delay unit is connected with the frequency division module to delay the frequency division signal, and the first logic unit is connected with the second delay unit to perform a logic operation on the delayed frequency division signal and the HRPWM signal to generate the first logic signal, and the frequency division signal is further used to control the latch unit.

[0015] In one or more embodiments of the present application, the signal test system further comprises a duty cycle test module, the duty cycle test module is used to test the duty cycle of the HRPWM signal.

[0016] In one or more embodiments of the present application, the duty cycle test module comprises a filter unit and a voltage detection unit, the filter unit is used to filter the HRPWM signal to generate a voltage signal, and the voltage detection unit is connected with the filter unit to detect the voltage value of the voltage signal and generate a voltage value signal.

[0017] One specific embodiment of the present application further provides a signal test method based on the above-mentioned signal test system, the signal test method comprises:

[0018] The frequency division module is used to divide the reference PWM signal based on the period of the HRPWM signal to generate a frequency division signal;

[0019] The operation module is used to calculate the period ratio of the frequency division signal and the HRPWM signal and generate an operation result.

[0020] Compared with the prior art, the signal test system and the test method can test the parameters of the HRPWM signal by using simple hardware instruments, have the advantages of high test precision, short test time and easy automatic test under various test conditions. BRIEF DESCRIPTION OF DRAWINGS

[0021] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or the prior art description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments described in the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0022] Figure 1 The system structure diagram of the signal test system in an embodiment of the present application.

[0023] Figure 2 The flow chart of the signal test method in an embodiment of the present application.

[0024] Figure 3 The partial flow chart of the signal test method in an embodiment of the present application.

[0025] Figure 4 The waveform diagram of each signal in an embodiment of the present application. DETAILED DESCRIPTION

[0026] In order to make the person skilled in the art better understand the technical solutions in the present disclosure, the technical solutions in the embodiments of the present disclosure will be clearly and completely described in the embodiments of the present disclosure combined with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only some of the embodiments of the present disclosure, not all the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those skilled in the art without creative labor should belong to the protection scope of the present disclosure.

[0027] In the specification, "coupling" or "connection" or "connection" includes both direct connection and indirect connection. Indirect connection is the connection through an intermediate medium, such as the connection through an electrically conductive medium, which can have parasitic inductance or parasitic capacitance; indirect connection can also include the connection through other active devices or passive devices on the basis of achieving the same or similar functional purposes, such as the connection through circuits or components such as switches, follower circuits, etc. In addition, in the invention, words such as "first", "second" are mainly used to distinguish one technical feature from another technical feature, and do not necessarily require or imply a certain actual relationship, quantity or order between the technical features.

[0028] In the detailed description of this specification, reference is made to the accompanying drawings, which form a part thereof, wherein like reference numerals always denote like parts, and wherein exemplary embodiments are shown by way of example that may be implemented. It should be understood that other embodiments may be utilized, and structural or logical changes may be made, without departing from the scope of this application. Therefore, the following detailed description should not be considered limiting.

[0029] The various operations in the specification may be described sequentially as multiple discrete actions or operations in a manner most conducive to understanding the claimed subject matter. However, the order of description should not be construed as implying that these operations must be sequentially related. Specifically, these operations may not be performed in the order presented. The described operations may be performed in a different order than in the described embodiments. Various additional operations may be performed in additional embodiments and / or the described operations may be omitted.

[0030] For the purposes of this application, the phrase "A and / or B" means (A), (B), or (A and B). For the purposes of this application, the phrase "A, B and / or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C).

[0031] Various components and devices may be mentioned or shown in the singular form herein, but only for the convenience of discussion, and any element mentioned in the singular form may include multiple such elements as taught herein.

[0032] The description uses the phrases "in one embodiment," "in other embodiments," or "in some embodiments," each of which can refer to one or more of the same or different embodiments. Furthermore, the terms "comprising," "including," "having," etc., used in relation to embodiments of this application are synonymous.

[0033] like Figure 1 As shown, in one embodiment of the present invention, the signal testing system is used to test HRPWM signals. Specifically, the signal testing system includes a frequency division module 10, an arithmetic module 20, and a duty cycle testing module 30.

[0034] The frequency divider module 10 is used to divide the reference PWM signal based on the period of the HRPWM signal to generate a divided frequency signal VA. The arithmetic module 20 is connected to the frequency divider module 10 and is used to calculate the period ratio of the divided frequency signal VA to the HRPWM signal and generate the calculation result. The duty cycle test module 30 is used to test the duty cycle of the HRPWM signal.

[0035] In an embodiment, both the HRPWM signal and the reference PWM signal are generated by the HRPWM module, wherein the period of the reference PWM signal and the duration of the high and low levels are all integer multiples of the system clock period Tck of the HRPWM module.

[0036] The HRPWM module can generate two kinds of HRPWM signals, namely a period high-precision signal HR-period and a duty cycle high-precision signal HR-duty.

[0037] The high level duration of the period high-precision signal HR-period is an integer multiple of the system clock period of the HRPWM module, and the period thereof is processed with high precision as an integer multiple and a fractional multiple of the system clock period. Specifically, the signal period of the period high-precision signal HR-period can be written as (N1+K1 / P1)*Tck, and the high level duration thereof can be written as M1*Tck. Wherein, M1, N1, K1, P1 are all positive integers, M1 is less than N1, and K1 is less than P1.

[0038] The period of the duty cycle high-precision signal HR-duty is an integer multiple of the system clock period of the HRPWM module, and the high level duration (i.e. the duty cycle) thereof is processed with high precision as an integer multiple and a fractional multiple of the system clock period. Specifically, the signal period of the duty cycle high-precision signal HR-duty can be written as N2*Tck, and the high level duration thereof can be written as (M2+K2 / P2)*Tck. Wherein, M2, N2, K2, P2 are all positive integers, M2 is less than N2, and K2 is less than P2.

[0039] The period of the reference PWM signal can be written as N3*Tck, and the high level duration of the reference PWM signal can be written as M3*Tck. Wherein, M3, N3 are all positive integers, and M3 is less than N3. That is, the reference PWM signal is a normal PWM signal generated based on the same system clock period as the HRPWM signal.

[0040] Preferably, the HRPWM module is configured such that N1=N2=N3. At this time, both the period high-precision signal HR-period and the duty cycle high-precision signal HR-duty have the same integer period as the reference PWM signal.

[0041] Further, the HRPWM module further comprises a multiplexer for selectively outputting the period high-precision signal HR-period and the duty cycle high-precision signal HR-duty. The signal test system can further comprise a control module 40 for controlling the multiplexer in the HRPWM module to output the period high-precision signal HR-period or the duty cycle high-precision signal HR-duty.

[0042] In other embodiments, the HRPWM signal and the reference PWM signal can also be generated by different signal modules, as long as the HRPWM signal and the reference PWM signal have the same system clock period, or the system clock period of the reference PWM signal and the system clock period of the HRPWM signal are integer multiples of each other.

[0043] In other embodiments, the HRPWM module may not generate a high-precision duty cycle signal HR-duty. The frequency division module 10 and the arithmetic module 20 in this signal testing system are mainly used to test the high-precision periodic signal HR-period, while the duty cycle testing module 30 can test both the high-precision periodic signal HR-period and the high-precision duty cycle signal HR-duty.

[0044] like Figure 1 As shown, the duty cycle test module 30 includes a filtering unit 31 and a voltage detection unit 32. The filtering unit 31 is connected to the multiplexer in the HRPWM module and is used to filter the HRPWM signal to generate a voltage signal. The voltage detection unit 32 is connected to the filtering unit 31 to detect the voltage value of the voltage signal and generate a voltage value signal.

[0045] In one embodiment, the filtering unit 31 includes a resistor R and a capacitor C. The first end of the resistor R is connected to the multiplexer in the HRPWM module to receive the HRPWM signal. The second end of the resistor R and the first end of the capacitor C are connected to the voltage detection unit 32 to generate a voltage signal. The second end of the capacitor C is connected to ground. The resistor R and the capacitor C form a low-pass filter, which can filter the HRPWM signal to generate a DC voltage signal.

[0046] Since the voltage value of the voltage signal output by the filter unit 31 will change with the duty cycle of the HRPWM signal, the corresponding duty cycle value can be calculated as long as the voltage value of the voltage signal is measured.

[0047] like Figure 1 As shown, in one embodiment, the frequency division module 10 includes a first frequency divider and a second frequency divider.

[0048] The first frequency divider is connected to the HRPWM module, and it divides the reference PWM signal by a ratio of 1 / (P1*N1+K1). The second frequency divider is connected to the first frequency divider, and it further divides the signal after the first frequency divider by a ratio of M3 / N3 (i.e., the duty cycle of the reference PWM signal) to generate the divided signal VA.

[0049] After passing through the first and second frequency dividers, the period of the divided signal VA is extended to (P1*N1+K1)*(N3). 2The high-level time of / M3)* Tck is (P1*N1+K1)*N3* Tck, and the low-level time is (P1*N1+K1)*(N3 / (N3-M3))* Tck.

[0050] In one specific embodiment, M3 / N3=1 / 2, that is, the duty cycle of the reference PWM signal is 1 / 2. Then, the second frequency divider further divides the signal after the first frequency divider with a division ratio of 1 / 2. The period of the divided signal VA is extended to (P1*N1+K1)*2*N3*Tck, and its high level time is (P1*N1+K1)*N3*Tck.

[0051] In other embodiments, the frequency division module 10 may also include one or more frequency dividers, as long as they can achieve the corresponding frequency division function.

[0052] like Figure 1 As shown, in one embodiment, the arithmetic module 20 includes a first logic unit, a counting unit, a reset unit, a latching unit, and a second delay unit 21.

[0053] The second delay unit 21 is connected to the frequency divider module 10 to delay the frequency divider signal VA to generate a delayed frequency divider signal VB. The first logic unit is connected to the second delay unit 21 and the multiplexer to perform logical operations on the delayed frequency divider signal VB and the high-precision periodic signal HR-period to generate a first logic signal VE. The reset unit is connected to the second delay unit 21 to generate a reset signal VF based on the delayed frequency divider signal VB. The counting unit is connected to the first logic unit and the reset unit to count the first logic signal VE to generate a counting signal VG representing the operation result, outputs the counting signal VG through its own signal output terminal QN, and resets the signal based on the control of the reset signal VF. The signal input terminal Din of the latch unit is connected to the signal output terminal QN of the counting unit to latch the counting signal VG.

[0054] The control terminal CK of the latch unit is also connected to the second frequency divider to receive the frequency division signal VA. The frequency division signal VA is also used to control the latch unit to perform latching. In one embodiment, when the frequency division signal VA is high, the latch unit outputs a latch signal VH through its own signal output terminal QD, which follows the change of the counting signal VG. When the frequency division signal VA is low, the latch signal VH is maintained. In other embodiments, the latch unit may also be controlled by the frequency division signal VA based on other control logic.

[0055] For example, the second delay unit 21 can delay the frequency division signal VA by M1*Tck to generate the delayed frequency division signal VB.

[0056] In one embodiment, the first logic unit may include an AND gate, the first input of which is connected to a multiplexer to receive a periodic high-precision signal HR-period, the second input of which is connected to a second delay unit 21 to receive a delayed frequency-divided signal VB, and the output of which is connected to the signal terminal CK of a counting unit to generate a first logic signal VE.

[0057] In one embodiment, the reset unit includes a first delay unit 22 and a second logic unit. The first delay unit 22 is connected to the second delay unit 21 to perform a first delay on the delayed frequency-divided signal VB to generate a first delayed signal VC, and a second delay on the delayed frequency-divided signal VD to generate a second delayed signal VD. The second logic unit is connected to the first delay unit 22 to perform logical operations on the first delayed signal VC and the second delayed signal VD to generate a reset signal VF.

[0058] The first delay unit 22 includes a first delayer and a second delayer. The first delayer is connected to the second delay unit 21 to delay the delayed frequency division signal VB to generate a first delayed signal VC. The second delayer is connected to the first delayer to delay the first delayed signal VC to generate a second delayed signal VD.

[0059] For example, the first delay unit can delay the delayed frequency-divided signal VB by 4 * Tck, and the second delay unit can delay the first delayed signal VC by 1 * Tck.

[0060] The second logic unit may include an NOT gate and an OR gate. The NOT gate is connected to the second delay unit to invert the second delayed signal VD to generate a second delayed NOT signal. The first input of the OR gate is connected to the first delay unit to receive the first delayed signal VC. The second input of the OR gate is connected to the NOT gate to receive the second delayed NOT signal. The output of the OR gate is connected to the reset terminal Reset of the counting unit to generate a reset signal VF.

[0061] like Figure 2 As shown, this embodiment also provides a signal testing method. Based on the above-described signal testing system, the signal testing method includes:

[0062] The frequency divider module 10 divides the reference PWM signal based on the period of the high-precision periodic signal HR-period to generate the frequency divider signal VA.

[0063] The calculation module 20 calculates the period ratio of the frequency-divided signal VA to the period-high precision signal HR-period and generates the calculation result.

[0064] For example, the frequency division ratio of the reference PWM signal by the frequency division module 10 is M3 / ((P1*N1+K1)*N3), and the period of the frequency division signal VA is (P1*N1+K1)*(N3).2 / M3)* Tck, its high level time is (P1*N1+K1)* N3* Tck, and its low level time is (P1*N1+K1)* (N3 / (N3-M3))* Tck.

[0065] In one specific embodiment, M3 / N3=1 / 2, and the frequency division ratio of the frequency divider module 10 to the reference PWM signal is 1 / ((P1*N1+K1)*2).

[0066] like Figure 3 As shown, the calculation module 20 calculates the period ratio of the frequency-divided signal to the high-precision periodic signal HR-period and generates the calculation result. In this embodiment, the specific steps may include:

[0067] The frequency division signal VA is delayed by the second delay unit 21.

[0068] The first logic signal VE is generated by performing logical operations on the delayed frequency-divided signal VB and the periodic high-precision signal HR-period through the first logic unit.

[0069] The reset unit generates a reset signal VF based on the delayed frequency-divided signal VB.

[0070] The counting unit counts the first logic signal VE to generate a counting signal VG representing the operation result, and resets it based on the control of the reset signal VF.

[0071] The counting signal VG is latched by the latch unit, and the latch unit is controlled by the frequency division signal VA.

[0072] Combination Figure 4 As shown, in one embodiment, the second delay unit 21 delays the frequency division signal VA by M1*Tck to obtain the delayed frequency division signal VB.

[0073] Next, the first logic signal VE is generated by performing an AND operation between the delayed frequency-divided signal VB and the periodic high-precision signal HR-period through an AND gate in the first logic unit. It can be seen that within the positive half-cycle of the delayed frequency-divided signal VB, the periodic high-precision signal HR-period experiences a total of P1*N3 cycles, and the first logic signal VE will generate P1*N3 or P1*N3+1 high-level signals. Specifically, if the rising edge of the delayed frequency-divided signal VB falls on the low level of the periodic high-precision signal HR-period, the first logic signal VE will generate P1*N3 high-level signals; if the rising edge of the delayed frequency-divided signal VB falls on the high level of the periodic high-precision signal HR-period, the first logic signal VE will generate P1*N3+1 high-level signals.

[0074] Then, the reset unit generates a reset signal VF based on the delayed frequency division signal VB. In this embodiment, the reset signal VF can be generated by the following steps:

[0075] The first delay unit 22 delays the delayed frequency division signal VB to generate a first delay signal VC and a second delay signal VD.

[0076] The second logic unit performs a logic operation on the first delay signal VC and the second delay signal VD to generate the reset signal VF.

[0077] In combination Figure 4 In one embodiment, the first delay unit 22 delays the delayed frequency division signal VB by 4*Tck to generate the first delay signal VC, and then delays the first delay signal VC by Tck to generate the second delay signal VD.

[0078] Then, the second logic unit generates a second delay non-signal by performing a NOT operation on the second delay signal VD, and generates the reset signal VF by performing an OR operation on the first delay signal VC and the second delay non-signal.

[0079] It can be seen that, by selecting appropriate delay times for the first delay unit and the second delay unit, the reset signal VF is located in the negative half cycle of the delayed frequency division signal VB, which means that the reset signal VF resets the counting unit when the frequency division signal VB is low, and ensures that the counting unit outputs the number of cycles of the high-precision period signal HR-period experienced in each positive half cycle of the frequency division signal VB.

[0080] Finally, the latch unit latches the counting signal VG, and the frequency division signal VA controls the latch unit.

[0081] In one embodiment, the latch unit latches the counting signal VG when the frequency division signal VA is high, and the output latch signal VH follows the change of the counting signal VG. When the frequency division signal VA is low, the latch signal VH remains unchanged.

[0082] In combination Figure 4As shown, the delayed frequency division signal VB is delayed relative to the frequency division signal VA by M1*Tck, i.e. by one high level time of the period high precision signal HR-period. This makes the output of the latch unit not follow the operation result change in the last M1*Tck time period of the positive half cycle of the delayed frequency division signal VB. This ensures that even if the rising edge of the delayed frequency division signal VB falls on the high level of the period high precision signal HR-period, the latch unit will not latch the last count of the operation result, and the maximum value of the latch signal VH is P1*N3. This value represents that the period ratio of the frequency division signal VA to the period high precision signal HR-period is P1*N3:1.

[0083] Based on the above derivation, when the frequency of the period high precision signal HR-period is correct, the latch signal VH should output P1*N3, i.e. P1*N1. When K1=(1, 2, 3...P1-1) is known, the period (N1+K1 / P1)*Tck of the period high precision signal HR-period can be accurately calculated.

[0084] It can be understood that the frequency division module 10 can also use other frequency division ratios to frequency divide the reference PWM signal. For example, a multiple 1 / X, X being a positive integer, can be further superimposed on the basis of M3 / (P1*N1+K1)*N3, to extend the period of the frequency division signal VA to (P1*N1+K1)*(N3 2 / M3)*X*Tck, and extend the high level time to (P1*N1+K1)*N3*X*Tck. The number of periods of the period high precision signal HR-period in the positive half cycle of the frequency division signal VA is increased, and the value of the latch signal VH is also increased, which is beneficial to improve the test precision.

[0085] Of course, based on the above principle, the period ratio of the frequency division signal VA to the period high precision signal HR-period can also be calculated by counting the number of periods of the period high precision signal HR-period in the negative half cycle of the frequency division signal VA, and the working principle and control logic of each device are adjusted accordingly.

[0086] In other embodiments, the first logic unit can also include an NOR gate or other logic operation gate, and the counting logic of the counting unit and the logic of the reset unit generating the reset signal VF are adjusted accordingly.

[0087] In other embodiments, the reset unit can also be directly connected to the frequency division module 10 and generate the reset signal VF directly based on the frequency division signal VA. The first delay unit 22 can also be set to other delay times, and the second logic unit can also use other operation logics as long as the required reset signal VF can be generated in the negative half cycle of the frequency division signal.

[0088] In other embodiments, the second delay unit 21 can not be provided in the signal test system, and the first logic unit is connected to the frequency division module 10 to perform logic operation on the period high-precision signal HR-period and the frequency division signal VA to generate the first logic signal VE. The reset unit is connected to the frequency division module 10 to generate the reset signal VF based on the frequency division signal. At this time, the latch signal VH output by the latch follows the count signal VG, and both of them can have the case of P*N+1, which can be avoided by controlling the delay between the frequency division signal VA and the period high-precision signal HR-period.

[0089] In other embodiments, the latch unit can not be provided in the signal test system, and the period of the period high-precision signal HR-period is directly calculated by the count signal VG. At this time, the error case can also be avoided by controlling the delay between the frequency division signal and the period high-precision signal HR-period.

[0090] In other embodiments, the duty cycle test module 30 can not be provided in the signal test system.

[0091] Preferably, the signal test method can further include testing the duty cycle of the HRPWM signal by the duty cycle test module 30. In this embodiment, it can specifically include the following steps:

[0092] The HRPWM signal is filtered by the filter unit 31 to generate a voltage signal.

[0093] The voltage value of the voltage signal is detected by the voltage detection unit 32, and a voltage value signal is generated.

[0094] For the duty cycle high-precision signal HR-duty, the period is N2*Tck, the time of the high level is (M2+K2 / P2)*Tck, and the voltage value of the voltage signal is VDDP*(M2+K2 / P2) / N2, where VDDP is the high-level voltage value of the duty cycle high-precision signal HR-duty.

[0095] For the period high-precision signal HR-period, the voltage value of the voltage signal is VDDP*M1 / (N1+K1 / P1), where VDDP is the high-level voltage value of the period high-precision signal HR-period.

[0096] By appropriately adjusting the values of M1 and N1, M2 and N2, and selecting a voltage detection unit 32 with appropriate precision, when K2=(1, 2, 3...P2-1) is taken, it is easy to make the step length of the voltage signal much larger than the precision of the voltage detection unit 32, and the duty cycle of the HRPWM signal can be accurately obtained according to the test voltage value of the voltage detection unit 32.

[0097] Preferably, the signal testing method can further comprise: controlling the multiplexer in the HRPWM module to output the period high-precision signal HR-period or the duty cycle high-precision signal HR-duty by the control module 40.

[0098] Those skilled in the art will appreciate that embodiments of the application can be supplied as a method, a system, or a computer program product. Accordingly, the application can be embodied in the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the application can be embodied in the form of a computer program product on one or more computer-usable storage media (including, but not limited to, disk memory, CD-ROMs, optical storage media, etc.) having computer usable program code embodied therein.

[0099] The present application is described in reference to the flowchart and / or block diagrams of the method, apparatus (system) and computer program product according to the embodiments of the present application. It should be understood that each flow and / or block in the flowchart and / or block diagram, and the combination of flows and / or blocks in the flowchart and / or block diagram can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing apparatus to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing apparatus produce the functions specified in the flowchart and / or block diagram block or blocks of the flowchart and / or block diagram. Figure 1 one or more flows and / or blocks Figure 1 means for performing the function specified by the flow or flows and / or block or blocks.

[0100] These computer program instructions can also be stored in a computer readable memory that can direct a computer or other programmable data processing apparatus to work in a specific manner, so that the instructions stored in the computer readable memory produce an article of manufacture including instruction means, which implement the function specified in the flowchart and / or block diagram block or blocks of the flowchart and / or block diagram. Figure 1 one or more flows and / or blocks Figure 1 means for performing the function specified by the flow or flows and / or block or blocks.

[0101] These computer program instructions can also be loaded onto a computer or other programmable data processing apparatus, so that a series of operational steps are performed on the computer or other programmable data processing apparatus to produce a computer implemented process, so that the instructions executed on the computer or other programmable data processing apparatus provide the functions specified in the flowchart and / or block diagram block or blocks of the flowchart and / or block diagram. Figure 1 one or more flows and / or blocks Figure 1 means for performing the function specified by the flow or flows and / or block or blocks.

[0102] It will be apparent to those skilled in the art that the disclosure is not limited to the details of the above-exemplified embodiments and that the disclosure can be implemented in other particular forms without departing from the spirit or essential characteristics of the disclosure. The presently disclosed embodiments are, therefore, to be considered in all respects as illustrative and not restrictive, the scope of the disclosure being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. No feature of the claims is to be construed as limiting the claims to the exact nature of the features described therein.

[0103] Furthermore, it should be understood that although the description is made on the basis of the embodiments, not every embodiment contains only one independent technical solution, and the description of the specification is only for the sake of clarity, and those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that those skilled in the art can understand.

Claims

1. A signal test system for testing an HRPWM signal, characterized by, The signal test system comprises: A frequency division module is configured to divide a reference PWM signal based on a period of the HRPWM signal to generate a frequency division signal, wherein the period of the HRPWM signal is (N1+K1 / P1)*Tck, the period of the reference PWM signal is N3*Tck, the time of the high level of the reference PWM signal is M3*Tck, and the frequency division ratio of the frequency division module is 1 / (P1*N1+K1)*M3 / N3; wherein Tck is a system clock period, N1, K1, P1, M3 and N3 are all positive integers, K1 is less than P1, and M3 is less than N3; An operation module is connected to the frequency division module and configured to calculate the period ratio of the frequency division signal and the HRPWM signal and generate an operation result; wherein the operation module comprises a first logic unit, a counting unit and a reset unit, the first logic unit is connected to the frequency division module to perform logical operation on the HRPWM signal and the frequency division signal to generate a first logic signal, the reset unit is connected to the frequency division module to generate a reset signal based on the frequency division signal, and the counting unit is connected to the first logic unit and the reset unit to count the first logic signal to generate a counting signal representing the operation result and reset based on the control of the reset signal.

2. The signal testing system of claim 1, wherein, The first logic unit comprises an AND gate, a first input end of the AND gate is configured to receive the HRPWM signal, a second input end of the AND gate is connected to the frequency division module to receive the frequency division signal, and an output end of the AND gate is configured to generate the first logic signal.

3. The signal testing system of claim 1, wherein, The reset unit comprises a first delay unit and a second logic unit, the first delay unit is connected to the frequency division module to delay the frequency division signal once to generate a first delay signal and delay the frequency division signal twice to generate a second delay signal, and the second logic unit is connected to the first delay unit to perform logical operation on the first delay signal and the second delay signal to generate the reset signal.

4. The signal testing system of claim 3, wherein, The second logic unit comprises a NOT gate and an OR gate, the NOT gate is connected to the first delay unit to take the NOT of the second delay signal to generate a second delay NOT signal, a first input end of the OR gate is connected to the first delay unit to receive the first delay signal, a second input end of the OR gate is connected to the NOT gate to receive the second delay NOT signal, and an output end of the OR gate is configured to generate the reset signal.

5. The signal testing system of claim 1, wherein, The operation module further comprises a latch unit connected to the counting unit to latch the counting signal.

6. The signal testing system of claim 5, wherein, The operation module further comprises a second delay unit connected to the frequency division module to delay the frequency division signal, the first logic unit is connected to the second delay unit to perform logical operation on the delayed frequency division signal and the HRPWM signal to generate the first logic signal, and the frequency division signal is further configured to control the latch unit.

7. The signal testing system of claim 1, wherein, The signal test system further comprises a duty cycle test module configured to test the duty cycle of the HRPWM signal.

8. The signal testing system of claim 7, wherein, The duty cycle test module comprises a filter unit and a voltage detection unit, the filter unit is configured to filter the HRPWM signal to generate a voltage signal, and the voltage detection unit is connected to the filter unit to detect the voltage value of the voltage signal and generate a voltage value signal.

9. A signal testing method based on the signal testing system according to any one of claims 1 to 8, characterized by, The signal test method comprises: The frequency division module generates a frequency division signal by frequency dividing the reference PWM signal based on the period of the HRPWM signal; The operation module calculates the period ratio of the frequency division signal and the HRPWM signal, and generates an operation result.

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