A modeling method and system based on improved dispersion type Angelov

Abstract

The application discloses a modeling method and system based on improved dispersion type Angelov, relates to the technical field of semiconductor device modeling, and constructs an improved dispersion type Angelov model current equation, including a drain current equation and a dispersion current equation; a transistor without dispersion and a transistor with dispersion parameter are extracted by using a pulse voltage current test method and a pulse test method with a pre-pulse respectively; the transistor without dispersion and the transistor with dispersion parameter are substituted into the drain current equation and the dispersion current equation respectively, the total drain source current of the transistor is calculated, and the simulation and the actual measurement difference of S parameters of the transistor under multi-bias are described by adding topological circuit parameters; optimization iteration is carried out on fitting parameters in the current equation, an optimal current equation is obtained, and finally, the improved dispersion type Angelov model of the transistor is obtained. The dispersion current equation is added, so that the S parameters of the transistor under different biases can be better simulated, and the modeling precision is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor device modeling, and particularly relates to a modeling method and system based on improved dispersion type Angelov. BACKGROUND

[0002] In the process of three-five group compound semiconductor, the model accuracy of the device can help the designer to design the required circuit. The device model can accurately represent the electrical characteristics of the device, and plays a guiding role in circuit design. Among them, the experience-based Angelov equivalent circuit model uses hyperbolic tangent function to reflect the relationship between the current and voltage of the transistor, which ensures the continuity and high-order derivability of the model, and it can also correctly represent the nonlinear effect of the device. With its good convergence and good prediction characteristics of transconductance and high-order transconductance, the Angelov model is widely used in the industry.

[0003] However, it is found in practical application that although the Angelov method can better fit the transistor IV curve (Ids-Vds curve under different Vgs), the die radio frequency test and radio frequency simulation using the method have large differences. The physical explanation of this dispersion phenomenon is usually attributed to the trapping of channel carriers at the channel-substrate interface and the channel-surface interface, i.e. the trap effect. The Angelov algorithm currently only describes the dispersion phenomenon by setting a dispersion capacitor and a dispersion resistor, and the simulated dispersion current has limited accuracy. SUMMARY

[0004] The purpose of the present application is to provide a modeling method and system based on improved dispersion type Angelov, which can better simulate the S parameters of the transistor under different bias by improving the Angelov equation and adding the dispersion current equation, compared with the traditional Angelov algorithm, and improve the modeling accuracy.

[0005] To achieve the above purpose, the present application provides the following scheme:

[0006] On the one hand, the present application provides a modeling method based on improved dispersion type Angelov, which specifically includes the following steps:

[0007] S1, constructing an Angelov model topological structure of the transistor according to the transistor test structure;

[0008] S2, constructing a current equation of the improved dispersion type Angelov model based on the Angelov model topological structure, the current equation including a drain current equation and a dispersion current equation;

[0009] S3, extract the transistor DC parameters without dispersion and with dispersion parameters of the transistor by using the pulse voltage current test method and the pulse test method with pre-pulse respectively;

[0010] S4, substitute the transistor DC parameters without dispersion and with dispersion into the drain current equation and the dispersion current equation respectively, calculate the basic drain-source current and the fitted dispersion current, and take the sum of the basic drain-source current and the fitted dispersion current as the total drain-source current of the transistor;

[0011] S5, obtain the topological circuit parameters from the Angelov model topology of the transistor, and describe the S parameters of the transistor under multi-bias based on the total drain-source current of the transistor and the topological circuit parameters;

[0012] S6, optimize and iterate the fitting parameters in the current equation of the improved dispersion type Angelov model by the difference between the simulation and the actual measurement of the S parameters under multi-bias, obtain the optimal current equation, and finally obtain the improved dispersion type Angelov model of the transistor.

[0013] In some specific embodiments, the transistor coefficients and topological circuit parameters are extracted from the transistor test structure by using the forward bias method to construct the Angelov model topology of the transistor, and the extracted topological circuit parameters include the parasitic resistance, parasitic inductance and intrinsic capacitance of the transistor.

[0014] In some specific embodiments, the transistor DC parameters without dispersion include: the voltage saturation coefficient of the second harmonic current, the transconductance control coefficient of the second harmonic, the transconductance control coefficient of the third harmonic, the voltage saturation coefficient of the third harmonic current, the gate-source voltage and the drain-source voltage when the transistor has the maximum transconductance, the parameters of the voltage saturation coefficient, and the drain-source current corresponding to the maximum transconductance.

[0015] In some specific embodiments, in step S4, the transistor DC parameters without dispersion are substituted into the drain current equation to calculate the basic drain-source current.

[0016] S01, calculate the polynomial coefficients of the control function based on the voltage saturation coefficient of the second harmonic current, the transconductance control coefficient of the second harmonic, the transconductance control coefficient of the third harmonic, the voltage saturation coefficient of the third harmonic current, and the drain-source voltage;

[0017] S02, calculate the fitted gate voltage based on the gate-source voltage when the transistor has the maximum transconductance, the parameters describing the voltage saturation coefficient, and the degree of control of the maximum transconductance of the transistor by the drain-source voltage;

[0018] S03, substitute the calculated polynomial coefficients and the fitted gate voltage into the control function to obtain the control value;

[0019] S04, calculating the final voltage saturation coefficient based on the control value;

[0020] S05, substituting the control value, the final voltage saturation coefficient, the drain-source voltage and the drain-source current corresponding to the maximum transconductance into the drain current equation to obtain the basic drain-source current.

[0021] In some embodiments, the expression of the drain current equation is:

[0022]

[0023] wherein, is the drain-source current corresponding to the maximum transconductance, represents the basic drain-source current, P 20 , P 21 , P 2o represents the transconductance control coefficient of the second harmonic, is the voltage saturation coefficient of the second harmonic current, P 30 , P 31 , P 3o is the transconductance control coefficient of the third harmonic, is the voltage saturation coefficient of the third harmonic current; P 1, P 1m , , is the polynomial coefficient of the control function ; V ds represents the drain-source voltage, V gs represents the gate-source voltage, B1, B2 represents P the coefficient varying with V ds , is the gate-source voltage when the transistor has the maximum transconductance, represents the degree describing that the maximum transconductance of the transistor is controlled by the gate-source voltage, represents the calculation of the intermediate value; α s , α r is a parameter describing the voltage saturation coefficient α, λ is a channel length modulation coefficient, which is used to simulate the channel modulation effect.

[0024] In some embodiments, the expression of the dispersion current equation is:

[0025]

[0026] wherein, is the drain-source current corresponding to the maximum transconductance, represents the fitted dispersion current, , , , represents the polynomial coefficients of the control function , , , represents the transconductance control coefficient of the second harmonic with dispersion extracted from the pre-pulse current, represents the voltage saturation coefficient of the second harmonic current with dispersion extracted from the pre-pulse current; , , represents the transconductance control coefficient of the third harmonic with dispersion extracted from the pre-pulse current; represents the voltage saturation coefficient of the third harmonic current with dispersion extracted from the pre-pulse current; V ds represents the drain-source voltage, V gs represents the gate-source voltage, B1, B2 represents a coefficient that varies with V ds , is the gate-source voltage at the maximum transconductance of the transistor, represents a parameter that describes the degree to which the maximum transconductance of the transistor is controlled by the gate-source voltage, represents the calculation of an intermediate value; α s , α r is a parameter that describes the voltage saturation coefficient a, and λ is a channel length modulation coefficient that is used to simulate the channel modulation effect.

[0027] In some specific embodiments, the fitted drain-source current of the transistor is the sum of the base drain-source current and the fitted dispersion current , which is zero when the frequency freq = 0. ;

[0028] The drain-source current is then ;

[0029] When the frequency freq ≠ 0, the drain-source current is: .

[0030] In some specific embodiments, when the fitting parameters in the current equation of the improved dispersion type Angelov model are optimized, it is verified whether the fitting parameters meet the modeling accuracy, if not, the transistor DC parameters with dispersion parameters are extracted again by the pre-pulse pulse test method and steps S3-S6 are repeated until the modeling accuracy is met, wherein the fitting parameters are the transistor DC parameters with dispersion parameters extracted by the pre-pulse pulse test method.

[0031] In some specific embodiments, the extraction term of the transistor gate-drain capacitance and the gate-source capacitance extracted by the method of the Cold-FET is also included, and when the fitting parameters in the current equation of the improved dispersion type Angelov model are optimized, it is also necessary to verify whether the extraction term of the transistor gate-drain capacitance and the gate-source capacitance meets the modeling accuracy.

[0032] When the fitting parameters and the extraction term of the transistor gate-drain capacitance and the gate-source capacitance meet the modeling accuracy at the same time, the improved dispersion type Angelov model of the transistor is obtained.

[0033] In a second aspect, the present application provides a modeling system based on an improved dispersion type Angelov, comprising:

[0034] A topology construction module is configured to construct an Angelov model topology structure of the transistor according to a transistor test structure.

[0035] An Angelov model construction module is configured to construct a current equation of the improved dispersion type Angelov model based on the Angelov model topology structure, wherein the current equation includes a drain current equation and a dispersion current equation.

[0036] A parameter extraction module is configured to extract transistor DC parameters without dispersion and with dispersion parameters by using a pulse voltage current test method and a pre-pulse pulse test method, respectively.

[0037] A fitting module is configured to substitute the transistor DC parameters without dispersion and with dispersion parameters into the drain current equation and the dispersion current equation, respectively, to calculate a basic drain-source current and a fitted dispersion current, and to take the sum of the basic drain-source current and the fitted dispersion current as a total drain-source current of the transistor, to obtain topological circuit parameters from the Angelov model topology structure of the transistor, and to describe S parameters of the transistor under multiple biases based on the total drain-source current of the transistor and the topological circuit parameters.

[0038] An Angelov model optimization module is configured to optimize and iterate the fitting parameters in the current equation of the improved dispersion type Angelov model through the difference between simulation and measurement of the S parameters under multiple biases, to obtain an optimal current equation, and finally to obtain the improved dispersion type Angelov model of the transistor.

[0039] The present application has the beneficial effects that:

[0040] The present application improves the control function of the current equation, increases the description parameters of the control function, so that it can better fit the transconductance of the transistor, increase the accuracy of the transconductance, and improve the convergence of the entire current equation.

[0041] In addition, the dispersion current equation is added in the current equation, the dispersion current is calculated based on the extraction of the transistor without dispersion DC parameters by the pulse test method with pre-pulse, and the robustness of fitting the drain-source current is increased based on the improved control function, so that it is easier to converge, and the description accuracy of the S parameter is also improved. BRIEF DESCRIPTION OF DRAWINGS

[0042] Figure 1 The modeling method flow chart based on the improved dispersion type Angelov provided for the embodiment of the present application is provided;

[0043] Figure 2 The equivalent circuit diagram of the Angelov model topology structure of the transistor provided for the embodiment of the present application is provided.

[0044] Figure 3 The comparison schematic diagram of the drain-source current simulation results under different drain-source voltages and by using the method of the present application is provided;

[0045] Figure 4 The comparison schematic diagram of the transconductance simulation results under different gate-source voltages and by using the method of the present application is provided; Figure 3 The root mean square error change schematic diagram of the measured transconductance and the simulated transconductance with the change of the drain-source voltage is provided;

[0046] Figure 5 The comparison schematic diagram of the transconductance simulation results under different gate-source voltages and by using the method of the present application is provided;

[0047] Figure 6 The root mean square error change schematic diagram of the measured transconductance and the simulated transconductance with the change of the drain-source voltage is provided; Figure 5 The root mean square error change schematic diagram of the measured transconductance and the simulated transconductance with the change of the drain-source voltage is provided;

[0048] Figure 7 The root mean square error change schematic diagram of the measured transconductance and the simulated transconductance with the change of the drain-source voltage is provided;

[0049] Figure 8 The root mean square error change schematic diagram of the measured transconductance and the simulated transconductance with the change of the drain-source voltage is provided;

[0050] Figure 9 The root mean square error change schematic diagram of the measured transconductance and the simulated transconductance with the change of the drain-source voltage is provided;

[0051] Figure 10 The root mean square error change schematic diagram of the measured transconductance and the simulated transconductance with the change of the drain-source voltage is provided;

[0052] Figure 11 A comparison diagram of the measured and simulated output power at different input power;

[0053] Figure 12 A comparison diagram of the measured and simulated power added efficiency at different input power. DETAILED DESCRIPTION

[0054] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. The description of the at least one exemplary embodiment is actually only illustrative, but not as any limitation on the present application and its application or use. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative labor fall within the scope of the present application.

[0055] Unless otherwise specified, the relative arrangement, numerical expressions and values of the components and steps set forth in these embodiments do not limit the scope of the present application.

[0056] It should be understood that the sizes of the various parts shown in the drawings are not drawn in accordance with the actual proportional relationship for the convenience of description.

[0057] In addition, the description of well-known structures, functions and configurations can be omitted for clarity and brevity. Those of ordinary skill in the art will recognize that various changes and modifications can be made to the examples described herein without departing from the spirit and scope of the present disclosure.

[0058] Techniques, methods, and equipment known to those of ordinary skill in the relevant art can not be discussed in detail, but should be considered part of the authorized description where appropriate.

[0059] In all examples shown and discussed herein, any specific values should be interpreted as merely exemplary and not as a limitation. Thus, other examples of the exemplary embodiments can have different values.

[0060] Embodiment 1

[0061] As Figure 1 shown, the present embodiment provides a modeling method based on improved dispersion type Angelov, specifically comprising the following steps:

[0062] S1, constructing an Angelov model topology of the transistor according to a transistor test structure; extracting transistor coefficients and topology circuit parameters from the transistor test structure to construct an Angelov model topology of the transistor by a forward bias method, the extracted topology circuit parameters including intrinsic capacitance, parasitic resistance, and parasitic inductance.

[0063] S2, constructing a current equation of an improved dispersion type Angelov model based on the Angelov model topology, the current equation including a drain current equation and a dispersion current equation;

[0064] S3, extracting transistor DC parameters of the transistor without dispersion and with dispersion by respectively using a pulse voltage current test method and a pulse test method with a pre-pulse;

[0065] S4, substituting the transistor DC parameters without dispersion and with dispersion into the drain current equation and the dispersion current equation respectively, calculating a basic drain source current and a fitted dispersion current, and taking the sum of the basic drain source current and the fitted dispersion current as a total drain source current of the transistor;

[0066] The transistor DC parameters without dispersion include: a voltage saturation coefficient of a second harmonic current, a transconductance control coefficient of the second harmonic, a transconductance control coefficient of a third harmonic, a voltage saturation coefficient of the third harmonic current, a gate source voltage and a drain source voltage at a maximum transconductance of the transistor, parameters describing the voltage saturation coefficient, and a drain source current corresponding to the maximum transconductance.

[0067] The process of substituting the transistor DC parameters without dispersion into the drain current equation to calculate the basic drain source current in step S4 is as follows:

[0068] S01, calculating polynomial coefficients of a control function based on the voltage saturation coefficient of the second harmonic current, the transconductance control coefficient of the second harmonic, the transconductance control coefficient of the third harmonic, the voltage saturation coefficient of the third harmonic current, and the drain source voltage;

[0069] S02, calculating a fitted gate voltage based on the gate source voltage at the maximum transconductance of the transistor, the parameters describing the voltage saturation coefficient, and a degree of control of the maximum transconductance of the transistor by the drain source voltage;

[0070] S03, substituting the calculated polynomial coefficients and the fitted gate voltage into the control function to obtain a control value;

[0071] S04, calculating a final voltage saturation coefficient based on the control value;

[0072] S05, substituting the control value, the final voltage saturation coefficient, the drain source voltage, and the drain source current corresponding to the maximum transconductance into the drain current equation to obtain the basic drain source current.

[0073] The expression of the leakage current equation is:

[0074]

[0075] where, is the drain-source current corresponding to the maximum transconductance; represents the base drain-source current, P 20 , P 21 , P 2o represents the transconductance control coefficient of the second harmonic, α p2 is the voltage saturation coefficient of the second harmonic current, P 30 , P 31 , P 3o is the transconductance control coefficient of the third harmonic, α p3 is the voltage saturation coefficient of the third harmonic current; P 1, P 1m , , is the polynomial coefficient of the control function ; V ds represents the drain-source voltage, V gs represents the gate-source voltage, B1, B2 represents P the coefficient varying with V ds , is the gate-source voltage when the transistor has the maximum transconductance, represents the degree describing the control of the maximum transconductance of the transistor by the gate-source voltage, represents the calculation of the intermediate value; α s , α r is the parameter describing the voltage saturation coefficient α , λ is the channel length modulation coefficient, which is used to simulate the channel modulation effect.

[0076] has the same meaning as , has the same meaning as , has the same meaning as , has the same meaning as , has the same meaning as , only the one with the db mark is the dispersion parameter extracted from the pre-pulse current. The expression of the dispersion current equation is:

[0077]

[0078] where, is the drain-source current corresponding to the maximum transconductance, represents the fitted dispersion current, , , , represents the polynomial coefficients of the control function , represents the transconductance control coefficient of the second harmonic with dispersion extracted from the pre-pulse current, represents the voltage saturation coefficient of the second harmonic current with dispersion extracted from the pre-pulse current; represents the transconductance control coefficient of the third harmonic with dispersion extracted from the pre-pulse current; represents the voltage saturation coefficient of the third harmonic current with dispersion extracted from the pre-pulse current; V ds represents the drain-source voltage, V gs represents the gate-source voltage, B1, B2 represents the coefficient that varies with V ds , is the gate-source voltage when the transistor has the maximum transconductance, represents the degree of description of the control of the maximum transconductance of the transistor by the gate-source voltage, represents the calculation of the intermediate value; α s , α r is the parameter that describes the voltage saturation coefficient α , λ is the channel length modulation coefficient, which is used to simulate the channel modulation effect.

[0079] The fitted drain-source current of the transistor is divided into a basic drain-source current and a fitted dispersion current , which has two independent variables, the gate-source voltage V gs and the drain-source voltage V ds .

[0080] When the frequency freq=0, the fitted dispersion current ;

[0081] At this time, the drain-source current is ;

[0082] When the frequency freq≠0, the drain-source current is: .

[0083] S5, obtaining topological circuit parameters (intrinsic capacitances (gate-source capacitance Cgs, gate-drain capacitance Cgd), parasitic resistances (Rg, Rd, Rs, Ri), parasitic inductances (Lg, Ld, Ls)) from the Angelov model topology of the transistor, and describing the S parameters of the transistor under multi-bias based on the total drain-source current of the transistor and the topological circuit parameters;

[0084] S6, optimizing and iterating the fitting parameters in the current equation of the improved dispersion type Angelov model through the difference between the simulation and the actual measurement of the S parameters under multi-bias, obtaining the optimal current equation, and finally obtaining the improved dispersion type Angelov model of the transistor.

[0085] When optimizing the fitting parameters in the current equation of the improved dispersion type Angelov model, it is verified whether the fitting parameters meet the modeling accuracy, and if not, the transistor DC parameters with dispersion parameters are re-extracted and steps S3-S6 are repeated until the modeling accuracy is met, wherein the fitting parameters are the transistor DC parameters with dispersion parameters extracted by the method of pre-pulse pulse test.

[0086] Specifically, it also includes the extraction term of the transistor gate-drain capacitance and gate-source capacitance extracted by the method of Cold-FET, and when optimizing the fitting parameters in the current equation of the improved dispersion type Angelov model, it is also necessary to verify whether the extraction term of the transistor gate-drain capacitance and gate-source capacitance meets the modeling accuracy;

[0087] When the fitting parameters and the extraction term of the transistor gate-drain capacitance and gate-source capacitance meet the modeling accuracy at the same time, the improved dispersion type Angelov model of the transistor is obtained.

[0088] It can be understood that the specific implementation mode of the present application is realized by Verilog-A program code, and the equivalent circuit diagram of the Angelov model topology of the transistor is as shown in Figure 2 The ideal capacitor Cdb is used to determine whether to use , wherein Rg, Rs, and Rd are the parasitic resistances of the transistor, Lg, Ls, and Ld are the parasitic inductances of the transistor, and Ri is the gate resistance of the transistor. Igd and Igs are the gate-drain current and the gate-source current of the transistor, respectively. Cgs, Cgd, and Cds are the gate-source capacitance, the gate-drain capacitance, and the drain-source capacitance of the transistor, respectively, and Cdb is an ideal capacitor. S represents the source of the transistor, D represents the drain of the transistor, and G represents the gate of the transistor, represents the basic drain-source current, represents the fitting dispersion current. Based on the equivalent circuit diagram of Figure 2 , the modeling process is:

[0089] Firstly, the On-Fet is used to extract the parasitic inductance Lg, Ls, Ld and the parasitic resistance Rg, Rd, Rs and the gate diode coefficient.

[0090] Secondly, the pulse voltage and current test method is used to extract the DC parameters without dispersion. The parameters extracted in this step are Compared with the traditional Angelov method, the expression of the control function is changed to , which can better fit the transconductance of the transistor. In addition, the is changed to , which increases the robustness of the drain-source current and makes it easier to converge.

[0091] Thirdly, the pulse test method with pre-pulse is used to extract the DC parameters of the transistor with dispersion. This step mainly extracts .

[0092] The fourth step is to extract the gate-drain capacitance Cgd and the gate-source capacitance Cgs using the Cold-Fet method.

[0093] The fifth step is to measure the S parameters of multiple bias. This step is to verify the accuracy of the parameter extraction results of steps three and four. If the modeling accuracy is not met, it needs to return to step three for extraction. That is, steps three to five are a process of cyclic optimization iteration.

[0094] The equation of the traditional Angelov method is:

[0095]

[0096] In the above equation, the parameters P 1、 P 2、 P 3、 B1 , B2、 V pks , D V pks 、 α s 、 α r 、 I pk 、 λ are extracted from the IV curve of the transistor test. is the drain-source current corresponding to the maximum transconductance . Among them is the polynomial coefficient of the control . B1, B2 represent the coefficient of P1 changing with Vds, is the Vgs of the transistor at the maximum transconductance, To describe the degree that the maximum transconductance of the transistor is controlled by Vds, To describe the parameter of the voltage saturation coefficient α, which controls the slope of the drain-source current Ids of the transistor in the linear region.

[0097] The above is the traditional Angelov equation. In practical application, it is found that this series of equations cannot accurately describe the transconductance Gm no matter how. Comprehensive analysis found that it is caused by too few parameters in the description. In order to increase the accuracy of the transconductance and improve the convergence of the entire current equation, the current equation is rewritten from the following aspects:

[0098] 1, by rewriting P2 as , rewriting P3 as Can better fit , so that the fitting accuracy of the transconductance is higher, and the drain current equation is from:

[0099]

[0100] Rewrite as:

[0101]

[0102] From Rewrite as Increase the robustness of the equation, so that it is easier to converge.

[0103] By increasing, The transconductance control coefficient of the second harmonic, The voltage saturation coefficient of the second harmonic current. The transconductance control coefficient of the third harmonic. The voltage saturation coefficient of the third harmonic current. By rewriting P2 as , rewriting P3 as Can better fit , so that the fitting accuracy of the transconductance is higher.

[0104] 2, in order to improve the description accuracy of the S parameter. The embodiment increases the dispersion current equation , Similar to , but the above traditional Angelov equation is rewritten as:

[0105]

[0106] Here, The meaning is the same as , the meaning of The meaning is the same as , the meaning of ​with the meaning of , with the meaning of , with the meaning of , except that the one with the db flag is the dispersion parameter extracted from the pre-pulse current.

[0107] 3, The drain-source current equation of the transistor is divided into two parts, namely the DC part and the discrete part

[0108]

[0109] As shown in the above formula is the total drain-source current of the transistor, which has two independent variables, namely the gate-source voltage and the drain-source voltage .

[0110] is the base drain-source current when the frequency freq =0. is the drain-source dispersion current when freq ≠0. In the Verilog-A of the present application, the current simulation frequency will be read from the simulator. In the circuit topology, an ideal capacitor is used to simulate the difference of the frequency-dependent current, based on the frequency characteristics of the ideal capacitor: DC does not pass, AC short circuit, then we can get:

[0111] When freq = 0 , the drain-source current of the transistor is:

[0112]

[0113] When freq ≠ 0 , the drain-source current of the transistor is:

[0114]

[0115] In order to better illustrate that the improved Angelov method of the present application has better modeling accuracy, this time, the GaAs P-HEMT process is modeled and simulated, wherein the selected die gate index is 8, the single-finger gate width is 100um, the threshold voltage is -1V, and the rated drain working voltage is 8V. The test comparison results by respectively using the improved dispersion type Angelov method of the present application and the test comparison results are as shown in Figures 3-12 , wherein the root mean square error RMS is defined as:

[0116]

[0117] As Figure 3The simulation results of drain-source current are compared between the test (black solid line) and the simulation (black dotted line) under different drain-source voltages (0.1V interval from -1V to 0V) as shown in the figure, Figure 4 For Figure 3 The root mean square error of the test drain-source current and the simulation drain-source current under each gate voltage is shown in the figure. It can be seen that the root mean square error gradually decreases as the gate-source voltage increases.

[0118] As Figure 5 shown, the simulation results of transconductance are compared between the test (black solid line) and the simulation (black dotted line) under different gate-source voltages (0.5V interval from 6V to 10V). Figure 6 For Figure 5 The root mean square error of the measured transconductance and the simulation transconductance under each drain-source voltage is shown in the figure. It can be seen that the root mean square error gradually decreases as the drain-source voltage increases.

[0119] As Figure 7 shown, the root mean square error (RMS) values of the measured and simulated input return loss (statistical frequency of 0.1 GHz-20 GHz) are shown when the drain-source voltage is 8V and the gate-source voltage is from -1V to -0.5V with an interval of 0.05V. It can be seen that the overall root mean square error is less than 5%, and the simulation results are basically consistent.

[0120] As Figure 8 shown, the RMS values of the measured and simulated S12 (statistical frequency of 0.1 GHz-20 GHz) are shown when the drain-source voltage is 8V and the gate-source voltage is from -1V to -0.5V with an interval of 0.05V. It can be seen that the root mean square error is less than 20% when the gate voltage is from -0.8V to -0.6V, which is the commonly used gate voltage range of the process.

[0121] As Figure 9 shown, the RMS values of the measured and simulated S21 (statistical frequency of 0.1 GHz-20 GHz) are shown when the drain-source voltage is 8V and the gate-source voltage is from -1V to -0.5V with an interval of 0.05V. It can be seen that the overall root mean square error value is less than 7%, and the simulation results are basically consistent.

[0122] As Figure 10 shown, the root mean square error (RMS) values of the measured and simulated output return loss (statistical frequency of 0.1 GHz-20 GHz) are shown when the drain-source voltage is 8V and the gate-source voltage is from -1V to -0.5V with an interval of 0.05V. It can be seen that the overall root mean square error value is less than 13%, and the simulation results are basically consistent.

[0123] As Figure 11As shown, when the drain-source voltage is 8V, the gate-source voltage is 0.8V, the frequency is freq=15GHz, and the impedance at the optimal output power point is tested, the measured (solid black line) and simulated (dashed black line) output power are compared. It can be seen that the simulation results based on the method of this invention are almost identical to the measured results.

[0124] like Figure 12 As shown, when the drain-source voltage is 8V, the gate-source voltage is 0.8V, the frequency is freq=15GHz, and the optimal output power point impedance is tested, the power-added efficiency is compared between the measured (solid black line) and the simulated (dashed black line) results. It can be seen that the simulation results based on the method of this invention are almost identical to the measured results.

[0125] Example 2

[0126] This embodiment 2 provides a modeling system based on the improved dispersive Angelov model, including:

[0127] The topology building module is used to build the Angelov model topology of transistors based on transistor test structures.

[0128] The Angelov model building module is used to construct the current equations of an improved dispersive Angelov model based on the Angelov model topology. The current equations include leakage current equations and dispersive current equations.

[0129] The parameter extraction module is used to extract the DC parameters of transistors with and without dispersion using the pulse voltage and current test method and the pulse test method with pre-pulse, respectively.

[0130] The fitting module is used to substitute the DC parameters of the transistor with and without dispersion parameters into the leakage current equation and the dispersion current equation, respectively, to calculate the basic drain-source current and the fitted dispersion current. The sum of the basic drain-source current and the fitted dispersion current is taken as the total drain-source current of the transistor. The topology circuit parameters are obtained from the Angelov model topology of the transistor. Based on the total drain-source current of the transistor and the topology circuit parameters, the S-parameters of the transistor under multiple biases are described.

[0131] The Angelov model optimization module optimizes and iterates the fitting parameters in the current equation of the improved dispersive Angelov model by comparing the simulation and measured S-parameters under multiple biases, thereby obtaining the optimal current equation and finally the improved dispersive Angelov model of the transistor.

[0132] The above is only the preferred embodiment of the present application, and does not limit the present application in any form. According to the technical essence of the present application, any simple modification, equivalent replacement and improvement of the above embodiment within the spirit and principle of the present application are still within the protection scope of the technical solution of the present application.

Claims

1. A modeling method based on improved dispersion type Angelov, characterized in that, Specifically comprising the following steps: S1, constructing an Angelov model topology structure of the transistor according to a transistor test structure; S2, constructing a current equation of an improved dispersion type Angelov model based on the Angelov model topology structure, the current equation including a drain current equation and a dispersion current equation; S3, extracting transistor DC parameters without dispersion and with dispersion of the transistor by using a pulse voltage current test method and a pulse test method with a pre-pulse respectively; S4, substituting the transistor DC parameters without dispersion and with dispersion into the drain current equation and the dispersion current equation respectively, calculating a basic drain source current and a fitted dispersion current, and taking a sum of the basic drain source current and the fitted dispersion current as a total drain source current of the transistor; S5, obtaining topology circuit parameters from the Angelov model topology structure of the transistor, and describing S parameters of the transistor under multi-bias based on the total drain source current of the transistor and the topology circuit parameters; S6, optimizing and iterating fitting parameters in the current equation of the improved dispersion type Angelov model through a difference between simulation and actual measurement of the S parameters under multi-bias, obtaining an optimal current equation, and finally obtaining the improved dispersion type Angelov model of the transistor.

2. The modeling method based on improved dispersion-type Angelov according to claim 1, characterized in that, The forward bias method is used to extract transistor coefficients and topology circuit parameters from the transistor test structure to construct the Angelov model topology structure of the transistor, and the extracted topology circuit parameters include a parasitic resistance, a parasitic inductance and an intrinsic capacitance of the transistor.

3. The modeling method based on improved dispersion-type Angelov according to claim 1, characterized in that, The transistor DC parameters without dispersion include a voltage saturation coefficient of a second harmonic current, a transconductance control coefficient of the second harmonic, a transconductance control coefficient of a third harmonic, a voltage saturation coefficient of the third harmonic current, a gate source voltage and a drain source voltage at maximum transconductance of the transistor, parameters describing the voltage saturation coefficient, and a drain source current corresponding to the maximum transconductance.

4. The modeling method based on improved dispersion-type Angelov according to claim 3, characterized in that, In step S4, the process of substituting the transistor DC parameters without dispersion into the drain current equation to calculate the basic drain source current is as follows: S01, calculating polynomial coefficients of a control function based on the voltage saturation coefficient of the second harmonic current, the transconductance control coefficient of the second harmonic, the transconductance control coefficient of the third harmonic, the voltage saturation coefficient of the third harmonic current, and the drain source voltage; S02, calculating a fitted gate voltage based on the gate source voltage at the maximum transconductance of the transistor, the parameters describing the voltage saturation coefficient, and a degree of control of the maximum transconductance of the transistor by the drain source voltage; S03, substituting the calculated polynomial coefficients and the fitted gate voltage into the control function to obtain a control value; S04, calculating a final voltage saturation coefficient based on the control value; S05, substituting the control value, the final voltage saturation coefficient, the drain source voltage, and the drain source current corresponding to the maximum transconductance into the drain current equation to obtain the basic drain source current.

5. The modeling method based on improved dispersion-type Angelov of claim 4, wherein, The expression of the drain current equation is as follows: wherein is the drain-source current corresponding to the maximum transconductance; denotes the base drain-source current, P 20 , P 21 , P 2o denotes the transconductance control coefficient of the second harmonic, α p2 is the voltage saturation coefficient of the second harmonic current, P 30 , P 31 , P 3o denotes the transconductance control coefficient of the third harmonic, α p3 is the voltage saturation coefficient of the third harmonic current; P 1、 P 1m 、 、 is the polynomial coefficient of the control function ; V ds denotes the drain-source voltage, V gs denotes the gate-source voltage, B1, B2 denotes P the coefficient of the function V ds , is the gate-source voltage at the maximum transconductance of the transistor, denotes the degree describing the control of the maximum transconductance of the transistor by the gate-source voltage, denotes the calculation of the intermediate value; α s 、 α r is the parameter describing the voltage saturation coefficient α , λ is the channel length modulation coefficient, used to simulate the channel modulation effect.

6. The modeling method based on improved dispersion-type Angelov of claim 1, wherein, The expression of the dispersion current equation is as follows: wherein is the drain-source current corresponding to the maximum transconductance, represents the fitted dispersive current, , , , represents the polynomial coefficients of the control function , , , represents the transconductance control coefficient of the second harmonic with dispersion extracted from the pre-pulse current, represents the voltage saturation coefficient of the second harmonic current with dispersion extracted from the pre-pulse current; , , represents the transconductance control coefficient of the third harmonic with dispersion extracted from the pre-pulse current; represents the voltage saturation coefficient of the third harmonic current with dispersion extracted from the pre-pulse current; V ds represents the drain-source voltage, V gs represents the gate-source voltage, B1, B2 represents the coefficient that varies with V ds , is the gate-source voltage at the maximum transconductance of the transistor, represents the degree of control of the maximum transconductance of the transistor by the gate-source voltage, represents the calculation of the intermediate value; α s , α r is the parameter that describes the voltage saturation coefficient α , λ is the channel length modulation coefficient, which is used to simulate the channel modulation effect.

7. The modeling method based on improved dispersion-type Angelov of claim 1, wherein, Fitted drain-source current of transistor Basic drain source current and fitted dispersive current The sum of the frequencies freq=0 When, fit the dispersive current The drain-source current is then ; When the frequency freq≠0 the drain-source current is: .

8. The modeling method based on improved dispersion-type Angelov of claim 1, wherein, In the optimization of the fitting parameters in the current equation of the improved dispersion type Angelov model, it is verified whether the fitting parameters meet the modeling accuracy. If not, the transistor DC parameters with dispersion parameters are extracted again by the pre-pulse pulse test method, and steps S3-S6 are repeated until the modeling accuracy is met. The fitting parameters are the transistor DC parameters with dispersion parameters extracted by the pre-pulse pulse test method.

9. The modeling method based on the improved dispersion-type Angelov of claim 8, wherein, Also included is the extraction of the transistor gate-drain and gate-source capacitances with the method Cold-FET The extraction terms of the transistor gate-drain and gate-source capacitances are also included, and when optimizing the parameters in the current equation of the improved dispersion type Angelov model, it is also necessary to verify whether the extraction terms of the transistor gate-drain and gate-source capacitances meet the modeling accuracy. When the fitting parameters and the extracted terms of the transistor gate-drain capacitance and the gate-source capacitance meet the modeling accuracy at the same time, the improved dispersion type Angelov model of the transistor is obtained.

10. A modeling system based on improved dispersion type Angelov, characterized by, Comprise: A topology construction module for constructing an Angelov model topology structure of the transistor according to a transistor test structure; An Angelov model construction module for constructing a current equation of an improved dispersion type Angelov model based on the Angelov model topology structure, the current equation including a drain current equation and a dispersion current equation; A parameter extraction module for extracting transistor DC parameters without dispersion and with dispersion parameters of the transistor by the pulse voltage current test method and the pre-pulse pulse test method, respectively; A fitting module for substituting the transistor DC parameters without dispersion and with dispersion parameters into the drain current equation and the dispersion current equation, respectively, calculating the basic drain-source current and the fitted dispersion current, and taking the sum of the basic drain-source current and the fitted dispersion current as the total drain-source current of the transistor, obtaining the topological circuit parameters from the Angelov model topology structure of the transistor, and describing the S parameters of the transistor under multi-bias based on the total drain-source current of the transistor and the topological circuit parameters; An Angelov model optimization module for optimizing and iterating the fitting parameters in the current equation of the improved dispersion type Angelov model through the difference between the simulation and the actual measurement of the S parameters under multi-bias, obtaining the optimal current equation, and finally obtaining the improved dispersion type Angelov model of the transistor.

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