An electronic device data analysis method and system

Abstract

The application discloses an electronic device data analysis method and system, and relates to the technical field of electronic device resource management. The method comprises the following steps: acquiring physical position information of logical units in an electronic device; calculating a logical resource quantity set according to the physical position information; calculating a Gini coefficient of target logical resource distribution according to the logical resource quantity set; and generating a target optimization strategy according to the Gini coefficient and a preset coefficient threshold. The application can realize electronic device data analysis by combining logical resource quantity and distribution, and improves analysis accuracy and resource utilization.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of electronic device resource management, and in particular to an electronic device data analysis method and system. BACKGROUND

[0002] In the design flow of field programmable gate array (FPGA), effective management and optimization of logic resources are the key to ensuring the performance and reliability of the chip. The traditional logic resource occupancy analysis method usually focuses on macro resource usage and overall routing accessibility, aiming to ensure that the design can efficiently adapt to the chip capacity. However, with the iterative update of FPGA development tools, their underlying algorithms (such as the congestion evaluation algorithm of the layout and routing tool) may undergo subtle adjustments. When the design team continues to use the design constraint scripts optimized for the old version of the tool, the new tool may have an unintended "semantic misunderstanding" of these old constraints, resulting in low analysis accuracy. At the same time, this misunderstanding may cause the layout and routing tool to excessively concentrate a large number of logic units in a specific physical area of the FPGA chip, forming a very high local logic resource density, while other areas have low logic resource density and low resource utilization.

[0003] In summary, the technical problems in the related art need to be improved. SUMMARY

[0004] The main purpose of the embodiments of the present application is to provide an electronic device data analysis method and system, which can realize electronic device data analysis by combining the number and distribution of logic resources, improving the analysis accuracy and resource utilization.

[0005] In one aspect, the present application provides an electronic device data analysis method, comprising the following steps:

[0006] Obtaining physical location information of logic units in an electronic device;

[0007] According to the physical location information, calculating a set of logic resource quantities;

[0008] According to the set of logic resource quantities, calculating the Gini coefficient of the target logic resource distribution;

[0009] According to the Gini coefficient and a preset coefficient threshold, generating a target optimization strategy.

[0010] In some embodiments, the calculation of the set of logic resource quantities according to the physical location information comprises:

[0011] Obtaining physical boundary information of a chip in the electronic device;

[0012] According to the physical boundary information of the chip, calculating the height and width of the chip;

[0013] According to the preset grid quantity, the chip height and the chip width, a virtual grid unit height and a virtual grid unit width are calculated;

[0014] According to the virtual grid unit height and the virtual grid unit width, the chip is regionally divided to obtain a plurality of virtual grid units;

[0015] According to the physical position information, an index corresponding to each logical unit is calculated, and the index is used to point to a virtual grid unit to which the logical unit belongs;

[0016] According to the indexes corresponding to a plurality of logical units, a logical resource quantity corresponding to each virtual grid unit is calculated;

[0017] A plurality of logical resource quantities are combined to obtain a logical resource quantity set.

[0018] In some embodiments, the calculation of the Gini coefficient of the target logical resource distribution according to the logical resource quantity set comprises:

[0019] A unit power consumption parameter and an expected activity rate parameter of the logical unit are obtained;

[0020] According to the logical resource quantity set, the number of logical units in a virtual grid unit is determined;

[0021] According to the unit power consumption parameter, the expected activity rate parameter and the number of logical units in the virtual grid unit, an estimated dynamic power consumption contribution of the virtual grid unit is calculated;

[0022] According to the estimated dynamic power consumption contribution, a weighted logical resource density of the virtual grid unit is calculated;

[0023] According to the weighted logical resource densities of a plurality of virtual grid units, the Gini coefficient of the target logical resource distribution is calculated.

[0024] In some embodiments, the generation of the target optimization strategy according to the Gini coefficient and a preset coefficient threshold value comprises:

[0025] When the Gini coefficient is greater than the preset coefficient threshold value, a target virtual grid in which the logical resource density in the physical area of the electronic device is greater than a preset local density is identified;

[0026] Logical module information to which logical units in the target virtual grid belong is obtained;

[0027] According to the logical module information, first design constraint information corresponding to the logical module is extracted;

[0028] According to the logical module information and the first design constraint information, the target optimization strategy is generated.

[0029] In some embodiments, the generating the target optimization strategy according to the logic module information and the first design constraint information comprises:

[0030] generating an initial optimization strategy containing the logic module information and the first design constraint information;

[0031] predicting a distribution of logic units in the logic module in the electronic device physical area according to the initial optimization strategy, to obtain a predicted logic resource distribution;

[0032] identifying a critical timing path according to the predicted logic resource distribution;

[0033] calculating a delay change of the critical timing path;

[0034] evaluating a timing performance impact degree of the initial optimization strategy according to the delay change, the timing performance impact degree being used to indicate whether there is a new global performance bottleneck;

[0035] updating a weighted logic resource density of the target virtual grid according to the predicted logic resource distribution;

[0036] evaluating a power consumption distribution impact degree of the initial optimization strategy according to the weighted logic resource density, the power consumption distribution impact degree being used to indicate whether there is a new local power consumption hotspot;

[0037] adjusting the initial optimization strategy according to the timing performance impact degree and the power consumption distribution impact degree, to obtain the target optimization strategy.

[0038] In some embodiments, the adjusting the initial optimization strategy according to the timing performance impact degree and the power consumption distribution impact degree, to obtain the target optimization strategy comprises:

[0039] generating a plurality of candidate adjustment schemes, the candidate adjustment schemes being used to modify the initial optimization strategy;

[0040] selecting one candidate adjustment scheme from the plurality of candidate adjustment schemes as a to-be-compared adjustment scheme;

[0041] updating a timing performance impact degree and a power consumption distribution impact degree corresponding to the to-be-compared adjustment scheme;

[0042] performing scheme evaluation on the to-be-compared adjustment scheme according to the updated timing performance impact degree and the power consumption distribution impact degree, to obtain a scheme evaluation result;

[0043] According to the optimization target weight, comparison is made on the scheme evaluation results corresponding to the multiple candidate adjustment schemes to obtain a target adjustment scheme.

[0044] According to the target adjustment scheme, adjustment is made on the initial optimization strategy to obtain the target optimization strategy.

[0045] In some embodiments, the generating of the multiple candidate adjustment schemes comprises:

[0046] Obtaining design stage information, field programmable gate array architecture information and second design constraint information of an electronic device;

[0047] Selecting a rule from a preset rule set as an initial optimization rule;

[0048] According to the design stage information, the field programmable gate array architecture information and the second design constraint information, adjustment is made on the initial optimization rule to obtain a target optimization rule, which is used for parameterized modification on the initial optimization strategy;

[0049] According to the target optimization rule, the multiple candidate adjustment schemes are generated.

[0050] In some embodiments, the obtaining of the target adjustment scheme according to the optimization target weight and comparison on the scheme evaluation results corresponding to the multiple candidate adjustment schemes comprises:

[0051] Obtaining a chip running environment parameter range, the chip running environment parameter range comprising a temperature range, a voltage range and a process deviation range;

[0052] According to the optimization target weight, comparison is made on the scheme evaluation results corresponding to the multiple candidate adjustment schemes to obtain a target adjustment scheme.

[0053] According to the chip running environment parameter range, multiple environment variation scenarios are generated;

[0054] In each of the environment variation scenarios, re-evaluation is made on the time sequence performance influence degree and the power consumption distribution influence degree corresponding to the initial adjustment scheme to obtain a re-evaluation result;

[0055] According to the re-evaluation result corresponding to each of the environment variation scenarios, a performance fluctuation index of the initial adjustment scheme is calculated;

[0056] If the performance fluctuation index is less than a preset stability threshold, the initial adjustment scheme is taken as the target adjustment scheme.

[0057] In some embodiments, the generating of the multiple environment variation scenarios according to the chip running environment parameter range comprises:

[0058] acquire statistical correlation information among the temperature range, the voltage range and the process bias range;

[0059] determine a sampling strategy according to the chip running environment parameter range and the statistical correlation information;

[0060] perform sampling according to the sampling strategy to obtain the plurality of environment variation scenarios.

[0061] In another aspect, an embodiment of the present application provides an electronic device data analysis system, comprising:

[0062] an information acquisition module configured to acquire physical location information of logical units in an electronic device;

[0063] a logical resource statistics module configured to calculate a logical resource quantity set according to the physical location information;

[0064] a coefficient calculation module configured to calculate a Gini coefficient of a target logical resource distribution according to the logical resource quantity set;

[0065] a strategy generation module configured to generate a target optimization strategy according to the Gini coefficient and a preset coefficient threshold.

[0066] The embodiments of the present application have at least the following beneficial effects: the embodiments of the present application first acquire physical location information of logical units in an electronic device, then calculate a logical resource quantity set according to the physical location information, and then calculate a Gini coefficient of a target logical resource distribution according to the logical resource quantity set, and finally generate a target optimization strategy according to the Gini coefficient and a preset coefficient threshold, so that the electronic device data analysis can be realized by combining the logical resource quantity and distribution, and the analysis accuracy and resource utilization rate are improved.

[0067] Other features and advantages of the present application will be set forth in the following description, and in part will become apparent to those skilled in the art from the description, or can be learned by practice of the present application. The objects and other advantages of the present application will be realized and achieved by means of the structures particularly pointed out in the description and the appended claims. BRIEF DESCRIPTION OF DRAWINGS

[0068] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative effort.

[0069] Figure 1 a flowchart of an electronic device data analysis method according to an embodiment of the present application;

[0070] Figure 2 FIG. 1 is a schematic diagram of an electronic device data analysis system according to an embodiment of the present application. DETAILED DESCRIPTION

[0071] For the purposes of the present application, the technical solutions and advantages thereof are more clearly apparent, further detailed descriptions of the present application are provided below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely intended to explain the present application and are not intended to limit the present application. When the following description refers to the accompanying drawings, the same numbers on different drawings represent the same or similar elements unless otherwise indicated.

[0072] In related art, field programmable gate arrays (FPGAs) play a core role in high-performance image processing units in the field of industrial automation and other fields. The design process usually relies on precise logic resource occupancy analysis methods to ensure that the design can efficiently adapt to the chip capacity. However, in the actual development process, due to the iteration and update of the development tools and the long-term design constraint habits of the design team, mismatches may occur, causing the tool to deviate from the interpretation of the design intent. This deviation may cause excessive concentration of local logic resources on the physical implementation of the FPGA chip, thereby forming heat-consuming hot spots, and ultimately triggering random and intermittent timing errors, and existing analysis methods often fail to detect such hidden hardware reliability problems.

[0073] For example, an FPGA engineer working on image processing units for industrial automation, daily development work revolves around a set of mature and well-defined processes. The custom image processing unit developed by the engineer needs to process high-resolution video streams in real-time, therefore the parallel logic carried inside the FPGA is large in scale and the efficiency of logic resource usage is strictly required. After each major design iteration, the FPGA design is checked using a logic resource utilization analysis method to ensure that it fully complies with the capacity requirements of the chip. This method reads the netlist file generated by the design tool, then uses its built-in rules, such as mapping the logic lookup table (LUT) to the actual FPGA resources, and evaluating the routing congestion situation. To ensure the accuracy of the analysis results, it is necessary to ensure that the analysis tool used is always compatible with the latest version of the FPGA device library and the logic synthesis, placement and routing tools. Signals in the design that cross different clock domains are also correctly handled, and the analysis method accurately evaluates the resources consumed by these synchronous logic according to its internal model. Finally, the analysis report clearly presents the usage of various logic resources (such as lookup tables, flip-flops, memory blocks, and digital signal processors), providing valuable information to the engineer about the size of the design. In this regular design and analysis scenario, the mapping rules from logic lookup tables to actual FPGA resources are clear and consistent with the current tool behavior; the placement and routing tool's evaluation of congestion is accurate; the structure of the design netlist is standard and easy to parse; the analysis tool's compatibility with different versions of the FPGA device library is good; and the evaluation model for resources consumed by cross-clock-domain signal processing is reliable. All these logical links work smoothly, ensuring the effectiveness of the analysis results and helping to efficiently manage and optimize the use of FPGA logic resources.

[0074] However, during actual development and deployment, some subtle changes can introduce unexpected complexity. For example, the supplier of the FPGA development tools may release a minor version update aimed at improving product performance or fixing known defects. In such an update, to optimize performance, the supplier may make an adjustment to the underlying "congestion evaluation algorithm" of the placement and routing tool that is not declared in a prominent place. This adjustment may change the internal weights of the algorithm when dealing with high-density logic, making it more inclined to physically cluster related logic units in order to shorten local routing lengths, thereby theoretically improving timing performance.

[0075] When the FPGA engineers responsible for the image processing unit development, following the technical strategy of "keeping tools up to date", upgrade the development environment to the latest version, a potential problem starts to emerge. Due to the tight project schedule, the engineers might not have carefully read the lengthy update log and missed the fine-grained adjustment description of the congestion algorithm. Meanwhile, the engineers have a long-standing "best practice" of reusing a set of design constraint scripts that have been well-optimized and validated through multiple projects. The scripts contain specific instructions that guide the tool to perform logic placement, which can produce the best performance under the old tool version.

[0076] When the constraint scripts optimized for the old tool version are applied to the new tool version, the placement instructions in the scripts might interact with the new congestion evaluation algorithm in an unintended way. The new algorithm might misinterpret the instructive instructions in the old scripts as hard constraints with the highest priority. For example, if there is a flexible "region constraint" instruction in the old scripts, which aims to guide the logic cells to be roughly distributed in a region, the new algorithm might misinterpret it as a must to compress all the relevant logic cells into the minimum physical space of the region, even if it leads to extreme local congestion. This misinterpretation might cause the place-and-route tool to generate a layout that is "legal" on the surface but has extremely poor physical implementation quality when processing a critical data processing module with high parallelism. It will over-concentrate a large number of logic cells in a very small physical region to satisfy the misinterpreted old constraint instruction, resulting in a much higher-than-normal level of wire congestion and logic density in that region.

[0077] In this case, the engineers run the standard logic resource utilization analysis method as usual. The method reads the design netlist and correctly counts the number of logic cells such as lookup tables and flip-flops used. Although the built-in wire resource evaluation model might detect that the local wire pressure is high, it does not issue a high-risk warning in the final analysis report because the total resource utilization is still within the safe threshold. This is because the analysis method usually focuses on the macro resource usage and overall wire reachability, and cannot identify the local layout quality deterioration caused by "semantic misunderstanding", i.e. it cannot judge whether the logic density in a certain region has reached an unhealthy level physically, even if the total resource usage is normal.

[0078] Based on the analysis report "pass" conclusion, this design with hidden dangers is officially burned into the FPGA chip and enters the hardware debugging stage. At this point, a logical level design process problem has been transformed into a solid physical entity problem. In the actual physical chip, that logic area that is over-compressed becomes a significant power "hot spot" during runtime due to its extremely high transistor density and wiring density. The local working temperature of this area can be 15-20 degrees Celsius higher than other areas on the chip. According to the physical properties of semiconductors, the switching speed of silicon-based transistors will decrease as the temperature rises. The continuous high temperature of this local "hot spot" area systematically reduces the timing slack of all signal paths in the area, and the operation of the entire module is on the edge of timing violation, becoming extremely sensitive to other factors such as voltage fluctuations and data patterns. For example, the design originally reserved 100 picoseconds of slack for signal transmission, but under high temperature, this slack may only be 10 picoseconds, making any minor disturbance likely to cause timing violations.

[0079] When performing high-load stress testing, for example, the image processing module needs to process data streams containing complex textures, resulting in high-frequency logic flips. This high load causes the "hot spot" area's power consumption and temperature to further climb, and the reduced timing slack cannot withstand this pressure. This does not cause stable violations of a fixed path, but rather random and intermittent timing errors within the area. This non-deterministic timing error causes random distribution of flickering bad points or small color block artifacts on the final output image, and the location and pattern of each test are different. For example, when processing the same video stream, the first time may appear a flickering green dot in the upper left corner, and the second time may appear a short blue color block in the lower right corner. This failure phenomenon is extremely difficult to reproduce and locate, and traditional logic resource occupancy analysis reports show that everything is normal and cannot provide any clues for debugging. Thus, a "semantic" problem caused by tool chain upgrades and technicians' old habits ultimately manifests as a seemingly random hardware failure or power instability phenomenon that existing analysis methods cannot identify and have low analysis accuracy. At the same time, this misunderstanding can cause the layout tool to over-concentrate a large number of logic units in a specific physical area of the FPGA chip, forming an extremely high local logic resource density, while other areas have low logic resource density and low resource utilization.

[0080] Therefore, the embodiment obtains the physical position information of the logic unit, calculates the logic resource quantity set based on the physical position information, further calculates the Gini coefficient of the target logic resource distribution, and finally generates the optimization strategy according to the Gini coefficient and the preset coefficient threshold, so as to effectively identify and solve the power consumption hotspot and timing problem caused by the local logic resource over-concentration, improve the analysis accuracy and resource utilization, and further improve the performance and reliability of the electronic device.

[0081] The embodiments of the present application will be explained in detail below with reference to the drawings:

[0082] Figure 1 is an optional flowchart of an electronic device data analysis method provided by the embodiment of the present application, Figure 1 The method in the embodiment can include but is not limited to steps S101 to S104.

[0083] Step S101, obtaining the physical position information of the logic unit in the electronic device;

[0084] Step S102, calculating the logic resource quantity set according to the physical position information;

[0085] Step S103, calculating the Gini coefficient of the target logic resource distribution according to the logic resource quantity set;

[0086] Step S104, generating the target optimization strategy according to the Gini coefficient and the preset coefficient threshold.

[0087] The steps S101 to S104 shown in the embodiment of the present application can realize the electronic device data analysis in combination with the logic resource quantity and distribution, and improve the analysis accuracy and resource utilization.

[0088] In some embodiments, the physical location information of the logic units in the electronic device can be obtained first in steps S101-S104. This can be achieved in various ways. For example, during the design phase of the electronic device, the designer can manually input the coordinate data of each logic unit on the chip layout diagram. This approach is suitable for small-scale or specific-area logic units whose location information is directly recorded in the design document. In another implementation, the physical location information can also be obtained by parsing the design file of the electronic device. For example, the design file can be stored in a text format, which contains the names of the logic units and their corresponding X, Y coordinates. At this time, a script or program can be written to read and extract these coordinate data. In addition, the physical location information can also be obtained by interfacing with electronic design automation (EDA) tools. For example, some EDA tools provide application programming interfaces (APIs) that allow external programs to query and export the physical location information of all logic units in the design. It can be understood that the physical location information refers to the coordinates or region identifiers of these logic units on the physical plane of the chip.

[0089] Then, according to the physical location information, the set of logic resource quantities is calculated. Illustratively, the physical area of the electronic device can be divided into several predefined rectangular areas of equal size, and then the number of logic units contained in each rectangular area is counted by traversing all the physical location information of the logic units. For example, the chip area can be divided into a 10x10 grid, and then the number of logic units in each grid is counted. In another implementation, different statistical areas can be defined according to the pre-set physical area boundaries, such as the boundaries of the macro units or functional modules of the chip. Then, each logic unit is attributed to the physical area where it is located, and the number of logic units in each area is accumulated. In this way, the number of logic units in each area obtained by statistics is combined to form the set of logic resource quantities, so as to switch from macroscopic resource occupancy analysis to fine-grained evaluation of local resource distribution, and thus clearly reveal which areas have potential risks of excessive concentration of logic resources.

[0090] According to the set of logical resource quantities, the Gini coefficient of the target logical resource distribution is calculated. For example, the values in the set of logical resource quantities can be arranged in ascending order, and then the Gini coefficient is calculated according to the definition formula. For example, if the set of logical resource quantities is {N1, N2,..., Nk}, where Ni represents the logical resource quantity of the i-th region, the Gini coefficient can be calculated using the Lorenz curve or a direct mathematical formula. Specifically, the proportion of the logical resource quantity of each region to the total logical resource quantity can be calculated, and the difference between these proportions is accumulated to finally obtain the Gini coefficient. In another implementation, the logical resource density of each region (i.e., the logical resource quantity divided by the area of the region) can be calculated first, and then the Gini coefficient is calculated based on these density values to reflect the uniformity of resource distribution per unit area. It can be understood that the Gini coefficient is a statistical index for measuring the degree of uniform distribution, which is used in the present application to evaluate the uniformity of logical resource distribution in the physical region of the chip. The embodiment can objectively evaluate the unevenness of logical resources in the entire physical region of the chip. When the Gini coefficient is high, it indicates that there is a significant local concentration of logical resources, which is the root cause of power hot spots and timing problems. By introducing the Gini coefficient, the present embodiment provides a quantitative and comparable index, so that the designer can intuitively understand the layout quality of the current design.

[0091] Finally, according to the Gini coefficient and the preset coefficient threshold, a target optimization strategy is generated. For example, if the calculated Gini coefficient is greater than the preset coefficient threshold, it indicates that the logical resource distribution is uneven, and at this time a general optimization suggestion can be generated, such as prompting the designer to manually adjust the layout. For example, a simple text report can be generated, indicating "local resource concentration detected, suggest manual optimization of layout". In another implementation, different levels of optimization strategies can be generated according to the numerical range of the Gini coefficient. For example, when the Gini coefficient is slightly higher than the threshold, a "suggest fine-tuning" strategy is generated; when the Gini coefficient is much higher than the threshold, a "suggest large-scale relocation" strategy is generated. These strategies can be presented in the form of text instructions, graphical prompts, or simple design rule suggestions. These strategies are intended to guide the designer to adjust the layout of the logical unit, thereby alleviating local power hot spots, improving timing performance, and ultimately improving the overall reliability of the electronic device.

[0092] By the technical solution, the physical position information of the logical units in the electronic device is acquired, and a logical resource quantity set is calculated based on the physical position information, so that the logical resource density of different regions inside the chip can be analyzed in detail. Then, the Gini coefficient of the target logical resource distribution is calculated, so that the degree of local resource concentration can be quantified objectively. Compared with the traditional method which only focuses on the overall occupancy rate, the embodiment can identify that there may be a local high-density region even if the overall resource utilization rate is not high. Therefore, when the calculated Gini coefficient is greater than a preset coefficient threshold, the embodiment can generate a targeted optimization strategy. The generation of such a strategy is based on the accurate identification of local unevenness, rather than a simple macroscopic judgment. For example, the traditional method may only suggest "optimizing the layout", while the embodiment can guide the designer to adjust the specific high-density region according to the quantification result of the Gini coefficient. This complete chain from "finding the problem" to "quantifying the problem" to "generating the solution" enables the embodiment to effectively warn and solve the local layout quality deterioration caused by "semantic misunderstanding" which cannot be identified by the traditional method, thereby avoiding random, intermittent timing errors and difficult-to-reproduce power hotspots that may occur during chip operation, and further significantly improving the reliability and performance of the electronic device design, providing designers with more detailed and effective analysis and optimization means.

[0093] In some embodiments, in step S102, calculating the logical resource quantity set according to the physical position information can include but is not limited to the following steps:

[0094] Obtaining physical boundary information of the chip in the electronic device;

[0095] Calculating the chip height and the chip width according to the physical boundary information of the chip;

[0096] Calculating the virtual grid unit height and the virtual grid unit width according to the preset grid quantity, the chip height and the chip width;

[0097] Dividing the chip into a plurality of virtual grid units according to the virtual grid unit height and the virtual grid unit width;

[0098] Calculating an index corresponding to each logical unit according to the physical position information, the index being used to point to a virtual grid unit to which the logical unit belongs;

[0099] Calculating a logical resource quantity corresponding to each virtual grid unit according to the indexes corresponding to the plurality of logical units;

[0100] Combining the plurality of logical resource quantities to obtain the logical resource quantity set.

[0101] In some embodiments, the physical boundary information of the chip in the electronic device can be obtained first. It can be understood that the physical boundary information refers to the peripheral contour or size data of the chip in the physical layout. These information can be usually extracted from the layout file (for example, GDSII file, LEF / DEF file) generated by the electronic design automation (EDA) tool, or obtained through the specification parameters of the chip. The physical boundary information defines the available physical area of the chip. According to the physical boundary information of the chip, the chip height and the chip width are calculated. Exemplarily, if the physical boundary information is given in the form of coordinates, the chip height can be obtained by subtracting the minimum Y coordinate from the maximum Y coordinate, and the chip width can be obtained by subtracting the minimum X coordinate from the maximum X coordinate.

[0102] Then, according to the preset grid number, the chip height and the chip width, the virtual grid unit height and the virtual grid unit width are calculated. The preset grid number can be a total grid number, or a grid number along the X axis and the Y axis. For example, if the preset grid number specifies the grid number N x in the X direction and the grid number N y in the Y direction, the virtual grid unit width can be calculated as the chip width divided by N x , and the virtual grid unit height can be calculated as the chip height divided by N y . This calculation ensures that the entire physical area of the chip can be evenly divided into a series of virtual grid units.

[0103] According to the virtual grid unit height and the virtual grid unit width, the chip is regionally divided to obtain a plurality of virtual grid units, which can discretize the continuous physical area of the chip into a series of regular virtual grid units with the same size. Each virtual grid unit represents a specific physical area on the chip, and its position can be uniquely identified by its row and column indices in the grid. According to the physical position information, the index corresponding to each logical unit is calculated. By comparing the physical position of the logical unit with the pre-divided virtual grid unit, the virtual grid unit to which each logical unit belongs can be determined, and an index corresponding thereto can be assigned. The index is used to point to the virtual grid unit to which the logical unit belongs, for example, the index can be a two-dimensional coordinate (row number, column number) indicating that the logical unit is located in which virtual grid unit.

[0104] Finally, according to the indexes corresponding to the plurality of logical units, the number of logical resources corresponding to each virtual grid unit is calculated. The number of logical units contained in each virtual grid unit can be counted by traversing all logical units and their corresponding indexes. The number of logical units reflects the logical resource density in the virtual grid unit. The plurality of logical resource numbers are combined to obtain a logical resource number set, which represents the distribution of logical resources on the physical area of the chip in a structured manner. For example, the set can be a list or an array, where each element corresponds to the number of logical resources of a virtual grid unit.

[0105] Through the above technical solutions, the embodiment divides the continuous physical area of the chip into discrete virtual grid units and accurately counts the number of logical resources in each grid unit, thereby converting the abstract logical unit physical location information into quantifiable logical resource distribution data, and a high-resolution resource density map can be obtained. This fine-grained area division and resource counting method makes it possible to analyze the unevenness of the logical resource distribution (for example, by Gini coefficient) subsequently, and lays a data foundation for identifying local resource hotspots and formulating targeted optimization strategies. At the same time, this refined data collection and organization method helps to more accurately assess the concentration and unevenness of logical resources on the chip, thereby providing reliable input data for subsequent power consumption analysis, timing optimization and hotspot management, effectively supporting the chip design and optimization process.

[0106] In some embodiments, in step S103, calculating the Gini coefficient of the target logical resource distribution according to the logical resource number set can include but is not limited to the following steps:

[0107] Obtaining the unit power consumption parameter and the expected activity rate parameter of the logical unit;

[0108] According to the logical resource number set, determining the number of logical units in the virtual grid unit;

[0109] According to the unit power consumption parameter, the expected activity rate parameter and the number of logical units in the virtual grid unit, calculating the estimated dynamic power consumption contribution of the virtual grid unit;

[0110] According to the estimated dynamic power consumption contribution, calculating the weighted logical resource density of the virtual grid unit;

[0111] According to the weighted logical resource density of the plurality of virtual grid units, calculating the Gini coefficient of the target logical resource distribution.

[0112] In some embodiments, the unit power consumption parameter and the expected activity rate parameter of the logic units can be obtained first. It can be understood that the unit power consumption parameter refers to the power consumed by a single logic unit in a unit of time, which can be estimated according to the type of the logic unit, the process node, the design library information, etc., or obtained through simulation, and the purpose is to quantify the energy consumption characteristics of each logic unit. The expected activity rate parameter refers to the frequency of activation or operation of the logic unit in a specific workload or time period, which can be set based on historical data, design specifications or user behavior patterns, and the purpose is to reflect the actual activity level of the logic unit. According to the set of logic resource quantities, the number of logic units in the virtual grid unit is determined, which can be determined according to the physical location information of each logic unit contained in the set of logic resource quantities, to determine the virtual grid unit to which it belongs, and count the number of logic units in each virtual grid unit to obtain the number of logic units in the virtual grid unit.

[0113] Then, according to the unit power consumption parameter, the expected activity rate parameter and the number of logic units in the virtual grid unit, the estimated dynamic power consumption contribution of the virtual grid unit is calculated. The estimated dynamic power consumption contribution can be obtained by multiplying and accumulating the unit power consumption parameter, the expected activity rate parameter of each logic unit and the number of logic units in the virtual grid unit, and the purpose is to provide a power consumption evaluation index that is closer to the actual running situation. According to the estimated dynamic power consumption contribution, the weighted logic resource density of the virtual grid unit is calculated. Exemplarily, the weighted logic resource density can be calculated by associating the estimated dynamic power consumption contribution of the virtual grid unit with the area of the virtual grid unit or a preset weight, so as to integrate the power consumption information into the evaluation of the resource density, so that the density index can reflect the potential power consumption hotspot area. According to the weighted logic resource density of the plurality of virtual grid units, the Gini coefficient of the target logic resource distribution is calculated. The Gini coefficient can more accurately reflect the imbalance degree of the distribution of logic resources (especially high-power or high-activity rate resources) in the physical area of the electronic device.

[0114] The embodiment introduces the unit power consumption parameter and the expected activity rate parameter of the logic unit, and calculates the estimated dynamic power consumption contribution and the weighted logic resource density of the virtual grid unit based on these parameters, so that the calculation of the Gini coefficient is no longer dependent only on the number of logic units, but also takes into account the actual energy consumption characteristics and activity level of the logic unit. This weighted processing makes the calculated Gini coefficient more effectively reveal the potential power consumption hotspots or areas of excessive concentration of resources in the physical area of the electronic device, which may be ignored when only considering the number.

[0115] To make the technical solution clearer, specific examples are used for explanation below. Assume that an electronic device chip is divided into multiple virtual grid units, such as virtual grid units A, B, and C. First, the unit power consumption parameter and the expected activity rate parameter of each logical unit are obtained. For example, the unit power consumption of logical unit type a is 0.5 mW, and the expected activity rate is 80%; the unit power consumption of logical unit type b is 0.2 mW, and the expected activity rate is 50%.

[0116] Next, according to the logical resource quantity set, the number of logical units in each virtual grid unit is determined. For example, virtual grid unit A contains 10 logical units of type a and 5 logical units of type b; virtual grid unit B contains 15 logical units of type b; and virtual grid unit C contains 5 logical units of type a and 10 logical units of type b. Then, according to the above parameters, the estimated dynamic power consumption contribution of each virtual grid unit is calculated. For virtual grid unit A: (10*0.5 mW*80%) + (5*0.2 mW*50%) = 4 mW + 0.5 mW = 4.5 mW. For virtual grid unit B: (15*0.2 mW*50%) = 1.5 mW. For virtual grid unit C: (5*0.5 mW*80%) + (10*0.2 mW*50%) = 2 mW + 1 mW = 3 mW.

[0117] Subsequently, according to the estimated dynamic power consumption contribution, the weighted logical resource density of each virtual grid unit is calculated. Assuming that the areas of all virtual grid units are the same, the weighted logical resource density is directly proportional to the estimated dynamic power consumption contribution. Finally, according to the weighted logical resource densities (4.5 mW, 1.5 mW, 3 mW) of virtual grid units A, B, and C, the Gini coefficient of the target logical resource distribution is calculated. By sorting and cumulatively summing these weighted density values, a Gini coefficient reflecting the unevenness of power consumption distribution can be obtained. For example, if only the number of logical units is considered, virtual grid unit A has 15, B has 15, and C has 15, and the Gini coefficient may show an even distribution. However, through the weighted processing, the power consumption contribution of virtual grid unit A is significantly higher than that of B and C, which will make the weighted Gini coefficient accurately reveal that virtual grid unit A is a potential power consumption hotspot area, thereby guiding the designer to prioritize optimization of this area.

[0118] By the technical solution, the embodiment can overcome the limitation of the conventional method that only relies on number statistics when evaluating the uniformity of logical resource distribution. By including the power consumption and activity rate information of the logical units in the calculation of the Gini coefficient, local power consumption hotspots or regions with uneven resource utilization in the physical region of the electronic device can be more accurately identified. This weighted evaluation method makes the generated Gini coefficient more truly reflect potential problems in the design, thereby providing more accurate and effective guidance for subsequent physical design optimization (such as layout and routing adjustment, power consumption management strategy formulation, etc.), which helps to improve the overall performance, reliability and energy efficiency of the electronic device.

[0119] In some embodiments, in step S104, generating the target optimization strategy according to the Gini coefficient and the preset coefficient threshold value can include but is not limited to the following steps:

[0120] Step S201, when the Gini coefficient is greater than the preset coefficient threshold value, identifying a target virtual grid in the physical region of the electronic device, where the logical resource density is greater than a preset local density;

[0121] Step S202, obtaining logical module information to which the logical units in the target virtual grid belong;

[0122] Step S203, extracting first design constraint information corresponding to the logical module according to the logical module information;

[0123] Step S204, generating a target optimization strategy according to the logical module information and the first design constraint information.

[0124] In some embodiments, when the Gini coefficient is greater than a preset coefficient threshold, it indicates that there is a significant imbalance in the distribution of logical resources inside the electronic device, which can lead to excessive concentration of resources in local areas, thereby causing problems such as power consumption hotspots, timing bottlenecks, or wiring congestion. The target virtual grid with a logical resource density greater than a preset local density in the physical area of the electronic device can be identified. The target virtual grid refers to those areas with abnormally high logical resource density among the multiple virtual grid units obtained after the chip is regionally divided. The preset local density can be an empirical value, or an average density or a certain percentile density obtained through statistical analysis. Identifying these target virtual grids can focus the optimization focus on areas where local hotspots or congestion actually exist. Then, the logical module information to which the logical units in the target virtual grid belong is obtained. The logical module information refers to the functional modules to which these logical units belong at the design level, such as CPU cores, DSP modules, memory controllers, etc. By obtaining the logical module information, the composition of the high-density area can be understood from the functional level. Then, according to the logical module information, the first design constraint information corresponding to the logical module is extracted, which can include but is not limited to timing constraints (such as critical path delay requirements), power consumption constraints (such as maximum power consumption budget), area constraints, and specific layout and routing rules, etc. Finally, according to the logical module information and the first design constraint information, a target optimization strategy is generated, which aims to specifically solve the problem of the identified high-density area, such as by adjusting the layout of the logical unit, optimizing the routing path, or splitting and recombining the logical module, etc., in order to improve the balance of the distribution of logical resources, so that the generated target optimization strategy has high specificity and operability, thereby effectively solving the potential problems caused by the imbalance of resource distribution.

[0125] To make the technical solution clearer, specific examples are used for explanation below. Assume that when performing placement and routing analysis on an electronic device (for example, a field programmable gate array (FPGA) chip), the Gini coefficient of the logical resource distribution is calculated to be 0.85, and the preset coefficient threshold is 0.7. Since 0.85 is greater than 0.7, it is determined that the logical resource distribution is significantly unbalanced. At this time, it can be further identified that in the chip physical area, for example, a plurality of virtual grid units located in the central area of the chip, the logical resource density is much higher than the preset local density. These target virtual grid units may concentrate a large number of computing logic units and storage units. Subsequently, the logical module information to which the logical units in these high-density virtual grid units belong can be obtained, for example, it is identified that they mainly belong to a high-performance digital signal processing (DSP) module and a complex control logic module. At the same time, the first design constraint information corresponding to these DSP modules and control logic modules is extracted, for example, the DSP module may have strict timing constraints and power consumption budget, and the control logic module may be sensitive to routing congestion. Based on the logical module information and the first design constraint information, a target optimization strategy is generated. The strategy may include suggestions to disperse certain parallel processing units in the DSP module or adjust the routing priority of certain critical paths in the control logic module to alleviate local congestion and power consumption hotspots while ensuring that the original timing and power consumption constraints are met.

[0126] Through the above technical solution, the embodiment can provide a more accurate and effective optimization strategy generation mechanism for the actual situation of unbalanced logical resource distribution in an electronic device. Specifically, by identifying local high-density areas and associating their logical modules and design constraints, the generated optimization strategy can avoid blind adjustment and ensure the relevance and feasibility of the optimization measures. This helps to effectively alleviate local power consumption hotspots, timing bottlenecks, and other problems while maintaining or improving overall performance, thereby improving the efficiency and quality of electronic device design.

[0127] In some embodiments, in step S204, generating a target optimization strategy according to the logical module information and the first design constraint information can include but is not limited to the following steps:

[0128] Step S301, generating an initial optimization strategy containing logical module information and first design constraint information;

[0129] Step S302, predicting the distribution of logical units in the logical module in the electronic device physical area according to the initial optimization strategy, to obtain a predicted logical resource distribution;

[0130] Step S303, identifying a critical timing path according to the predicted logical resource distribution;

[0131] Step S304, calculate the delay variation of the critical timing path;

[0132] Step S305, according to the delay variation, evaluate the timing performance influence degree of the initial optimization strategy, the timing performance influence degree is used to indicate whether there is a new global performance bottleneck;

[0133] Step S306, according to the predicted logic resource distribution, update the weighted logic resource density of the target virtual grid;

[0134] Step S307, according to the weighted logic resource density, evaluate the power consumption distribution influence degree of the initial optimization strategy, the power consumption distribution influence degree is used to indicate whether there is a new local power consumption hotspot;

[0135] Step S308, according to the timing performance influence degree and the power consumption distribution influence degree, adjust the initial optimization strategy to obtain the target optimization strategy.

[0136] In some embodiments, since it is possible that the potential influence on the overall performance (such as timing performance) and power consumption distribution of the electronic device cannot be comprehensively evaluated based on only the logic module information and the first design constraint information, thereby possibly introducing a new global performance bottleneck or a local power consumption hotspot, affecting the stability and reliability of the electronic device. Therefore, an initial optimization strategy containing the logic module information and the first design constraint information can be generated first, and according to the initial optimization strategy, the distribution of the logic cells in the logic module in the physical area of the electronic device is predicted to obtain a predicted logic resource distribution. Illustratively, the simulation tool or the layout and routing tool can be used to virtually place or allocate the logic cells based on the initial optimization strategy, so as to obtain the expected position and density distribution of these logic cells in the physical area of the chip. The predicted logic resource distribution reflects the potential physical layout state after the implementation of the initial optimization strategy.

[0137] Then, according to the predicted logic resource distribution, the critical timing path is identified, and the delay variation of the critical timing path is calculated. Illustratively, the timing analysis tool can identify the signal transmission path that has the greatest impact on the overall running speed of the electronic device as the critical timing path. These paths usually have the longest delay or the smallest timing margin, and the difference in signal transmission delay of the critical timing path before and after the application of the initial optimization strategy is quantified to obtain the delay variation. According to the delay variation, the timing performance influence degree of the initial optimization strategy is evaluated, wherein the timing performance influence degree is used to indicate whether there is a new global performance bottleneck. The timing performance influence degree can be a quantitative index, such as the percentage of the maximum clock frequency drop or the increase in the critical path delay. When the influence degree exceeds the preset threshold, it indicates that the initial optimization strategy can cause a new global performance bottleneck, i.e., the overall running speed of the electronic device is limited.

[0138] According to the predicted logical resource distribution, the weighted logical resource density of the target virtual grid is updated to reflect the power consumption contribution of the logical unit after the redistribution. According to the weighted logical resource density, the power distribution impact degree of the initial optimization strategy is evaluated, where the power distribution impact degree is used to indicate whether there is a new local power hotspot. The power distribution impact degree can be a hotspot temperature rise value or a power density peak value. When the impact degree exceeds a preset threshold, it indicates that the initial optimization strategy may cause a new local power hotspot, i.e., the temperature of the local region of the chip is too high, which may affect the reliability of the device.

[0139] Finally, according to the timing performance impact degree and the power distribution impact degree, the initial optimization strategy is adjusted to obtain a target optimization strategy. The timing performance impact degree and the power distribution impact degree can be used as feedback to iteratively correct the initial optimization strategy, so as to avoid introducing new timing or power problems while optimizing the logical resource distribution. The adjustment can include modifying the placement position of the logical unit, adjusting the routing strategy, or modifying the design constraints, etc. The embodiment enables the initial optimization strategy to be adjusted in time, thereby avoiding the introduction of new global performance bottlenecks or local power hotspots while solving the problem of uneven distribution of logical resources, ensuring the comprehensiveness and robustness of the optimization strategy.

[0140] Through the above technical solutions, the embodiment can generate a more comprehensive and optimized target optimization strategy. The strategy not only effectively solves the problem of uneven distribution of logical resources in electronic devices, but more importantly, through the pre-evaluation and feedback adjustment of timing performance and power distribution, it can significantly reduce the risk of introducing new global performance bottlenecks and local power hotspots due to the optimization of logical resource distribution. As a result, the overall performance, running stability and reliability of the electronic device are improved, and the high cost and time consumption caused by discovering and repairing these problems in the later design stage are avoided.

[0141] In some embodiments, in step S308, adjusting the initial optimization strategy according to the timing performance impact degree and the power distribution impact degree to obtain a target optimization strategy can include but is not limited to the following steps:

[0142] Step S401, a plurality of candidate adjustment schemes are generated, and the candidate adjustment schemes are used to modify the initial optimization strategy;

[0143] Step S402, selecting one candidate adjustment scheme from the plurality of candidate adjustment schemes as a to-be-compared adjustment scheme;

[0144] Step S403, updating the timing performance impact degree and the power distribution impact degree corresponding to the to-be-compared adjustment scheme;

[0145] In step S404, a scheme evaluation result is obtained by performing scheme evaluation on the to-be-compared adjustment scheme according to the updated timing performance influence degree and the power consumption distribution influence degree.

[0146] In step S405, a target adjustment scheme is obtained by comparing the scheme evaluation results corresponding to the plurality of candidate adjustment schemes according to the optimization target weight.

[0147] In step S406, the initial optimization strategy is adjusted according to the target adjustment scheme to obtain a target optimization strategy.

[0148] In some embodiments, a plurality of candidate adjustment schemes can be generated first, and a series of candidate schemes that can modify the initial optimization strategy are generated through preset rules, algorithms or heuristic methods. The candidate adjustment scheme is used to modify the initial optimization strategy. These candidate adjustment schemes can be fine tuning or major changes to the design parameters such as layout position, routing path, cell size, drive strength, etc. of the logic module, aiming to explore different optimization paths. One candidate adjustment scheme is selected from the plurality of candidate adjustment schemes as the to-be-compared adjustment scheme, which can be selected for detailed analysis in the evaluation process, and the selection can be in order, randomly or based on a certain priority strategy. The timing performance influence degree and the power consumption distribution influence degree corresponding to the to-be-compared adjustment scheme are updated, and prediction and analysis are performed again for the selected to-be-compared adjustment scheme to obtain the latest influence evaluation of the overall timing performance and local power consumption distribution of the electronic device after implementation of the scheme. This usually involves re-performing layout and routing prediction, timing analysis and power consumption estimation.

[0149] Then, scheme evaluation is performed on the to-be-compared adjustment scheme according to the updated timing performance influence degree and the power consumption distribution influence degree to obtain a scheme evaluation result. Exemplarily, the data in two dimensions can be converted into a unified and quantifiable evaluation result through a certain comprehensive evaluation model or function. For example, a weighted sum, a multi-objective optimization function or a Pareto frontier analysis method can be used to reflect the overall advantages and disadvantages of the scheme. Then, a target adjustment scheme is obtained by comparing the scheme evaluation results corresponding to the plurality of candidate adjustment schemes according to the optimization target weight. When there are multiple optimization targets (such as timing, power consumption, area, etc.), the importance of each target can be quantified through preset weights. For example, if timing is the main target, the evaluation result related to timing has a higher weight. Finally, the initial optimization strategy is adjusted according to the target adjustment scheme to obtain a target optimization strategy, so that a better balance is achieved in the global performance.

[0150] By the technical solution, the embodiment can provide a more fine and intelligent optimization strategy adjustment mechanism. The mechanism generates and evaluates multiple candidate adjustment schemes systematically, and comprehensively compares them in combination with optimization target weights, effectively avoiding local optimal or suboptimal solutions that may be caused by traditional single adjustment methods. Thus, the final generated target optimization strategy can achieve a better balance between timing performance and power consumption distribution, significantly improving the overall quality and performance of electronic device design. Especially in complex design scenarios, it can more effectively solve timing bottlenecks and local power consumption hotspots, thereby improving the success rate and efficiency of design.

[0151] In some embodiments, in step S401, generating multiple candidate adjustment schemes can include but is not limited to the following steps:

[0152] Obtaining design stage information, field programmable gate array architecture information, and second design constraint information of the electronic device;

[0153] Selecting a rule from a preset rule set as an initial optimization rule;

[0154] Adjusting the initial optimization rule according to the design stage information, the field programmable gate array architecture information, and the second design constraint information to obtain a target optimization rule, the target optimization rule being used for parameterized modification of the initial optimization strategy;

[0155] Generating multiple candidate adjustment schemes according to the target optimization rule.

[0156] In some embodiments, since the candidate adjustment schemes are randomly generated, they lack pertinence or basis, which may lead to generation of a large number of inefficient or irrelevant schemes, thereby increasing the computational overhead of subsequent evaluation and reducing the efficiency of finding the optimal adjustment scheme. Therefore, the design stage information, the field programmable gate array architecture information, and the second design constraint information of the electronic device can be obtained first. The design stage information can be the stage in which the current design is located, such as the logic synthesis stage, the layout stage, the routing stage, or the post-layout routing stage, etc. Different design stages have different flexibility and influence range for optimization strategy adjustment. The field programmable gate array architecture information can be the internal structure, resource type (such as lookup table, flip-flop, DSP block, RAM block, etc.), interconnection resource, and timing characteristics of a specific field programmable gate array (FPGA) used. These architecture information is crucial for generating effective optimization rules, because the optimization scheme needs to be matched with the target hardware architecture. The second design constraint information can include but is not limited to area constraints, power consumption constraints, timing constraints, placement constraints or routing constraints of specific modules, etc., which are key factors guiding the optimization process.

[0157] Then, an initial optimization rule is selected from a pre-defined rule set, which can be a series of optimization rules or heuristic algorithms that aim to solve common problems in electronic device design, such as reducing wire congestion, optimizing timing, reducing power consumption, or balancing resource utilization. The initial optimization rule is a basic rule selected from the pre-defined rule set, and its selection can be based on the main problem or optimization goal currently facing the design.

[0158] According to the design stage information, field programmable gate array architecture information, and second design constraint information, the initial optimization rule is adjusted to obtain a target optimization rule, aiming to make the rule more targeted and effective. For example, in the layout stage, the rule can be adjusted to focus more on physical location optimization; for a specific FPGA architecture, the rule can be adjusted to utilize its unique resources or interconnection structure; and the second design constraint information can guide the adjustment direction of the rule to meet specific performance, power consumption, or area requirements. Thus, the target optimization rule is a parameterized modification of the initial optimization rule, which means that certain parameters or behaviors of the rule can be dynamically adjusted according to the input information, making it adaptable to different design scenarios and optimization goals. The target optimization rule is used to parameterize and modify the initial optimization strategy.

[0159] Finally, a plurality of candidate adjustment schemes are generated according to the target optimization rule. These candidate adjustment schemes are specific modification suggestions for the initial optimization strategy, such as repositioning of logic cells, redivision of logic modules, optimization adjustment of timing paths, or dispersion of power consumption hotspots, etc. In this way, the generated candidate adjustment schemes are more relevant and effective, providing high-quality input for subsequent scheme evaluation. The target optimization rule fully considers the specific circumstances and limitations of the current design, enabling it to guide the generation of candidate adjustment schemes that are more relevant, more effective, and more likely to bring positive effects. This context-based rule adjustment mechanism ensures that the generated candidate schemes can better solve the specific problems faced by the current design, avoiding the generation of a large number of unrealistic or inefficient schemes, thereby significantly improving the efficiency and success rate of the entire optimization process.

[0160] Through the above technical solutions, the embodiment can significantly improve the efficiency and quality of generating candidate adjustment schemes. Since the generation process of candidate schemes fully considers the design stage, hardware architecture, and specific design constraints, the generated schemes are more targeted and feasible, thereby reducing the number of invalid or inefficient schemes. This not only reduces the computational complexity and time cost of subsequent scheme evaluation, but also improves the probability of finding the optimal or near-optimal adjustment scheme. In addition, the scheme enables the optimization process to better adapt to the needs of different design scenarios and hardware platforms, improving the flexibility and robustness of the overall optimization strategy.

[0161] In some embodiments, in step S405, according to the optimization target weight, comparing the scheme evaluation results corresponding to the plurality of candidate adjustment schemes to obtain the target adjustment scheme can include but is not limited to the following steps:

[0162] Step S501, obtaining a chip running environment parameter range, the chip running environment parameter range including a temperature range, a voltage range and a process deviation range;

[0163] Step S502, according to the optimization target weight, comparing the scheme evaluation results corresponding to the plurality of candidate adjustment schemes, and taking the candidate adjustment scheme with the best evaluation as the initial adjustment scheme;

[0164] Step S503, generating a plurality of environment change scenarios according to the chip running environment parameter range;

[0165] Step S504, re-evaluating the timing performance influence degree and the power consumption distribution influence degree corresponding to the initial adjustment scheme under each environment change scenario to obtain a re-evaluation result;

[0166] Step S505, calculating the performance fluctuation index of the initial adjustment scheme according to the re-evaluation result corresponding to each environment change scenario;

[0167] Step S506, if the performance fluctuation index is less than a preset stability threshold, taking the initial adjustment scheme as the target adjustment scheme.

[0168] In some embodiments, since the selected optimization strategy can only perform best under nominal or ideal working conditions, the complex and changeable environmental factors that the electronic device may face in actual operation, such as temperature, voltage fluctuation and manufacturing process deviation, are not fully considered. This limitation can lead to insufficient performance stability of the generated optimization strategy in actual application, and even cause new performance bottlenecks or reliability problems under certain extreme environments. Therefore, the chip running environment parameter range can be obtained first, wherein the chip running environment parameter range includes a temperature range, a voltage range and a process deviation range. The temperature range refers to the minimum and maximum environmental temperatures that the electronic device can withstand during normal operation, for example, from -40°C to 125°C; the voltage range refers to the allowable fluctuation range of the supply voltage, for example, from 0.9V to 1.1V of the nominal voltage; and the process deviation range reflects the possible parameter changes in the semiconductor manufacturing process, such as fast angle and slow angle. The comprehensive consideration of these parameters is crucial to ensure the stable operation of the electronic device in various actual application scenarios.

[0169] Then, according to the optimization target weight, the scheme evaluation results corresponding to multiple candidate adjustment schemes are compared, and the candidate adjustment scheme with the best evaluation result is taken as the initial adjustment scheme. In order to comprehensively evaluate the robustness of the initial adjustment scheme, multiple environment variation scenarios can be generated according to the chip running environment parameter range. These scenarios represent various extreme or atypical combination conditions that the chip may encounter in actual operation. For example, multiple combination scenarios such as high temperature, high pressure, and slow process, low temperature, low pressure, and fast process can be generated, or more detailed variation combinations can be generated through statistical sampling methods. Under each environment variation scenario, the timing performance influence degree and the power distribution influence degree corresponding to the initial adjustment scheme are re-evaluated to obtain re-evaluation results. This re-evaluation process is similar to the process of generating the initial evaluation results, but the input conditions are specific environment variation scenario parameters. The purpose of re-evaluation is to obtain the timing performance influence degree and the power distribution influence degree of the initial adjustment scheme under different environment conditions. In this way, a series of re-evaluation results can be obtained, each corresponding to a specific environment variation scenario.

[0170] According to the re-evaluation results corresponding to each environment variation scenario, the performance fluctuation index of the initial adjustment scheme is calculated. The performance fluctuation index is used to quantify the performance stability of the initial adjustment scheme under different environment variation scenarios. For example, the index can be the difference between the maximum and minimum values, the standard deviation, or the maximum deviation relative to the nominal value of the evaluated performance parameter (such as the worst timing margin, the maximum local power density) under all environment variation scenarios. The smaller the index value, the more stable the performance of the scheme. If the performance fluctuation index is less than a preset stability threshold, it is considered that the initial adjustment scheme has sufficient robustness and stability under various environment variations, and the initial adjustment scheme is taken as the target adjustment scheme. Conversely, if the performance fluctuation index exceeds the threshold, it indicates that the initial adjustment scheme is not stable enough and may need to be reconsidered or further adjusted. This embodiment ensures that the selected optimization strategy not only performs well under ideal conditions, but also maintains stable performance and reliability in actual complex and variable working environments.

[0171] Through the above technical solutions, the embodiment can effectively solve the problems of poor environmental adaptability and insufficient robustness that may exist in traditional optimization strategies. By strictly evaluating the performance fluctuation of the initial optimization strategy under multiple environment variation scenarios and introducing a stability threshold for screening, it can be ensured that the final generated target optimization strategy can maintain the expected timing performance and power distribution stability when facing uncertain factors such as temperature, voltage, and process deviation during actual chip operation. This significantly improves the reliability and practicality of electronic device design, reduces the risk of performance degradation or hot spot generation due to environmental changes, and thus provides a solid guarantee for the long-term stable operation of electronic devices.

[0172] In some embodiments, in step S503, generating a plurality of environmental variation scenarios according to the chip operating environment parameter range can include, but is not limited to, the following steps:

[0173] Obtaining statistical correlation information between the temperature range, the voltage range, and the process deviation range;

[0174] Determining a sampling strategy according to the chip operating environment parameter range and the statistical correlation information;

[0175] Sampling according to the sampling strategy to obtain a plurality of environmental variation scenarios.

[0176] In some embodiments, if the generation method of the environmental variation scenario fails to fully consider the internal statistical correlation between different environmental parameters (such as temperature, voltage, and process deviation), it can lead to the generated scenario being unable to truly reflect the extreme or typical combination that the chip may encounter in actual operation, thereby affecting the accuracy and reliability of the performance fluctuation index evaluation, and making the final target adjustment scheme unable to maintain optimal performance under all actual operating conditions. Therefore, statistical correlation information between the temperature range, the voltage range, and the process deviation range can be obtained first to identify the statistical correlation between these parameters. For example, in some semiconductor processes, higher temperature can cause the leakage current of the transistor to increase, thereby affecting the voltage drop, or a specific process deviation can be associated with voltage sensitivity. These statistical correlation information can be represented as a covariance matrix, a correlation coefficient matrix, or a more complex joint probability distribution model. The purpose is to ensure that the subsequently generated environmental variation scenarios can more realistically simulate the actual operation of the chip, where these parameters are not independent but are influenced by each other in a complex situation.

[0177] Then, according to the chip operating environment parameter range and the statistical correlation information, a sampling strategy is determined, and an effective method can be designed to select or generate a series of specific environmental parameter combinations. For example, Monte Carlo sampling, Latin Hypercube Sampling, or Importance Sampling can be used. When determining the sampling strategy, the statistical correlation information will be fully utilized. For example, if temperature and voltage are negatively correlated, the sampling strategy will tend to generate high-temperature low-voltage or low-temperature high-voltage combinations to more effectively cover potential performance bottleneck areas to ensure that the generated environmental variation scenarios can cover the parameter space and highlight key, representative, or extreme situations, thereby improving the efficiency and accuracy of the evaluation.

[0178] According to the sampling strategy, sampling is performed to obtain multiple environmental variation scenarios. Exemplarily, a series of specific temperature, voltage and process deviation value combinations can be randomly or systematically extracted from the joint distribution of the chip running environment parameters. Each combination constitutes an independent environmental variation scenario. For example, if the sampling strategy is based on the Monte Carlo method and considers parameter correlation, a large number of random parameter combinations that comply with the correlation law will be generated. These scenarios can include typical working points, extreme working points and various cases therebetween, providing diversified and representative test conditions for subsequent performance evaluation.

[0179] Through the above technical solutions, the statistical correlation between temperature, voltage and process deviation is fully considered, and an optimized sampling strategy is adopted, so that the generated scenarios are more representative and realistic. This significantly improves the accuracy of the evaluation of the timing performance influence degree and the power consumption distribution influence degree of the initial adjustment scheme, so that the calculated performance fluctuation index can more realistically reflect the robustness of the scheme under complex environments. As a result, the target adjustment scheme that can maintain stable performance under various running conditions can be more reliably identified, effectively reducing the risk of performance degradation or power consumption hotspots of the chip after actual deployment, and improving the reliability and stability of the design scheme.

[0180] The beneficial effects of implementing the embodiments of the present application include that the embodiments of the present application first acquire physical location information of a logical unit in an electronic device, then calculate a logical resource quantity set according to the physical location information, and further calculate a Gini coefficient of a target logical resource distribution according to the logical resource quantity set, and finally generate a target optimization strategy according to the Gini coefficient and a preset coefficient threshold, so as to realize electronic device data analysis in combination with logical resource quantity and distribution, thereby improving analysis accuracy and resource utilization.

[0181] As shown in Figure 2 The embodiments of the present application further provide an electronic device data analysis system, which comprises:

[0182] An information acquisition module 601 is configured to acquire physical location information of a logical unit in an electronic device.

[0183] A logical resource statistics module 602 is configured to calculate a logical resource quantity set according to the physical location information.

[0184] A coefficient calculation module 603 is configured to calculate a Gini coefficient of a target logical resource distribution according to the logical resource quantity set.

[0185] A strategy generation module 604 is configured to generate a target optimization strategy according to the Gini coefficient and a preset coefficient threshold.

[0186] The contents in the method embodiments are applicable to the system embodiments, the system embodiments specifically implement the same functions as the method embodiments, and achieve the same beneficial effects as the method embodiments.

[0187] The embodiments described in the embodiments of the present application are for more clearly illustrating the technical solutions of the embodiments of the present application, and do not constitute a limitation on the technical solutions provided by the embodiments of the present application. Those skilled in the art can know that, with the evolution of technology and the appearance of new application scenarios, the technical solutions provided by the embodiments of the present application are also applicable to similar technical problems.

Claims

1. A method for analyzing data from electronic devices, characterized in that, Includes the following steps: Obtain the physical location information of logic units in electronic devices; Based on the physical location information, calculate the set of logical resource quantities; Calculate the Gini coefficient of the target logical resource distribution based on the set of logical resource quantities. Based on the Gini coefficient and the preset coefficient threshold, a target optimization strategy is generated; The step of calculating the Gini coefficient of the target logical resource distribution based on the set of logical resource quantities includes: Obtain the unit power consumption parameter and expected activity rate parameter of the logic unit; Based on the set of logical resource quantities, determine the number of logical units in the virtual grid cell; The estimated dynamic power consumption contribution of the virtual mesh cell is calculated based on the unit power consumption parameter, the expected activity rate parameter, and the number of logic cells in the virtual mesh cell. Based on the estimated dynamic power consumption contribution, the weighted logical resource density of the virtual mesh cell is calculated; The Gini coefficient of the target logical resource distribution is calculated based on the weighted logical resource density of the multiple virtual grid cells.

2. The method according to claim 1, characterized in that, The step of calculating the set of logical resource quantities based on the physical location information includes: Obtain the physical boundary information of chips in electronic devices; Calculate the chip height and chip width based on the chip's physical boundary information; Calculate the virtual grid cell height and virtual grid cell width based on the preset grid number, the chip height, and the chip width; The chip is divided into regions based on the height and width of the virtual mesh unit to obtain multiple virtual mesh units; Based on the physical location information, calculate the index corresponding to each logical unit, and the index is used to point to the virtual grid unit to which the logical unit belongs; Calculate the number of logical resources corresponding to each virtual grid unit based on the indexes corresponding to multiple logical units; The sets of logical resource quantities are obtained by combining multiple logical resource quantities.

3. The method according to claim 1, characterized in that, The step of generating a target optimization strategy based on the Gini coefficient and a preset coefficient threshold includes: When the Gini coefficient is greater than the preset coefficient threshold, a target virtual mesh in the physical region of the electronic device with a logical resource density greater than a preset local density is identified. Obtain the logical module information to which the logical unit within the target virtual mesh belongs; Based on the logic module information, extract the first design constraint information corresponding to the logic module; The target optimization strategy is generated based on the logical module information and the first design constraint information.

4. The method according to claim 3, characterized in that, The step of generating the target optimization strategy based on the logic module information and the first design constraint information includes: Generate an initial optimization strategy that includes the logical module information and the first design constraint information; Based on the initial optimization strategy, the distribution of logic units in the logic module within the physical area of ​​the electronic device is predicted to obtain the predicted logic resource distribution. Based on the predicted logical resource distribution, identify key time-series paths; Calculate the delay variation of the key timing path; Based on the delay change, the temporal performance impact of the initial optimization strategy is evaluated, and the temporal performance impact is used to indicate whether there is a new global performance bottleneck; Update the weighted logical resource density of the target virtual grid based on the predicted logical resource distribution; Based on the weighted logic resource density, the degree of influence of the power consumption distribution of the initial optimization strategy is evaluated, and the degree of influence of the power consumption distribution is used to indicate whether there are new local power consumption hotspots; Based on the impact of timing performance and the impact of power consumption distribution, the initial optimization strategy is adjusted to obtain the target optimization strategy.

5. The method according to claim 4, characterized in that, The step of adjusting the initial optimization strategy based on the degree of impact of timing performance and the degree of impact of power consumption distribution to obtain the target optimization strategy includes: Multiple candidate adjustment schemes are generated, and the candidate adjustment schemes are used to modify the initial optimization strategy; One candidate adjustment scheme is selected from the plurality of candidate adjustment schemes as the adjustment scheme to be compared; Update the timing performance impact and power consumption distribution impact of the proposed adjustment scheme; Based on the updated impact of timing performance and power consumption distribution, the proposed adjustment scheme is evaluated to obtain the evaluation results. Based on the optimization objective weights, the evaluation results of multiple candidate adjustment schemes are compared to obtain the objective adjustment scheme; Based on the target adjustment scheme, the initial optimization strategy is adjusted to obtain the target optimization strategy.

6. The method according to claim 5, characterized in that, The generation of multiple candidate adjustment schemes includes: Acquire design phase information, field-programmable gate array (FPGA) architecture information, and second design constraint information for electronic devices; Select one rule from the preset rule set as the initial optimization rule; Based on the design phase information, the field-programmable gate array architecture information, and the second design constraint information, the initial optimization rule is adjusted to obtain the target optimization rule, which is used to parametrically modify the initial optimization strategy. Based on the target optimization rules, the multiple candidate adjustment schemes are generated.

7. The method according to claim 5, characterized in that, The step of comparing the evaluation results of multiple candidate adjustment schemes based on the optimization target weight to obtain the target adjustment scheme includes: Obtain the range of chip operating environment parameters, which includes temperature range, voltage range, and process deviation range; Based on the optimization target weight, compare the evaluation results of multiple candidate adjustment schemes, and take the candidate adjustment scheme with the best evaluation as the initial adjustment scheme; Based on the range of chip operating environment parameters, multiple environmental change scenarios are generated; In each of the aforementioned environmental change scenarios, the impact of the initial adjustment scheme on timing performance and power consumption distribution is reassessed to obtain the reassessment results. Based on the reassessment results corresponding to each of the aforementioned environmental change scenarios, the performance fluctuation index of the initial adjustment scheme is calculated; If the performance fluctuation index is less than the preset stability threshold, then the initial adjustment scheme will be used as the target adjustment scheme.

8. The method according to claim 7, characterized in that, The process of generating multiple environmental change scenarios based on the chip's operating environment parameter range includes: Obtain statistical correlation information among the temperature range, the voltage range, and the process deviation range; The sampling strategy is determined based on the range of chip operating environment parameters and the statistical correlation information. According to the sampling strategy, sampling is performed to obtain the multiple environmental change scenarios.

9. An electronic device data analysis system, characterized in that, include: The information acquisition module is used to acquire the physical location information of logic units in electronic devices; The logical resource statistics module is used to calculate the set of logical resource quantities based on the physical location information. The coefficient calculation module is used to calculate the Gini coefficient of the target logical resource distribution based on the set of logical resource quantities. The strategy generation module is used to generate a target optimization strategy based on the Gini coefficient and a preset coefficient threshold. The step of calculating the Gini coefficient of the target logical resource distribution based on the set of logical resource quantities includes: Obtain the unit power consumption parameter and expected activity rate parameter of the logic unit; Based on the set of logical resource quantities, determine the number of logical units in the virtual grid cell; The estimated dynamic power consumption contribution of the virtual mesh cell is calculated based on the unit power consumption parameter, the expected activity rate parameter, and the number of logic cells in the virtual mesh cell. Based on the estimated dynamic power consumption contribution, the weighted logical resource density of the virtual mesh cell is calculated; The Gini coefficient of the target logical resource distribution is calculated based on the weighted logical resource density of the multiple virtual grid cells.

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