Step-down power regulation control method based on parameter-free structure

Abstract

The invention discloses a step-down power regulation control method based on a parameter-free structure, particularly relates to the field of power electronics and direct-current power supply control, and is used for solving the problems of unstable output and jitter interference caused by parameter mismatch under multiple working conditions of a step-down device. Low credible states are filtered in real time through a learning model according to cross direction difference and rate characteristics, then a duty factor is seamlessly output through table look-up logic, dynamic amplitude limiting is applied to switching frequency through back-end jitter estimation, and a self-adaptive curing duty reference is stably identified; the front-end sampling provides a high-resolution starting point, the middle-end discrimination and gating cooperation block distortion mistaken touch, the sign quantity guided state discrimination has natural immunity to noise, the rear-end amplitude limiting suppresses high-frequency jitter and performs cyclic refreshing by using a stable identifier to form a self-driven cycle without gain parameters, the electromagnetic interference peak value is reduced, and the convergence time is shortened; and meanwhile, the traditional parameter drift mismatch problem is avoided.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of power electronics and DC power supply control, and more particularly, to a step-down power regulation control method based on a parameter-free structure. BACKGROUND

[0002] DC step-down topology is commonly used in front-end photovoltaic grid-connected inverter, vehicle low-voltage bus and automation device power supply link. The output voltage is stabilized by modifying the duty cycle in real time relying on high-speed power switches, thereby reducing the drop caused by load mutation or bus drift. In recent years, sliding mode control is favored in engineering practice, which uses nonlinear strategy to resist element aging, temperature rise and external disturbance. First, the inductor current and the output voltage are linearly or nonlinearly combined to construct a "sliding surface". Then, a "switching law" is formulated, and positive and negative discrete control quantities are applied according to which side of the sliding surface the working trajectory is located, so as to guide the trajectory to quickly adhere to the surface and slide along the surface until the set voltage is reached. This process uses discrete switching to replace continuous regulation, and can obtain fast convergence and external disturbance suppression ability without relying on accurate models.

[0003] However, the sliding mode strategy triggers high-frequency jitter near the sliding surface. The discrete control quantities are repeatedly exchanged within a limited switching frequency, and the trajectory is forced to swing back and forth on both sides, resulting in a sharper current ripple than traditional regulation. The jitter increases the speed of voltage and current change per unit time at the switching node, which increases the magnetic field radiation and conducted noise, and introduces electromagnetic interference hazards. At the same time, the sampling signal contains quantization and sensor noise, and the jitter is equivalent to forcibly adding a high-gain amplification link in the loop, which increases the steady-state error. In engineering, the boundary layer saturation function is often used to expand the sliding surface into a finite width band, or upgrade to a high-order sliding surface and add an observer, in order to sacrifice the regulation degree of freedom to suppress jitter. However, the thickness of the boundary layer and the steady-state error are mutually restrained. If the gain is too large, the suppression will fail, and if the gain is too small, the response will be delayed. High-order sliding surfaces introduce more gain and phase configurations, and the parameter coupling increases sharply with the order, so the tuning difficulty and on-site maintenance cost increase simultaneously. The elements continue to drift due to temperature rise and aging, and the off-line tuning gradually mismatches, and the real-time model is also lacking, which hinders parameter reconfiguration. The step-down loop is prone to response delay, ripple rebound and even instability when the load jumps. High-frequency jitter and multi-parameter coupling amplify each other, which has become the most prominent technical obstacle in the pursuit of steady-state accuracy, robustness and electromagnetic compatibility of step-down power regulation.

[0004] To solve the above problems, a technical solution is provided. SUMMARY

[0005] To overcome the above-mentioned defects of the prior art, embodiments of the present application provide a step-down power regulation control method based on a parameter-free structure, which uses symbol accumulation to capture the deviation trend, cross direction difference and rate characteristics to filter low-confidence states in real time through a learning model, and then seamlessly outputs a duty cycle factor using lookup table logic, with a back-end jitter estimation imposing dynamic amplitude limiting on switching frequency to stabilize the identification and adaptively solidify the duty cycle reference; each loop is positively closed, with high-resolution starting points provided by front-end sampling, distortion and false triggering blocked by the cooperation of discrimination and gating, state discrimination guided by symbol quantity naturally immune to noise, back-end amplitude limiting suppressing high-frequency jitter and using a stable identification cycle to refresh, forming a gain-free parameter self-driven cycle to solve the problems raised in the background art.

[0006] To achieve the above object, the present application provides the following technical solutions: S1: at the beginning of each control cycle, collect the current input voltage, output voltage and inductor current, and immediately calculate the instantaneous symbol of the output voltage deviation, write it into the sliding window in time sequence to form a symbol accumulation vector; S2: generate a cross-determination result based on the direction difference between the symbol accumulation vector and the zero vector, and simultaneously count the frequency of symbol flipping within a unit time to output a polarity rate identifier, which together describe the state direction and change rate; S3: use the current change quantity and voltage drift quantity to construct state discrimination parameters, and obtain a confidence compression coefficient through a machine learning model; if the cross-determination result and the confidence compression coefficient together satisfy a preset condition, combine the polarity rate identifier and the cross-determination result into a joint input and send it to a lookup table logic; S4: the lookup table logic receives the joint input and maps a new duty cycle factor according to its state combination to drive the power switch to complete step-down switching; S5: after the power switch is actuated, re-collect the output voltage, update the sliding window and calculate the difference between the new and old windows to obtain a jitter estimation value, which is used to immediately constrain the switching frequency of the duty cycle factor to suppress high-frequency jitter for continuous accumulation; S6: when the jitter estimation value is lower than a threshold and the symbol accumulation vector converges, register the current duty cycle factor as a candidate reference and mark a stable state, and if either condition is not met, jump back to S1 for the next round of collection and determination.

[0007] In a preferred embodiment, step S1 includes the following contents: At the beginning of each control cycle, the input voltage value, output voltage value and inductor current value of the step-down circuit are synchronously collected, the output voltage deviation is calculated by subtracting a preset target voltage value from the output voltage value, the instantaneous symbol is generated according to the positive and negative nature of the output voltage deviation, and the instantaneous symbol is written into a fixed-length sliding window in time sequence to generate a symbol accumulation vector.

[0008] In a preferred embodiment, step S1 further includes the following: A positive sign indicates that the output voltage is higher than the target voltage; a negative sign indicates that the output voltage is lower than the target voltage; and a zero sign indicates that the output voltage is equal to the target voltage.

[0009] In a preferred embodiment, step S2 includes the following: A positive cross-judgment result indicates that the overall output voltage is higher than the target voltage value; a negative cross-judgment result indicates that the overall output voltage is lower than the target voltage value; and a zero cross-judgment result indicates that the overall output voltage is consistent with the target voltage value. The number of symbol flips is obtained by counting the number of changes of adjacent instantaneous symbols within the sliding window. The symbol flip frequency is generated by normalizing the number of symbol flips by dividing the number of symbol flips by the length of the sliding window. The polarity rate identifier is generated by comparing the symbol flip frequency with a preset threshold. The cross-judgment result and the polarity rate identifier are combined into a joint feature pair.

[0010] In a preferred embodiment, step S3 includes the following: The state discrimination parameters include the state bounce intensity index and the stationary shift index; The state bounce strength index generates the symbol flip frequency by the number of times the positive and negative polarities of adjacent instantaneous symbols alternate in the symbol accumulation vector. The symbol flip frequency is generated by multiplying the absolute value of the change in inductor current value corresponding to each flip, accumulating the results, and then normalizing by the sliding window length and the maximum absolute value of the change in inductor current value. The stationary drift index is generated by fitting the local linear drift rate through a sliding window of the output voltage value, calculating the difference between the mean output voltage value and the target voltage value to obtain the mean deviation magnitude, and then normalizing by multiplying the local linear drift rate by the mean deviation magnitude and dividing by the product of the maximum drift rate and the maximum mean deviation magnitude.

[0011] In a preferred embodiment, step S3 further includes the following: The confidence compression coefficient is calculated using the state bounce strength index and the stationary offset index through a support vector machine model based on a linear kernel function. The support vector machine model optimizes the classification decision function using an offline training dataset. If the absolute value of the cross-decision result is positive one and the confidence compression coefficient is greater than a preset threshold, the cross-decision result and the polarity rate label are combined as a joint input and passed to the lookup table logic. Otherwise, the existing duty cycle is maintained and the delayed update state is marked.

[0012] In a preferred embodiment, step S4 further includes the following: The combined input includes the cross-determination result and the polarity rate identifier. A new duty cycle factor is generated by mapping the combination of the cross-determination result and the polarity rate identifier using a preset lookup table. The new duty cycle factor is then used to generate a pulse signal through a pulse width modulation controller, which drives the power switch to perform opening and closing actions to complete the step-down switching.

[0013] In a preferred embodiment, step S4 further includes the following: The lookup table uses the crossover result as the row index and the polarity rate indicator as the column index. When the crossover result is negative one and the polarity rate indicator is zero, the current duty cycle is increased by the low oscillation increment adjustment value to generate a new duty cycle. When the crossover result is positive one and the polarity rate indicator is zero, the current duty cycle is decreased by the low oscillation decrement adjustment value to generate a new duty cycle. When the crossover result is negative one and the polarity rate indicator is positive one, the current duty cycle is increased by the high oscillation increment adjustment value to generate a new duty cycle. When the crossover result is positive one and the polarity rate indicator is positive one, the current duty cycle is decreased by the high oscillation decrement adjustment value to generate a new duty cycle. When the crossover result is zero, the current duty cycle remains unchanged.

[0014] In a preferred embodiment, step S5 includes the following: After the buck switching is completed, the output voltage value is re-acquired. Based on the updated output voltage value sliding window and the previous cycle output voltage value sliding window, the sum of the absolute values ​​of the output voltage value difference at the corresponding position is calculated. This sum is divided by the sliding window length and the maximum value of the absolute value of the output voltage value difference to generate a jitter estimate. If the jitter estimate is greater than the preset threshold, the current duty cycle switching frequency is multiplied by an attenuation coefficient less than 1 to generate an adjusted switching frequency. If the jitter estimate is less than or equal to the preset threshold, the current switching frequency is kept unchanged.

[0015] In a preferred embodiment, step S6 includes the following: When the jitter estimate is less than the preset jitter threshold, the jitter evaluation result is marked as positive one; otherwise, it is marked as zero. The proportion of zero symbols in the cumulative symbol vector is calculated to generate the zero symbol proportion. When the zero symbol proportion is greater than the preset convergence threshold, the convergence evaluation result is marked as positive one; otherwise, it is marked as zero. If both the jitter evaluation result and the convergence evaluation result are positive one, the system is determined to have reached a stable state. The current duty cycle factor is registered as the candidate baseline duty cycle factor, and the stable state identifier is marked as positive one. The candidate baseline duty cycle factor is stored in the controller register. If the jitter evaluation result or the convergence evaluation result is zero, the stable state identifier is kept at zero, and the return step S1 is triggered. The temporary data of the current period is cleared, and the next round of acquisition and judgment begins.

[0016] The technical effects and advantages of the buck power regulation control method based on the parameterless structure of this invention are as follows: This invention utilizes symbol accumulation to capture deviation trends. Cross-direction difference and rate characteristics are filtered for low-confidence states in real time through a learning model. The duty cycle factor is then seamlessly output using lookup table logic. Back-end jitter estimation applies dynamic limiting to the switching frequency, and a stable identifier adaptively solidifies the duty cycle reference. Each loop is positively closed. Front-end sampling provides a high-resolution starting point, and mid-end discrimination and gating work together to prevent distortion and false triggers. Symbol-guided state discrimination is naturally immune to noise, and back-end limiting suppresses high-frequency jitter and refreshes the stable identifier cyclically, forming a gain-free parameter-driven loop. The integrated link maintains steady-state accuracy under load changes and voltage drift environments, reduces electromagnetic interference peaks, shortens convergence time, and avoids the traditional parameter drift mismatch problem. The application layer can achieve wide-condition reliability and efficiency improvements without manual parameter tuning. Attached Figure Description

[0017] Figure 1 This is a schematic flowchart of the buck power regulation control method based on a parameterless structure according to the present invention. Detailed Implementation

[0018] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0019] Example 1: Figure 1 The present invention provides a buck power regulation control method based on a parameterless structure, comprising: S1: At the beginning of each control cycle, the current input voltage, output voltage and inductor current are collected, and the instantaneous sign of the output voltage deviation is immediately calculated and written into the sliding window in time order to form a sign accumulation vector.

[0020] S2: Generate cross-determination results based on the direction difference between the symbol accumulation vector and the zero vector, and simultaneously count the frequency of symbol flipping per unit time, outputting the polarity rate indicator. These two quantities together describe the state direction and rate of change.

[0021] S3: Construct state discrimination parameters using current change and voltage drift, and obtain confidence compression coefficient through machine learning model; if the cross-determination result and confidence compression coefficient both meet the preset conditions, combine the polarity rate identifier and cross-determination result as joint input and send it to the lookup table logic; otherwise, maintain the existing duty cycle and mark the delayed update.

[0022] S4: The lookup table logic receives the combined input, maps out the new duty factor based on its state combination, and drives the power switch to complete the buck switching.

[0023] S5: After the power switch operates, the output voltage is re-acquired, the sliding window is updated, and the difference between the old and new windows is calculated to obtain the jitter estimate. The jitter estimate is then used to constrain the duty cycle switching frequency in real time to suppress the continued accumulation of high-frequency jitter.

[0024] S6: When the jitter estimate is below the threshold and the symbol accumulation vector converges, register the current duty cycle as a candidate benchmark and mark the stable state. If any condition is not met, jump back to S1 to enter the next round of collection and judgment.

[0025] This invention employs gain-free symbol processing throughout the entire process. First, it captures the input voltage, output voltage, and inductor current in each control cycle, symbolizing the output deviation in real time and accumulating it into a vector to construct a high-time-resolution state profile. Then, it depicts the deviation trend using the direction difference between the vector and the zero vector, and characterizes the rate of change using the sign-flipping frequency, synthesizing a polarity rate identifier from these two features. Simultaneously, it extracts current changes and voltage drift to generate discrimination parameters, compressing them into confidence coefficients through machine learning. These coefficients, along with cross-judgment, collaboratively screen states, eliminating low-confidence samples and inputting only high-confidence identifiers into the lookup table logic to directly map the duty cycle factor, avoiding continuous gain tuning. After switching, it dynamically monitors the output voltage, calculates the difference within a sliding window to obtain a jitter estimate, and immediately limits the frequency, continuously weakening high-frequency jitter sources. When the jitter estimate and the symbol vector converge, the duty cycle reference is automatically solidified, completing an adaptive closed loop. The innovation lies in decoupling continuous errors by using symbol accumulation and direction difference, introducing adaptive gating by combining machine learning confidence compression, and integrating a triple strategy of lookup table driving, frequency limiting and jitter suppression, and reference solidification to achieve zero-gain parameter step-down control, which significantly shortens the tuning cycle and improves steady-state consistency in load fluctuation and electromagnetic compatibility scenarios.

[0026] Step S1 involves acquiring the input voltage, output voltage, and inductor current in real time, calculating the instantaneous sign of the output voltage deviation, and organizing it into a symbolic cumulative vector in chronological order. This processing logic captures the dynamic trend of system state changes in a symbolic manner. The generation of the symbolic cumulative vector avoids the dependence on continuous gain parameters in traditional control, reduces the risk of model mismatch, and provides high-resolution input for confidence compression of subsequent machine learning models.

[0027] S1.1: Collect input voltage, output voltage, and inductor current.

[0028] At the start of the control cycle, a high-precision analog-to-digital converter (ADC) synchronously acquires the input voltage, output voltage, and inductor current of the buck converter. The input voltage represents the potential state on the power supply side, the output voltage reflects the actual output at the load end, and the inductor current characterizes the dynamic process of energy transfer. A fixed sampling frequency is used during the acquisition process to ensure sufficient time resolution to capture transient changes caused by load abrupt changes or bus drift. The acquisition device converts the analog signals into digital signals via the ADC and stores them as input voltage, output voltage, and inductor current values, providing raw data for subsequent deviation calculations.

[0029] S1.2: The instantaneous sign for calculating the output voltage deviation.

[0030] The output voltage deviation is calculated based on the acquired output voltage value and the preset target voltage value. The output voltage deviation is obtained by subtracting the target voltage value from the output voltage value of the current control cycle. The target voltage value is the stable output voltage value expected by the buck converter, which is preset according to load requirements. The output voltage deviation represents the difference between the actual output and the expected output, reflecting the system's control error.

[0031] A momentary sign is generated based on the sign of the output voltage deviation.

[0032] If the output voltage deviation is greater than zero, the instantaneous sign is recorded as positive one, indicating that the output voltage is higher than the target voltage; If the output voltage deviation is less than zero, the instantaneous sign is recorded as negative one, indicating that the output voltage is lower than the target voltage; If the output voltage deviation is zero, the instantaneous sign is recorded as zero, indicating that the output voltage is consistent with the target voltage.

[0033] The instantaneous symbol generation process is achieved through comparison operations, which quantize the continuous voltage deviation into discrete symbol representations, retaining only the direction information of the deviation and ignoring its specific amplitude.

[0034] Quantizing the output voltage deviation into a symbolic form eliminates the interference of quantization noise and sensor drift on the deviation amplitude, focusing on the directional changes in the system state. Discretization simplifies the computational complexity of subsequent analysis while retaining the core information for state discrimination. Symbolic processing is naturally immune to noise, avoiding the error accumulation introduced by gain amplification in traditional continuous control, and providing a simple and robust input for time series analysis.

[0035] S1.3: Construct the symbolic cumulative vector.

[0036] The generated instantaneous symbols are written into a fixed-length sliding window in chronological order to generate a symbol accumulation vector. The sliding window is a fixed-length time-series container used to store instantaneous symbols from the most recent control cycles. After a new instantaneous symbol is generated for each control cycle, it is added to the end of the sliding window, while the oldest instantaneous symbol in the window is removed, keeping the window length unchanged. The symbol accumulation vector consists of all the instantaneous symbols in the sliding window, arranged in chronological order, with the oldest symbol at the beginning of the vector and the newest symbol at the end.

[0037] The length of the sliding window is preset based on the dynamic response characteristics and control cycle time of the buck circuit, ensuring that short-term trends in system state are captured while avoiding the storage of redundant data. The generation process of the symbol accumulation vector is implemented using a first-in-first-out data structure to ensure the continuity and consistency of the time series.

[0038] The symbol accumulation vector organizes instantaneous symbols using a time series, capturing the dynamic trend of output voltage deviation over multiple control cycles. A fixed-length sliding window ensures data structure consistency, facilitating subsequent calculations of direction difference and flip frequency. The symbol accumulation vector provides a high-time-resolution state description, reflecting the system's short-term behavior patterns under load fluctuations or external disturbances.

[0039] Step S1 synchronously acquires the input voltage, output voltage, and inductor current values ​​of the buck circuit, calculates the instantaneous sign of the output voltage deviation, and organizes it into a cumulative symbol vector in chronological order, thus completing a high-time-resolution characterization of the system state. The cumulative symbol vector retains the directional information of the deviation and eliminates noise interference, providing reliable data input for the direction difference calculation and flip frequency statistics in step S2, ensuring the accuracy and robustness of subsequent state discrimination and jitter suppression.

[0040] Step S1 generates instantaneous symbols for the output voltage deviation by synchronously acquiring input voltage, output voltage, and inductor current, and organizes them into a symbol accumulation vector, providing a high-time-resolution state profile for state analysis. However, a single symbol accumulation vector only reflects the direction of the deviation and cannot comprehensively describe the rate of change and dynamic trend of the system state. Further extraction of directional and rate features is needed to support subsequent state discrimination. The core task of step S2 is to analyze the directionality and rate of change of the symbol accumulation vector to generate cross-judgment results and polarity rate identifiers, thus fully describing the direction and dynamic characteristics of the system state. The combination of directional difference analysis and flip frequency statistics can effectively capture the system's behavioral patterns under load fluctuations or external disturbances, providing a reliable basis for the confidence compression and lookup logic of subsequent machine learning models.

[0041] S2.1: Calculate the direction difference between the symbolic cumulative vector and the zero vector.

[0042] Based on the symbol accumulation vector generated in step S1, calculate the direction difference between it and the zero vector to generate the crossover determination result.

[0043] The symbol accumulation vector consists of the instantaneous symbols of the most recent control cycles within the sliding window. Each instantaneous symbol is positive, negative, or zero, representing the positive, negative, or no deviation of the output voltage, respectively. The zero vector is a sequence of all zeros with the same length as the symbol accumulation vector, representing the ideal steady state.

[0044] The direction difference is achieved by calculating the sum of all instantaneous symbols in the symbol accumulation vector. Specifically, the instantaneous symbol values ​​in the symbol accumulation vector are summed to obtain the symbol sum. The symbol sum represents the overall trend of the output voltage deviation within the sliding window. If the symbol sum is greater than zero, the cross-judgment result is recorded as positive one, indicating that the overall output voltage is higher than the target voltage; if the symbol sum is less than zero, the cross-judgment result is recorded as negative one, indicating that the overall output voltage is lower than the target voltage; if the symbol sum is equal to zero, the cross-judgment result is recorded as zero, indicating that the overall output voltage is consistent with the target voltage.

[0045] S2.2: Statistical sign flipping frequency.

[0046] Based on the symbol accumulation vector, the frequency of symbol flipping per unit time is statistically analyzed to generate a polarity rate identifier. Symbol flipping is defined as the instantaneous change of symbol between adjacent control cycles within a sliding window, including changing from positive to negative, from negative to positive, from non-zero to zero, or from zero to non-zero.

[0047] The calculation process iterates through the symbol accumulation vector, comparing the values ​​of adjacent instantaneous symbols. If the two values ​​are different, it is recorded as a flip. The number of flips within the sliding window is counted to obtain the symbol flip count. The symbol flip frequency is normalized by dividing the symbol flip count by the sliding window length to obtain the flip frequency per unit time. The polarity rate indicator is generated based on the comparison between the symbol flip frequency and a preset threshold: if the symbol flip frequency is greater than the preset threshold, the polarity rate indicator is recorded as positive one, indicating that the system state has high-frequency oscillations; if the symbol flip frequency is less than or equal to the preset threshold, the polarity rate indicator is recorded as zero, indicating that the system state has low oscillations or is stable.

[0048] Sign-flip frequency statistics can quantify the oscillation characteristics of the system state, reflect the dynamic rate of change of the output voltage deviation, and highlight the degree of high-frequency jitter. Polarity rate identification reduces computational complexity by discretizing the oscillation characteristics, and at the same time provides dynamic information for the joint feature generation in step S3, thus aiding in jitter suppression.

[0049] S2.3: Combination and transmission cross-determination results and polarity rate identifier.

[0050] The cross-determination result and the polarity rate identifier are combined into a joint feature pair, stored in a structure, and passed to step S3. The joint feature pair contains the cross-determination result and the polarity rate identifier, representing the directionality and oscillation rate of the system state, respectively. The storage procedure binds the two together through a data structure to ensure time synchronization and data consistency. The transmission process adopts a real-time data stream mechanism, directly sending the joint feature pair to the processing module of step S3 to ensure that subsequent steps can receive and process it immediately.

[0051] Step S2 generates a cross-determination result by calculating the sum of instantaneous symbols in the symbol accumulation vector, generates a polarity rate identifier by statistically analyzing the symbol flip frequency, and combines them into a joint feature pair, thus completing a comprehensive characterization of the system state direction and rate of change. The cross-determination result and the polarity rate identifier together describe the trend and oscillation characteristics of the output voltage deviation, providing accurate and robust input features for confidence compression and state discrimination in step S3.

[0052] Step S2 generates cross-decision results and polarity rate identifiers based on the symbolic cumulative vector, providing a description of the directionality and rate of change of the system state. However, single directionality and rate features cannot directly determine the confidence level of the state; they must be combined with the dynamic characteristics of current and voltage for screening to ensure the accuracy of control decisions. Step S3 generates state discrimination parameters based on current changes and voltage drift, calculates the confidence compression coefficient using a support vector machine model, and uses it together with the cross-decision results to screen states, ensuring that only high-confidence features are used for control decisions, thereby improving the stability of the buck circuit under load fluctuations and external disturbances.

[0053] S3.1: Construction state discrimination parameter.

[0054] Based on the inductor current and output voltage values ​​collected in step S1, the change in inductor current and the drift in output voltage are calculated to construct state discrimination parameters. These parameters include a state bounce strength index and a stability offset index, which respectively characterize the oscillation characteristics of the inductor current and the continuous drift trend of the output voltage.

[0055] Calculation of the State Jump Intensity Index: In the symbol accumulation vector generated in step S2, the number of times the positive and negative polarities of the instantaneous symbols in adjacent control cycles alternate is found to obtain the symbol flip frequency. The symbol flip frequency is obtained by counting the number of changes of adjacent instantaneous symbols in the symbol accumulation vector and dividing by the sliding window length, representing the frequency of instantaneous symbol changes per unit time. For each symbol flip, the corresponding change in inductor current value is extracted, defined as the difference between the inductor current value of the current control cycle and the inductor current value of the previous cycle. The symbol flip frequency is multiplied by the absolute value of the change in inductor current value corresponding to each flip to obtain the weighted contribution of each flip. The weighted contributions of all flips are summed to obtain the cumulative sum. The cumulative sum is divided by the maximum value of the absolute value of the change in inductor current value and the sliding window length for normalization, generating the state jump intensity index. The state jump intensity index characterizes the oscillation trend of inductor current caused by repeated corrections in the system, reflecting the intensity of high-frequency jitter.

[0056] The calculated state bounce strength index quantifies the dynamic characteristics of system oscillations by combining sign reversal with current changes.

[0057] Calculation of the stationary drift index: Based on a sliding window of the output voltage values ​​acquired in step S1, the local linear drift rate of the output voltage values ​​is fitted. The sliding window of output voltage values ​​contains the output voltage values ​​of the most recent control cycles. The slope of the output voltage value changing with time within the window is calculated using the least squares method to obtain the local linear drift rate. Specifically, the deviation of each output voltage value from the mean of the window is calculated, multiplied by the deviation of the corresponding time point from the time mean, summed, and divided by the sum of the squares of the time point deviations to obtain the local linear drift rate. The difference between the mean of the output voltage value sliding window and the target voltage value is calculated to obtain the mean deviation magnitude. The local linear drift rate is multiplied by the mean deviation magnitude to obtain the drift weight, which is then divided by the product of the maximum drift rate and the maximum mean deviation magnitude for normalization, generating the stationary drift index. The stationary drift index characterizes the low-amplitude continuous drift trend of the output voltage and reflects the degree of deviation of the system from the target voltage.

[0058] The steady-state offset index captures the long-term drift characteristics of the output voltage through fitting and normalization, thus compensating for the short-term limitations of the instantaneous sign.

[0059] S3.2: Calculate the confidence compression coefficient using the support vector machine model.

[0060] The confidence compression coefficient is calculated using a Support Vector Machine (SVM) model, employing a linear kernel function and built upon an offline training dataset. The training data comprises historical data from a step-down circuit under various load conditions and bus voltage fluctuations, including inductor current changes, output voltage sequences, sign accumulation vectors, and corresponding steady-state labels. The steady-state labels are experimentally labeled; a positive value indicates a stable system, while a value of zero indicates an unstable system. The training process optimizes the SVM model parameters by maximizing the classification hyperplane margin, generating a classification decision function. Specifically, for each support vector, the linear inner product of its state bounce strength index and stationary offset index is calculated, multiplied by the corresponding Lagrange multiplier and the label value, summed, and then a bias term is added to obtain the confidence compression coefficient. The confidence compression coefficient represents the confidence level of the current state; a larger value indicates that the state is closer to a stable state.

[0061] During the training of the support vector machine model, a set of data was collected on the buck circuit under load switching from light to heavy load and bus voltage fluctuations. For example, this included inductor current values, output voltage values, and sign accumulation vectors for 1000 control cycles. For each set of data, experimental records were used to determine whether the output voltage reached a steady state at the target voltage value, generating labels. Cross-validation was used during training, with 70% of the data used for training and 30% for validation. The linear kernel function parameters were optimized to generate the classification decision function. During runtime, the current state bounce strength index and stationary offset index were input to calculate the confidence compression coefficient.

[0062] Support Vector Machine (SVM) models quantify state confidence through classification decisions, filtering out low-confidence states and reducing the risk of misclassification. Linear kernel functions and offline training ensure the model's computational efficiency and generalization ability. Confidence compression coefficients provide a quantitative basis for state selection, enhancing the reliability of control decisions.

[0063] S3.3: State filtering and joint input generation.

[0064] Based on the cross-determination result and confidence compression coefficient generated in step S2, state filtering is performed. A cross-determination result of positive one, negative one, or zero indicates that the overall output voltage is higher than, lower than, or equal to the target voltage value, respectively. If the absolute value of the cross-determination result is positive one and the confidence compression coefficient is greater than a preset threshold, the current state is considered reliable. The cross-determination result and the polarity rate identifier generated in step S2 are combined into a joint input, stored in a structure, and passed to the lookup logic in step S4. The joint input includes the cross-determination result and the polarity rate identifier, representing the directionality and oscillation rate of the system state. If the absolute value of the cross-determination result is not positive one or the confidence compression coefficient is less than or equal to the preset threshold, the current state is considered unreliable. The existing duty cycle remains unchanged, and the state is marked as delayed update, awaiting re-determination in the next control cycle.

[0065] Step S3 constructs state discrimination parameters by calculating the state bounce strength index and the stationary offset index, generates confidence compression coefficients using a support vector machine model, and filters high-confidence states based on cross-decision results. This generates joint inputs or label delay updates, thus completing the accurate filtering of system states. The joint inputs provide a reliable control basis for the lookup logic in step S4, ensuring the stability and robustness of the buck circuit under dynamic environments.

[0066] Step S3 constructs state discrimination parameters using the change in inductor current and the drift in output voltage. A support vector machine model is used to generate confidence compression coefficients and filter high-confidence states, generating a joint input. However, the joint input only provides the directionality and oscillation characteristics of the state; it needs to be mapped to a specific control quantity to drive the power switch. Step S4 receives the joint input generated in step S3 and maps it to a new duty cycle factor using lookup table logic, driving the power switch to achieve buck switching and ensuring dynamic adjustment and stability of the output voltage.

[0067] Sub-step S4.1: Receive combined input The system receives the combined input transmitted in step S3. This combined input includes a cross-determination result and a polarity rate identifier. The cross-determination result is positive one, negative one, or zero, indicating that the overall output voltage is higher than, lower than, or equal to the target voltage value, respectively. The polarity rate identifier is positive one or zero, indicating that the system state exhibits high-frequency oscillation or low oscillation, respectively. The combined input is stored in a structure that binds the cross-determination result and the polarity rate identifier, ensuring their time synchronization and data consistency. The receiving process is implemented through a real-time data stream mechanism, loading the combined input into the input buffer of the lookup logic to ensure that the lookup logic can access and process it immediately.

[0068] The receipt of combined inputs, through structured storage and a real-time data stream mechanism, ensures the integrity and timeliness of state characteristics, avoiding data loss or delay. Combined inputs provide highly reliable control basis for table lookup logic, enhancing the reliability and real-time performance of control decisions.

[0069] S4.2: Table lookup logic mapping duty cycle.

[0070] Based on the joint input, a new duty cycle is generated through a pre-defined lookup table logic. The lookup table is constructed offline and indexed by a combination of the cross-determination result and the polarity rate identifier, corresponding to a predefined duty cycle adjustment value. The mapping rules for the lookup table are as follows: When the cross-determination result is negative one and the polarity rate is zero, it indicates that the output voltage is lower than the target voltage value and the oscillation is low. The new duty factor is calculated by adding the low oscillation increment adjustment value to the current duty factor. When the cross-determination result is positive one and the polarity rate is zero, it indicates that the output voltage is higher than the target voltage value and the oscillation is low. The new duty factor is calculated by subtracting the low oscillation reduction adjustment value from the current duty factor. When the cross-determination result is negative one and the polarity rate identifier is positive one, it indicates that the output voltage is lower than the target voltage value and there is high-frequency oscillation. The new duty factor is calculated by adding the high oscillation increment adjustment value to the current duty factor. The high oscillation increment adjustment value is a fixed step value calibrated offline based on the electrical parameters of the buck circuit and the load characteristics when the cross-determination result is negative one and the polarity rate identifier is positive one. The new duty factor is generated by adding this value to the current duty factor to speed up the response and adapt to the high-frequency oscillation state.

[0071] When the cross-determination result is positive one and the polarity rate identifier is positive one, it indicates that the output voltage is higher than the target voltage value and there is high-frequency oscillation. The new duty factor is calculated by subtracting the high oscillation reduction adjustment value from the current duty factor. When the cross-determination result is zero, it means that the output voltage is equal to the target voltage value, and the new duty cycle remains unchanged from the current duty cycle.

[0072] The low oscillation increment adjustment value, low oscillation decrement adjustment value, high oscillation increment adjustment value, and high oscillation decrement adjustment value are predefined adjustment values ​​calibrated offline based on the electrical parameters and load characteristics of the step-down circuit, ensuring that the adjustment range of the duty factor is suitable for different operating conditions.

[0073] The lookup table logic converts state characteristics into control variables through discrete mapping, avoiding the complexity and parameter coupling problems of continuous gain regulation. The lookup table, based on experimental calibration, adapts to various operating conditions, ensuring the stability and adaptability of control decisions. The new duty cycle directly reflects the dynamic demands of the system state, providing precise control adjustments for the buck converter.

[0074] S4.3: Drive power switch.

[0075] A new duty cycle factor is applied to the power switch of the buck converter to complete the buck switching. The power switch is a high-speed switching device that receives the new duty cycle factor through a pulse width modulation (PWM) controller. The PWM controller calculates the ratio of the switch's on-time to off-time based on the new duty cycle factor and generates a corresponding pulse signal. The pulse signal drives the power switch to perform on-off actions, adjusting the energy transfer of the buck converter to make the output voltage value close to the target voltage value. The driving process is implemented through hardware circuitry to ensure that the new duty cycle factor is quickly and accurately converted into an electrical signal to complete the buck switching.

[0076] The power switch driver translates the lookup table logic output into actual control actions, completing a closed-loop mapping from state characteristics to voltage regulation. The hardware driver, through a pulse-width modulation controller, ensures rapid response and high-precision execution of the control signal, providing a stable control output for subsequent jitter suppression and steady-state determination.

[0077] Step S4 receives the combined input, uses lookup table logic mapping to generate a new duty cycle factor, and drives the power switch to complete the buck switching, thus completing the conversion from system state characteristics to control actions. The new duty cycle factor accurately reflects the dynamic requirements of the system state, providing reliable control actions for the output voltage acquisition and jitter suppression in step S5, ensuring the stability of the buck circuit in dynamic environments.

[0078] Step S4 maps the combined input to a new duty cycle using lookup table logic and drives the power switch to complete the buck switching. However, the power switch operation may introduce new jitter, requiring real-time monitoring of the output voltage to assess the jitter level and constrain the switching frequency to suppress high-frequency jitter accumulation. Step S5 involves re-acquiring the output voltage value after the power switch operation, updating the output voltage value sliding window, calculating the difference between the old and new windows to generate a jitter estimate, and using the jitter estimate to constrain the duty cycle switching frequency, suppressing high-frequency jitter and ensuring the stability of the buck circuit.

[0079] S5.1: Reacquire the output voltage value and update the sliding window.

[0080] After the power switch completes the buck switching based on the new duty cycle generated in step S4, the output voltage value of the buck circuit is re-acquired using a high-precision analog-to-digital converter. The output voltage value reflects the actual output state after the power switch operates, characterizing the dynamic response of the buck circuit. The acquisition process uses the same fixed sampling frequency as in step S1 to ensure consistent time resolution and capture transient changes in the output voltage. The acquired output voltage values ​​are written into the output voltage value sliding window in chronological order, updating the sliding window content. The output voltage value sliding window is a fixed-length sequence containing the output voltage values ​​of the most recent control cycles. The update process is implemented using a first-in, first-out (FIFO) approach, removing the oldest output voltage value from the sliding window and adding the latest acquired output voltage value to the end of the sliding window, while keeping the sliding window length unchanged.

[0081] Reacquiring the output voltage value and updating the sliding window can reflect the voltage change after the power switch is activated in real time, capturing the short-term trend of the system's dynamic response.

[0082] S5.2: Calculate the jitter estimate by differentiating the old and new windows.

[0083] Based on the updated output voltage value sliding window and the previous cycle's output voltage value sliding window, the difference between the old and new windows is calculated to generate a jitter estimate. The calculation process involves comparing the output voltage values ​​at corresponding positions in the two sliding windows, calculating the absolute value of the difference between each pair of corresponding output voltage values, and summing all the absolute values ​​of the differences to obtain a cumulative difference sum. This cumulative difference sum is then normalized by dividing by the maximum absolute value of the difference between the sliding window length and the output voltage value, generating the jitter estimate. The jitter estimate characterizes the short-term fluctuation intensity of the output voltage between adjacent control cycles, reflecting the degree of high-frequency jitter introduced by power switching operations.

[0084] The new and old window differential calculations capture the jitter characteristics after power switching by quantifying voltage fluctuations, thus avoiding the computational overhead of complex frequency domain analysis.

[0085] S5.3: Constrain duty cycle switching frequency.

[0086] Based on jitter estimation, the duty cycle switching frequency is constrained to suppress high-frequency jitter accumulation. The duty cycle switching frequency is defined as the number of times the duty cycle is updated per unit time, initially set to the default frequency of the pulse width modulation controller. The constraint process is achieved by comparing the jitter estimation value with a preset threshold. If the jitter estimation value is greater than the preset threshold, it indicates significant high-frequency jitter, and the duty cycle switching frequency is reduced. Specifically, the current switching frequency is multiplied by an attenuation coefficient, a dimensionless value less than 1, pre-calibrated based on the dynamic response characteristics of the buck converter. If the jitter estimation value is less than or equal to the preset threshold, the current switching frequency remains unchanged. The adjusted switching frequency is applied to the pulse width modulation controller to limit the duty cycle update rate and reduce high-frequency jitter accumulation.

[0087] The constraint duty cycle switching frequency is dynamically adjusted to suppress high-frequency jitter, balancing response speed and stability. The attenuation coefficient calibration ensures the adaptability of the constraint force, making it suitable for different load conditions. The adjusted switching frequency reduces jitter accumulation, providing a stable control environment for the steady-state determination in step S6.

[0088] Step S5 involves re-acquiring the output voltage value and updating the sliding window. The difference between the old and new windows is calculated to generate a jitter estimate. This jitter estimate is then used to constrain the duty cycle switching frequency, completing the dynamic feedback and frequency suppression of jitter quantization. The jitter estimate and the adjusted switching frequency effectively suppress high-frequency jitter, providing stable control feedback for the steady-state determination and duty cycle fixing in step S6.

[0089] Step S5 re-acquires the output voltage value and generates a jitter estimate to constrain the switching frequency. However, the control state after jitter suppression needs further evaluation to determine whether a steady state has been reached, in order to solidify the optimized duty cycle and complete the closed loop. Step S6, based on the jitter estimate and the sign accumulation vector, determines whether the system has reached a steady state, registers the candidate reference duty cycle and marks the steady state, or triggers the next round of acquisition and evaluation, forming an adaptive closed loop.

[0090] S6.1: Evaluate jitter estimates.

[0091] Based on the jitter estimate generated in step S5, the system jitter is assessed to determine whether it has reached a low level. The jitter estimate is obtained by normalizing the difference between the old and new output voltage values ​​through a sliding window, representing the short-term fluctuation intensity of the output voltage after the power switch is activated. The assessment process is achieved by comparing the jitter estimate with a preset jitter threshold, which is calibrated offline based on the dynamic response characteristics of the buck circuit. If the jitter estimate is less than the preset jitter threshold, the system jitter is considered to be at a low level, meeting the jitter conditions for a steady state, and the jitter assessment result is marked as positive one. If the jitter estimate is greater than or equal to the preset jitter threshold, the jitter assessment result is marked as zero, indicating that the jitter level is still high and the system has not reached a steady state.

[0092] S6.2: Evaluate the convergence of the symbolic cumulative vector.

[0093] The convergence of the accumulated symbol vector generated in step S1 is evaluated. The accumulated symbol vector contains instantaneous symbols from the most recent control cycles within the sliding window. These instantaneous symbols are positive, negative, or zero, representing the positive, negative, or no deviation of the output voltage deviation, respectively. Convergence evaluation is achieved by calculating the proportion of zero symbols in the accumulated symbol vector. Specifically, the accumulated symbol vector is traversed, the number of times an instantaneous symbol is zero is counted, and this number is divided by the sliding window length to obtain the proportion of zero symbols. The proportion of zero symbols indicates the degree to which the output voltage deviation tends to stabilize within the sliding window. If the proportion of zero symbols is greater than a preset convergence threshold, the accumulated symbol vector is considered convergent, and the convergence evaluation result is marked as positive, indicating that the system is close to a deviation-free state. If the proportion of zero symbols is less than or equal to the preset convergence threshold, the convergence evaluation result is marked as zero, indicating that the system has not yet reached a steady state. The preset convergence threshold is calibrated offline based on the steady-state characteristics of the buck converter.

[0094] The convergence of the evaluation symbol cumulative vector reflects the long-term stability of the output voltage deviation by quantifying the proportion of zero symbols, thus compensating for the short-term limitations of jitter estimation. The discretized convergence evaluation results simplify the decision-making logic and facilitate integration with jitter evaluation results. The convergence evaluation results provide long-term stability characteristics for steady-state determination, enhancing the comprehensiveness of the decision.

[0095] S6.3: Steady-state determination and cyclic control.

[0096] Based on the jitter evaluation results and convergence evaluation results, a steady-state determination is performed. If both the jitter evaluation result and the convergence evaluation result are positive, the system is considered to have reached a steady state. The current duty cycle factor is registered as a candidate reference duty cycle factor, and the steady-state identifier is marked as positive. The current duty cycle factor is the new duty cycle factor generated in step S4, reflecting the control quantity of the current control cycle. The candidate reference duty cycle factor is stored in the controller's register as a reference value for subsequent control. If the jitter evaluation result or the convergence evaluation result is zero, the system is considered not to have reached a steady state. The steady-state identifier is kept at zero, and a return to step S1 is triggered to enter the next round of acquisition and determination. Upon returning to step S1, the temporary data of the current cycle is cleared, and the acquisition and subsequent processing of input voltage, output voltage, and inductor current values ​​are re-executed, forming a progressive closed loop.

[0097] The registration of alternate reference duty cycle and the cyclic control mechanism ensure the adaptability and continuity of the control link. Steady-state identification and cyclic triggering realize a dynamic closed loop, enhancing the stability of the buck circuit under various operating conditions.

[0098] Step S6 determines whether the system has reached a steady state by evaluating the convergence of the jitter estimate and the sign accumulation vector, registers the candidate reference duty cycle factor and marks the steady state, or triggers a return to step S1 to continue the loop, thus completing the closed feedback of the control link. The steady state identifier and the candidate reference duty cycle factor ensure the long-term stability of the buck circuit and provide a reliable basis for adaptive control under load fluctuations and external disturbances.

[0099] The above formulas are all dimensionless calculations. The formulas are derived from software simulations based on a large amount of collected data to obtain the most recent real-world results. The preset parameters in the formulas are set by those skilled in the art according to the actual situation.

[0100] It should be noted that the system of the present invention can be deployed on the device itself to realize embedded applications, or it can run on a PC or other terminal with a user interface, thereby meeting a variety of hardware environments and usage requirements.

[0101] The foregoing has only described certain exemplary embodiments of the present invention by way of illustration. Undoubtedly, those skilled in the art can modify the described embodiments in various ways without departing from the spirit and scope of the present invention. Therefore, the foregoing drawings and descriptions are illustrative in nature and should not be construed as limiting the scope of protection of the claims of the present invention.

[0102] It should be noted that, in this document, the use of relational terms such as "first" and "second" is merely to distinguish one entity or operation from another, and does not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes the element.

[0103] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A step-down power regulation control method based on a parameterless structure, characterized in that, Including the following steps: S1: At the beginning of each control cycle, the current input voltage, output voltage and inductor current are collected, and the instantaneous sign of the output voltage deviation is immediately calculated and written into the sliding window in time order to form a sign accumulation vector; S2: Generate cross-determination results based on the direction difference between the symbol accumulation vector and the zero vector, and simultaneously count the frequency of symbol flipping per unit time, outputting the polarity rate indicator. These two quantities together describe the state direction and rate of change. S3: Construct state discrimination parameters using current change and voltage drift, and obtain confidence compression coefficients through machine learning model; If the cross-determination result and the confidence compression coefficient both satisfy the preset conditions, then the polarity rate identifier and the cross-determination result are combined as a joint input and sent to the lookup table logic. S4: The lookup table logic receives the combined input, maps out a new duty factor based on its state combination, and drives the power switch to complete the buck switching. S5: After the power switch operates, the output voltage is re-acquired, the sliding window is updated, and the difference between the old and new windows is calculated to obtain the jitter estimate. The jitter estimate is used to constrain the duty factor switching frequency in real time to suppress the continued accumulation of high-frequency jitter. S6: When the jitter estimate is below the threshold and the symbol accumulation vector converges, register the current duty cycle as a candidate benchmark and mark the stable state. If any condition is not met, jump back to S1 to enter the next round of collection and judgment.

2. The step-down power regulation control method based on a parameterless structure according to claim 1, characterized in that, Step S1 includes the following: At the beginning of each control cycle, the input voltage, output voltage, and inductor current of the buck circuit are synchronously acquired. The output voltage deviation is calculated by subtracting the preset target voltage value from the output voltage value. An instantaneous symbol is generated based on the sign of the output voltage deviation. The instantaneous symbols are written into a fixed-length sliding window in chronological order to generate a symbol accumulation vector.

3. The step-down power regulation control method based on a parameterless structure according to claim 2, characterized in that, Step S1 also Includes the following: A positive sign indicates that the output voltage is higher than the target voltage; a negative sign indicates that the output voltage is lower than the target voltage; and a zero sign indicates that the output voltage is equal to the target voltage.

4. The step-down power regulation control method based on a parameterless structure according to claim 3, characterized in that, Step S2 includes the following: A positive cross-judgment result indicates that the overall output voltage is higher than the target voltage value; a negative cross-judgment result indicates that the overall output voltage is lower than the target voltage value; and a zero cross-judgment result indicates that the overall output voltage is consistent with the target voltage value. The number of symbol flips is obtained by counting the number of changes of adjacent instantaneous symbols within the sliding window. The symbol flip frequency is generated by normalizing the number of symbol flips by dividing the number of symbol flips by the length of the sliding window. The polarity rate identifier is generated by comparing the symbol flip frequency with a preset threshold. The cross-judgment result and the polarity rate identifier are combined into a joint feature pair.

5. The step-down power regulation control method based on a parameterless structure according to claim 4, characterized in that, Step S3 includes the following: The state discrimination parameters include the state bounce intensity index and the stationary shift index; The state bounce strength index generates the symbol flip frequency by the number of times the positive and negative polarities of adjacent instantaneous symbols alternate in the symbol accumulation vector. The symbol flip frequency is generated by multiplying the absolute value of the change in inductor current value corresponding to each flip, accumulating the results, and then normalizing by the sliding window length and the maximum absolute value of the change in inductor current value. The stationary drift index is generated by fitting the local linear drift rate through a sliding window of the output voltage value, calculating the difference between the mean output voltage value and the target voltage value to obtain the mean deviation magnitude, and then normalizing by multiplying the local linear drift rate by the mean deviation magnitude and dividing by the product of the maximum drift rate and the maximum mean deviation magnitude.

6. The step-down power regulation control method based on a parameterless structure according to claim 5, characterized in that, Step S3 also Includes the following: The confidence compression coefficient is calculated using the state bounce strength index and the stationary offset index through a support vector machine model based on a linear kernel function. The support vector machine model optimizes the classification decision function using an offline training dataset. If the absolute value of the cross-decision result is positive one and the confidence compression coefficient is greater than a preset threshold, the cross-decision result and the polarity rate label are combined as a joint input and passed to the lookup table logic. Otherwise, the existing duty cycle is maintained and the delayed update state is marked.

7. The step-down power regulation control method based on a parameterless structure according to claim 6, characterized in that, Step S4 also includes the following: The combined input includes the cross-determination result and the polarity rate identifier. A new duty cycle factor is generated by mapping the combination of the cross-determination result and the polarity rate identifier using a preset lookup table. The new duty cycle factor is then used to generate a pulse signal through a pulse width modulation controller, which drives the power switch to perform opening and closing actions to complete the step-down switching.

8. The step-down power regulation control method based on a parameterless structure according to claim 7, characterized in that, Step S4 also includes the following: The lookup table uses the crossover result as the row index and the polarity rate indicator as the column index. When the crossover result is negative one and the polarity rate indicator is zero, the current duty cycle is increased by the low oscillation increment adjustment value to generate a new duty cycle. When the crossover result is positive one and the polarity rate indicator is zero, the current duty cycle is decreased by the low oscillation decrement adjustment value to generate a new duty cycle. When the crossover result is negative one and the polarity rate indicator is positive one, the current duty cycle is increased by the high oscillation increment adjustment value to generate a new duty cycle. When the crossover result is positive one and the polarity rate indicator is positive one, the current duty cycle is decreased by the high oscillation decrement adjustment value to generate a new duty cycle. When the crossover result is zero, the current duty cycle remains unchanged.

9. The step-down power regulation control method based on a parameterless structure according to claim 8, characterized in that, Step S5 includes the following: After the buck switching is completed, the output voltage value is re-acquired. Based on the updated output voltage value sliding window and the previous cycle output voltage value sliding window, the sum of the absolute values ​​of the output voltage value difference at the corresponding position is calculated. This sum is divided by the sliding window length and the maximum value of the absolute value of the output voltage value difference to generate a jitter estimate. If the jitter estimate is greater than the preset threshold, the current duty cycle switching frequency is multiplied by an attenuation coefficient less than 1 to generate an adjusted switching frequency. If the jitter estimate is less than or equal to the preset threshold, the current switching frequency is kept unchanged.

10. The step-down power regulation control method based on a parameterless structure according to claim 9, characterized in that, Step S6 includes the following: When the jitter estimate is less than the preset jitter threshold, the jitter evaluation result is marked as positive one; otherwise, it is marked as zero. The proportion of zero symbols in the cumulative symbol vector is calculated to generate the zero symbol proportion. When the zero symbol proportion is greater than the preset convergence threshold, the convergence evaluation result is marked as positive one; otherwise, it is marked as zero. If both the jitter evaluation result and the convergence evaluation result are positive one, the system is determined to have reached a stable state. The current duty cycle factor is registered as the candidate baseline duty cycle factor, and the stable state identifier is marked as positive one. The candidate baseline duty cycle factor is stored in the controller register. If the jitter evaluation result or the convergence evaluation result is zero, the stable state identifier is kept at zero, and the return step S1 is triggered. The temporary data of the current period is cleared, and the next round of acquisition and judgment begins.

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