Circuit and method for setting PWM (Pulse Width Modulation) duty ratio and power management system

Abstract

The invention provides a circuit and method for setting a PWM duty ratio and a power management system. The circuit comprises a comparison module, a logic control module, a digital logic module, a voltage selection module and a PWM generation module. The comparison module comprises a demand voltage generation unit and a comparison unit. The demand voltage generation unit generates demand voltage in a certain scene, the comparison unit compares the demand voltage with voltage provided by the voltage selection module, the logic control module analyzes the comparison result to generate a digital signal, and the digital logic module determines the range of the demand voltage. The logic level signal corresponding to the required voltage is obtained and sent to the PWM generation module, so that the PWM generation module sets the duty ratio, and therefore, the interference of power supply variation and signal noise can be reduced, the control precision of the duty ratio can be improved, the setting of different required duty ratios can be realized by adjusting the external resistor, the design is simple, and the integration level is high.

Description

Technical Field

[0001] This invention relates to the field of duty cycle modulation technology, and more particularly to a circuit and method for setting the PWM duty cycle, and a power management system. Background Technology

[0002] In power electronic systems, pulse width modulation (PWM) is the mainstream control method. By adjusting the ratio of the high-level time of the signal to the period, it can achieve flexible control of the average output power and is widely used in integrated circuits such as microcontrollers, motor driver chips, and LED drivers.

[0003] Normally, the duty cycle setting can be dynamically adjusted using an external analog signal. However, external analog signals are susceptible to power fluctuations and noise interference, which can lead to a decrease in control accuracy. Summary of the Invention

[0004] This invention provides a circuit and method for setting the PWM duty cycle, as well as a power management system, to solve the defects in the prior art where the duty cycle is dynamically adjusted by external analog signals, which is easily affected by power fluctuations and noise interference, leading to a decrease in control accuracy.

[0005] On one hand, the present invention provides a circuit for setting the PWM duty cycle, which includes a comparison module, a logic control module, a digital logic module, a voltage selection module, and a PWM generation module; wherein, the comparison module includes a demand voltage generation unit and a comparison unit;

[0006] The first terminal of the demand voltage generation unit is electrically connected to the first power supply; the second terminal of the demand voltage generation unit is electrically connected to the pin of the system chip and the first input terminal of the comparison unit; the third terminal of the demand voltage generation unit is electrically connected to the first output terminal of the digital logic module; and the pin of the system chip is electrically connected to an external resistor.

[0007] The second input terminal of the comparison unit is electrically connected to the output terminal of the voltage selection module, and the output terminal of the comparison unit is electrically connected to the input terminal of the logic control module.

[0008] The output terminal of the logic control module is electrically connected to the input terminal of the digital logic module;

[0009] The second output terminal of the digital logic module is electrically connected to the input terminal of the voltage selection module, and the third output terminal of the digital logic module is electrically connected to the PWM generation module.

[0010] The voltage selection module follows the voltage selection signal at the second output terminal of the digital logic module and outputs the voltage corresponding to the voltage selection signal;

[0011] The comparison unit compares the voltage corresponding to the voltage selection signal with the demand voltage generated by the demand voltage generation unit, and converts the comparison result into a digital signal via the logic control module.

[0012] The digital logic module generates the control signal for the demand voltage generation unit, the voltage selection signal for the voltage selection module, and the logic level signal for the PWM generation module based on the digital signal.

[0013] The PWM generation module is used to set the duty cycle by changing the charging current and discharging current under the influence of the logic level signal.

[0014] According to the present invention, a circuit for setting the PWM duty cycle is provided, wherein the voltage selection module includes a voltage regulator reference unit, a voltage divider switching unit, and a resistor network voltage divider unit;

[0015] The input terminal of the voltage regulator reference unit is electrically connected to the second power supply, and the output terminal of the voltage regulator reference unit is electrically connected to the first terminal of the voltage divider switching unit and the first terminal of the resistor network voltage divider unit.

[0016] The second terminal of the voltage divider switching unit is electrically connected to the ground terminal; the third terminal of the voltage divider switching unit is electrically connected to the second terminal of the resistor network voltage divider unit; and the fourth terminal of the voltage divider switching unit is electrically connected to the digital logic module.

[0017] The third terminal of the resistor network voltage divider unit is electrically connected to the ground terminal;

[0018] The voltage divider switching unit is configured to follow the voltage selection signal of the second output terminal of the digital logic module, switch the resistor path of the resistor network voltage divider unit, and output the voltage corresponding to the voltage selection signal.

[0019] According to a circuit for setting the PWM duty cycle provided by the present invention, the voltage divider switching unit includes multiple parallel voltage divider switching switch groups, each voltage divider switching switch group including an upper bridge switching switch and a lower bridge switching switch;

[0020] The first terminal of the upper bridge switch is electrically connected to the output terminal of the voltage regulator reference unit, the second terminal of the upper bridge switch is electrically connected to the first terminal of the lower bridge switch and the resistor network voltage divider unit, and the control terminals of the upper bridge switch and the lower bridge switch are electrically connected to the digital logic module.

[0021] The second terminal of the lower bridge switching switch is electrically connected to the grounding terminal.

[0022] The plurality of parallel voltage divider switching groups are configured as follows:

[0023] If the upper bridge switching switch of the current voltage divider switching switch group is turned on, the lower bridge switching switch of the current voltage divider switching switch group is turned off;

[0024] If the upper bridge switch of the current voltage divider switch group is open, the lower bridge switch of the current voltage divider switch group is open.

[0025] According to the present invention, a circuit for setting the PWM duty cycle is provided, wherein the plurality of parallel voltage divider switching groups include a first voltage divider switching group, a second voltage divider switching group, a third voltage divider switching group, and a fourth voltage divider switching group;

[0026] The first terminal of the upper bridge switch in the first voltage divider switch group, the first terminal of the upper bridge switch in the second voltage divider switch group, the first terminal of the upper bridge switch in the third voltage divider switch group, and the first terminal of the upper bridge switch in the fourth voltage divider switch group are electrically connected to the output terminal of the voltage regulator reference unit.

[0027] The second terminal of the upper bridge switch in the first voltage divider switch group is electrically connected to the first terminal of the lower bridge switch in the first voltage divider switch group; the second terminal of the upper bridge switch in the second voltage divider switch group is electrically connected to the first terminal of the lower bridge switch in the second voltage divider switch group; the second terminal of the upper bridge switch in the third voltage divider switch group is electrically connected to the first terminal of the lower bridge switch in the third voltage divider switch group; the second terminal of the upper bridge switch in the fourth voltage divider switch group is electrically connected to the first terminal of the lower bridge switch in the fourth voltage divider switch group.

[0028] The second terminal of the lower bridge switch in the first voltage divider switch group, the second terminal of the lower bridge switch in the second voltage divider switch group, the second terminal of the lower bridge switch in the third voltage divider switch group, and the second terminal of the lower bridge switch in the fourth voltage divider switch group are electrically connected to the ground terminal.

[0029] According to a circuit for setting the PWM duty cycle provided by the present invention, the resistor network voltage divider unit includes a first resistor to a tenth resistor;

[0030] The first end of the first resistor is electrically connected to the output terminal of the voltage regulator reference unit; the second end of the first resistor is electrically connected to the ground terminal.

[0031] The first end of the second resistor is electrically connected to the output end of the voltage regulator reference unit; the second end of the second resistor is electrically connected to the first end of the third resistor and the first end of the fourth resistor.

[0032] The second end of the third resistor is electrically connected to the second end of the upper bridge switching switch in the fourth voltage divider switching switch group;

[0033] The second end of the fourth resistor is electrically connected to the first end of the fifth resistor and the first end of the sixth resistor;

[0034] The second end of the fifth resistor is electrically connected to the second end of the upper bridge switching switch in the third voltage divider switching switch group;

[0035] The second end of the sixth resistor is electrically connected to the first end of the seventh resistor and the first end of the eighth resistor;

[0036] The second end of the seventh resistor is electrically connected to the second end of the upper bridge switching switch in the second voltage divider switching switch group;

[0037] The second end of the eighth resistor is electrically connected to the PWM generation module;

[0038] The first end of the ninth resistor is electrically connected to the output end of the voltage regulator reference unit; the second end of the ninth resistor is electrically connected to the first end of the tenth resistor and the PWM generation module.

[0039] The second end of the tenth resistor is electrically connected to the second end of the upper bridge switch in the first voltage divider switch group.

[0040] According to a circuit for setting the PWM duty cycle provided by the present invention, the voltage regulation reference unit includes a second switching transistor and an amplifier;

[0041] The first terminal of the second switching transistor is electrically connected to the second power supply;

[0042] The second terminal of the second switching transistor is electrically connected to the first terminal of the amplifier;

[0043] The control terminal of the second switching transistor is electrically connected to the output terminal of the amplifier;

[0044] The second terminal of the amplifier is electrically connected to the reference voltage terminal.

[0045] According to a circuit for setting the PWM duty cycle provided by the present invention, the demand voltage generation unit includes a first switching transistor;

[0046] The first terminal of the first switching transistor is electrically connected to the first power supply.

[0047] The second terminal of the first switching transistor is electrically connected to the external resistor and the first input terminal of the comparison unit.

[0048] The control terminal of the first switching transistor is electrically connected to the first output terminal of the digital logic module.

[0049] According to the present invention, a circuit for setting the duty cycle of a PWM is provided, wherein the PWM generation module includes a first control switch, a second control switch, a third control switch, a fourth control switch, an eleventh resistor, a twelfth resistor, a thirteenth resistor, a comparator, a logic NOT gate, a capacitor, and a controlled resistor.

[0050] The positive terminal of the first control switch is connected to the third power supply. The negative terminal of the first control switch is connected to the first end of the controlled resistor and the positive terminal of the second control switch. The negative terminal of the second control switch is grounded. The second end of the controlled resistor is connected to the positive terminal of the capacitor and the non-inverting input terminal of the comparator. The first end of the eleventh resistor is connected to the third power supply. The second end of the eleventh resistor is connected to the first end of the twelfth resistor and the positive terminal of the third control switch. The negative terminal of the third control switch is connected to the inverting input terminal of the comparator. The second end of the twelfth resistor is connected to the positive terminal of the fourth control switch and the first end of the thirteenth resistor. The second end of the thirteenth resistor is grounded. The negative terminal of the fourth control switch is connected to the inverting input terminal of the comparator. The output of the comparator is connected to the input terminal of the NOT gate. The output terminal of the NOT gate outputs a PWM signal.

[0051] On the other hand, the present invention also provides a method for setting the PWM duty cycle, which is applied to a circuit for setting the PWM duty cycle as described in any of the preceding claims, the method comprising:

[0052] By setting the resistance value of the external resistor, the demand voltage generation unit generates the demand voltage and sends it to the first input terminal of the comparison unit.

[0053] The voltage selection signal is output through the digital logic module, so that the voltage selection module outputs a voltage corresponding to the voltage selection signal and sends it to the second input terminal of the comparison unit;

[0054] The comparison unit compares the voltage corresponding to the voltage selection signal with the required voltage and sends the comparison result to the logic control module.

[0055] The comparison result is converted into a digital signal and sent to the digital logic module through the logic control module.

[0056] The digital logic module generates control signals for the demand voltage generation unit, voltage selection signals for the voltage selection module, and logic level signals for the PWM generation module based on the digital signals. This allows the PWM generation module to set the duty cycle by changing the charging current and discharging current under the influence of the logic level signals.

[0057] On the other hand, the present invention also provides a power management system, which includes a circuit for setting the PWM duty cycle as described in any of the preceding claims.

[0058] The circuit and method for setting the PWM duty cycle and the power management system provided by this invention generate a demand voltage for a certain scenario through a demand voltage generation unit. After comparing the demand voltage with the voltage provided by the voltage selection module using a comparison unit, the logic control module analyzes the comparison result and generates a digital signal. Then, the digital logic module determines the range of the demand voltage and finally obtains the logic level signal corresponding to the demand voltage, which is sent to the PWM generation module. The PWM generation module sets the duty cycle by changing the charging current and discharging current under the action of the logic level signal. This reduces interference from power fluctuations and signal noise, improves the control accuracy of the duty cycle, and allows different demand duty cycles to be set by adjusting the external resistor. The design is simple and highly integrated. Attached Figure Description

[0059] To more clearly illustrate the technical solutions in this invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0060] Figure 1 This is a schematic diagram of the circuit for setting the PWM duty cycle provided in an embodiment of the present invention;

[0061] Figure 2 yes Figure 1 A schematic diagram of the medium voltage selection module;

[0062] Figure 3 This is a schematic diagram illustrating the specific implementation logic of voltage selection;

[0063] Figure 4 This is a schematic diagram of the simulation results of the circuit for setting the PWM duty cycle using the present invention;

[0064] Figure 5 This is a flowchart illustrating the method for setting the PWM duty cycle provided in an embodiment of the present invention;

[0065] Figure 6 yes Figure 1 A schematic diagram of the PWM generation module;

[0066] Figure 7 yes Figure 6 The circuit for adjusting the controlled resistor RX. Detailed Implementation

[0067] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0068] In this invention, the first terminal can be the drain and the second terminal can be the source, or the first terminal can be the source and the second terminal can be the drain. In cases where MOSFETs with opposite polarities are used or where the current direction changes during circuit operation, the functions of the "source" and "drain" are sometimes interchanged. Therefore, in this disclosure, the "source" and "drain" can be interchanged.

[0069] Figure 1 This is a schematic diagram of the circuit for setting the PWM duty cycle provided in an embodiment of the present invention.

[0070] like Figure 1 As shown, the circuit for setting the PWM duty cycle provided in this embodiment of the invention may include a comparison module 11, a logic control module 12, a digital logic module 13, a voltage selection module 14, and a PWM generation module 15; wherein, the comparison module 11 includes a demand voltage generation unit 111 and a comparison unit COMP.

[0071] See Figure 1 The first terminal of the demand voltage generation unit 111 is electrically connected to the first power supply VDD1, the second terminal of the demand voltage generation unit 111 is electrically connected to the SET pin of the system chip and the first input terminal of the comparator unit COMP, and the third terminal of the demand voltage generation unit 111 is electrically connected to the first output terminal of the digital logic module 13; the SET pin of the system chip is electrically connected to the external resistor R; wherein, the first input terminal of the comparator unit COMP can be an inverting input.

[0072] The second input terminal of the comparison unit COMP is electrically connected to the output terminal of the voltage selection module 14, and the output terminal of the comparison unit COMP is electrically connected to the input terminal of the logic control module 12; wherein, the second input terminal of the comparison unit COMP can be a non-inverting terminal.

[0073] The output terminal of the logic control module 12 is electrically connected to the input terminal of the digital logic module 13;

[0074] The second output terminal of the digital logic module 13 is electrically connected to the input terminal of the voltage selection module 14, and the third output terminal of the digital logic module 13 is electrically connected to the PWM generation module 15.

[0075] In one specific implementation, the demand voltage generation unit 111 is configured to generate a demand voltage based on the external resistor R and send it to the first input terminal of the comparison unit COMP.

[0076] Specifically, when the external resistor R is connected to the second terminal of the demand voltage generation unit 111, the demand voltage generation unit 111 is turned on, and the first power supply VDD1, the demand voltage generation unit 111 and the external resistor R form a circuit, so that the second terminal of the demand voltage generation unit 111 generates the demand voltage and sends it to the first input terminal of the comparison unit COMP.

[0077] The demand voltage generation unit 111 may include a first switching transistor M1; the first end of the first switching transistor M1 is connected to the first power supply VDD1; the second end of the first switching transistor M1 is electrically connected to the external resistor R and the first input terminal of the comparison unit COMP; and the control terminal of the first switching transistor M1 is electrically connected to the first output terminal of the digital logic module 13.

[0078] In a specific implementation process, a closed loop is formed between the comparison unit COMP, the logic control module 12, the digital logic module 13 and the voltage selection module 14. After the voltage selection module 14 outputs different voltages multiple times, the specific range of the required voltage can be determined. Finally, the digital logic module 13 outputs the logic level signal of the PWM generation module 15 corresponding to the required voltage.

[0079] Specifically, each time the second output terminal of the digital logic module 13 inputs a voltage selection signal to the voltage selection module 14, the voltage selection module 14 can output the voltage of the voltage selection signal to the second terminal of the comparison unit COMP. Then, the comparison unit COMP compares the voltage of the voltage selection signal with the required voltage, obtains the comparison result, and sends it to the logic control module 12. The logic control module 12 analyzes the comparison result and converts it into a digital signal, which is then sent to the digital logic module 13. When the digital logic module 13 determines the range of the required voltage based on the received digital signal, it generates a control signal for the required voltage generation unit 111, causing the required voltage generation unit 111 to disconnect, thereby reducing the power consumption of the power management system during actual operation. Additionally, it generates a voltage selection signal for the system chip, enabling the system chip to adjust its duty cycle based on the voltage selection signal.

[0080] The digital logic module outputs the final duty cycle adjustment information, presented as a logic control level signal. This signal is then sent to other modules in the system for further processing. This level signal acts as a switching signal, controlling the gate of the MOSFET, enabling it to turn on or off, thereby further controlling the current signal. This current is used to generate the pulse width for adjusting the duty cycle. Specifically, based on the basic formula for capacitor charging and discharging, I*T = C*V, where I represents current, T represents time, C represents capacitance, and V represents voltage, changing I, under otherwise constant conditions, will change the total period T. When the total period T changes, the duty cycle can be changed, thus enabling the system chip to ultimately control the duty cycle.

[0081] Figure 2 yes Figure 1 A schematic diagram of the medium voltage selection module is shown below. Figure 2 As shown, the voltage selection module 14 in this embodiment may include a voltage regulator reference unit 141, a voltage divider switching unit 142, and a resistor network voltage divider unit 143.

[0082] The input terminal of the voltage regulator reference unit 141 is electrically connected to the second power supply VDD2, and the output terminal of the voltage regulator reference unit 141 is electrically connected to the first terminal of the voltage divider switching unit 142 and the first terminal of the resistor network voltage divider unit 143.

[0083] The second terminal of the voltage divider switching unit 142 is electrically connected to the ground terminal; the third terminal of the voltage divider switching unit 142 is electrically connected to the second terminal of the resistor network voltage divider unit 143; and the fourth terminal of the voltage divider switching unit 142 is electrically connected to the digital logic module 13.

[0084] The third terminal of the resistor network voltage divider unit 143 is electrically connected to the ground terminal;

[0085] In one specific implementation, the voltage divider switching unit 142 is configured to follow the voltage selection signal of the second output terminal of the digital logic module 13, switch the resistance path of the resistor network voltage divider unit 143, and output the voltage corresponding to the voltage selection signal.

[0086] Specifically, the voltage divider switching unit 142 includes multiple parallel voltage divider switching switch groups, each voltage divider switching switch group including an upper bridge switching switch and a lower bridge switching switch;

[0087] The first terminal of the upper bridge switch is electrically connected to the output terminal of the voltage regulator reference unit 141, the second terminal of the upper bridge switch is electrically connected to the first terminal of the lower bridge switch and the resistor network voltage divider unit 143, and the control terminal of the upper bridge switch and the control terminal of the lower bridge switch are electrically connected to the digital logic module 13.

[0088] The second terminal of the lower bridge switching switch is electrically connected to the grounding terminal.

[0089] In one specific implementation, the multiple parallel voltage divider switching groups are configured such that: if the upper bridge switching switch of the current voltage divider switching group is turned on, the lower bridge switching switch of the current voltage divider switching group is turned off; the on / off state of the upper bridge switching switches of the remaining voltage divider switching groups is determined by the comparison result between the output voltage Vout of the voltage selection module 14 and the required voltage Vpxfr; the lower bridge switching switches of the remaining voltage divider switching groups follow the result of the upper bridge switching. In this way, the resistor path of the resistor network voltage divider unit 143 can be switched according to the voltage selection signal of the second output terminal of the digital logic module 13, and the voltage corresponding to the output voltage selection signal can be output.

[0090] See Figure 2 In this embodiment, the voltage divider switching unit 142 may include a first voltage divider switching switch group, a second voltage divider switching switch group, a third voltage divider switching switch group, and a fourth voltage divider switching switch group. The first terminal of the upper bridge switching switch in the first voltage divider switching switch group, the first terminal of the upper bridge switching switch in the second voltage divider switching switch group, the first terminal of the upper bridge switching switch in the third voltage divider switching switch group, and the first terminal of the upper bridge switching switch in the fourth voltage divider switching switch group are electrically connected to the output terminal of the voltage regulator reference unit 141. Wherein, as... Figure 2 As shown, the upper bridge switch of the first voltage divider switching group can be designated as the third switch M3, and the lower bridge switch of the first voltage divider switching group can be designated as the fourth switch M4. The upper bridge switch of the second voltage divider switching group can be designated as the fifth switch M5, and the lower bridge switch of the second voltage divider switching group can be designated as the sixth switch M6. The upper bridge switch of the third voltage divider switching group can be designated as the seventh switch M7, and the lower bridge switch of the third voltage divider switching group can be designated as the eighth switch M8. The upper bridge switch of the fourth voltage divider switching group can be designated as the ninth switch M9, and the lower bridge switch of the fourth voltage divider switching group can be designated as the tenth switch M10. Each switch can be a MOSFET.

[0091] The second terminal of the upper bridge switch (M3) in the first voltage divider switch group is electrically connected to the first terminal of the lower bridge switch (M4) in the first voltage divider switch group; the second terminal of the upper bridge switch (M5) in the second voltage divider switch group is electrically connected to the first terminal of the lower bridge switch (M6) in the second voltage divider switch group; the second terminal of the upper bridge switch (M7) in the third voltage divider switch group is electrically connected to the first terminal of the lower bridge switch (M8) in the third voltage divider switch group; and the second terminal of the upper bridge switch (M9) in the fourth voltage divider switch group is electrically connected to the first terminal of the lower bridge switch (M10) in the fourth voltage divider switch group.

[0092] The second terminal of the lower bridge switch (M4) in the first voltage divider switch group, the second terminal of the lower bridge switch (M6) in the second voltage divider switch group, the second terminal of the lower bridge switch (M8) in the third voltage divider switch group, and the second terminal of the lower bridge switch (M10) in the fourth voltage divider switch group are electrically connected to the ground terminal.

[0093] See also Figure 2 The resistor network voltage divider unit 143 may include a first resistor R1 to a tenth resistor R10;

[0094] The first end of the first resistor R1 is electrically connected to the output terminal of the voltage regulator reference unit 141; the second end of the first resistor R1 is electrically connected to the ground terminal.

[0095] The first end of the second resistor R2 is electrically connected to the output end of the voltage regulator reference unit 141; the second end of the second resistor R2 is electrically connected to the first end of the third resistor R3 and the first end of the fourth resistor R4.

[0096] The second end of the third resistor R3 is electrically connected to the second end of the upper bridge switching switch in the fourth voltage divider switching switch group;

[0097] The second end of the fourth resistor R4 is electrically connected to the first end of the fifth resistor R5 and the first end of the sixth resistor R6.

[0098] The second end of the fifth resistor R5 is electrically connected to the second end of the upper bridge switching switch in the third voltage divider switching switch group;

[0099] The second end of the sixth resistor R6 is electrically connected to the first end of the seventh resistor R7 and the first end of the eighth resistor R8.

[0100] The second end of the seventh resistor R7 is electrically connected to the second end of the upper bridge switching switch in the second voltage divider switching switch group;

[0101] The second terminal of the eighth resistor R8 is electrically connected to the PWM generation module;

[0102] The first end of the ninth resistor R9 is electrically connected to the output end of the voltage regulator reference unit 141; the second end of the ninth resistor R9 is electrically connected to the first end of the tenth resistor R10 and the PWM generation module.

[0103] The second end of the tenth resistor R10 is electrically connected to the second end of the upper bridge switch in the first voltage divider switch group.

[0104] In one specific implementation, the voltage regulator reference unit 141 includes a second switch M2 and an amplifier OP;

[0105] The first terminal of the second switching transistor M2 is electrically connected to the second power supply VDD2 (the voltage provided by VDD2 may be the same as or different from the voltage provided by the first power supply VDD1);

[0106] The second terminal of the second switching transistor M2 is electrically connected to the first terminal of the amplifier OP;

[0107] The control terminal of the second switching transistor M2 is electrically connected to the output terminal of the amplifier OP;

[0108] The second terminal of the amplifier OP is electrically connected to the reference voltage terminal. The amplifier OP functions as a buffer to stabilize the voltage. The non-inverting input terminal of the amplifier OP is connected to the reference voltage Vref, which is generated by the system reference voltage.

[0109] In a specific implementation, the working principle of the circuit for setting the PWM duty cycle in this embodiment is as follows:

[0110] The control signals K1 / K1_ / K2 / K2_ / K3 / K3_ / K4 / K4_ corresponding to each switch in the voltage selection module 14 originate from the digital logic module 13 and are fixed clock pulse signals. Within a fixed time period, the conduction time of K1 / K2 / K3 / K4 (K1_K2_K3_K4_ are the inverses of K1, K2, K3, and K4, respectively) is different. After feedback through the loop amplifier OP, the voltage value output by the voltage selection module 14 is different at different times. Figure 1Different resistances to ground (i.e., external resistance R) of the SET pin of the system chip can result in different required voltages Vpxfr. That is, the voltage corresponding to the SET pin of the system chip is the required voltage Vpxfr. Thus, the required voltage Vpxfr is different in different scenarios. I1 is a fixed current source generated inside the system chip. The voltage Vout output by the output terminal of the voltage selection module 14 is compared with the required voltage Vpxfr to obtain a comparison result. Under normal conditions, there are only two results: larger or smaller. However, they are distinguished according to time. The comparison result of the comparison unit COMP is output to the logic control module 12. The logic control module 12 is only used to identify the comparison result of the previous stage and output this comparison result to the logic control module 12. After processing in the logic control module 12, the control K1 / K2 / K3 / K4 is output again to complete the closed loop.

[0111] In this system, the control signal C1 at the control terminal of the first switching transistor M1 originates from the logic control module 12. Its main function is a one-time operation: after the circuit setting the PWM duty cycle is started, the control signal C1 at the control terminal of the first switching transistor M1 controls a series of detections to be initiated and provide results. This process operates within a fixed time period, and after completion, the detection system is shut down to reduce energy consumption. In other words, when the digital logic module 13 starts, it begins timing and generates the on signal of the demand voltage generation unit 111 as the control signal; when the digital logic module 13 receives the logic level signal from the PWM generation module, it stops timing and generates the off signal of the demand voltage generation unit 111 as the control signal to reduce energy consumption.

[0112] For example, the specific implementation of voltage selection module 14 is as follows: the amplifier OP stabilizes the voltage, i.e., V2 = Vref; when signal K1 indicates conduction, the third switch M3 is turned on. At this time, the fourth switch M4 is turned off, the fifth switch M5, the seventh switch M7, and the ninth switch M9 are turned off, and the sixth switch M6, the eighth switch M8, and the tenth switch M10 are turned on, thus obtaining the value of the first voltage Vout. The relationship between the value of the first voltage Vout and V2 can be expressed by the following formula:

[0113]

[0114] in,

[0115]

[0116] When the K2 signal indicates that the circuit is on, the fifth switch M5 is turned on and the sixth switch M6 is turned off. At this time, the third switch M3, the seventh switch M7, and the ninth switch M9 are turned off, while the fourth switch M4, the eighth switch M8, and the tenth switch M10 are turned on, resulting in the second voltage Vout. The specific relationship between Vout and V2 can be represented by different voltage divider resistors, which will not be explained here.

[0117] When the K3 signal indicates that the circuit is on, the seventh switch M7 is on and the eighth switch M8 is off. At this time, the third switch M3, the fifth switch M5, and the ninth switch M9 are off, while the fourth switch M4, the sixth switch M6, and the tenth switch M10 are on, resulting in the third voltage Vout. Its specific relationship with V2 can be represented by different voltage divider resistors, which will not be explained here.

[0118] When the K4 signal indicates that the circuit is on, the ninth switch M9 is on and the tenth switch M10 is off. At this time, the third switch M3, the fifth switch M5, and the seventh switch M7 are off, while the fourth switch M4, the sixth switch M6, and the eighth switch M8 are on, resulting in the fourth voltage Vout. The specific relationship between Vout and V2 can be represented by different voltage divider resistors, which will not be explained here.

[0119] It should be noted that the above example is only illustrated with only one of K1-K4 being on. In actual applications, during the i-th selection, the Ki signal indicates on, while whether the Kj signal indicates on depends on the comparison between the output voltage Vout of the voltage selection module 14 and the required voltage Vpxfr. i = 1, 2, 3, 4, j = 1, 2, 3, 4, and j ≠ i.

[0120] Suppose that in a certain scenario, after adding an external resistor R, the voltage at pin SET is 400mV. During the first detection, signal K1 indicates conduction, and the voltage Vout is approximately 600mV. It is determined that Vpxfr < Vout, and this result is output to digital logic module 13 via logic control module 12. At this time, the processed logic control can detect and adjust the required voltage Vpxfr range to 0 to 600mV. During the second detection, signal K2 indicates conduction, and the voltage Vout is controlled to approximately 300mV. At this time, Vpxfr > Vout, and the result is again output to digital logic module 13. After processing, it is fed back to the detection module, where the processed logic control can detect and adjust the required voltage Vpxfr range to 300 to 600mV. During the third detection... During the test, signal K3 indicates conduction and can control the voltage Vout value to approximately 450mV. Since Vpxfr < Vout, the required voltage Vpxfr range is determined to be 300 to 450mV. During the fourth test, signal K4 indicates conduction and can control the voltage Vout range to be between 300mV and 450mV, such as 375mV. Since Vpxfr > Vout, the required voltage Vpxfr range is determined to be 375 to 450mV. This is very close to the actual 400mV. Therefore, the logic level signal corresponding to 400mV can be obtained and sent to the PWM generation module. Under the influence of the logic level signal, the PWM generation module 15 sets the duty cycle by changing the charging current and discharging current, outputting the power required for this scenario.

[0121] Figure 3 This is a schematic diagram illustrating the specific implementation logic of voltage selection, such as... Figure 3 As shown, the power control is specifically achieved by changing the control signals K1, K2, K3, and K4; Figure 3 In this context, the 0000 digital control signal is represented by switches K1K2K3K4. Initially, assuming K1K2K3K4 = 0000, when the first clock signal arrives (generated by digital logic module 13), K1K2K3K4 = 1000. The output voltage Vout is compared with the required voltage Vpxfr. The voltage Vout changes with the logic control signal, which is provided by digital logic module 13. The increase or decrease of voltage Vout indirectly gives the approximate value of the required voltage Vpxfr. Although the required voltage Vpxfr remains unchanged, the comparison object changes. The comparison result generates an output based on the change of the comparison object, ultimately providing a unique voltage selection result, namely the logic level signal corresponding to the required voltage Vpxfr.

[0122] The logic control signals are 4-bit binary codes:

[0123] Upon the first trigger, the first bit becomes high, outputting 1000, corresponding to a voltage Vout; the voltage Vout is compared with the required voltage Vpxfr, and the system waits for the second trigger.

[0124] When triggered a second time, the second bit becomes a high bit, and the comparison result after the first trigger is displayed in the first bit; for example, if Vpxfr > Vout, the first bit is high and the output is 1100; if Vpxfr < Vout, the first bit is low and the output is 0100; Vout is the updated Vout this time, and the comparison unit COMP is the updated COMP this time.

[0125] When triggered for the third time, the third bit becomes a high bit, and the comparison result after the second bit trigger is displayed in the second bit, the same principle as above;

[0126] When triggered for the fourth time, the fourth bit becomes the high bit, and the comparison result after the third bit trigger result is displayed in the third bit, the same principle as above;

[0127] It should be noted that although this embodiment uses four triggers as an example, in actual applications, it is not necessary to complete four triggers. It is sufficient to determine the value of the required voltage Vpxfr within a finite number of triggers, and then stop once the logic level signal corresponding to the required voltage Vpxfr is generated. For example, in the above example, after completing three triggers, the required voltage Vpxfr has been determined to be between 300mV and 450mV, and is already close to 400mV, so the process can stop, and a fourth trigger is not performed.

[0128] Figure 4 This is a simulation result diagram of the circuit for setting the PWM duty cycle using the present invention. Vpxfr is the voltage signal generated after flowing through the SET pin's ground resistor; X119_y, x115_y, x110_y, and x122_y signals are digital control signals generated by the digital logic module, which are input to the logic control module after comparing the voltage generated by the voltage selection module with a reference; p2070_s signal is the voltage signal output by the voltage selection module; x1887_a signal is the comparison result signal of the comparator module; and x1906_y signal is the overall control signal for the voltage selection module.

[0129] Figure 4After the basic modules such as the reference voltage and reference current of the chip system are established, the system is enabled. Vpxfr and p2070_s are compared for the first time after enabling, resulting in the x1887_a signal output being low. Subsequently, the digital logic module generates control signals x119_y, x115_y, x110_y, and x122_y, all equal to 1000. Simultaneously, combined with the previous comparison result Vpxfr > Vout, the voltage selection module's output signal p2070_s also changes at this point. A further comparison is reflected in the next signal generated by the digital logic module, resulting in an output of 1100. Subsequently, if Vpxfr < Vout, the x1887_a signal changes, and the digital logic module responds accordingly, with the next output being 1010. If the comparison result is Vpxfr > Vout, the x1887_a signal changes, and the digital logic module responds accordingly, with the next output being 1001. The final comparison result is Vpxfr < Vout, and the x1887_a signal reacts accordingly. Since the system does not need to continue classification, the outputs x119_y, x115_y, x110_y, and x122_y signals remain at the previous state of 1001. This process can be compared with... Figure 3 The processes in the above steps corroborate each other; once the above actions are completed, the x1906_y signal goes low, which will disable the above series of functions, but the enable signal will still work, so normal digital signal output can be maintained, greatly reducing power consumption.

[0130] The circuit for setting the PWM duty cycle in this embodiment generates a required voltage for a specific scenario through a required voltage generation unit 111. The required voltage is then compared with the voltage provided by the voltage selection module 14 using a comparison unit COMP. The logic control module 12 analyzes the comparison result and generates a digital signal. The digital logic module 13 then determines the range of the required voltage and finally obtains the corresponding logic level signal, which is sent to the PWM generation module. The PWM generation module then sets the duty cycle by changing the charging and discharging currents under the influence of the logic level signal. This reduces interference from power supply fluctuations and signal noise, improving the control accuracy of the duty cycle. Furthermore, different required duty cycles can be set by adjusting the external resistor R. The design is simple and highly integrated.

[0131] Based on the same general inventive concept, this invention also protects a method for setting the PWM duty cycle. The method for setting the PWM duty cycle provided by this invention will be described below. The method for setting the PWM duty cycle described below is applied to the circuit for setting the PWM duty cycle described above.

[0132] Figure 5This is a flowchart illustrating a method for setting the PWM duty cycle according to an embodiment of the present invention. The method for setting the PWM duty cycle may include:

[0133] 501. By setting the resistance value of the external resistor, the demand voltage generation unit generates the demand voltage and sends it to the first input terminal of the comparison unit;

[0134] 502. A voltage selection signal is output through the digital logic module, so that the voltage selection module outputs a voltage corresponding to the voltage selection signal and sends it to the second input terminal of the comparison unit;

[0135] 503. The voltage corresponding to the voltage selection signal is compared with the required voltage by the comparison unit, and the comparison result is sent to the logic control module;

[0136] 504. The comparison result is converted into a digital signal and sent to the digital logic module through the logic control module;

[0137] 505. The digital logic module generates the control signal of the demand voltage generation unit, the voltage selection signal of the voltage selection module, and the logic level signal of the PWM generation module according to the digital signal, so that the PWM generation module sets the duty cycle by changing the charging current and the discharging current under the action of the logic level signal.

[0138] In a specific implementation, the above method for setting the PWM duty cycle can also include the following operations:

[0139] When the digital logic module starts, it begins timing and generates an on signal for the demand voltage generation unit as the control signal. When the digital logic module receives the logic level signal, it stops timing and generates an off signal for the demand voltage generation unit as the control signal. This one-time action reduces power consumption during actual chip operation.

[0140] Figure 6 yes Figure 1 A schematic diagram of the PWM generation module is shown below. Figure 6As shown, the circuit connection of the PWM generation module is as follows: The positive terminal of the first control switch K5 is connected to the third power supply VDD3; the negative terminal of the first control switch K5 is connected to the first terminal of the controlled resistor RX and the positive terminal of the second control switch K6; the negative terminal of the second control switch K6 is grounded; the second terminal of the controlled resistor RX is connected to the positive terminal of the capacitor C and the non-inverting input terminal of the comparator U1; the first terminal of the eleventh resistor R11 is connected to the third power supply VDD3; the second terminal of the eleventh resistor R11 is connected to the first terminal of the twelfth resistor R12 and the positive terminal of the third control switch K7; the negative terminal of the third control switch K7 is connected to the inverting input terminal of the comparator U1; the second terminal of the twelfth resistor R12 is connected to the positive terminal of the fourth control switch K8 and the first terminal of the thirteenth resistor R13; the second terminal of the thirteenth resistor R13 is grounded; the negative terminal of the fourth control switch K8 is connected to the inverting input terminal of the comparator U1; the output of the comparator U1 is connected to the input terminal of the NOT gate U2; and the output terminal of the NOT gate U2 outputs the PWM signal. The voltage provided by the third power supply VDD3 can be the same as or different from the voltage provided by the first power supply VDD1 and the voltage provided by the second power supply VDD2.

[0141] The controlled resistor RX is affected by the output of the digital logic control module. When the external resistor R connected to the SET pin changes, after the aforementioned actions, a unique logic level signal is generated. This logic level signal controls the change of the controlled resistor RX, which can generate two different resistance values: RC during charging and RD during discharging. The specific process of generating the PWM wave is as follows: When the voltage VC is small, the PWM output is high, K5 is turned on, and K6 is turned off. At this time, I will be generated. C Charging capacitor C generates voltage VC, specifically... When VC > V2, an output control signal is sent to close switch K5 and open switch K6. At this time, VC will discharge, and the specific discharge current will be... When RC and RD change, the corresponding I c and I d It will also change. According to I*T=C*V, the corresponding T will change, and finally a PWM wave with the duty cycle set according to the external resistor R connected to the pin SET can be generated.

[0142] Figure 6 V3 and V4 are voltage dividers for the third power supply VDD3, where the voltage of the third power supply VDD3 can be denoted as VDD. Assuming the voltage divider resistors have the same value, then V3 = 2 / 3 VDD and V4 = 1 / 3 VDD. At startup, the voltage across capacitor C is low, VC is low, comparator U1 outputs a control signal, K5 and K7 are turned on, K6 and K8 are turned off, and the current I... cWhen capacitor C is charged, VC is compared with V2. When VC is greater than V2, comparator U1 outputs a control signal, K6 and K8 turn on, K5 and K7 turn off, and capacitor C discharges with a discharge current of I. d When the voltage of VC drops to V4 through discharge, comparator U1 continues to operate. That is, VC charges from V1 to V2, then discharges to V4, and then charges again to V3, repeating this process to generate a PWM signal. This signal is output through the NOT gate U2. Therefore, the average voltage of VC is (V3+V4) / 2 = 1 / 2VDD. During charging, according to I... c *T c =C*V,I c For the charging current, T c For a charging cycle, C is the capacitance value, and V is the average charging current; at this time, T c =C*V / I c The average current V = 1 / 2VDD and After substituting, we get T. c =C*RX C Similarly, we can obtain T d =C*RX d Then the total period of the PWM is T = T c +T d At this point, the controlled resistor RX directly determines the duty cycle of the PWM.

[0143] Figure 7 yes Figure 6 The circuit for adjusting the controlled resistor RX, where K1, K2, K3, and K4 are generated by the digital logic module, is connected to... Figure 2 K1, K2, K3, and K4 are the same signal. Changes in this control signal control the switching on and off of the switch, thus determining the resistance change of the controlled resistor RX. Through K1, K2, K3, K4, and... Figure 7 The resistance values ​​of the fourteenth resistor R14 to the seventeenth resistor R17 can be adjusted.

[0144] Furthermore, the present invention also provides a power management system, which includes the circuit for setting the PWM duty cycle of the above embodiments. The circuit embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without creative effort.

[0145] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus necessary general-purpose hardware platforms, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions, in essence or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in the various embodiments or some parts of the embodiments.

[0146] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A circuit for setting the PWM duty cycle, characterized in that, It includes a comparison module, a logic control module, a digital logic module, a voltage selection module, and a PWM generation module; wherein, the comparison module includes a demand voltage generation unit and a comparison unit; The first terminal of the demand voltage generation unit is electrically connected to the first power supply; the second terminal of the demand voltage generation unit is electrically connected to the pin of the system chip and the first input terminal of the comparison unit; the third terminal of the demand voltage generation unit is electrically connected to the first output terminal of the digital logic module; and the pin of the system chip is electrically connected to an external resistor. The second input terminal of the comparison unit is electrically connected to the output terminal of the voltage selection module, and the output terminal of the comparison unit is electrically connected to the input terminal of the logic control module. The output terminal of the logic control module is electrically connected to the input terminal of the digital logic module; The second output terminal of the digital logic module is electrically connected to the input terminal of the voltage selection module, and the third output terminal of the digital logic module is electrically connected to the PWM generation module. The voltage selection module follows the voltage selection signal at the second output terminal of the digital logic module and outputs the voltage corresponding to the voltage selection signal; The comparison unit compares the voltage corresponding to the voltage selection signal with the demand voltage generated by the demand voltage generation unit, and converts the comparison result into a digital signal via the logic control module. The digital logic module generates the control signal for the demand voltage generation unit, the voltage selection signal for the voltage selection module, and the logic level signal for the PWM generation module based on the digital signal. The PWM generation module is used to set the duty cycle by changing the charging current and discharging current under the influence of the logic level signal.

2. The circuit for setting the PWM duty cycle according to claim 1, characterized in that, The voltage selection module includes a voltage regulation reference unit, a voltage divider switching unit, and a resistor network voltage divider unit; The input terminal of the voltage regulator reference unit is electrically connected to the second power supply, and the output terminal of the voltage regulator reference unit is electrically connected to the first terminal of the voltage divider switching unit and the first terminal of the resistor network voltage divider unit. The second terminal of the voltage divider switching unit is electrically connected to the ground terminal; the third terminal of the voltage divider switching unit is electrically connected to the second terminal of the resistor network voltage divider unit; and the fourth terminal of the voltage divider switching unit is electrically connected to the digital logic module. The third terminal of the resistor network voltage divider unit is electrically connected to the ground terminal; The voltage divider switching unit is configured to follow the voltage selection signal of the second output terminal of the digital logic module, switch the resistor path of the resistor network voltage divider unit, and output the voltage corresponding to the voltage selection signal.

3. The circuit for setting the PWM duty cycle according to claim 2, characterized in that, The voltage divider switching unit includes multiple parallel voltage divider switching switch groups, each voltage divider switching switch group including an upper bridge switching switch and a lower bridge switching switch; The first terminal of the upper bridge switch is electrically connected to the output terminal of the voltage regulator reference unit, the second terminal of the upper bridge switch is electrically connected to the first terminal of the lower bridge switch and the resistor network voltage divider unit, and the control terminals of the upper bridge switch and the lower bridge switch are electrically connected to the digital logic module. The second terminal of the lower bridge switching switch is electrically connected to the grounding terminal. The plurality of parallel voltage divider switching groups are configured as follows: If the upper bridge switching switch of the current voltage divider switching switch group is turned on, the lower bridge switching switch of the current voltage divider switching switch group is turned off; If the upper bridge switch of the current voltage divider switch group is open, the lower bridge switch of the current voltage divider switch group is open.

4. The circuit for setting the PWM duty cycle according to claim 3, characterized in that, The plurality of parallel voltage divider switching switch groups include a first voltage divider switching switch group, a second voltage divider switching switch group, a third voltage divider switching switch group, and a fourth voltage divider switching switch group; The first terminal of the upper bridge switch in the first voltage divider switch group, the first terminal of the upper bridge switch in the second voltage divider switch group, the first terminal of the upper bridge switch in the third voltage divider switch group, and the first terminal of the upper bridge switch in the fourth voltage divider switch group are electrically connected to the output terminal of the voltage regulator reference unit. The second terminal of the upper bridge switch in the first voltage divider switch group is electrically connected to the first terminal of the lower bridge switch in the first voltage divider switch group; the second terminal of the upper bridge switch in the second voltage divider switch group is electrically connected to the first terminal of the lower bridge switch in the second voltage divider switch group; the second terminal of the upper bridge switch in the third voltage divider switch group is electrically connected to the first terminal of the lower bridge switch in the third voltage divider switch group; the second terminal of the upper bridge switch in the fourth voltage divider switch group is electrically connected to the first terminal of the lower bridge switch in the fourth voltage divider switch group. The second terminal of the lower bridge switch in the first voltage divider switch group, the second terminal of the lower bridge switch in the second voltage divider switch group, the second terminal of the lower bridge switch in the third voltage divider switch group, and the second terminal of the lower bridge switch in the fourth voltage divider switch group are electrically connected to the ground terminal.

5. The circuit for setting the PWM duty cycle according to claim 4, characterized in that, The resistor network voltage divider unit includes a first resistor to a tenth resistor; The first end of the first resistor is electrically connected to the output terminal of the voltage regulator reference unit; the second end of the first resistor is electrically connected to the ground terminal. The first end of the second resistor is electrically connected to the output end of the voltage regulator reference unit; the second end of the second resistor is electrically connected to the first end of the third resistor and the first end of the fourth resistor. The second end of the third resistor is electrically connected to the second end of the upper bridge switching switch in the fourth voltage divider switching switch group; The second end of the fourth resistor is electrically connected to the first end of the fifth resistor and the first end of the sixth resistor; The second end of the fifth resistor is electrically connected to the second end of the upper bridge switching switch in the third voltage divider switching switch group; The second end of the sixth resistor is electrically connected to the first end of the seventh resistor and the first end of the eighth resistor; The second end of the seventh resistor is electrically connected to the second end of the upper bridge switching switch in the second voltage divider switching switch group; The second end of the eighth resistor is electrically connected to the PWM generation module; The first end of the ninth resistor is electrically connected to the output end of the voltage regulator reference unit; the second end of the ninth resistor is electrically connected to the first end of the tenth resistor and the PWM generation module. The second end of the tenth resistor is electrically connected to the second end of the upper bridge switch in the first voltage divider switch group.

6. The circuit for setting the PWM duty cycle according to claim 2, characterized in that, The voltage regulation reference unit includes a second switching transistor and an amplifier; The first terminal of the second switching transistor is electrically connected to the second power supply; The second terminal of the second switching transistor is electrically connected to the first terminal of the amplifier; The control terminal of the second switching transistor is electrically connected to the output terminal of the amplifier; The second terminal of the amplifier is electrically connected to the reference voltage terminal.

7. The circuit for setting the PWM duty cycle according to any one of claims 1-6, characterized in that, The demand voltage generation unit includes a first switching transistor; The first terminal of the first switching transistor is electrically connected to the first power supply. The second terminal of the first switching transistor is electrically connected to the external resistor and the first input terminal of the comparison unit. The control terminal of the first switching transistor is electrically connected to the first output terminal of the digital logic module.

8. The circuit for setting the PWM duty cycle according to any one of claims 1-6, characterized in that, The PWM generation module includes a first control switch, a second control switch, a third control switch, a fourth control switch, an eleventh resistor, a twelfth resistor, a thirteenth resistor, a comparator, a logic NOT gate, a capacitor, and a controlled resistor. The positive terminal of the first control switch is connected to the third power supply. The negative terminal of the first control switch is connected to the first end of the controlled resistor and the positive terminal of the second control switch. The negative terminal of the second control switch is grounded. The second end of the controlled resistor is connected to the positive terminal of the capacitor and the non-inverting input terminal of the comparator. The first end of the eleventh resistor is connected to the third power supply. The second end of the eleventh resistor is connected to the first end of the twelfth resistor and the positive terminal of the third control switch. The negative terminal of the third control switch is connected to the inverting input terminal of the comparator. The second end of the twelfth resistor is connected to the positive terminal of the fourth control switch and the first end of the thirteenth resistor. The second end of the thirteenth resistor is grounded. The negative terminal of the fourth control switch is connected to the inverting input terminal of the comparator. The output of the comparator is connected to the input terminal of the NOT gate. The output terminal of the NOT gate outputs a PWM signal.

9. A method for setting the PWM duty cycle, characterized in that, The method, applied to a circuit for setting the PWM duty cycle as described in any one of claims 1-8, comprises: By setting the resistance value of the external resistor, the demand voltage generation unit generates the demand voltage and sends it to the first input terminal of the comparison unit. The voltage selection signal is output through the digital logic module, so that the voltage selection module outputs a voltage corresponding to the voltage selection signal and sends it to the second input terminal of the comparison unit; The comparison unit compares the voltage corresponding to the voltage selection signal with the required voltage and sends the comparison result to the logic control module. The comparison result is converted into a digital signal and sent to the digital logic module through the logic control module. The digital logic module generates control signals for the demand voltage generation unit, voltage selection signals for the voltage selection module, and logic level signals for the PWM generation module based on the digital signals. This allows the PWM generation module to set the duty cycle by changing the charging current and discharging current under the influence of the logic level signals.

10. A power management system, characterized in that, Includes a circuit for setting the PWM duty cycle as described in any one of claims 1-8.

Images