Adjustable leading edge blanking time generation circuit

Abstract

The invention discloses an adjustable leading edge blanking time generating circuit, which is characterized in that an operational amplifier and a first NMOS (N-channel Metal Oxide Semiconductor) tube form a source follower, and an external resistor is connected to the joint of the negative end of the operational amplifier and the source electrode of the first NMOS tube, so that the reference voltage of the positive end of the operational amplifier follows the external resistor; current generated on the external resistor flows through the capacitor after being mirrored by the current mirror, the capacitor is connected between the drain electrode and the source electrode of the second NMOS tube, one end of the capacitor is connected with the positive end of the comparator, and the negative end of the comparator is connected with reference voltage; and the grid electrode of the second NMOS tube is connected with a grid electrode driving signal of the external MOS tube so as to control the mirror current to charge and discharge the capacitor, and when the voltage of the capacitor exceeds the voltage of the external resistor, the comparator outputs the delay matched with the effective conduction rising time of the external MOS tube, and further outputs the leading edge blanking time in combination with the fixed delay. According to the invention, accurate leading edge blanking delay adjustment is realized by adjusting the external resistance.

Description

TECHNICAL FIELD

[0001] The present application belongs to the field of semiconductor design, and more particularly, relates to a MOS / IGBT tube driving circuit and a motor driving circuit. BACKGROUND

[0002] At present, switching power supply and motor are increasingly applied to industrial production and daily life. In these circuit systems, MOS tubes are usually used as switching tubes, and driving circuits are used to control the conduction and cutoff of the switching tubes. When the MOS is turned on, it works in the linear region, and if the current is too large, the MOS tube will be burned out. The driving circuit needs to detect the working state of the switching tube to avoid overcurrent or saturation. The detection circuit needs to detect the working state of the MOS tube after the MOS tube is effectively turned on and make a working state decision. Different MOS tubes have different input capacitances, input resistances and other device parameters, and different systems have different parasitic inductances, resistances, capacitances and other parameters, which directly affect the conduction time of the MOS tube. Usually, the driving circuit delays for a period of time, that is, the blanking time, after sending a conduction signal to detect the conduction state of the MOS tube and determine whether overcurrent or saturation occurs.

[0003] The prior art uses an internal RC delay circuit to generate a fixed time for the front blanking time, which cannot be adjusted according to the parameters of the external MOS tube and other external driven devices and the parasitic parameters of the system, and the internal RC delay precision is not high, which may cause a decision error and further cause the overcurrent protection or desaturation function to fail. SUMMARY

[0004] To solve at least one of the above technical problems, the present application provides a adjustable front blanking time generating circuit, which realizes accurate front blanking delay adjustment by adjusting an external resistance.

[0005] According to an aspect of the present application, an adjustable front blanking time generating circuit is provided, which comprises a source follower composed of an operational amplifier and a first NMOS tube, an external resistance connected at a connection between a negative terminal of the operational amplifier and a source of the first NMOS tube, so that a reference voltage at a positive terminal of the operational amplifier is followed to the external resistance; a current generated on the external resistance flows through a capacitor after being imaged through a current mirror, the capacitor is connected between a drain and a source of a second NMOS tube and one end of the capacitor is connected to a positive terminal of a comparator, a negative terminal of the comparator is connected to a reference voltage; a gate of the second NMOS tube is connected to a gate drive signal of an external MOS tube to control the charging and discharging of the capacitor by the mirror current, when the voltage of the capacitor exceeds the voltage on the external resistance, the comparator outputs a delay time matching the effective conduction rise time of the external MOS tube, and further outputs the front blanking time in combination with a fixed delay time.

[0006] As a further technical solution, the current mirror is composed of two PMOS tubes, wherein the gate of the first PMOS tube is connected with the gate of the second PMOS tube, the drain and the gate of the first PMOS tube and the gate of the second PMOS tube are respectively connected with the drain of the first NMOS tube, and the drain of the second PMOS tube is connected with the positive terminal of the comparator, the drain of the second NMOS tube and one end of the capacitor.

[0007] As a further technical solution, the size of the second PMOS tube is m times of the first PMOS tube.

[0008] As a further technical solution, the gate drive signal of the external MOS tube is connected to the gate of the second NMOS tube through an inverter.

[0009] As a further technical solution, the fixed delay is greater than the RLC resonance time caused by the parasitic resistance, inductance and capacitance of the system.

[0010] As a further technical solution, the resistance of the external resistance is adjustable.

[0011] As a further technical solution, when the capacitance is fixed, the delay that matches the effective conduction rising time of the external MOS tube and the external resistance is in a linear relationship.

[0012] According to one aspect of the specification of the present application, a MOS / IGBT tube driving circuit is provided, which is configured with the adjustable front porch blanking time generating circuit.

[0013] According to one aspect of the specification of the present application, a motor driving circuit is provided, which is configured with the adjustable front porch blanking time generating circuit.

[0014] Compared with the prior art, the present application has the following beneficial effects: 1. The present application provides an adjustable front porch blanking time generating circuit, which realizes accurate front porch blanking delay adjustment by adjusting the external resistance, and guarantees correct overcurrent or saturation detection.

[0015] 2. The present application is simple and can save chip area. DETAILED DESCRIPTION

[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings used in the embodiments or the prior art description will be briefly described below. Obviously, the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0017] Figure 1 A schematic diagram of an adjustable front porch blanking time generating circuit provided by the embodiments of the present application is shown. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention. In addition, the technical features of the various embodiments or individual embodiments provided by the present invention can be arbitrarily combined to form new technical solutions. Such combinations are not bound by the order of steps and / or structural composition patterns, but must be based on the ability of those skilled in the art to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection claimed by the present invention.

[0019] In existing technologies, the leading-edge blanking time is generated by an internal RC delay circuit, which is a fixed time and cannot be adjusted according to the parameters of external driven devices such as external MOSFETs, or system parasitic parameters. Furthermore, the internal RC delay accuracy is not high, leading to decision errors and consequently causing overcurrent protection or desaturation function failure. Based on this situation, this invention proposes an adjustable leading-edge blanking time generation circuit to solve the following problems: 1. The leading-edge blanking time can be adjusted according to external driven devices, which may include characteristic parameters such as the parasitic capacitance of external MOSFETs, and the series resistance of the external MOSFET gate in the driving circuit; 2. The leading-edge blanking time is made more accurate.

[0020] The present invention aims to achieve precise leading-edge blanking delay adjustment through the simple method of adjusting an external resistor. Based on parameters such as MOSFET device parameters and system parasitic parameters, the MOSFET's turn-on time and resonant jitter time are calculated. Using a delay algorithm, the blanking time is flexibly adjusted to match the effective turn-on time of the MOSFET. The blanking time generation circuit provided by this invention is suitable for MOSFET / IGBT drive circuits and motor drive circuits.

[0021] like Figure 1As shown, this embodiment of the invention provides an adjustable leading-edge blanking time generation circuit, which consists of an operational amplifier and a first NMOS transistor MN1 forming a source follower. An external resistor R1 is connected at the point where the negative terminal of the operational amplifier is connected to the source of the first NMOS transistor MN1, so that the reference voltage VREF at the positive terminal of the operational amplifier follows the external resistor R1. The current generated on the external resistor R1 flows through a capacitor C1 after being mirrored by a current mirror. The capacitor C1 is connected between the drain and source of the second NMOS transistor MN2, and one end of it is connected to the positive terminal of a comparator. The negative terminal of the comparator is connected to the reference voltage VREF. The gate of the second NMOS transistor MN2 is connected to the gate drive signal GHA of the external MOS transistor to control the charging and discharging of the mirrored current on the capacitor C1. When the voltage of the capacitor C1 exceeds the voltage on the external resistor R1, the comparator outputs a delay that matches the effective turn-on rise time of the external MOS transistor. Combined with a fixed delay, the leading-edge blanking time is further output.

[0022] The current mirror is composed of two PMOS transistors. The gate of the first PMOS transistor MP1 is connected to the gate of the second PMOS transistor MP2. The drain and gate of the first PMOS transistor MP1 and the gate of the second PMOS transistor MP2 are respectively connected to the drain of the first NMOS transistor MN1. The drain of the second PMOS transistor MP2 is connected to the positive terminal of the comparator, the drain of the second NMOS transistor MN2, and one end of the capacitor.

[0023] See Figure 1 The operational amplifier and MN1 form a source follower, making the voltage across the external resistor R1 V. REF The generating circuits I1, MP1, and MP2 form a current mirror, with I2 mirroring I1. GHA controls I2 to charge and discharge C1. When the voltage of C1 exceeds V... REF The comparator outputs a high level, generating a delay T_ADJ controlled by external R1. This delay matches the effective turn-on rise time of the MOSFET. It is superimposed with a fixed 500ns delay inside the chip, which is greater than the RLC resonant time caused by the system's parasitic resistance, inductance, and capacitance. The circuit outputs the final leading-edge blanking time T_BLK.

[0024] GHA controls the charging and discharging of C1 by I2. Specifically, when GHA is high, it charges C1, and when it is low, it discharges C1.

[0025] The specific implementation principle is as follows: The amplifier and MN1 form a source follower, and the voltage across resistor R1 is equal to the reference voltage V at the positive input terminal of the op-amp. REF The current I1 flowing through MP1, MN1, and R1 is: (1) MP1 and MP2 form a current mirror, with MP2 mirroring the current of MP1. The size of MP2 is m times the size of MP1. Therefore, the current I2 flowing through MP2 is: (2) GHA is the gate drive signal for the external MOSFET. When GHA is high, the MOSFET is turned on. As GHA rises, MN2 is turned off, and I2 begins charging capacitor C1. When the voltage across C1 exceeds VREF, the comparator outputs high, generating a delay time T_ADJ equivalent to the rising edge of GHA. T_ADJ is: (3) As shown in the above formula, when the internal capacitance is fixed, T_ADJ is determined by the external resistor R1 and has a linear relationship with R1.

[0026] The final front disappearance time is: (4) Based on the same inventive concept as the foregoing embodiments, this embodiment of the invention also provides a MOS / IGBT driving circuit, configured with the aforementioned adjustable leading-edge blanking time generation circuit. Based on the aforementioned adjustable leading-edge blanking time generation circuit, correct overcurrent or saturation detection can be ensured.

[0027] Based on the same inventive concept as the foregoing embodiments, this embodiment of the invention also provides a motor drive circuit configured with the aforementioned adjustable leading-edge blanking time generation circuit. The adjustable leading-edge blanking time generation circuit ensures accurate overcurrent or saturation detection.

[0028] Any points not elaborated above are common knowledge in this field.

[0029] The terms “comprising” and “having”, and any variations thereof, in the specification, claims, and accompanying drawings of this invention are intended to cover a non-exclusive inclusion, such as a process, method, system, product, or apparatus that includes a series of steps or units, not necessarily limited to those explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0030] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the technical solutions of the embodiments of the present invention.

Claims

1. An adjustable leading-edge blanking time generation circuit, characterized in that, An operational amplifier and a first NMOS transistor form a source follower. An external resistor is connected at the junction of the negative terminal of the operational amplifier and the source of the first NMOS transistor, so that the reference voltage at the positive terminal of the operational amplifier follows the external resistor. The current generated on the external resistor is mirrored by a current mirror and flows through a capacitor. The capacitor is connected between the drain and source of the second NMOS transistor, with one end connected to the positive terminal of a comparator. The negative terminal of the comparator is connected to the reference voltage. The gate of the second NMOS transistor is connected to the gate drive signal of the external MOS transistor to control the charging and discharging of the capacitor by the mirrored current. When the capacitor voltage exceeds the voltage on the external resistor, the comparator outputs a delay that matches the effective turn-on rise time of the external MOS transistor. Combined with a fixed delay, the leading-edge blanking time is further output.

2. The adjustable leading-edge blanking time generation circuit according to claim 1, characterized in that, The current mirror is composed of two PMOS transistors. The gate of the first PMOS transistor is connected to the gate of the second PMOS transistor. The drain and gate of the first PMOS transistor and the gate of the second PMOS transistor are respectively connected to the drain of the first NMOS transistor. The drain of the second PMOS transistor is connected to the positive terminal of the comparator, the drain of the second NMOS transistor, and one end of the capacitor.

3. The adjustable leading-edge blanking time generation circuit according to claim 2, characterized in that, The size of the second PMOS transistor is m times that of the first PMOS transistor.

4. The adjustable leading-edge blanking time generation circuit according to claim 1, characterized in that, The external MOS transistor gate drive signal is connected to the gate of the second NOMS transistor via an inverter.

5. The adjustable leading-edge blanking time generation circuit according to claim 1, characterized in that, The fixed delay is greater than the RLC resonant time caused by the system's parasitic resistance, inductance, and capacitance.

6. The adjustable leading-edge blanking time generation circuit according to claim 1, characterized in that, The resistance value of the external resistor is adjustable.

7. The adjustable leading-edge blanking time generation circuit according to claim 1, characterized in that, When the capacitor is fixed, the effective turn-on rise time of the matched external MOSFET is linearly related to the external resistance.

8. A MOS / IGBT driving circuit, characterized in that, It is equipped with an adjustable leading-edge blanking time generation circuit as described in any one of claims 1-7.

9. A motor drive circuit, characterized in that, It is equipped with an adjustable leading-edge blanking time generation circuit as described in any one of claims 1-7.

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