Substrate selection circuit with function of adjusting threshold voltage of switching tube based on NMOS (N-channel Metal Oxide Semiconductor) switching tube

Abstract

The invention discloses a substrate selection circuit with a switching tube threshold voltage adjusting function based on an NMOS switching tube, and relates to the technical field of integrated circuit switches, the substrate selection circuit comprises the NMOS switching tube and a boost charge pump BOOST, the NMOS switching tube comprises an NMOS switching tube grid electrode, an NMOS switching tube drain electrode, an NMOS switching tube source electrode and an NMOS switching tube substrate, the input end of the NMOS switching tube is connected in parallel with a switch S0 and a switch S1, and the input end of the NMOS switching tube is connected in parallel with the switch S1. A substrate of the NMOS switch tube is connected to one end of the switch S3, a source electrode of the NMOS switch tube is connected with an input signal VIN, the substrate of the NMOS switch tube is connected with the switch S2 and the switch S3 in parallel, an input end of the boost charge pump BOOST is connected with the input signal VIN, and an output end of the boost charge pump BOOST is connected with one end of the switch S0; the NMOS switching tube is used as a switching tube, the on-resistance is reduced compared with the PMOS under the same condition, and the substrate is connected with the output end during conduction, so that the threshold voltage is further reduced, and the on-resistance is reduced.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit switching technology, and more specifically to a substrate selection circuit based on an NMOS switch transistor with adjustable threshold voltage. Background Technology

[0002] With the continuous advancement of integrated circuit switching technology, high speed, small size, and low power consumption have become important design trends. As a key component of integrated circuit switching technology, the switching transistor plays a crucial role in analog switching chips. These chips require the switching transistor to possess characteristics such as low internal resistance, low leakage current, and high speed.

[0003] Chinese patent CN116805872A discloses an analog switching circuit. When the switch is off, the substrate of the switching transistor is controlled by a resistor and a pulse generation circuit to pull up the NMOS switching transistor, causing the PMOS switching transistor to be completely turned off at the substrate, thus eliminating leakage current. However, the circuit uses PMOS instead of NMOS as the switching transistor. NMOS is an N-type channel transistor, and its charge carrier is electrons; PMOS is a P-type channel transistor, and its charge carrier is holes. Electron mobility is generally five to ten times that of hole mobility. Therefore, NMOS has advantages in terms of power loss and switching speed.

[0004] Chinese patent CN117713778A provides an analog switching circuit that solves the risk of leakage current caused by crosstalk at the output and the problem of substrate bias effect by separately providing substrate voltages for the NMOS and PMOS switching transistors. However, the circuit still uses a PMOS transistor as the switching transistor, so it is inferior in terms of loss and switching speed compared to using only an NMOS switching transistor.

[0005] Chinese patent CN107370487A provides a sample-and-hold switch, in which an NMOS transistor is used as the switching transistor. The gate voltage of the switching transistor is obtained by doubling the power supply voltage of the input signal using a boost charge pump. In the operating state, the substrate voltage of the switching transistor is obtained by capacitive coupling of the charge pump output voltage. In the off state, the substrate voltage of the switching transistor is consistent with the chip ground voltage. However, the substrate voltage of the switching transistor, coupled by capacitive coupling, can introduce uncertainty in the substrate voltage due to manufacturing deviations. Summary of the Invention

[0006] In order to overcome the above-mentioned technical problems, the purpose of this invention is to provide a substrate selection circuit based on an NMOS switch with adjustable switch threshold voltage, so as to solve the problem in the prior art that the substrate voltage of the switch is uncertain due to manufacturing deviations caused by capacitive coupling.

[0007] The objective of this invention can be achieved through the following technical solutions:

[0008] Specifically, a substrate selection circuit based on an NMOS switch with adjustable threshold voltage is provided, including an NMOS switch and a boost charge pump BOOST. The NMOS switch includes an NMOS switch gate, an NMOS switch drain, an NMOS switch source, and an NMOS switch substrate. Switches S0 and S1 are connected in parallel to the input terminal of the NMOS switch, and switches S2 and S3 are connected in parallel to the substrate of the NMOS switch (the output terminal is replaced with the substrate). The substrate of the NMOS switch is connected to one end of switch S3. The source of the NMOS switch is connected to the input signal VIN. The input terminal of the boost charge pump BOOST is connected to the input signal VIN, and the output terminal of the boost charge pump BOOST is connected to one end of switch S0.

[0009] As a further aspect of the present invention: the substrate of the NMOS switch is connected to ground via switch S2.

[0010] As a further aspect of the present invention: the substrate of the NMOS switch is connected to the drain of the NMOS switch via switch S3.

[0011] As a further aspect of the present invention: the drain of the NMOS switch is connected to the output signal VOUT.

[0012] As a further aspect of the present invention: the gate of the NMOS switch is connected to ground via switch S1.

[0013] As a further aspect of the present invention: the gate of the NMOS switch is connected to the output terminal of the boost charge pump BOOST via switch S0.

[0014] As a further aspect of the present invention: the voltage threshold of the NMOS switch is calculated using the following formula:

[0015]

[0016] Where V th For the threshold voltage, v t0 Where the bias voltage is zero, and γ is the attenuation coefficient. For the built-in potential, V sb This is the voltage between the source and the base.

[0017] As a further aspect of the present invention: the voltage of the NMOS switch satisfies the formula:

[0018] V ds <<2(V gs -V th );

[0019] Where V dsV is the voltage difference between the drain and source of the NMOS switch. gs V is the voltage difference between the gate and source of the NMOS switch. th This is the threshold voltage.

[0020] As a further aspect of the present invention: the drain current I of the NMOS switch D Calculated using the following formula:

[0021]

[0022] Where I D The drain current of the NMOS switch, μ n C represents the electron mobility of an NMOS switch. OX is the gate oxide capacitance per unit area, W is the gate width of the NMOS switch, and L is the channel length of the NMOS switch.

[0023] As a further aspect of the present invention: the on-resistance R of the NMOS switch transistor on Calculated using the following formula:

[0024]

[0025] Where R on Let v be the on-resistance of the NMOS switch. The electron velocity of the NMOS and PMOS transistors in the NMOS switch is v = μE, where μ is the mobility and E is the electric field strength.

[0026] The beneficial effects of this invention are:

[0027] 1. In this invention, the substrate selection circuit based on the NMOS switch has the ability to adjust the threshold voltage of the switch, which has better transmission characteristics. This is mainly due to the use of NMOS switch as the switch. NMOS has a faster electron mobility, and its on-resistance is reduced compared with PMOS under the same conditions. Furthermore, when it is turned on, the substrate is connected to the output terminal, which further reduces the threshold voltage and reduces the on-resistance.

[0028] 2. In this invention, the substrate selection circuit for adjusting the threshold voltage of the NMOS switch provides better turn-off characteristics. This is mainly due to the fact that when the NMOS switch is off, the substrate of the NMOS switch is connected to ground through the switch S2. Compared with connecting it to the drain, this rapidly increases the threshold voltage of the switch, thereby increasing the on-resistance RON and reducing leakage current. Furthermore, the gate of the NMOS switch is quickly connected to ground through the switch S1, turning off the NMOS switch NM1. Attached Figure Description

[0029] The invention will now be further described with reference to the accompanying drawings.

[0030] Figure 1 This is a schematic diagram of an embodiment of the substrate selection circuit based on an NMOS switch transistor with adjustable threshold voltage provided by the present invention.

[0031] Figure 2 This is a schematic diagram showing the NMOS switch substrate voltage connected to a drain threshold voltage of approximately 723mV;

[0032] Figure 3 This is a schematic diagram showing the NMOS switch substrate connected to ground with a threshold voltage of approximately 1.476V;

[0033] Figure 4 This is a waveform diagram of the substrate selection circuit for adjusting the threshold voltage of the NMOS switch, which is based on the present invention.

[0034] Figure 5 This invention modifies an NMOS to a PMOS of the same size under the same conditions. Detailed Implementation

[0035] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0036] Example 1

[0037] like Figures 1-5 As shown, this invention discloses a substrate selection circuit based on an NMOS switch with adjustable threshold voltage, including an NMOS switch and a boost charge pump BOOST. The NMOS switch includes an NMOS switch gate, an NMOS switch drain, an NMOS switch source, and an NMOS switch substrate. Switches S0 and S1 are connected in parallel to the input terminal of the NMOS switch, and switches S2 and S3 are connected in parallel to the substrate of the NMOS switch. The substrate of the NMOS switch is connected to one end of switch S3, and the source of the NMOS switch is connected to the input signal VIN. The input terminal of the boost charge pump BOOST is connected to the input signal VIN, and the output terminal of the boost charge pump BOOST is connected to one end of switch S0.

[0038] The NMOS switch substrate is connected to ground via switch S2. It should be noted that the NMOS switch substrate is P-type silicon, forming a hole-dominated semiconductor. The NMOS switch substrate is located at the bottom layer of the NMOS switch, serving as the physical support and electrical isolation layer of the MOSFET. The NMOS switch substrate provides structural stability to the NMOS switch, ensuring that the NMOS switch will not deform or be damaged during manufacturing and use. The NMOS switch substrate forms a PN junction with the drain and source of the NMOS switch. Under normal operating conditions, the PN junction is reverse biased to prevent current from flowing from the drain and source of the NMOS switch to the NMOS switch substrate, thus achieving electrical isolation between devices in the NMOS switch. In addition, it should be noted that in integrated circuits, multiple NMOS switches share the same NMOS switch substrate, and isolation between devices is achieved through the reverse biased PN junction. The composition of the NMOS switch substrate directly affects the threshold voltage of the NMOS switch, that is, the minimum gate voltage required by the NMOS switch.

[0039] When there is a voltage difference between the NMOS switch substrate and the NMOS switch source, the threshold voltage will increase, affecting the switching characteristics. Shorting the NMOS switch substrate and the NMOS switch source avoids the NMOS switch substrate bias effect and simplifies the driving circuit.

[0040] The NMOS switch substrate is connected to the drain of the NMOS switch via switch S3. It should be noted that in NMOS switch applications, the NMOS switch substrate is typically shorted to the source to ensure stable operation. When switch S3 is closed, the NMOS switch substrate potential dynamically changes with the drain voltage. In the on-state, the increase in the drain voltage leads to an increase in the NMOS switch substrate potential, causing the voltage difference between the source and substrate to become negative. According to the body effect formula, this lowers the threshold voltage, thereby enhancing the conduction capability. This connection method of the NMOS switch substrate to the drain will... The performance of NMOS switches is affected by multiple dimensions, with the most direct impact being on the threshold voltage. When the drain voltage of an NMOS switch increases, the voltage difference between the negative source and substrate of the NMOS switch will lower the threshold voltage. This characteristic may be advantageous in low-voltage drive scenarios, as it can enhance conduction capability and reduce on-resistance. During dynamic operation, the rapid change in the substrate potential of the NMOS switch can also generate displacement current through junction capacitance coupling. These transient currents may interfere with the normal operation of surrounding circuits. In practical applications, precise timing control is necessary to coordinate the relationship between switch S3 and the gate drive signal of the NMOS switch to avoid substrate potential conflicts.

[0041] When the drain of an NMOS switch is connected to the output signal VOUT, it should be noted that when the gate voltage of the NMOS switch exceeds the threshold voltage, the NMOS switch is turned on, and a low-resistance path is formed between the drain and source of the NMOS switch. At this time, the potential of VOUT is mainly determined by the source voltage and on-resistance of the NMOS switch. If the source of the NMOS switch is grounded, VOUT will be pulled down to near ground potential. If the source of the NMOS switch is connected to a specific bias voltage, VOUT will change with that bias voltage. In the off state, the gate voltage of the NMOS switch is lower than the threshold, and the NMOS switch presents a high-resistance state. At this time, the potential of VOUT is determined by the load circuit or pull-up element and is basically isolated from the drain of the NMOS switch.

[0042] The gate of the NMOS switch is connected to ground via switch S1. It's important to note that when S1 is closed, the NMOS switch gate is forcibly pulled low to ground potential, ensuring that the gate-source voltage VGS of the NMOS switch is below the threshold voltage, thus reliably turning off the NMOS switch. This configuration is particularly suitable for applications requiring active discharge, quickly eliminating residual charge on the NMOS switch gate and preventing false triggering caused by a floating gate. In actual circuits, S1 is typically implemented using another MOS transistor or bipolar transistor; its on-resistance and response speed directly affect the turn-off performance. It's worth noting that this connection will create a voltage drop from the NMOS gate... The low-impedance path from the gate of the S-switch to ground may cause momentary overload of the gate drive circuit of the NMOS switch during high-speed switching. When S1 is open, the gate potential of the NMOS switch is determined by the preceding drive circuit. At this time, the normal switching function of the NMOS switch is not affected. This flexible switching characteristic makes it widely used in complex logic control. From a dynamic perspective, the design of the NMOS switch gate being grounded through S1 will significantly affect the turn-off process of the NMOS switch. When S1 is on, the gate capacitance of the NMOS switch discharges rapidly through the low-impedance path, which can greatly shorten the turn-off delay time, which is particularly beneficial for high-frequency switching applications.

[0043] The gate of the NMOS switch is connected to the output of the boost charge pump BOOST via switch S0. It should be noted that when S0 is turned on, this increased voltage is directly applied to the gate of the NMOS switch, ensuring that the NMOS switch enters the deep saturation region, significantly reducing conduction losses. This is suitable for low-voltage scenarios such as battery-powered equipment. It can ensure the full conduction of the power transistor and avoid the use of complex level conversion circuits, which has obvious advantages in space-constrained applications.

[0044] The increased gate voltage of the NMOS switch increases the transconductance gain of the NMOS switch and significantly speeds up the switching speed, making it particularly suitable for high-frequency switching applications. Due to the reduced on-resistance, the temperature rise of the NMOS switch is significantly reduced when operating at high current, improving the reliability and efficiency of the NMOS switch. The introduction of the charge pump can also achieve adaptive drive, maintaining a stable gate drive capability of the NMOS switch even when the input voltage fluctuates.

[0045] like Figure 1 As shown, the threshold adjustment process of this NMOS switch is as follows:

[0046] For a metal-oxide-semiconductor field-effect transistor (MOSFET), its threshold voltage can be calculated using the following formula:

[0047]

[0048] Where V th Represents the threshold voltage, V t0 Where the bias voltage is zero, and γ is the attenuation coefficient. For the built-in potential, V sb The threshold voltage (TV) is the voltage difference between the source and substrate of an NMOS switch. It's important to note that the TV is the minimum gate-source voltage required for channel formation, a critical parameter for MOSFET operation. When the gate-source voltage is below the TV, the NMOS is off; when it exceeds the TV, a conductive channel forms, and the NMOS switch begins to conduct. The TV is primarily determined by the manufacturing process and is influenced by factors such as substrate doping concentration, gate oxide thickness, and material properties, typically ranging from 0.3V to 1V. The TV varies with operating conditions, with the substrate bias effect (body effect) being the most significant factor. When a voltage difference exists between the source and substrate of the NMOS switch, the TV increases. This effect requires special attention in integrated circuits because changes in the TV can affect circuit performance when multiple NMOS switches share the same substrate. In practical applications, the selection of the TV requires balancing multiple factors. A lower TV is beneficial for low-voltage operation but increases leakage current in the off state; a higher TV reduces static power consumption.

[0049] The zero bias voltage of an NMOS switch refers to the voltage at which the substrate of the NMOS switch is shorted to the source of the NMOS switch (V). sbThe zero-bias voltage is the threshold voltage when the NMOS switch is 0. At this time, the NMOS switch is not affected by the substrate bias effect. This parameter is the most basic performance indicator of MOSFET and directly determines the turn-on characteristics of NMOS switch. Precise control of zero bias voltage is crucial for circuit design. In digital circuits, a lower zero bias voltage is beneficial for low-voltage operation, but it will increase the subthreshold leakage current. For power NMOS switches, the zero bias voltage is usually set higher (2V-4V) to enhance the anti-interference capability.

[0050] It can be seen from formula (1) that for NMOS switches under the same conditions, if V sb The larger V is th The higher the voltage, the better; this invention connects the substrate potential and drain of the NMOS switch together in the on state, and connects the substrate potential and ground together in the off state, thereby making the V of the NMOS switch higher in the on state. sb Less than V in the off state sb This ensures that the V of the NMOS switch is in the on state. th Less than V in the off state th This enables the selection of substrates that allow for adjustment of the threshold voltage of NMOS switches.

[0051] The built-in potential of an NMOS switch is an important parameter of semiconductor physics, reflecting the potential difference between the Fermi level and the intrinsic Fermi level in a P-type substrate. Its magnitude is mainly determined by the substrate doping concentration, typically in the range of 0.3V-0.4V. This potential essentially originates from the concentration difference between majority carriers (holes) and minority carriers (electrons) in the P-type semiconductor, and is the theoretical basis for the built-in electric field of the PN junction. It directly affects the threshold voltage and bulk effect coefficient of the NMOS switch. When the NMOS switch is working, the built-in potential participates in the formation of the surface barrier, determining the ease of inversion layer formation. When a voltage is applied to the gate of the NMOS switch, the built-in potential must be overcome before the surface can be depleted, thereby forming a conductive channel.

[0052] The voltage of the NMOS switch in this invention satisfies V DS <<2(V GS -V TH Therefore, the drain current I of the NMOS switch... D It can be represented as:

[0053]

[0054] Where I D The drain current of the NMOS switch, μ n C represents the electron mobility of an NMOS switch. OXHere, W is the gate oxide capacitance per unit area, W is the gate width of the NMOS switch, and L is the channel length of the NMOS switch, which is the physical size of the conductive channel below the gate of the NMOS switch. It directly affects the performance and power consumption characteristics of the NMOS switch. As a core parameter of the manufacturing process, the channel length is usually determined by photolithography. Modern advanced processes have achieved nanoscale (such as 7nm, 5nm). A shorter channel length can improve the switching speed and transconductance, but it will exacerbate the short-channel effect, leading to a decrease in threshold voltage and an increase in leakage current. Therefore, the short-channel effect is suppressed by optimizing the doping distribution and device structure.

[0055]

[0056] Among them, R on This is the on-resistance of the NMOS switch.

[0057] The on-resistance R of the NMOS switch can be obtained using formula (3). on With threshold voltage V TH It increases as it increases.

[0058] The electron velocity of NMOS and PMOS described herein is:

[0059] v = μE (4);

[0060] Where μ is the mobility and E is the electric field strength.

[0061] Formula (4) shows that under the same electric field strength, the greater the carrier mobility, the faster the movement speed; at room temperature, the electron mobility in low-doped silicon is 1350 cm⁻¹. 2 V -1 s -1 The hole's migration rate is only 480 cm. 2 V -1 s -1 .

[0062] At the same carrier concentration, the higher the mobility, the lower the resistivity. Therefore, this invention uses NMOS as the switching transistor.

[0063] The foregoing has provided a detailed description of one embodiment of the present invention, but this description is merely a preferred embodiment and should not be construed as limiting the scope of the invention. All equivalent variations and modifications made within the scope of the claims of this invention should still fall within the patent coverage of this invention.

Claims

1. A substrate selection circuit based on an NMOS switch with adjustable threshold voltage, characterized in that, It includes an NMOS switch and a boost charge pump, wherein the NMOS switch includes an NMOS switch gate, an NMOS switch drain, an NMOS switch source, and an NMOS switch substrate; The input terminal of the NMOS switch is connected in parallel with switches S0 and S1, and the substrate of the NMOS switch is connected to one end of switch S3. The source of the NMOS switch is connected to the input signal VIN, the input terminal of the boost charge pump BOOST is connected to the input signal VIN, and the output terminal of the boost charge pump BOOST is connected to one end of the switch S0.

2. The substrate selection circuit based on an NMOS switch with adjustable threshold voltage as described in claim 1, characterized in that, The substrate of the NMOS switch is connected to ground via switch S2.

3. The substrate selection circuit based on an NMOS switch with adjustable threshold voltage as described in claim 1, characterized in that, The NMOS switch substrate is connected to the drain of the NMOS switch via switch S3.

4. The substrate selection circuit based on an NMOS switch with adjustable threshold voltage as described in claim 3, characterized in that, The drain of the NMOS switch is connected to the output signal VOUT.

5. The substrate selection circuit based on an NMOS switch with adjustable threshold voltage as described in claim 1, characterized in that, The gate of the NMOS switch is connected to ground via switch S1.

6. The substrate selection circuit based on an NMOS switch with adjustable threshold voltage as described in claim 1, characterized in that, The gate of the NMOS switch is connected to the output terminal of the boost charge pump BOOST via switch S0.

7. The substrate selection circuit based on an NMOS switch with adjustable threshold voltage as described in claim 1, characterized in that, The voltage threshold of the NMOS switch is calculated using the following formula: Where V th V is the threshold voltage. t0 Where the bias voltage is zero, and γ is the attenuation coefficient. For the built-in potential, V sb This is the voltage between the source and the base.

8. The substrate selection circuit based on an NMOS switch with adjustable threshold voltage according to claim 1, characterized in that, The voltage of the NMOS switch satisfies the formula: V ds <<2(V gs -V th ); Where V ds V is the voltage difference between the drain and source of the NMOS switch. gs V is the voltage difference between the gate and source of the NMOS switch. th This is the threshold voltage.

9. The substrate selection circuit based on an NMOS switch with adjustable threshold voltage as described in claim 8, characterized in that, The drain current ID of the NMOS switch is calculated using the following formula: Where I D The drain current of the NMOS switch, μ n C represents the electron mobility of an NMOS switch. OX is the gate oxide capacitance per unit area, W is the gate width of the NMOS switch, and L is the channel length of the NMOS switch.

10. The substrate selection circuit based on an NMOS switch with adjustable threshold voltage according to claim 9, characterized in that, The on-resistance R of the NMOS switch on Calculated using the following formula: Where R on Let v be the on-resistance of the NMOS switch. The electron velocity of the NMOS and PMOS transistors in the NMOS switch is v = μE, where μ is the mobility and E is the electric field strength.

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