High-speed parallel real-time forming method for digital nuclear pulse signals

Abstract

The invention relates to the field of nuclear signal processing, and discloses a high-speed parallel real-time forming method of a digital nuclear pulse signal, which comprises the following steps: S1, a detector receives a radiation signal emitted by a radioactive source, converts the radiation signal into an electric signal and outputs the electric signal; s2, the electric signal enters a pre-amplifier for preliminary amplification, and then is optimized through a signal conditioning circuit; s3, digitally sampling the optimized analog signal by a superspeed analog-to-digital converter, and converting the optimized analog signal into a high-precision digital pulse signal; s4, splitting the high-precision digital pulse signal in the FPGA, performing multi-channel parallel synchronous real-time pulse forming on the split digital pulse signal, and then merging; and S5, analyzing the amplitude of the formed waveform after merging to obtain energy spectrum information. According to the invention, the pulse processing rate of the FPGA can be effectively improved to cope with the high-speed nuclear pulse signal generated by the high-performance ADC, so that the problems of data loss, processing delay and the like in the high-speed pulse forming process are avoided.

Description

Technical Field

[0001] This invention relates to the field of nuclear signal processing, and in particular to a high-speed parallel real-time shaping method for digital nuclear pulse signals. Background Technology

[0002] In modern high-radiation field applications, such as nuclear physics experiments, particle accelerator operations, space exploration missions, and medical imaging, systems face the challenge of signal acquisition and processing under extreme conditions. These environments are typically accompanied by high-intensity radiation and complex electromagnetic interference, causing signals to exhibit high frequency, high amplitude, and high dynamic range characteristics. Accurately capturing transient events places extremely high demands on data acquisition equipment, particularly regarding pulse signal count rates.

[0003] In high-count-rate applications (such as gamma-ray detection or high-energy particle collision experiments), front-end electronics must be able to process a large number of pulse signals in a short time, posing a significant challenge to the performance of analog-to-digital converters (ADCs). To meet the requirements of high throughput, ADCs with ultra-high sampling rates have become one of the key technologies. Traditional ADCs, limited by their sampling rate and bandwidth, struggle to effectively handle signal frequencies up to gigahertz or even higher. Therefore, ADCs with ultra-high-speed sampling capabilities are crucial. These ADCs not only need extremely high sampling rates but also need to find a balance between low noise, high linearity, and high dynamic range to ensure accurate reproduction of the original signal even in complex environments.

[0004] However, relying solely on high-performance ADCs is insufficient to completely solve signal processing problems. In practical applications, high-performance ADCs often mean faster conversion rates. This requires subsequent digital signal shaping algorithms to also have sufficiently fast processing speeds to handle the high-speed pulse signals output by high-performance ADCs, enabling real-time pulse shaping, separation, and parameter extraction. Therefore, developing efficient ultra-high-speed pulse signal shaping methods has become a key research focus.

[0005] Currently, FPGA-based digital pulse shaping suffers from technical problems such as pulse data loss and processing delays when processing high-speed pulse signals due to insufficient processing speed. Specifically, current FPGA-based digital pulse shaping has the following technical shortcomings when dealing with high-radiation field application environments and their related challenges:

[0006] 1. As for high-speed digital pulse shaping technology based on FPGA processing, although it can realize pulse signal processing to a certain extent and provide flexibility to adapt to different application scenarios, its processing speed is limited by the internal clock frequency of the FPGA.

[0007] 2. With the increasing demand for ultra-high sampling rate ADCs, especially when operating in frequency bands above gigahertz, existing FPGAs may not be able to process such a large number of pulse data streams in real time, resulting in data loss or increased processing latency.

[0008] These problems limit the application of existing digital pulse shaping techniques in high-speed nuclear energy spectrum analysis. Summary of the Invention

[0009] This invention addresses the mismatch between data processing speed and ultra-high sampling rate ADC data output speed encountered in the digital pulse shaping process of FPGA. It proposes a high-speed parallel real-time shaping method for digital core pulse signals. This method uses a parallel digital pulse shaping method to achieve high-speed digital pulse shaping, which significantly improves the speed and efficiency of FPGA pulse data processing, thereby avoiding problems such as data loss and processing delay in the high-speed pulse shaping process.

[0010] This invention provides the following technical solution:

[0011] A high-speed parallel real-time shaping method for digital nuclear pulse signals includes the following steps:

[0012] S1: The detector receives the radiation signal emitted by the radiation source and converts it into an electrical signal for output;

[0013] S2: The electrical signal enters the preamplifier for initial amplification, and then the signal is further optimized by the signal conditioning circuit;

[0014] S3: The optimized analog signal is digitally sampled by an ultra-high-speed analog-to-digital converter and converted into a high-precision digital pulse signal;

[0015] S4: The high-precision digital pulse signal is transmitted to the FPGA, where it is split into multiple channels. The split digital pulse signals are then subjected to multi-channel parallel synchronous real-time pulse shaping and finally merged.

[0016] S5: Energy spectrum information is obtained by analyzing the amplitude of the merged waveform.

[0017] Preferably, the FPGA's splitting, shaping, and merging of the digital core pulse signal in step S4 includes the following steps:

[0018] S41: The one-dimensional sequence of digital kernel pulse signals is periodically divided into several sub-sequence signals according to a certain sampling interval;

[0019] S42: Perform multi-channel parallel synchronous real-time pulse shaping on the several sub-sequence signals, input the several sub-sequence signals into the corresponding pulse shaping channels respectively, and output several shaping data; each pulse shaping channel has an independent shaping path, and there is also interaction of shaping data between the corresponding pulse shaping channels, which is used to realize the function of parallel synchronous real-time pulse shaping.

[0020] S43: The signals processed in step S42 are reassembled into a complete one-dimensional sequence of signals according to the original signal arrangement order, thereby completing the high-speed nuclear pulse signal shaping.

[0021] Preferably, the algorithm design of the FPGA is assisted by constructing a Simulink-based four-channel laddering simulation model, and the recursive formula of the four-channel laddering algorithm is as follows:

[0022] Channel 1:

[0023] v1[n]=s1[n]-d·s4[n-1] (5)

[0024]

[0025] q1[n]=p1[n]+q4[n-1] (7)

[0026] r1[n]=q1[n]+r4[n-1] (8)

[0027] Channel 2:

[0028] v2[n]=s2[n]-d·s1[n] (9)

[0029]

[0030] q2[n]=p2[n]+q1[n] (11)

[0031] r2[n]=q2[n]+r1[n] (12)

[0032] Channel 3:

[0033] v3[n]=s3[n]-d·s2[n] (13)

[0034]

[0035] q3[n]=p3[n]+q2[n] (15)

[0036] r3[n]=q3[n]+r2[n] (16)

[0037] Channel 4:

[0038] v4[n]=s4[n]-d·s3[n] (17)

[0039]

[0040] q4[n]=p4[n]+q3[n] (19)

[0041] r4[n]=q4[n]+r3[n] (20)

[0042] Where s[n] is the input pulse signal of a certain channel, which is successively formed into v[n], p[n], q[n] and the final ladder-shaped signal r[n].

[0043] Preferably, the algorithm design of the FPGA is assisted by constructing a simulation model of a four-channel parallel ladder model based on Simulink. The specific steps are as follows:

[0044] The input one-dimensional pulse data sequence X:(y1, y2, y3, y4, ..., y 4n It is divided into 4 subsequences according to a fixed interval pattern, and the specific division method is as follows:

[0045] Subsequence X1: Contains the first data point of the pulse data sequence X and the data points at every four positions thereafter, i.e., X1 = (y 1, y5,y9,y 13 ,y 17 ,…,y 4n-3 );

[0046] Subsequence X2: Contains the second data point of the pulse data sequence X and the data points at every four positions thereafter, i.e., X2 = (y2, y6, y7) 10 ,y 14 ,…,y 4n-2 );

[0047] Subsequence X3: Contains the third data point of the pulse data sequence X and the data points at every four positions thereafter, i.e., X3 = (y3, y7, y8) 11 ,y 15 ,…,y 4n-1 );

[0048] Subsequence X4: Contains the 4th data point of the pulse data sequence X and the data points at every subsequent 4 positions, i.e., X4 = (y4, y8, y9) 12 ,y 16 ,…,y 4n );

[0049] Where n is a positive integer, the length of the data sequence satisfies a multiple of 4n. After splitting, the split data is simultaneously processed by multi-channel pulse shaping in parallel to obtain four shaped data sets: out.simout1, out.simout2, out.simout3, and out.simout4. Then, according to the original data arrangement order, the data in the four sub-sequences are sequentially and alternately spliced ​​together to restore a complete one-dimensional sequence.

[0050] Preferably, the step of sequentially and alternately splicing the sequences to restore them to a complete one-dimensional sequence includes:

[0051] Take the first data from out.simout1, then take the first data from out.simout2, then take the first data from out.simout3 and out.simout4 respectively; continue to take subsequent data from out.simout1, out.simout2, out.simout3, out.simout4 in this order until all data is recombined, thus completing the four-channel parallel ladder formation.

[0052] Compared with the prior art, the present invention has the following beneficial effects:

[0053] The present invention provides a high-speed parallel real-time shaping method for digital nuclear pulse signals. After splitting the digital nuclear pulse signal, it performs multi-channel parallel real-time pulse shaping, which breaks through the limitation of FPGA digital signal processing rate by system clock frequency, further improves the shaping rate of pulse signals, and thus improves the pulse throughput capability of the energy spectrum measurement system in a high count rate environment.

[0054] This invention effectively overcomes the data processing bottleneck encountered by traditional FPGAs when processing digital pulse signals with ultra-high sampling rates. It ensures reduced data loss and lower processing latency during real-time processing of large pulse data streams. The processing speed of this real-time shaping method is not limited by the FPGA's clock frequency, the number of parallel channels is unlimited, and the digital shaping algorithm is unrestricted. This flexibility allows it to adapt to various complex digital pulse signal processing needs while maintaining high efficiency and low latency data processing performance. Attached Figure Description

[0055] Figure 1 A flowchart of high-speed pulse signal processing based on FPGA parallel shaping is provided for an embodiment of the present invention.

[0056] Figure 2 This is a schematic diagram of a four-channel parallel pulse shaping system architecture based on FPGA provided in an embodiment of the present invention.

[0057] Figure 3This is a Simulink-based single-channel ladder model simulation model provided for embodiments of the present invention.

[0058] Figure 4 The present invention provides a Simulink-based four-channel parallel ladder model for simulation. Detailed Implementation

[0059] The present invention will now be described in detail with reference to embodiments and accompanying drawings. However, it should be understood that the embodiments and drawings are for illustrative purposes only and do not constitute any limitation on the scope of protection of the present invention. All reasonable modifications and combinations included within the inventive spirit of the present invention fall within the scope of protection of the present invention.

[0060] The present invention will be further described below with reference to the accompanying drawings.

[0061] Figure 1 This paper demonstrates a high-speed pulse signal processing flow based on FPGA parallel shaping technology. First, the detector receives the radiation signal emitted by the radiation source and converts it into an electrical signal output. These signals are then pre-amplified by a preamplifier and further optimized by signal conditioning circuitry (e.g., filtering or gain adjustment). The optimized analog signal is digitized by an ultra-high-speed analog-to-digital converter (ADC) and converted into a high-precision digital pulse signal. Next, these digital signals are transmitted to the FPGA, where they are split and processed internally. The split digital pulse signals undergo multi-channel parallel synchronous real-time pulse shaping and are then combined. Finally, energy spectrum information is obtained by analyzing the amplitude of the combined shaped waveform.

[0062] Example 1

[0063] Figure 2 A schematic diagram of a four-channel parallel pulse shaping system architecture is shown. The one-dimensional sequence of digital kernel pulse signals is periodically divided into four sub-sequences (X1, X2, X3, X4) at certain sampling intervals, and then distributed across the four channels. Multi-channel parallel synchronous real-time pulse shaping is performed on each sub-sequence signal. The processed signals are then reassembled in the original signal order to form the shaped waveform of the one-dimensional sequence, resulting in the final synthesized signal.

[0064] In some other implementations, there is no limit to the number of subsequence signals after splitting. Compared with the traditional digital pulse shaping method without splitting, the method of using parallel signal processing of subsequences can increase the processing speed of pulse shaping by several times.

[0065] There are no restrictions on the algorithm for parallel pulse shaping; the desired shaping algorithm can be selected based on the actual detector.

[0066] The processing speed of parallel pulse shaping methods is not limited by the clock frequency of the FPGA itself; the maximum shaping rate is determined by the number of channels processed in parallel. For example, using four-channel parallel synchronous real-time pulse shaping can increase the maximum shaping rate to four times that of single-channel pulse shaping.

[0067] Example 2

[0068] Figure 3 The figure shows a single-channel laddering simulation model based on Simulink, demonstrating how the pulse signal s[n] is sequentially formed into signals v[n], p[n], q[n], and finally the laddered signal r[n]. Equations (1) to (4) illustrate the recursive formulas of the laddering algorithm:

[0069] v[n]=s[n]-d·s[n-1] (1)

[0070] p[n]=v[n]-v[nb]-v[n-3·b]+v[n-4·b] (2)

[0071] q[n]=p[n]+q[n-1] (3)

[0072] r[n]=q[n]+r[n-1] (4)

[0073] in T is the ADC sampling period, τ RC It is the decay time of the nuclear signal, and parameter b determines the width of the shaped signal.

[0074] Example 3

[0075] Figure 4 A simulation model of a four-channel parallel laddering model based on Simulink is presented. This model is achieved by splitting and parallelizing a single-channel laddering simulation model. As shown in equations (5) to (20), the recursive formula of the four-channel parallel laddering algorithm is presented:

[0076] Channel 1:

[0077] v1[n]=s1[n]-d·s4[n-1] (5)

[0078]

[0079] q1[n]=p1[n]+q4[n-1] (7)

[0080] r1[n]=q1[n]+r4[n-1] (8)

[0081] Channel 2:

[0082] v2[n]=s2[n]-d·s1[n] (9)

[0083]

[0084] q2[n]=p2[n]+q1[n] (11)

[0085] r2[n]=q2[n]+r1[n] (12)

[0086] Channel 3:

[0087] v3[n]=s3[n]-d·s2[n] (13)

[0088]

[0089] q3[n]=p3[n]+q2[n] (15)

[0090] r3[n]=q3[n]+r2[n] (16)

[0091] Channel 4:

[0092] v4[n]=s4[n]-d·s3[n] (17)

[0093]

[0094] q4[n]=p4[n]+q3[n] (19)

[0095] r4[n]=q4[n]+r3[n] (20)

[0096] This demonstrates how a pulse signal s[n] in a certain channel is sequentially formed into signals v[n], p[n], q[n], and finally into a ladder-shaped signal r[n].

[0097] This simulation model can be used to assist in FPGA algorithm design, but it requires conversion from Simulink algorithm to FPGA algorithm. The specific process is as follows:

[0098] The input one-dimensional pulse data sequence X:(y1, y2, y3, y4, ..., y 4n It is divided into 4 subsequences according to a fixed interval pattern, and the specific division method is as follows:

[0099] Subsequence X1: Contains the first data point of the pulse data sequence X and the data points at every four positions thereafter, i.e., X1 = (y 1, y5,y9,y 13 ,y 17 ,…,y 4n-3 ).

[0100] Subsequence X2: Contains the second data point of the pulse data sequence X and the data points at every four positions thereafter, i.e., X2 = (y2, y6, y7) 10 ,y 14 ,…,y 4n-2 ).

[0101] Subsequence X3: Contains the third data point of the pulse data sequence X and the data points at every four positions thereafter, i.e., X3 = (y3, y7, y8) 11 ,y 15 ,…,y 4n-1 ).

[0102] Subsequence X4: Contains the 4th data point of the pulse data sequence X and the data points at every subsequent 4 positions, i.e., X4 = (y4, y8, y9) 12 ,y 16 ,…,y 4n ).

[0103] Where n is a positive integer, and the length of the data sequence is a multiple of 4n. After splitting, these data are simultaneously processed in parallel using multi-channel pulse shaping to obtain four shaped data sets: out.simout1, out.simout2, out.simout3, and out.simout4. Following the original data arrangement, the data from these four sub-sequences are then alternately concatenated to restore a complete one-dimensional sequence. The specific steps are as follows:

[0104] Take the first data from out.simout1, then take the first data from out.simout2, then take the first data from out.simout3 and out.simout4 respectively; continue to take subsequent data from out.simout1, out.simout2, out.simout3, out.simout4 in this order until all data is recombined, thus completing the four-channel parallel ladder formation.

[0105] In terms of forming results, the four-channel parallel ladder forming in Example 3 is completely consistent with the single-channel ladder forming in Example 2. However, compared with the single-channel ladder forming, the processing speed of pulse forming can be increased to 4 times that of the original by using the four-channel parallel processing method.

[0106] The above embodiments are merely preferred embodiments of the present invention, and the scope of protection of the present invention is not limited to the above embodiments. All technical solutions falling within the scope of the present invention's concept are within the scope of protection of the present invention. It should be noted that for those skilled in the art, improvements and modifications made without departing from the principles of the present invention should also be considered within the scope of protection of the present invention.

Claims

1. A method of high speed parallel real-time shaping of digital nuclear pulse signals, characterized by: The method comprises the following steps: S1: the detector receives the radiation signal emitted by the radiation source and converts it into an electrical signal output; S2: the electrical signal enters a preamplifier for preliminary amplification, and then passes through a signal conditioning circuit for further optimization of the signal; S3: the optimized analog signal is digitized and sampled by a super-speed analog-to-digital converter and converted into a high-precision digital pulse signal; S4: the high-precision digital pulse signal is transmitted to the FPGA, where the digital nuclear pulse signal is split and processed, the split digital pulse signal is subjected to multi-channel parallel synchronous real-time pulse shaping, and then combined; S5: the amplitude of the shaped waveform after combination is analyzed to obtain energy spectrum information.

2. The method of claim 1, wherein: the digital nuclear pulse signal is a high speed parallel real time shaping method. The splitting, shaping and combining of the digital nuclear pulse signal in the FPGA in step S4 comprise the following steps: S41: periodically split the one-dimensional sequence of digital nuclear pulse signals into a plurality of sub-sequence signals according to a certain sampling interval; S42: perform multi-channel parallel synchronous real-time pulse shaping on the plurality of sub-sequence signals, input the split plurality of sub-sequence signals into corresponding pulse shaping channels, and output a plurality of shaped data; each pulse shaping channel has an independent shaping path, and there is also interaction of shaped data between corresponding pulse shaping channels to realize the function of parallel synchronous real-time pulse shaping; S43: re-splice the signals processed in step S42 into a one-dimensional sequence of complete shaped signals according to the original signal arrangement order, thereby completing the high-speed nuclear pulse signal shaping.

3. The high-speed parallel real-time shaping method for digital nuclear pulse signals according to claim 2, characterized in that: The four-channel ladder shaping algorithm is designed with the aid of a four-channel ladder shaping simulation model based on simulink, and the recursive formula of the four-channel ladder shaping algorithm is as follows: Channel 1: v1[n]=s1[n]-d·s4[n-1] (5) q1[n]=p1[n]+q4[n-1] (7) r1[n]=q1[n]+r4[n-1] (8) Channel 2: v2[n]=s2[n]-d·s1[n] (9) q2[n]=p2[n]+q1[n] (11) r2[n]=q2[n]+r1[n] (12) Channel 3: v3[n]=s3[n]-d·s2[n] (13) q3[n]=p3[n]+q2[n] (15) r3[n]=q3[n]+r2[n] (16) Channel 4: v4[n]=s4[n]-d·s3[n] (17) q4[n]=p4[n]+q3[n] (19) r4[n]=q4[n]+r3[n] (20) Where s[n] is the input pulse signal of a certain channel, which is sequentially shaped into v[n], p[n], q[n] and the final ladder-shaped signal r[n].

4. The method of claim 2, wherein: the digital nuclear pulse signal is a high speed parallel real time shaping method. The four-channel parallel ladder shaping simulation model based on simulink is constructed to assist the algorithm design of the FPGA, and the specific steps are as follows: The input one-dimensional pulse data sequence X: (y1, y2, y3, y4, …, y 4n ) is split into 4 subsequences according to fixed interval rules, and the specific division method is as follows: Subsequence X1: contains the 1st data of the pulse data sequence X and every 4th data after that, i.e., X1 = (y 1, y5, y9, y 13 , y 17 , y 4n-3 ); Subsequence X2: Contains the second data point of the pulse data sequence X and the data points at every four positions thereafter, i.e., X2 = (y2, y6, y7) 10 ,y 14 ,…,y 4n-2 ); Subsequence X3: contains the 3rd data of the pulse data sequence X and every 4th data after that, i.e., X3 = (y3, y7, y 11 ,y 15 ,…,y 4n-1 ); Subsequence X4: Contains the 4th data point of the pulse data sequence X and the data points at every subsequent 4 positions, i.e., X4 = (y4, y8, y9) 12 ,y 16 ,…,y 4n ); Wherein, n is a positive integer, the length of the data sequence satisfies the multiple relationship of 4n, after the splitting, the split data is simultaneously processed by multi-channel pulse shaping, and four shaped data out.simout1, out.simout2, out.simout3 and out.simout4 are obtained.

5. The method of claim 4, wherein: the digital nuclear pulse signal is a high speed parallel real time shaping method, and the digital nuclear pulse signal is a high speed parallel real time shaping method. The step of sequentially alternately splicing and restoring into a complete one-dimensional sequence comprises: The first data is taken out from out.simout1, then the first data is taken out from out.simout2, and then the first data is taken out from out.simout3 and out.simout4; the subsequent data is sequentially taken out from out.simout1, out.simout2, out.simout3 and out.simout4 in this order, until all the data is recombined, and the four-channel parallel ladder shaping is completed.

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