A high linearity programmable signal amplitude alarm monitoring method insensitive to pvt

Abstract

The application discloses a high-linearity programmable signal amplitude alarm monitoring method insensitive to PVT, and relates to the technical field of optical communication, comprising the following steps: generating a differential reference signal with programmable amplitude according to a programmable alarm threshold level and synchronizing with an external clock signal; using a control clock with non-overlapping high-level periods to time-division multiplexedly feed a to-be-tested input signal and the differential reference signal into a same amplification and amplitude detection channel for processing; demultiplexing according to the control clock to separate a signal detection value representing the amplitude of the to-be-tested input signal and a reference detection value representing the amplitude of the differential reference signal; and sampling and differentially comparing the reference detection value and the signal detection value using a third control clock and outputting an alarm signal according to a comparison result. The application can effectively eliminate common-mode errors introduced by PVT changes and circuit nonlinearities, thereby realizing high-linearity and high-precision signal amplitude alarm monitoring while significantly reducing power consumption and chip area.

Description

Technical Field

[0001] This invention relates to the field of optical communication technology, and more specifically, to a method for monitoring the amplitude of a highly linear programmable signal that is insensitive to PVT in a continuous-mode limiting amplifier for optical communication. Background Technology

[0002] In an optical receiver, the Receiving Optical Sub-Assembly (ROSA) converts the binary non-return-to-zero (NRZ) optical signal transmitted through the optical fiber into an electrical signal. The output electrical signal is then amplified to a sufficiently large amplitude by a limiting amplifier before being sent to the subsequent signal processing unit, such as... Figure 1 As shown.

[0003] In optical communication receivers, to ensure reliable signal reception, it is typically necessary to monitor the amplitude of the input signal. By comparing the detected voltage value, representing the signal amplitude, with a set voltage threshold, it is determined whether the received signal is a normal transmission signal. A digital logic signal is then output as an alarm condition for the receiving system to ensure that the signal received by the signal processing unit meets system requirements and to prevent packet loss during communication. The signal amplitude alarm monitor is usually located in the receiver's limiting amplifier.

[0004] In high-speed optical communication receivers, due to the high code rate of the input optical signal, the transimpedance amplifier chip in the ROSA optical receiver component typically has a low transimpedance gain, generally in the range of several thousand to tens of kiloohms, to ensure a sufficiently wide bandwidth. This results in the alarm signal amplitude output from the ROSA to the limiting amplifier ranging from a few mVpp to tens of mVpp. This necessitates that the signal amplitude detector in the signal amplitude alarm monitor needs to detect very small signal amplitudes, sometimes even as low as a few millivolts. For example, the limiting amplifier chip in the GPON / XGPON / XGSPON ONU needs to detect whether the input signal amplitude is lost, down to the level of a few millivolts. Because typical amplitude detectors have low conversion efficiency under small signal conditions, their detection amplitude may even approach zero when the input signal amplitude is small, leading to the inability to perform small signal detection.

[0005] Therefore, traditional signal amplitude alarm monitor architectures typically introduce an amplifier before the signal amplitude detector to amplify the signal amplitude sufficiently. The amplitude detector then measures the amplitude voltage, which is subsequently compared to a set alarm threshold voltage by a comparator. The comparator's result is output to the next-stage chip to indicate the signal alarm. Figure 2 As shown. Figure 2While traditional signal amplitude alarm monitors have solved the problem of small signal amplitude detection, their input-output characteristics (high gain, low nonlinearity) of single-pole or multi-stage amplifiers, such as... Figure 3 As shown, this will cause the signal amplitude alarm monitor to have problems such as low linearity of input signal amplitude detection, narrow input signal amplitude detection range, and signal alarm monitoring amplitude changing with PVT.

[0006] In order to solve Figure 2 The existing architectural problems, and a current improved signal amplitude alarm monitor architecture, such as Figure 4 As shown. Comparison Figure 2 It can be seen that, Figure 4 A reference signal is generated from the input clock signal, and then, in the subsequent stage, the same replication circuitry as that between the input signal and the comparator input is used. This allows the reference signal and the input signal to pass through similar amplifiers and detectors, so nonlinearity and PVT factors have almost the same effect on both. Then, the nonlinearity and PVT sensitivity is improved by subtracting and canceling them at the differential input of the comparator.

[0007] Because unavoidable mismatches exist in actual semiconductor manufacturing processes, the replicated circuit cannot be exactly the same as the original circuit; therefore, the effects of PVT and nonlinearity cannot be completely canceled out. Furthermore, Figure 4 The main problem with the architecture is that the added replication circuitry sacrifices chip area and power consumption. Figure 4 Architecture compared Figure 2 An input clock signal has been added, but most mainstream optical communication COMBO chips that include limiting amplifiers already integrate clock signal generation circuits, so the impact of the clock signal can be disregarded in terms of power consumption and area. This is especially true given the generally high bit rates in current optical communication, such as the 2.5Gbps receive rate of GPON ONU and the 10Gbps receive rate of XGPON / XGSPONONU. These amplifiers are high-speed amplifiers with correspondingly high power consumption. Figure 2 Architecture, Figure 4 The power consumption of the architecture is almost Figure 2 Twice as much. Summary of the Invention

[0008] This invention provides a high-linearity programmable signal amplitude alarm monitoring method that is insensitive to PVT in continuous-mode limiting amplifiers for optical communication. It controls a programmable amplitude reference signal generator, a path selector, a time-division amplitude detector, and a sampling comparator using different clock signals. This method solves the problems of low linearity in input signal amplitude detection, narrow input signal amplitude detection range, and signal alarm monitoring amplitude variation with PVT in current optical communication systems, while maintaining low power consumption and a small area. It meets the current demand for high-performance programmable signal amplitude alarm monitors in gigabit / ten-gigahertz continuous-mode optical communication receivers.

[0009] To solve the above problems, the technical solution adopted by the present invention is as follows:

[0010] The technical terms used in this invention are explained as follows:

[0011] ROSA: Receiving Optical Sub-Assembly;

[0012] NRZ: Non-Return-To-Zero (binary non-return-to-zero);

[0013] O / E: Optical / Electrical, the conversion of optical signals into electrical signals;

[0014] TIA: Trans-Impedance Amplifier;

[0015] ONU: Optical Network Unit, is a terminal device for fiber optic access;

[0016] GPON: Gigabit Passive Optical Network;

[0017] XGPON: 10 Gigabit-Capable Passive Optical Network;

[0018] XGSPON: 10-Gigabit-capable Symmetric Passive Optical Network

[0019] PVT: Process, Voltage, and Temperature, which refers to semiconductor process, voltage, and temperature.

[0020] COMBO: combination, a combined chip that integrates functions such as a receiver limiting amplifier and a transmitter driver.

[0021] This invention provides a high linearity programmable signal amplitude alarm monitoring method, comprising the following steps:

[0022] a) Generate a differential reference signal with programmable amplitude based on the programmable alarm threshold level and synchronized with an external clock signal (CLKIN);

[0023] b) Using a set of first control clock signals (CLK1) and second control clock signals (CLK2) with non-overlapping high-level periods generated by the external clock signal, one input signal under test and the differential reference signal are fed into the same amplification and amplitude detection path in a time-division multiplexing manner.

[0024] c) The same amplification and amplitude detection path processes the input signal under test during the validity period of the first control clock signal and processes the differential reference signal during the validity period of the second control clock signal. After processing, it is demultiplexed again according to the first and second control clock signals to separate the signal detection value representing the amplitude of the input signal under test and the reference detection value representing the amplitude of the differential reference signal.

[0025] d) Using a third control clock signal (CLK3), the reference detection value and the signal detection value are sampled sequentially and differentially compared to output an alarm signal based on the comparison result.

[0026] Further, the process of generating the differential reference signal in step a) specifically involves: adjusting an 8-bit programmable current source (ILOSLVL) through a resistor (RLOSLVL) to generate a programmable DC voltage drop (VLOSLVL); using an operational amplifier (AMP1) configured as a unity-gain buffer to output a stable common-mode voltage (VCM_BUF); and using a pair of switches (SWIN_1, SWIN_2) driven by the external clock signal (CLKIN) to alternately superimpose the positive and negative values ​​of the DC voltage drop onto the common-mode voltage in each cycle of the external clock signal, thereby generating the differential reference signal, the peak-to-peak amplitude of which is precisely controlled by the programmable current source.

[0027] Furthermore, the first, second, and third control clock signals are all generated by a clock logic circuit. This clock logic circuit receives the external clock signal (CLKIN) and internally contains a frequency divider chain composed of cascaded multi-level D flip-flops (DFF1-DFF5) and a logic AND gate. By performing multiple frequency divisions and logic combinations on the external clock signal, it ensures that the high-level active windows of the output first control clock signal (CLK1) and second control clock signal (CLK2) are strictly separated in time, providing timing guarantees for conflict-free time-division multiplexing and demultiplexing operations.

[0028] Furthermore, the method of the present invention is implemented through a monitoring architecture, which includes a clock logic circuit, a reference signal generator, a path selector, the same amplification and amplitude detection path, a time-division amplitude detector, and a sampling comparator; wherein, the path selector is used to perform step b), which includes a first switch group controlled by the first control clock signal and a second switch group controlled by the second control clock signal, which respectively connect the differential path of the input signal under test or the differential reference signal to the input terminal of the same amplification and amplitude detection path within a specified time period.

[0029] Furthermore, the core of the same amplification and amplitude detection path is one or more cascaded high-speed amplifiers. Since the input signal under test and the differential reference signal flow through the same amplifier in different time windows, the gain drift, offset and nonlinear distortion caused by the amplifier's own process, voltage and temperature (PVT) changes will all act equally on the two signals and be canceled as common-mode error in the final differential comparison step d), thereby achieving high linearity monitoring that is insensitive to PVT.

[0030] Furthermore, the time-division amplitude detector is used to perform the demultiplexing operation in step c), and it integrates a broadband amplitude detection core circuit. The output of this circuit is connected to two sets of sample-and-hold circuits composed of capacitors (CAP3, CAP7) and switches (SW1_7, SW1_8, SW2_7, SW2_8). The first set of sample-and-hold circuits is controlled by the first control clock signal and is used to capture and hold the signal detection value. The second set of sample-and-hold circuits is controlled by the second control clock signal and is used to capture and hold the reference detection value, thereby separating the time-domain interleaved detection results to two independent differential storage nodes.

[0031] Further, the sampling comparator is used to perform step d), which employs a two-phase switched capacitor circuit; in the first phase defined by the third control clock signal (CLK3), the sampling comparator connects its input sampling capacitors (CAP4, CAP8) to the reference detection value to complete sampling; in the subsequent second phase, the circuit instead applies the signal detection value to the sampling capacitors that have stored charge, and using the principle of charge conservation, generates a voltage at the input of the internal operational amplifier (AMP2) that is proportional to the difference between the two detection values, thereby achieving high-precision differential amplification and comparison.

[0032] Furthermore, during the first phase, the sampling comparator configures the internal operational amplifier (AMP2) in a unity negative feedback state by closing the offset cancellation switches (SW3_3, SW3_4) to measure and sample its own input offset voltage onto an offset storage capacitor (CAP6). During the comparison in the second phase, the stored offset voltage can automatically compensate for the inherent offset of the operational amplifier, thereby ensuring that the comparison result is not affected by the operational amplifier offset voltage and further improving the monitoring accuracy.

[0033] Furthermore, the method of the present invention is applied to the optical network unit (ONU) receiver chip of a gigabit or 10-gigabit passive optical network (GPON / XGPON) to monitor whether the amplitude of the binary non-return-to-zero (NRZ) electrical signal output by the transimpedance amplifier (TIA) is lower than the signal loss decision threshold; the programmable alarm threshold level corresponds to this decision threshold, and the final output alarm signal (VSD) is directly fed into the digital processing unit of the chip as a logic level.

[0034] Furthermore, the input signal under test, the differential reference signal, the signal detection value, and the reference detection value are all differential signals. The entire method process, from the generation of the reference signal, time-division multiplexing, path processing, demultiplexing to the final sampling comparison, is completed in the full differential signal domain. This processing method enables the method to effectively suppress the interference of common-mode noise, power supply ripple, and substrate noise, ensuring the stability and robustness of the monitoring results in a high-interference environment.

[0035] Compared with the prior art, the beneficial effects of the present invention are:

[0036] (1) This invention uses time-division multiplexing technology to ensure that the input signal under test and the dynamically generated reference signal flow through the exact same amplification and amplitude detection path. This fundamentally solves the monitoring error problem caused by the mismatch or nonlinearity between the signal path and the comparison reference path. Since any gain drift, offset, and nonlinear distortion caused by process, voltage, and temperature (PVT) variations will act equally on both signals and be precisely canceled as common-mode error in the final differential comparison, the highly linear and accurate monitoring results are ensured and are not affected by PVT fluctuations.

[0037] (2) This invention achieves high-precision monitoring using only one set of processing paths through “sharing” rather than “copying”, completely avoiding the need to copy high-power, large-area circuits. This has great application value in high-speed optical communication COMBO chips that are sensitive to cost, power consumption and size.

[0038] (3) By employing a reference signal generator controlled by a programmable current source, the present invention can realize the digitalization and high-precision flexible adjustment of the alarm threshold. In addition, by employing a two-phase working switched capacitor sampling comparator with automatic offset cancellation function, the offset voltage of the comparator itself can be eliminated, which greatly improves the sensitivity and accuracy of the comparison, enabling it to reliably detect weak signal amplitude differences.

[0039] (4) A dedicated clock logic circuit composed of D flip-flops and logic gates is used to generate a strictly non-overlapping control clock, which ensures that no signal conflict or crosstalk occurs during the switching process between the signal under test and the reference signal, providing a solid timing foundation for the reliable operation of the entire monitoring method.

[0040] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, embodiments of the present invention are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0041] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0042] Figure 1 This is a block diagram of an existing fiber optic receiver system;

[0043] Figure 2 This is the architecture diagram of a traditional signal amplitude alarm monitor;

[0044] Figure 3 This is a schematic diagram of the amplifier's input and output amplitudes;

[0045] Figure 4 This is an architecture diagram of an improved signal amplitude alarm monitoring method;

[0046] Figure 5 This is a flowchart of a high linear programmable signal amplitude alarm monitoring method that is insensitive to PVT in an embodiment of the present invention. The flowchart has two branches at the beginning: the left branch is the input signal branch, and the right branch is the amplitude programmable reference signal generation branch.

[0047] Figure 6 This is an architecture diagram of a high linear programmable signal amplitude alarm monitor that is insensitive to PVT in an embodiment of the present invention;

[0048] Figure 7 This is a clock logic circuit architecture diagram in an embodiment of the present invention;

[0049] Figure 8 This is a schematic diagram of a clock logic waveform in an embodiment of the present invention;

[0050] Figure 9 This is an architecture diagram of an amplitude-programmable reference signal generator according to an embodiment of the present invention;

[0051] Figure 10 This is a schematic diagram of an amplitude-programmable reference signal waveform in an embodiment of the present invention;

[0052] Figure 11 This is an architecture diagram of a path selector according to an embodiment of the present invention;

[0053] Figure 12 This is a waveform diagram of a path selector according to an embodiment of the present invention;

[0054] Figure 13 This is an architectural diagram of an amplitude detector according to an embodiment of the present invention;

[0055] Figure 14 This is a waveform diagram of an amplitude detector according to an embodiment of the present invention;

[0056] Figure 15 This is an architecture diagram of a sampling comparator in an embodiment of the present invention;

[0057] Figure 16 In phase domain 1 Figure 15 The equivalent architecture diagram of the sampling comparator;

[0058] Figure 17 In phase domain 2 Figure 15 The equivalent architecture diagram of the sampling comparator;

[0059] Figure 18This is a waveform diagram of a sampling comparator according to an embodiment of the present invention;

[0060] Figure 19 This is an architecture diagram of a programmable threshold periodic signal in an embodiment of the present invention;

[0061] Figure 20 This invention is different from Figure 7 An example diagram of a clock logic circuit architecture. Detailed Implementation

[0062] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are some embodiments of the present invention, but not all embodiments.

[0063] This invention provides a method for monitoring the amplitude alarm of a highly linear programmable signal that is insensitive to PVT in a continuous-mode limiting amplifier for optical communication, the flowchart of which is shown below. Figure 5 As shown, the details are as follows:

[0064] (1) First, a static DC level VLOSLVL is generated using a programmable alarm threshold level. The magnitude of VLOSLVL is programmable. Then, by determining whether the clock signal CLKIN is high or low, +VLOSLVL is output when it is high and -VLOSLVL is output when it is low, thereby generating a programmable reference signal with an amplitude of VLOSLVL and a period the same as CLKIN.

[0065] (2) Input the input signal and the amplitude programmable reference signal into the selection path, and select the output according to the high and low level states of clock signals CLK1 and CLK2. Select the input signal when CLK1 is high and select the amplitude programmable reference signal when CLK2 is high. Since the high levels of CLK1 and CLK2 are not overlapping, the path will only output one signal from the input signal and the amplitude programmable reference signal at any time, thereby converting the two signals into one signal and realizing the time division multiplexing of the path.

[0066] (3) After the time-division multiplexed signal undergoes the same amplification and amplitude detection, the output is selected according to the high and low level states of clock signals CLK1 and CLK2. When CLK1 is high, the output is selected to the left branch, and when CLK2 is high, the output is selected to the right branch. As mentioned above, for the time-division multiplexed signal, the high level period of CLK1 corresponds to the input signal, and the high level period of CLK2 corresponds to the amplitude programmable reference signal. Therefore, the output of the left branch represents the amplitude of the input signal, and the output of the right branch represents the amplitude of the amplitude programmable reference signal.

[0067] (4) The branch representing the amplitude of the input signal and the branch representing the amplitude programmable reference signal amplitude are selected for sampling according to the high and low level states of the clock signal CLK3. When CLK3 is high, the sampling is selected to represent the amplitude of the amplitude programmable reference signal. When CLK3 is low, the sampling is selected to represent the amplitude of the input signal.

[0068] (5) Finally, the sampled signal is selected for output according to the low level state of the clock signal CLK3. When the clock signal CLK3 is high, the sampled signal is not output, that is, it remains in the previous state. When the clock signal CLK3 is low, the sampled signal is compared and the output signal alarm is output.

[0069] This invention also provides an architecture for a highly linear programmable signal amplitude alarm monitor that is insensitive to PVT in a continuous-mode limiting amplifier for optical communication, such as... Figure 6 As shown, the high linearity programmable signal amplitude alarm monitor architecture is used to implement the above-mentioned high linearity programmable signal amplitude alarm monitoring method. Its inputs are the input signal SIGNAL and the clock signal CLKIN, and its output is the signal alarm output VSD.

[0070] The clock signal CLKIN is input to both the clock logic circuit and the amplitude-programmable reference signal generator. The clock logic circuit is a digital logic circuit that generates the clock signals CLK1, CLK2, and CLK3 required by the control path selector, the time-division amplitude detector, and the sampling comparator. Under the control of CLKIN, the amplitude-programmable reference signal generator converts the programmable threshold DC level into an amplitude-programmable reference signal with an amplitude of VLOSLVL and a period identical to CLKIN.

[0071] Then, the input signal and the amplitude programmable reference signal are input to the path selector. The path selector combines the two signals into a single VMUX signal based on the high and low levels of the input CLK1 and CLK2 clocks, thus achieving time-division multiplexing.

[0072] The VMUX signal is amplified by a single-stage or multi-stage amplifier and then input to a time-division multiplexed amplitude detector. Under the control of clocks CLK1 and CLK2, the time-division multiplexed signal is converted into two signals: one representing the signal replication detection voltage VSIG_AMP, and the other representing the alarm threshold detection voltage VLOS_AMP. These two signals are input to a sampling comparator, and the comparison is completed by sampling and holding the two signals using clock CLK3. Finally, the alarm output signal VSD is output.

[0073] The detailed implementation details of the functions of each of the above sub-modules are as follows:

[0074] A clock logic circuit architecture of the present invention is as follows: Figure 7As shown, it includes D flip-flops DFF1, DFF2, DFF3, DFF4, and DFF5, as well as an AND gate. The input of this clock logic circuit architecture is the CLKIN signal, and the outputs are the CLK1, CLK2, and CLK3 signals. Figure 7 The D flip-flop shown has its D terminal as the data input port, Clk terminal as the clock rising edge sampling port, set terminal as the reset port, and Q terminal as the sampling positive output port. The terminal is the negative output port for sampling. The clock CLKIN input is connected to the clock port of DFF1, and DFF1's... The negative output port is fed back to the D port of DFF1, thereby generating the frequency-divided CLK_DIV2 signal. Then, CLK_DIV2 is input to the clock port of DFF2. The port feedback input is fed to the D port of DFF2, which is then divided again to generate the CLK3N signal. Simultaneously, the Q port of DFF2 generates the CLK3 signal. CLK3N and CLK3 are input to the clock ports of the DFF3 and DFF4 flip-flops, respectively, and then... The feedback is sent to the corresponding D ports, generating the third frequency-divided signals CLK_DIV8_1 and CLK_DIV8_2 respectively. CLK_DIV8_1 is input to DFF5, and DFF5's... The port feedback input is fed to the D port of the DFF5, generating the signal CLK_DIV16 after the fourth frequency division. The CLK1 signal is generated at the input terminal. Finally, the CLK_DIV16 and CLK_DIV8_2 signals are input to the AND gate logic to generate the CLK2 signal. The waveform diagram of the above clock logic circuit is shown below. Figure 8 As shown in the figure, it can be seen that the high levels of the CLK1 and CLK2 clock signals do not overlap.

[0075] An amplitude-programmable reference signal generator architecture of the present invention is as follows: Figure 9As shown, the system includes operational amplifier AMP1, resistor RLOSLVL, current source ILOSLVL, polarized capacitors CAP1 and CAP2, and selection switches SWIN_1 and SWIN_2. The positive input of operational amplifier AMP1 is the VCM level, and the negative input is the output of AMP1. Since AMP1 is a high-gain operational amplifier, the VCM_BUF level is a copy of the VCM level and has considerable driving capability. The ILOSLVL current is an 8-bit programmable current source, and its value can be adjusted via ADJ<7:0>. The ILOSLVL current flowing through resistor RLOSLVL generates a voltage drop VLOSLVL. The voltage VCM_BUF plus the voltage VLOSLVL equals the VADJ voltage. When the CLKIN signal is high, the output port VLOSLVL_P of the selection switch SWIN_1 is connected to the VADJ level, and the output port VLOSLVL_N of the selection switch SWIN_2 is connected to the VCM_BUF level. At this time, the differential output voltage amplitude of VLOSLVL_P - VLOSLVL_N is +VLOSLVL. When the CLKIN signal is low, the output port VLOSLVL_P of the selection switch SWIN_1 is connected to the VCM_BUF level, and the output port VLOSLVL_N of the selection switch SWIN_2 is connected to the VADJ level. At this time, the differential output voltage amplitude of VLOSLVL_P - VLOSLVL_N is -VLOSLVL. This generates a reference clock signal with the same period as CLKIN and an amplitude of VLOSLVL, i.e., a programmable reference signal. The waveform diagram of the above clock logic circuit is shown below. Figure 10 As shown.

[0076] One path selector architecture of the present invention is as follows: Figure 11As shown, the circuit includes switches SW1_1, SW1_2, SW1_3, SW1_4, SW1_5, SW1_6, SW2_1, SW2_2, SW2_3, SW2_4, SW2_5, and SW2_6. The inputs to this path selector are input signals (differential signals VSIGNAL_P and VSIGNAL_N) and amplitude-programmable reference signals (differential signals VLOSLVL_P and VLOSLVL_N). When clock CLK1 is high, switches SW1_1, SW1_2, SW1_3, and SW1_4 are closed, SW1_5 and SW1_6 are open, and VSIGNAL_P and VSIGNAL_N are connected to the differential output ports VMUX_P and VMUX_N, respectively. When clock CLK1 is low, switches SW1_1, SW1_2, SW1_3, and SW1_4 are open, and SW1_5 and SW1_6 are closed. When clock CLK2 is high, switches SW2_1, SW2_2, SW2_3, and SW2_4 are closed, and SW2_5 and SW2_6 are open. VLOSLVL_P and VLOSLVL_N are connected to the differential output ports VMUX_P and VMUX_N, respectively. When clock CLK2 is low, switches SW2_1, SW2_2, SW2_3, and SW2_4 are open, and SW2_5 and SW2_6 are closed. CLK1 and CLK2 are non-overlapping clock signals, therefore the differential input signal and the amplitude-programmable reference signal are connected to the differential output ports VMUX_P and VMUX_N in a time-division multiplexing manner. When neither CLK1 nor CLK2 is high, switches SW12N_1 and SW12N_2 are closed, and the VCMBUF level is connected to the differential output ports VMUX_P and VMUX_N; otherwise, SW12N_1 and SW12N_2 are open. The waveform diagram of the above path selector is shown below. Figure 12 As shown.

[0077] A time-division amplitude detector architecture of the present invention is as follows: Figure 13As shown, the circuit includes an amplitude detection circuit, switches SW1_7, SW1_8, SW2_7, and SW2_8, and polarized capacitors CAP3 and CAP7. The input signals to this time-division multiplexed amplitude detector include differential signals VMUX_A_P and VMNUX_A_N, which are amplified signals from the time-division multiplexed signals VMUX_P and VMUX_N. These signals are first input to the amplitude detection circuit to detect the differential amplitude in real time, and then the switches are selected at the output of the amplitude detection circuit by clock signals CLK1 and CLK2. When CLK1 is low, switches SW1_7 and SW1_8 are open; when CLK1 is high, switches SW1_7 and SW1_8 are closed, and the differential detection amplitude is output to the VSIG_AMP_P and VSIG_AMP_N ports respectively, representing the detected input signal amplitude. When CLK2 is low, switches SW2_7 and SW2_8 are open; when CLK2 is high, switches SW2_7 and SW2_8 are closed, and the differential detection amplitude is output to the VLOS_AMP_P and VLOS_AMP_N ports respectively, representing the detected reference signal amplitude. The waveform diagram of the above amplitude detector is shown below. Figure 14 As shown.

[0078] An architecture of a sampling comparator according to the present invention is as follows: Figure 15 As shown, the system includes selection switches SW3_1, SW3_2, SW3_3, SW3_4, and SW3_5; polarized capacitors CAP4, CAP5, CAP6, and CAP8; operational amplifier AMP2; and comparator CMP. The input signals to this sampling comparator include differential signals VSIG_AMP_P and VSIG_AMP_N, and differential signals VLOS_AMP_P and VLOS_AMP_N. The operation of the sampling comparator is controlled by clock CLK3.

[0079] First, in phase domain 1, when CLK3 is high, selector switch SW3_1 selects the VLOS_AMP_P port, selector switch SW3_2 selects the VLOS_AMP_N port, and selector switch SW3_5 selects VSOUT to connect to the upper plate of CAP5. Switches SW3_3 and SW3_4 are closed, and the positive terminal VDECT of comparator CMP is connected to the upper plate of CAP6. Figure 16 As shown.

[0080] In phase domain 2, when CLK3 is low, selector switch SW3_1 selects the VSIG_AMP_P port, selector switch SW3_2 selects the VSIG_AMP_N port, and selector switch SW3_5 selects VSOUT to connect to the upper plate of CAP6. Switches SW3_3 and SW3_4 are disconnected, and the positive terminal VDECT of the comparator is connected to VSOUT. Figure 17 As shown.

[0081] For phase domain 1, the voltages across the upper and lower plates of the polarized capacitor CAP4 connected to the positive input terminal of AMP2 are VLOS_AMP_P and VBIAS, respectively; the voltages across the upper and lower plates of the polarized capacitor CAP8 connected to the negative input terminal of AMP2 are VLOS_AMP_N and VBIAS, respectively. Therefore, the voltage difference across CAP4 is VLOS_AMP_P - VBIAS, and the voltage difference across CAP8 is VLOS_AMP_N - VBIAS, thus achieving sampling of the amplitude of the programmable reference signal. At this time, the positive input VDECT of the comparator is connected to capacitor CAP6, and the comparator is in the hold phase.

[0082] For phase domain 2, the voltage on the upper plate of the polarized capacitor CAP4 connected to the positive input terminal of AMP2 is VSIG_AMP_P, and the voltage on the upper plate of the polarized capacitor CAP8 connected to the negative input terminal of AMP2 is VSIG_AMP_N. Since there is no discharge path on the lower plate of CAP4 and CAP8, the voltage difference between their upper and lower plates cannot change abruptly. Therefore, the voltage at the positive input terminal of AMP2 becomes VSIG_AMP_P - VLOS_AMP_P + VBIAS; the voltage at the negative input terminal of AMP2 becomes VSIG_AMP_N - VLOS_AMP_N + VBIAS. At this time, the difference between the differential input terminals of the operational amplifier is (VSIG_AMP_P - VSIG_AMP_N) minus (VLOS_AMP_P - VLOS_AMP_N), which realizes differential amplification of the input signal amplitude and the amplitude programmable reference signal amplitude. Then, the signal alarm monitoring is realized by comparing it with the VBIAS level through the comparator CMP (corresponding to zero amplitude difference).

[0083] The waveform diagram of the above sampling comparator is shown below. Figure 18 As shown.

[0084] It should be noted that, regarding the clock signals CLK1, CLK2, and CLK3 mentioned in this invention, as long as the high-level times of CLK1 and CLK2 are guaranteed to be non-overlapping, changing the clock phase relationship of CLK1, CLK2, and CLK3 does not affect the protection of this invention. In this invention, the high and low levels of the clock signals CLKIN, CLK1, CLK2, and CLK3 mentioned in the amplitude programmable reference signal generator, path selector, time-division amplitude detector, and sampling comparator correspond to different selections and switching on / off states. Swapping the corresponding selections and switching on / off states of the high and low levels of the clocks does not affect the protection of this invention. The example diagrams of this invention are typical structural diagrams. Changing the connection method of the programmable threshold reference signal does not affect the protection of this invention. Figure 19 As shown. Increasing the number of D flip-flop stages in the clock logic circuit does not affect the protection of this invention, as... Figure 20 As shown.

[0085] The example diagrams of this invention are simplified structural diagrams. Adding non-impact functional modules, as long as the main scheme remains consistent with this invention, will not affect the protection of this invention. For example, the clock logic circuit, amplitude-programmable reference signal generator, path selector, amplifier, time-division amplitude detector, and sampling comparator are the main functional modules in the architecture of this invention. Non-logic modules such as DC blocking capacitors, DC offset calibrators, delay units, drivers, level shifters, and single-ended to differential converters can also be introduced. The functional modules mentioned in this invention are described in the simplest form. Adding detailed descriptions of these modules will not affect the protection of this invention. For example, the switching transistors, D flip-flops, and operational amplifiers used in various architectures. The functional module names mentioned in this invention are clock logic circuit, amplitude-programmable reference signal generator, path selector, amplifier, time-division amplitude detector, and sampling comparator. Changing the wording of the module names will not affect the protection of this invention.

[0086] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A method for monitoring the amplitude alarm of a highly linear programmable signal that is insensitive to PVT, characterized in that, Includes the following steps: a) Generate a differential reference signal with programmable amplitude based on the programmable alarm threshold level and synchronized with an external clock signal; b) Using a set of first and second control clock signals with non-overlapping high-level periods generated by the external clock signal, one input signal under test and the differential reference signal are fed into the same amplification and amplitude detection path in a time-division multiplexing manner. c) The same amplification and amplitude detection path processes the input signal to be measured during the effective period of the first control clock signal and processes the differential reference signal during the effective period of the second control clock signal. Then, it is demultiplexed again according to the first control clock signal and the second control clock signal to separate the signal detection value representing the amplitude of the input signal to be measured and the reference detection value representing the amplitude of the differential reference signal. d) Using the third control clock signal, the reference detection value and the signal detection value are sampled sequentially and differentially compared to output an alarm signal based on the comparison result.

2. The high linearity programmable signal amplitude alarm monitoring method according to claim 1, characterized in that, In step a), the process of generating the differential reference signal includes: generating a programmable DC voltage drop by adjusting the flow of an 8-bit programmable current source through a resistor; outputting a common-mode voltage using an operational amplifier configured as a unity-gain buffer; and generating the differential reference signal by alternately superimposing the positive and negative values ​​of the DC voltage drop onto the common-mode voltage in each cycle of the external clock signal using a pair of switches driven by the external clock signal, wherein the peak-to-peak amplitude of the differential reference signal is controlled by the programmable current source.

3. The high linearity programmable signal amplitude alarm monitoring method according to claim 1, characterized in that, The first, second, and third control clock signals are all generated by a clock logic circuit. This clock logic circuit receives the external clock signal and internally contains a frequency divider chain composed of cascaded multi-level D flip-flops and a logic AND gate. By performing multiple frequency divisions and logic combinations on the external clock signal, it ensures that the high-level active windows of the output first and second control clock signals are separated in time, providing timing guarantees for conflict-free time-division multiplexing and demultiplexing operations.

4. The high linearity programmable signal amplitude alarm monitoring method according to claim 1, characterized in that, This method is implemented through a high linearity programmable signal amplitude alarm monitoring architecture, which includes a clock logic circuit, a reference signal generator, a path selector, the same amplification and amplitude detection path, a time-division amplitude detector, and a sampling comparator. The path selector includes a first switch group controlled by the first control clock signal and a second switch group controlled by the second control clock signal, which respectively connect the differential path of the input signal under test or the differential reference signal to the input terminal of the same amplification and amplitude detection path within a specified time period.

5. The high linearity programmable signal amplitude alarm monitoring method according to claim 4, characterized in that, The same amplification and amplitude detection path includes one or more cascaded amplifiers. Since the input signal under test and the differential reference signal flow through the same amplifier in different time windows, the gain drift, offset and nonlinear distortion caused by the amplifier's own process, voltage and temperature changes all act equally on the input signal under test and the differential reference signal, and are canceled out as common-mode error in step d), so as to achieve high linearity monitoring that is insensitive to process, voltage and temperature.

6. The high linearity programmable signal amplitude alarm monitoring method according to claim 4, characterized in that, The time-division amplitude detector is used to perform the demultiplexing operation in step c). It integrates an amplitude detection circuit, the output of which is connected to two sets of sample-and-hold circuits consisting of capacitors and switches. The first set of sample-and-hold circuits is controlled by the first control clock signal and is used to capture and hold the signal detection value. The second set of sample-and-hold circuits is controlled by the second control clock signal and is used to capture and hold the reference detection value, thereby separating the time-domain interleaved detection results to two independent differential storage nodes.

7. The high linearity programmable signal amplitude alarm monitoring method according to claim 4, characterized in that, The sampling comparator is used to perform step d), which employs a two-phase switched capacitor circuit. In the first phase defined by the third control clock signal, the sampling comparator connects its input sampling capacitor to the reference detection value to complete sampling. In the subsequent second phase, the circuit instead applies the signal detection value to the sampling capacitor with stored charge, generating a voltage proportional to the difference between the two detection values ​​at the input of the internal operational amplifier, thereby achieving differential amplification and comparison.

8. The high linearity programmable signal amplitude alarm monitoring method according to claim 7, characterized in that, During the first phase, the sampling comparator configures the internal operational amplifier in a unity negative feedback state by closing the offset cancellation switch to measure and sample its own input offset voltage onto the offset storage capacitor; during the comparison in the second phase, the stored offset voltage can automatically compensate for the inherent offset of the operational amplifier.

9. The high linearity programmable signal amplitude alarm monitoring method according to claim 1, characterized in that, This method is applied to the receiver chip of the optical network unit in gigabit or 10-gigabit passive optical networks to monitor whether the amplitude of the binary non-return-to-zero electrical signal output by the transimpedance amplifier is lower than the signal loss decision threshold; the programmable alarm threshold level corresponds to this decision threshold, and the final output alarm signal is directly fed into the digital processing unit of the chip as a logic level.

10. The high linearity programmable signal amplitude alarm monitoring method according to claim 1, characterized in that, The input signal to be tested, the differential reference signal, the signal detection value, and the reference detection value are all differential signals. The entire method process, from the generation of the reference signal, time-division multiplexing, path processing, demultiplexing to the final sampling comparison, is completed in the full differential signal domain.

Images