Circuit board, circuit assembly, and electronic device

Abstract

The application provides a circuit board, a circuit assembly and an electronic device, which can be applied to the technical field of hardware. The circuit board comprises: a plurality of first differential via pairs, which penetrate at least a part of the circuit board and are connected with signal transmission channels in the circuit board, and the plurality of first differential via pairs are arranged in a first array; a plurality of second differential via pairs, which penetrate at least a part of the circuit board and are connected with signal receiving channels in the circuit board, and the plurality of second differential via pairs are arranged in a second array, and the second array is located on one side of the first array along a row direction; wherein the included angle of the center line extension lines of the first differential via pairs adjacent in the row direction and the included angle of the center line extension lines of the second differential via pairs adjacent in the row direction are both in the range of 60 degrees to 120 degrees.

Description

Technical Field

[0001] At least one embodiment of this application relates to the field of hardware technology, and more specifically to a circuit board, circuit assembly, and electronic device. Background Technology

[0002] The core requirement of next-generation data network systems is massive data exchange, necessitating higher bandwidth and faster data rates to maximize throughput. 50T switching systems typically incorporate high-performance forwarding chips, providing the "hardware foundation" for stable network operation. 50T switching systems employ PAM4 (Pulse Amplitude Modulation 4-Level) technology, which can double the data processing speed, enabling the construction of higher-capacity switching systems. However, transmission loss remains a key challenge for PAM4 technology. Summary of the Invention

[0003] According to a first aspect of this application, a circuit board is provided, the circuit board comprising: a plurality of first differential via pairs penetrating at least a portion of the circuit board and connected to a signal transmission channel in the circuit board, the plurality of first differential via pairs being arranged in a first array; and a plurality of second differential via pairs penetrating at least a portion of the circuit board and connected to a signal reception channel in the circuit board, the plurality of second differential via pairs being arranged in a second array, the second array being located on one side of the first array along a row direction; wherein the angle between the extension lines of the center lines of adjacent first differential via pairs in the row direction and the angle between the extension lines of the center lines of adjacent second differential via pairs in the row direction are both in the range of 60 degrees to 120 degrees.

[0004] Another aspect of this application provides a circuit assembly comprising: the aforementioned circuit board; and a chip located on the circuit board and electrically connected to a signal transmission channel and a signal reception channel in the circuit board.

[0005] Another aspect of this application provides an electronic device comprising: the aforementioned circuit assembly; and a connector, one end of which is connected to a pad on a circuit board in the circuit assembly, and the other end of which is connected to another component in the electronic device other than the aforementioned circuit assembly.

[0006] According to embodiments of this application, adjacent first differential via pairs in the row direction are arranged at an angle to reduce via crosstalk between adjacent first differential via pairs. Similarly, adjacent second differential via pairs in the row direction are arranged at an angle to reduce via crosstalk between adjacent second differential via pairs, thereby reducing crosstalk on the circuit board. Arranging multiple first differential via pairs into a first array and multiple second differential via pairs into a second array, with the first and second arrays not intersecting spatially, reduces signal crosstalk during differential signal transmission and reception, further reducing crosstalk on the circuit board. This reduces transmission loss, improves signal integrity, and provides a more robust transmission environment for high-speed signals. Attached Figure Description

[0007] The above-mentioned contents, other objects, features and advantages of this application will become clearer from the following description of embodiments with reference to the accompanying drawings, in which:

[0008] Figure 1 A schematic diagram of a solder ball array package is shown;

[0009] Figure 2A A schematic diagram of a circuit board according to an embodiment of this application is shown;

[0010] Figure 2B A schematic diagram of a first differential via pair on a circuit board according to an embodiment of this application is shown;

[0011] Figure 2C A schematic diagram of a second differential via pair on a circuit board according to an embodiment of this application is shown;

[0012] Figure 3 A schematic diagram of a circuit board according to an embodiment of this application is shown;

[0013] Figure 4 A schematic diagram of the simulation results using two rows of grounding holes is shown;

[0014] Figure 5A A schematic diagram of a circuit board according to an embodiment of this application is shown;

[0015] Figure 5B A schematic diagram of a circuit board according to an embodiment of this application is shown;

[0016] Figure 6A A schematic diagram of a circuit board according to an embodiment of this application is shown;

[0017] Figure 6B A schematic diagram of the cutout area of ​​a circuit board according to an embodiment of this application is shown;

[0018] Figure 6CA schematic diagram of a cross-section of the main wiring area according to an embodiment of this application is shown;

[0019] Figure 6D A schematic diagram showing the simulation results of cross-layer routing according to an embodiment of this application is illustrated;

[0020] Figure 7A A schematic diagram of a circuit board according to an embodiment of this application is shown;

[0021] Figure 7B A schematic diagram of a circuit board according to an embodiment of this application is shown;

[0022] Figure 7C A schematic diagram showing the simulation results of the remnants of the connection pads according to an embodiment of this application is illustrated.

[0023] Figure 8 A schematic diagram of a circuit assembly according to an embodiment of this application is shown;

[0024] Figure 9 A schematic diagram of an electronic device according to an embodiment of this application is shown;

[0025] Figure 10 A schematic diagram showing the simulation results of the connection vias according to an embodiment of this application is illustrated;

[0026] Figure 11 A flowchart illustrating the operation of an optimized design method for a high-speed link in a 224G switching system according to an embodiment of this application is shown. Detailed Implementation

[0027] The embodiments of this application will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of this application. In the following detailed description, numerous specific details are set forth to provide a thorough understanding of the embodiments of this application for ease of explanation. However, it will be apparent that one or more embodiments may be implemented without these specific details. Furthermore, descriptions of well-known structures and technologies are omitted in the following description to avoid unnecessarily obscuring the concepts of this application.

[0028] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. The terms “comprising,” “including,” etc., as used herein indicate the presence of the stated features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.

[0029] All terms used herein (including technical and scientific terms) have the meanings commonly understood by those skilled in the art, unless otherwise defined. It should be noted that the terms used herein are to be interpreted in a manner consistent with the context of this specification, and not in an idealized or overly rigid way.

[0030] When using expressions such as "at least one of A, B and C", they should generally be interpreted in accordance with the meaning that is commonly understood by those skilled in the art (e.g., "a system having at least one of A, B and C" should include, but is not limited to, a system having A alone, a system having B alone, a system having C alone, a system having A and B, a system having A and C, a system having B and C, and / or a system having A, B and C, etc.).

[0031] A 50T switching system, configured with 512 112Gbps channels, has a total switching capacity calculated as "number of channels × single channel rate," approximately equal to 56T. The actual 50T figure represents the usable capacity after considering redundancy design and actual forwarding efficiency. When the data processing speed needs to be increased from 112Gbps to 224Gbps, if the number of channels remains unchanged at 512, the new total capacity is approximately 112T, and the actual usable capacity doubles to 100T.

[0032] Switching systems can utilize PAM4 technology to double switching capacity directly by optimizing signal encoding without altering the physical bandwidth. Transistor technology and process nodes are well-suited to the baud rate requirements of PAM4 signals. Provided the serial-to-parallel converter supports the PAM4 bandwidth, PAM4 signals achieve superior signal-to-noise ratio performance, ensuring stable signal transmission. Compared to higher-order modulations such as PAM6 (Pulse Amplitude Modulation 6-Level), PAM4 has a simpler encoding structure, eliminating the need for complex multi-level control logic. This reduces chip design complexity, power consumption, and chip footprint. PAM4 is compatible with 112Gbps switching systems, directly adapting to existing high-speed switching architectures without requiring large-scale system refactoring, facilitating a smooth upgrade from low to high speeds. Optical links using PAM4 modulation are widely used in host interconnect scenarios, making the coordination of electrical and optical signals in switching system design easier, reducing the complexity of adapting different signal types, and consequently lowering overall system power consumption and hardware costs.

[0033] In the process of evolving towards 224Gbps-PAM4 technology, electrical channel design faces two major challenges.

[0034] First, the performance degradation of passive components in high-frequency scenarios leads to channel deterioration. When the system operating frequency exceeds 45GHz, the electrical performance of most passive components deteriorates. For example, the insertion loss of connectors increases, the return loss of cables worsens, and crosstalk on circuit boards increases. This degradation in electrical performance directly leads to overall channel performance deterioration and signal integrity impairment, failing to meet the signal quality requirements of a 224Gbps-PAM4 system.

[0035] Secondly, the integration of high-density serial-to-parallel converters further increases the design difficulty of high-bandwidth systems. 224Gbps systems place higher demands on the input / output integration of serial-to-parallel converters, requiring the placement of more high-speed input / output interfaces within a limited space. High integration directly increases the risk of crosstalk between adjacent interfaces. Simultaneously, high-speed signals are prone to reflections and time delay deviations in dense wiring, which, combined with the inherent design challenges of high bandwidth, further increases the design complexity of the electrical channels.

[0036] Optimizing circuit board materials can mitigate channel degradation caused by the performance decline of passive components. However, the bottleneck of the interface design for cable assemblies and connectors is easily overlooked; optimizing the interface design of existing cable assemblies and connectors can provide a margin for system performance.

[0037] This application provides a circuit board that can effectively reduce transmission loss by designing the circuit board traces with impedance matching, loss control and material upgrades.

[0038] Figure 1 A schematic diagram of a solder ball array package is shown.

[0039] like Figure 1 As shown, the packaging substrate at the bottom of the chip is connected to the pads on the circuit board via a solder ball array. Ball Grid Array (BGA) packaging distributes solder balls in a full-area array on the bottom of the chip's packaging substrate, replacing the pins located around the perimeter of traditional packaging, thus achieving electrical connection and mechanical fixation between the chip and the circuit board.

[0040] Figure 2A A schematic diagram of a circuit board according to an embodiment of this application is shown.

[0041] Figure 2B A schematic diagram of a first differential via pair on a circuit board according to an embodiment of this application is shown.

[0042] Figure 2C A schematic diagram of a second differential via pair on a circuit board according to an embodiment of this application is shown.

[0043] like Figure 2A , Figure 2B and Figure 2CAs shown, the circuit board includes multiple first differential via pairs 110 and multiple second differential via pairs 210. A differential via pair can be two vias used in pairs and are physically and electrically highly symmetrical, used to transmit differential signal pairs from one routing layer of the circuit board to another in a high-speed differential signal transmission line. The circuit board includes multiple alternating conductive layers, including alternating signal layers and reference layers, with signal transmission channels and signal reception channels located in at least one signal layer. A dielectric layer may be provided between the signal layer and the reference layer.

[0044] A plurality of first differential via pairs 110 penetrate at least a portion of the circuit board (e.g., at least one conductive layer) and are connected to a signal transmission channel 120 in the circuit board. The plurality of first differential via pairs 110 are arranged in a first array 10. A plurality of second differential via pairs 210 penetrate at least a portion of the circuit board and are connected to a signal reception channel 220 in the circuit board. The plurality of second differential via pairs 210 are arranged in a second array 20. The second array 20 is located on one side of the first array 10 along the row direction. Figure 2A As shown, in the first array 10 and the second array 20, differential via pairs are arranged in rows and columns along the X and Y directions. For example, the first differential via pair 110 is arranged in multiple rows along the X direction and multiple columns along the Y direction, thus forming the first array 10; the second differential via pair 210 is arranged in multiple rows along the X direction and multiple columns along the Y direction, thus forming the second array 20. Therefore, the X direction is also referred to as the row direction and the Y direction as the column direction in the following text. The X and Y directions intersect, for example, they can be perpendicular to each other.

[0045] The first differential via pair 110 includes a first differential via 1101 and a second differential via 1102. The second differential via pair 210 includes a third differential via 2101 and a fourth differential via 2102. The center-to-center spacing of the first differential via 1101 and the second differential via 1102 remains constant to maintain the continuity of the differential impedance. The first differential via 1101 and the second differential via 1102 are routed simultaneously as a whole, and the route arrangement is completely symmetrical to avoid introducing phase deviation. The center-to-center spacing of the third differential via 2101 and the fourth differential via 2102 remains constant to maintain the continuity of the differential impedance. The third differential via 2101 and the fourth differential via 2102 are routed simultaneously as a whole, and the route arrangement is completely symmetrical to avoid introducing phase deviation.

[0046] In one example, the first differential via 1101, the second differential via 1102, the third differential via 2101, and the fourth differential via 2102 may each include a central conductive post. The central conductive post may be a copper plating layer. The circuit board also includes multiple reference layers L-GND. During the circuit board design process, the conductive layer around the differential vias is removed to form a cutout area surrounding the differential vias. The cutout area is filled with dielectric material to form antipads surrounding the differential vias.

[0047] Multiple first differential via pairs 110 can obtain differential signals through the signal transmission channel 120 of the intermediate layer of the circuit board and lead the differential signals to the top layer of the circuit board for transmission. Multiple second differential via pairs 210 can lead the differential signals from the top layer of the circuit board to the signal reception channel 220 of the intermediate layer for reception.

[0048] The BGA solder balls are vertically connected to the circuit board and are directly soldered to the top layer of the circuit board. The BGA solder balls can extend the connection to the signal transmission channel 120 of other layers in the circuit board through the first differential via pair 110. The BGA solder balls can extend the connection to the signal reception channel 220 of other layers in the circuit board through the second differential via pair 210.

[0049] A differential via pair includes a pair of differential vias, and the centerline of the differential via pair refers to the line connecting the geometric centers of the projections of the two differential vias onto the circuit board in a top view. In some embodiments, the angle between the extended centerlines of adjacent first differential via pairs 110 in the row direction and the angle between the extended centerlines of adjacent second differential via pairs 210 in the row direction are both in the range of 60 degrees to 120 degrees. Figure 2A As shown, the centerline extensions of two adjacent first differential via pairs 110 in the row direction (X direction in the figure) are the first centerline extension C1 and the second centerline extension C2, respectively. The included angle between the first centerline extension C1 and the second centerline extension C2 can be in the range of 60 degrees to 120 degrees, and in some embodiments, it can be in the range of 80 degrees to 90 degrees, for example, around 89 degrees. When the included angle between the first centerline extension C1 and the second centerline extension C2 is 90 degrees, the via crosstalk between two adjacent first differential via pairs 110 is relatively small. Thus, the first differential via pairs 110 are arranged in a zigzag pattern in the row direction. The second differential via pair 210 can also adopt the same layout. Figure 2AAs shown, the centerline extensions of two adjacent second differential via pairs 210 in the row direction (X direction in the figure) are the third centerline extension C3 and the fourth centerline extension C4, respectively. The included angle between the third centerline extension C3 and the fourth centerline extension C4 can be in the range of 60 degrees to 120 degrees, and in some embodiments, it can be in the range of 80 degrees to 90 degrees, for example, around 89 degrees. When the included angle between the third centerline extension C3 and the fourth centerline extension C4 is 90 degrees, the via crosstalk between two adjacent second differential via pairs 210 is relatively small. In this way, the second differential via pairs 210 also form a sawtooth-like arrangement in the row direction.

[0050] Correspondingly, multiple first BGA solder ball pairs are arranged in a first array 10, and multiple second BGA solder ball pairs are arranged in a second array 20. The angle between the extended centerlines of adjacent first BGA solder ball pairs in the row direction and the angle between the extended centerlines of adjacent second BGA solder balls in the row direction are both within the range of 60 degrees to 120 degrees. The BGA solder ball layout can directly affect the via crosstalk and via loss of the circuit board. By planning the solder ball layout, the vertical damage target and crosstalk requirements of the circuit board can be met, and it also helps with the routing of the circuit board.

[0051] According to embodiments of this application, adjacent first differential via pairs in the row direction are arranged at an angle to reduce via crosstalk between adjacent first differential via pairs. Similarly, adjacent second differential via pairs in the row direction are arranged at an angle to reduce via crosstalk between adjacent second differential via pairs, thereby reducing crosstalk on the circuit board. Arranging multiple first differential via pairs into a first array and multiple second differential via pairs into a second array, with the first and second arrays not intersecting spatially, reduces signal crosstalk during differential signal transmission and reception, further reducing crosstalk on the circuit board. This reduces transmission loss, improves signal integrity, and provides a more robust transmission environment for high-speed signals.

[0052] The angle between the extended centerlines of adjacent first differential via pair 110 and second differential via pair 210 in the row direction is within the range of 60 degrees to 120 degrees. For example... Figure 2AAs shown, the centerline extensions of adjacent first differential via pair 110 and second differential via pair 210 in the row direction (X direction in the figure) are respectively the first centerline extension C1 and the fourth centerline extension C4. The included angle between the first centerline extension C1 and the fourth centerline extension C4 can be in the range of 60 degrees to 120 degrees, and in some embodiments, it can be in the range of 80 degrees to 90 degrees, for example, around 89 degrees. When the included angle between the first centerline extension C1 and the fourth centerline extension C4 is 90 degrees, the via crosstalk between adjacent first differential via pair 110 and second differential via pair 210 is relatively small.

[0053] The center lines of the first differential via pair 110 located in the same column can be parallel to each other, and the center lines of the second differential via pair 210 located in the same column can be parallel to each other. For example... Figure 2A As shown, the centerline extensions of the first differential via pair 110 located in the same column, for example, the first centerline extension C1 and the fifth centerline extension C5, are parallel. In some embodiments, the first differential via pair 110 located in the same column can be aligned in the column direction to form a straight-line arrangement pattern. The second differential via pair 210 can also be arranged in the same column direction. Figure 2A As shown, the centerline extensions of the second differential via pair 210 located in the same column, such as the fourth centerline extension C4 and the sixth centerline extension C6, are parallel. The second differential via pairs 210 located in the same column can also be aligned in the column direction to form a straight-line arrangement pattern.

[0054] Figure 3 A schematic diagram of a circuit board according to an embodiment of this application is shown.

[0055] like Figure 3 As shown, the circuit board also includes multiple ground vias 130. The multiple ground vias 130 are connected to at least one of multiple reference layers. The reference layer may be a full copper layer on the circuit board that provides a common ground reference, providing a low-impedance return path for signal transmission.

[0056] During the transmission of high-speed signals, the first differential via pair 110 generates an outward-radiating electromagnetic field, which may couple to adjacent first differential via pairs 110 or second differential via pairs 210. By providing a ground via 130 to the first differential via pair 110, the interference current from the electromagnetic field radiated by the first differential via pair 110 can be directly introduced into the reference layer. This reduces the propagation of interference current in the circuit board and lessens its impact on other first differential via pairs 110 or second differential via pairs 210.

[0057] The first differential via pair 110 and the second differential via pair 210 are each surrounded by a grounding via 130. For example, the first differential via pair 110 is surrounded by a first grounding via loop 131, and the second differential via pair 210 is surrounded by a second grounding via loop 132.

[0058] According to embodiments of this application, the first differential via pair is surrounded by a grounding via, which forms an electromagnetic shield. This shield blocks electromagnetic field coupling between the first differential via pair and other first differential via pairs and second differential via pairs, reducing the transmission strength of interference signals and significantly reducing crosstalk. The second differential via pair is surrounded by a grounding via, which weakens crosstalk between the second differential via pair and other second differential via pairs and first differential via pairs, protecting signal integrity.

[0059] At least two rows of grounding vias 130 are provided between the first array 10 and the second array 20. For example, Figure 3 As shown, the dual grounding via column 133 includes two columns of grounding vias 130, and the dual grounding via column 133 can be arranged between the first array 10 and the second array 20. At least two grounding vias 130 are arranged between adjacent first differential via pairs 110 and second differential via pairs 210 in the row direction.

[0060] Figure 4 A schematic diagram of the simulation results using two rows of grounding holes is shown.

[0061] Two grounding vias are placed between adjacent first and second differential via pairs in the row direction, and two corresponding grounding pins are provided in the lead-out. The grounding pins and grounding vias can be connected via grounding copper foil on the surface layer of the circuit board to increase isolation. The differential signal arrangement of adjacent first and second differential via pairs in the row direction is simulated.

[0062] like Figure 4 As shown, the horizontal axis represents the signal frequency in GHz, and the vertical axis represents the loss in dB. The loss on the vertical axis is negative; the larger the absolute value of the negative value, the more severe the loss. Multiple curves exhibit a pattern of "the higher the frequency, the greater the loss." With two ground vias placed between adjacent first and second differential via pairs in the row direction, m1 represents a loss of -40.8899 at position 16.00. With one ground via placed between adjacent first and second differential via pairs in the row direction, m2 represents a loss of -56.1040 at position 16.00. Placing two ground vias between adjacent first and second differential via pairs in the row direction significantly improves crosstalk.

[0063] According to embodiments of this application, by using two rows of grounding vias for grounding shielding between the first and second arrays, near-end crosstalk between the signal transmission channel and the signal reception channel can be reduced, the signal integrity of the channel link can be improved, signal failure caused by crosstalk can be avoided, and the reliability of the system design can be increased.

[0064] According to embodiments of this application, at least one column of grounding vias 130 is provided between two adjacent columns of first differential via pairs 110 and between two adjacent columns of second differential via pairs 210. For example, as Figure 3 As shown, a first grounding via column 134 can be provided between two adjacent columns of first differential via pairs 110 to reduce crosstalk between them. A second grounding via column 135 can be provided between two adjacent columns of second differential via pairs 210 to reduce crosstalk between them.

[0065] like Figure 2B , Figure 2C and Figure 3 As shown, the circuit board also includes a plurality of differential pads 140, which are respectively connected to a plurality of first differential via pairs 110 and second differential via pairs 210, for connecting the plurality of first differential via pairs 110 and the plurality of second differential via pairs 210 to chips outside the circuit board. The spacing between adjacent differential pads 140 is in the range of 0.5mm to 1.5mm.

[0066] In some embodiments, the spacing between adjacent differential pads 140 can be in the range of 0.7 mm to 0.8 mm, for example, around 0.78 mm. When the spacing between adjacent differential pads 140 is 0.8 mm, the spacing between adjacent solder balls connected to the chip is also 0.8 mm, resulting in less electromagnetic field coupling between adjacent solder balls.

[0067] The area on the circuit board that corresponds to the solder ball array is the pad area. The pad area includes multiple first differential via pairs, multiple second differential via pairs, ground vias, and multiple differential pads. By designing the layout of the pad area, crosstalk in the pad area can be effectively reduced, and the transmission loss of the circuit board can be reduced.

[0068] Figure 5A A schematic diagram of a circuit board according to an embodiment of this application is shown.

[0069] like Figure 5A As shown, in a direction parallel to the circuit board, the circuit board includes a main wiring area 30 and a fan-out area 40 located on one side of the main wiring area.

[0070] Signal transmission channel 120 and signal reception channel 220 each include a first trace located in the main wiring area 30 and a second trace located in the fan-out area 40. The first trace is connected to a corresponding first differential via pair 110 or second differential via pair 210 via the second trace. Figure 5A As shown, a signal transmission channel 120 and a signal reception channel 220 are schematically illustrated. A first trace 1201 of the signal transmission channel 120 is connected to a corresponding first differential via pair 110 via a second trace 1202 of the signal transmission channel 120. A first trace 2201 of the signal reception channel 220 is connected to a corresponding second differential via pair 210 via a second trace 2202 of the signal reception channel 220.

[0071] According to an embodiment of this application, the first trace and the second trace each include a differential trace pair. The differential trace pair of the first trace is connected to a corresponding first differential via pair 110 or second differential via pair 210 through the differential trace pair of the second trace. The differential trace pair of the first trace includes a first differential trace and a second differential trace. The differential trace pair of the second trace includes a third differential trace and a fourth differential trace.

[0072] like Figure 5A and Figure 2B As shown, the first differential trace A1 of the first trace 1201 of the signal transmission channel 120 can be connected to the first differential via 1101 via the third differential trace A3 of the second trace 1202 of the signal transmission channel 120. The second differential trace A2 of the first trace 1201 of the signal transmission channel 120 can be connected to the second differential via 1102 via the fourth differential trace A4 of the second trace 1202 of the signal transmission channel 120. For example... Figure 5A and Figure 2C As shown, the first differential trace B1 of the first trace 2201 of the signal receiving channel 220 can be connected to the third differential via 2101 via the third differential trace B3 of the second trace 2202 of the signal receiving channel 220. The second differential trace B2 of the first trace 2201 of the signal receiving channel 220 can be connected to the fourth differential via 2102 via the fourth differential trace B4 of the second trace 2202 of the signal receiving channel 220.

[0073] Similarly, such as Figure 5A , Figure 2B and Figure 2C As shown, both the signal transmission channel 120 and the signal reception channel 220 further include a third trace located in the region where the first array 10 is located. The third trace also includes differential trace pairs, which include a fifth differential trace and a sixth differential trace. The differential trace pairs of the second trace can be connected to the corresponding first differential via pairs or second differential via pairs through the third trace pairs, respectively.

[0074] The third differential trace A3 of the second trace 1202 of the signal transmission channel 120 can be connected to the first differential via 1101 via the fifth differential trace A5 of the third trace of the signal transmission channel 120. The fourth differential trace A4 of the second trace 1202 of the signal transmission channel 120 can be connected to the second differential via 1102 via the sixth differential trace A6 of the third trace of the signal transmission channel 120. The third differential trace B3 of the second trace 2202 of the signal reception channel 220 can be connected to the third differential via 2101 via the fifth differential trace B5 of the third trace of the signal reception channel 220. The fourth differential trace B4 of the second trace 2202 of the signal reception channel 220 can be connected to the fourth differential via 2102 via the sixth differential trace B6 of the third trace of the signal reception channel 220.

[0075] In one example, the second trace 2202 of the signal receiving channel 220 is connected to the second differential via pair 210 via a third trace of the signal receiving channel 220. The third trace of the signal receiving channel 220 has a wavy shape, which can avoid layout obstacles in a limited space.

[0076] like Figure 5A As shown, the first array 10 is located on the side of the fan-out area 40 away from the main wiring area 30, and the second array 20 is located on the side of the first array 10 away from the fan-out area 40.

[0077] The differential vias in the first array 10 are used to transmit the differential signals sent by the serial-to-parallel converter to the middle layer of the circuit board, and the differential vias in the second array 20 are used to transmit the differential signals from the middle layer of the circuit board to the serial-to-parallel converter. The differential vias in the first array 10 are closer to the fan-out area than the differential vias in the second array 20, which can relatively reduce the transmission distance of the first array 10 and better maintain the signal integrity of the differential signals sent by the serial-to-parallel converter before they are processed by the circuit board.

[0078] Figure 5B A schematic diagram of a circuit board according to an embodiment of this application is shown.

[0079] like Figure 5A and Figure 5B As shown, the main wiring area 30 can accommodate the first traces of multiple signal transmission channels 120 and signal reception channels 220. The routing rules in the main wiring area 30 are relatively loose, and the space is relatively ample. The fan-out area 40 can accommodate the second traces of multiple signal transmission channels 120 and signal reception channels 220. The routing rules in the fan-out area 40 are relatively compact, and the space is relatively limited. For example, differential signals need to "escape" from the relatively dense multiple first differential via pairs 110 of the first array 10, and transition through the fan-out area 40 to the main wiring area 30.

[0080] In a direction perpendicular to the circuit board, the circuit board includes multiple signal layers, multiple reference layers alternately arranged with the signal layers, and dielectric layers located between adjacent signal layers and reference layers. Signal transmission channels and signal reception channels are located in at least one of the multiple signal layers. At least one of the signal transmission channel 120 and signal reception channel 220 is a high-speed channel used to transmit signals at a data rate of 224 Gbps.

[0081] Figure 6A A schematic diagram of a circuit board according to an embodiment of this application is shown.

[0082] Figure 6B A schematic diagram of a cutout area of ​​a circuit board according to an embodiment of this application is shown.

[0083] Figure 6C A schematic diagram of a cross-section of the main wiring area according to an embodiment of this application is shown.

[0084] In one example, such as Figure 6B As shown, the circuit board includes a first signal layer TOP, a second reference layer L2, a third signal layer L3, a fourth reference layer L4, a fifth signal layer L5, a sixth reference layer L6, a seventh signal layer L7, an eighth reference layer L8, a ninth signal layer L9, a tenth reference layer L10, and an eleventh signal layer L11. The circuit board also includes, for example, a dielectric layer between the first signal layer TOP and the second reference layer L2.

[0085] Besides crosstalk in the pad area, the transmission loss of a circuit board also includes vertical loss, which represents the electrical performance loss of a differential signal as it travels from the top layer to the middle layers. Vertical loss includes dielectric loss and conductor loss. Low-loss materials can be used to mitigate dielectric and conductor losses. For example, Megtron-8 grade low-loss materials can be used to reduce signal loss during transmission. Megtron-8 grade materials have a low dielectric constant and ultra-low dielectric loss factor. This low-loss characteristic reduces energy attenuation of high-speed signals during transmission, preventing signal integrity degradation due to excessive loss and maintaining signal integrity. Megtron-8 materials also offer loss control capabilities at high frequencies above 45 GHz.

[0086] Vertical losses on a circuit board can also be reduced by designing the routing of multiple signal layers, multiple reference layers, and multiple dielectric layers.

[0087] A serial-to-parallel converter (Serial-to-Parallel converter) can convert parallel data to serial data and vice versa. The Serial-to-Parallel converter signal represents the high-speed serial signal after processing by the converter. The shallow layer of a circuit board refers to the area near the surface of the board, such as the first signal layer (TOP). The Serial-to-Parallel converter signal can be set on the first signal layer (TOP). The transmitter of the Serial-to-Parallel converter receives parallel data and performs a parallel-to-serial conversion to generate a high-speed serial data stream. A differential driver receives the serial data stream and converts it into a pair of differential signals. A differential receiver receives the differential signals through circuit board traces and restores the differential signals to the serial data stream. The receiver of the Serial-to-Parallel converter receives the serial data stream and performs a serial-to-parallel conversion to recover the parallel data.

[0088] According to embodiments of this application, by placing the serial-to-parallel converter in a shallow layer of the circuit board, the via depth required for differential signal layer switching can be significantly reduced, which can further reduce the vertical loss and interlayer crosstalk of the circuit board.

[0089] In the main routing area 30, the reference layer and signal layer adjacent to the signal layer where the first trace of the high-speed channel is located include a cutout area 310, and the orthographic projection of the first trace of the high-speed channel on the circuit board at least partially overlaps with the orthographic projection of the cutout area on the circuit board.

[0090] According to embodiments of this application, at least one of the plurality of signal transmission channels and the plurality of signal reception channels in the circuit board can be a high-speed channel. For example, the number of high-speed channels can be multiple, including both signal transmission channels and signal reception channels. Figure 6A and Figure 6B As shown, the high-speed channel 150 can be located in the fifth signal layer L5. In the main cabling area 30, the reference layers adjacent to the fifth signal layer L5 include the fourth reference layer L4 and the sixth reference layer L6. The fourth reference layer L4 includes a first cutout area 3101, and the sixth reference layer L6 includes a second cutout area 3102. The signal layers adjacent to the fifth signal layer L5 include the third signal layer L3 and the seventh signal layer L7. The third signal layer L3 includes a third cutout area 3103, and the seventh signal layer L7 includes a fourth cutout area 3104. In other words, the cutout area 310 includes the first cutout area 3101 in the fourth reference layer L4, the second cutout area 3102 in the sixth reference layer L6, the third cutout area 3103 in the third signal layer L3, and the fourth cutout area 3104 in the seventh signal layer L7.

[0091] In the main wiring area 30, the orthographic projection of the first trace 1501 of the high-speed channel 150 on the circuit board at least partially overlaps with the orthographic projection of the cutout area 310 on the circuit board. In one example, such as Figure 6CAs shown, the first trace 1501 of the high-speed channel 150 is located in the fifth signal layer L5. The adjacent reference layers of the fifth signal layer L5 include the fourth reference layer L4, which includes a first cutout region 3101. The orthographic projection T1 of the first trace 1501 on the circuit board and the orthographic projection T2 of the first cutout region 3101 on the circuit board partially overlap. When the third signal layer L3, fourth reference layer L4, sixth reference layer L6, and seventh signal layer L7 are not cutout-designed, these layers are all metallic conductors, which can interfere with the high-frequency current of the adjacent first trace 1501 of the high-speed channel 150. When the third signal layer L3, fourth reference layer L4, sixth reference layer L6, and seventh signal layer L7 are cutout-designed, the cutout region 310 around the first trace 1501 of the high-speed channel 150 can effectively block electromagnetic coupling effects. The high-speed channel 150 can connect the second reference layer L2 and the eighth reference layer L8 across layers, reducing the transmission loss of the high-speed channel 150, further reducing the vertical loss of the circuit board, and thus further reducing the transmission loss of the circuit board.

[0092] like Figure 6A , Figure 6B and Figure 6C As shown, in one embodiment, the orthographic projection of the first trace 1501 of the high-speed channel 150 onto the circuit board may lie within the orthographic projection of the cutout area onto the circuit board. In one example, as... Figure 6C As shown, the orthographic projection T1 of the first trace 1501 of the high-speed channel 150 on the circuit board is located inside the orthographic projection T2 of the first cutout area 3101 on the circuit board.

[0093] like Figure 6A , Figure 6B and Figure 6C As shown, in one embodiment, the ratio of the gap width between the orthographic projection of the first trace 1501 of the high-speed channel 150 on the circuit board and the orthographic projection of the cutout area on the circuit board to the width of the first trace 1501 of the high-speed channel 150 can be in the range of 20% to 40%. In one example, as... Figure 6CAs shown, the ratio of the gap width W1 between the orthographic projection T1 of the first trace 1501 of the high-speed channel 150 on the circuit board and the orthographic projection T2 of the first cutout area 3101 on the circuit board to the width W2 of the first trace 1501 of the high-speed channel 150 can be in the range of 20% to 40%. For example, the ratio of the gap width W1 to the width W2 of the first trace 1501 of the high-speed channel 150 can be 20%, 30%, or 40%. When the ratio of the gap width W1 to the width W2 of the first trace 1501 of the high-speed channel 150 is 30%, the width of the first cutout area 3101 is 30% greater than the width W2 of the first trace 1501 of the high-speed channel 150.

[0094] According to an embodiment of this application, the medium layers on both sides of the hollowed-out region 310 are in contact with each other in the hollowed-out region 310.

[0095] According to an embodiment of this application, the medium layer on one side of the hollowed-out area can be a prepreg (pre-impregnated) material, and the medium layer on the other side of the hollowed-out area can be a core material. In the hollowed-out area 310, the medium layer including the prepreg material collapses toward the medium layer including the core material.

[0096] like Figure 6C As shown, the dielectric layer on the upper side of the fourth reference layer L4 is a prepreg material, and the dielectric layer on the lower side of the fourth reference layer L4 is a core board material. In the first cutout region 3101, the dielectric layer on the upper side of the fourth reference layer L4 collapses towards the dielectric layer on the lower side of the fourth reference layer L4, and the dielectric layers on the upper and lower sides of the fourth reference layer L4 come into contact in the first cutout region 3101.

[0097] The prepreg material is malleable and melts, flows, and eventually fully cures under certain temperature and pressure. The dielectric layer of the prepreg material can fill the empty areas on its upper and lower surfaces. The core board material is a fully cured rigid board. The dielectric layer between the fourth reference layer L4 and the third signal layer L3 is the prepreg material, and the dielectric layer between the fourth reference layer L4 and the fifth signal layer L5 is the core board material. During the circuit board processing and lamination, the dielectric layer between the fourth reference layer L4 and the third signal layer L3 fills the first cutout area 3101 and the third cutout area 3103 with the prepreg material.

[0098] Figure 6D A schematic diagram showing the simulation results of cross-layer routing according to an embodiment of this application is illustrated.

[0099] like Figure 6DAs shown, the horizontal axis represents frequency in GHz, and the vertical axis represents loss in dB / inch. With cross-layer routing, m3 indicates a crosstalk of -0.95 at position 53.00, achieving a loss of 0.95 dB / inch. Without cross-layer routing, m4 indicates a crosstalk of -1.5 at position 53.00, resulting in a loss of 1.5 dB / inch. According to embodiments of this application, using cross-layer routing can reduce circuit board trace losses.

[0100] Figure 7A A schematic diagram of a circuit board according to an embodiment of this application is shown.

[0101] Figure 7B A schematic diagram of a circuit board according to an embodiment of this application is shown.

[0102] like Figure 7A and Figure 7B As shown, the circuit board also includes a connection via 160 connected to the high-speed channel 150. The connection via 160 electrically connects the first trace 1501 and the second trace 1502 of the high-speed channel 150, or electrically connects the first trace 1501 or the second trace 1502 of the high-speed channel 150 to other components.

[0103] When the first trace 1501 and the second trace 1502 of the high-speed channel 150 are located on different layers of the circuit board, the connecting via 160 can electrically connect the first trace 1501 and the second trace 1502 of the high-speed channel 150.

[0104] In the presence of other components on the circuit board, where it is not necessary to connect them through the first differential via pair 110 and the second differential via pair 210, the connecting via 160 can electrically connect the first trace 1501 of the high-speed channel 150 to other components, or the connecting via 160 can electrically connect the second trace 1502 of the high-speed channel 150 to other components.

[0105] At least one of the first differential via pair 110, the second differential via pair 210, and the connecting via 160 connected to the high-speed channel 150 has a via depth in the range of 55 mil to 75 mil and a via remnant S1 length of less than 4 mil, the via remnant S1 being the portion of the via that does not serve an effective connection function.

[0106] In one example, such as Figure 7A and Figure 7BAs shown, the connecting via 160 electrically connects the high-speed channel 150 to other components. The connecting via 160 has a via depth in the range of 55 mil to 75 mil and a via fragment S1 length of less than 4 mil. In some embodiments, the via length of the connecting via 160 can be in the range of 60 mil to 65 mil, for example, around 64 mil. In some embodiments, the via fragment S1 length can be in the range of 3.8 mil to 4 mil. With a via length of 65 mil and a via fragment S2 length of 4 mil, the loss of the connecting via 160 is 1 dB.

[0107] Vias introduce parasitic inductance and capacitance when penetrating multiple layers of a circuit board, and the via remnant S1 can also cause resonance, resulting in vertical loss. Shorter via depths can introduce less parasitic inductance, and shorter via remnants S1 can reduce resonance and impedance discontinuities, thereby effectively reducing energy attenuation and phase distortion of differential signals when vertically traversing the medium, ensuring the rising edge quality and timing of serial link signals.

[0108] like Figure 7B As shown, the circuit board is also provided with a connection pad 170. The first trace of the high-speed channel 150 is connected to the connection pad 170 via the connection via 160. The connection pad 170 is used to connect to the pin 510 of the connector outside the circuit board.

[0109] With the connection pad 170 connected to the connector pin 510, the size of the residual segment S2 of the connection pad 170 is in the range of 5 mil to 15 mil. This residual segment S2 is the portion of the connection pad 170 that does not effectively connect the via 160 to the connector. The size of the residual segment S2 is its length along the extending direction of the connection pad 170. In some embodiments, the size of the residual segment S2 of the connection pad 170 can be in the range of 9 mil to 11 mil, for example, around 10 mil.

[0110] The connector can be a surface-mount (SMT) connector. SMT connectors are mounted on pads on a circuit board using surface-mount technology. A reflow oven melts and solidifies the solder paste, thus securing the surface-mount connector to the circuit board. In one embodiment, the SMT connector can be an OSFP (Octal Small Form-factor Pluggable) connector. The OSFP connector is connected to connection pad 170 for simulation verification.

[0111] Figure 7CA schematic diagram showing simulation results of the remnants of the connection pads according to an embodiment of this application is illustrated.

[0112] like Figure 7C As shown, the horizontal axis represents frequency in GHz, and the vertical axis represents loss in dB / inch. With a 27mil dimension for the stub S2 connecting pad 170, m6 indicates a crosstalk of -4.26 dB / inch and a loss of 4.26 dB / inch at position 53.00. With a 10mil dimension for the stub S2 connecting pad 170, m5 indicates a crosstalk of -2.65 dB / inch and a loss of 2.65 dB / inch at position 53.00. Reducing the dimension of the stub S2 connecting pad 170 from 27mil to 10mil reduces the loss by 1.6 dB. With two OSFP connectors included, the loss can be improved by 3.2 dB, allowing for a trace extension of approximately 3 inches on the board.

[0113] This application also provides a circuit assembly.

[0114] Figure 8 A schematic diagram of a circuit assembly according to an embodiment of this application is shown.

[0115] like Figure 8 As shown, the circuit assembly 800 includes a circuit board 100 and a chip 200.

[0116] Chip 200 is located on circuit board 100. For example... Figure 1 , Figure 4 and Figure 8 As shown, chip 200 is electrically connected to signal transmission channel 120 and signal reception channel 220 in circuit board 100. In one example, a plurality of first solder ball pairs, such as a first array 10, and a plurality of second solder ball pairs, such as a second array 20, are provided between chip 200 and circuit board 100. Chip 200 is electrically connected to signal transmission channel 120 via first differential via pairs 110 on circuit board 100 through first solder ball pairs. Chip 200 is electrically connected to signal reception channel 220 via second differential via pairs 210 on circuit board 100 through second solder ball pairs.

[0117] The chip 200 is soldered to the circuit board through multiple first solder ball pairs and multiple second solder ball pairs, thereby achieving electrical connection and mechanical fixation between the chip 200 and the circuit board 100.

[0118] According to an embodiment of this application, chip 200 is connected to signal transmission channel 120 and signal reception channel 220 in circuit board 100 via a plurality of differential pads on circuit board 100. Chip 200 is electrically connected to signal transmission channel 120 via a first solder ball pair connected to the differential pads of a first differential via pair 110 on circuit board 100. Chip 200 is electrically connected to signal reception channel 220 via a second solder ball pair connected to the differential pads of a second differential via pair 210 on circuit board 100.

[0119] According to embodiments of this application, the circuit assembly 800 may be a switch motherboard, a network card, or a general-purpose substrate.

[0120] In one example, circuit assembly 800 may be a switch motherboard. The switch motherboard may include a multi-port switching chip and a circuit board. The multi-port switching chip is connected to signal transmission and signal reception channels on the circuit board via multiple differential pads on the circuit board.

[0121] In one example, circuit assembly 800 can be a network interface card (NIC). The NIC can include a PCIe (Peripheral Component Interconnect express) chip and a circuit board. PCIe NIC chips have a large number of pins, which can be fully connected on a small circuit board using BGA packaging. The PCIe NIC chip connects to the signal transmission and reception channels on the circuit board via multiple differential pads, enabling high-speed signal transmission and reception within a limited space.

[0122] Figure 9 A schematic diagram of an electronic device according to an embodiment of this application is shown.

[0123] like Figure 9 As shown, the electronic device 900 includes a circuit assembly 800 and a connector 50.

[0124] One end of connector 50 is connected to the pads of circuit board 100 in circuit assembly 800, and the other end of connector 50 is connected to another component in electronic device 900 other than circuit assembly 800. The other end of connector 50 can be connected to another component in electronic device 900 other than circuit assembly 800 via cable 60.

[0125] In one embodiment, the electronic device 900 may be a 224G switching system. The 224G switching system includes 512 channels, each with a data rate of 224Gbps and a capacity of 100T when using PAM4 technology. Each channel may include a circuit assembly 800 and cables. The circuit assembly 800 may include a chip 200 and a circuit board 100. The chip 200 may be a 224G switch chip. The total length of the wiring for the signal transmission channel 120 and the signal reception channel 220 on the circuit board 100 may be 10 inches. Two connectors 50 are provided at both ends of the cable 60, and the cable 60 is 1 meter long.

[0126] To address the link loss of a 224G switching system at 53GHz, system-level simulation methods can be used to predict system performance before circuit board manufacturing.

[0127] The link loss of a 224G switching system at 53GHz can be evaluated using a frequency domain testing method based on a vector network analyzer. By connecting the ports of the vector network analyzer to the input and output of the link under test via precision cables, a continuous loss curve is obtained. The continuous loss curve visually reveals the degree of link attenuation at different frequency points, including the total loss caused by the combined effects of dielectric materials, conductor roughness, and impedance discontinuities.

[0128] In the design of 224G switching system channels, the selection of circuit board substrate and conductor surface treatment processes can ensure signal integrity. The circuit board substrate can use Megtron-8 grade EM892K board material. EM892K board material has extremely low and stable dielectric constant and loss factor, which can effectively suppress distortion and energy attenuation of high-frequency signals during transmission. The signal layer and reference layer of the circuit board use copper foil, such as Hyper Very Low Profile Copper Foil (HVLP). HVLP3 has a low surface roughness, making the surface of the signal layer and reference layer of the circuit board smoother, which can effectively reduce signal transmission distance and loss.

[0129] Table 1 shows the link loss evaluation table for the 224G switching system under the first design.

[0130] In the first design, the via fragment length of the 224G switching system circuit board is designed to be 4 mil. As shown in Table 1, the chip package loss is 3.7 dB. The connector and cable loss is 15 dB. The trace length in the main wiring area of ​​the PCB (Printed Circuit Board) is 4 inches, and the trace length in the fan-out area of ​​the PCB is 1 inch. The trace loss in the main wiring area of ​​the PCB is 1.5 dB / inch. The trace loss in the fan-out area of ​​the PCB is 2.37 dB / inch.

[0131] Under the first design, the 224G switching system has a via loss of 1dB and an estimated link loss of 44.14dB. The PDG (Platform Design Guide) estimates the link channel loss at 40dB. Therefore, the link loss is relatively high under the first design.

[0132] Table 1

[0133]

[0134] Table 2

[0135]

[0136] Table 2 shows a schematic diagram of the circuit board trace stack for the channels of the 224G switching system.

[0137] As shown in Table 2, the circuit board of the 224G switching system includes multiple signal layers, multiple reference layers alternating with the signal layers, and dielectric layers located between adjacent signal and reference layers. High-speed channels reside in at least one of the signal layers. The circuit board can use Megtron-8 grade EM892K board material. The signal and reference layers use copper foil; the copper foil type for the top of the first signal layer is 0.5oz HTE (High Temperature Elongation) copper foil, which is electroplated for thickness. The copper foil type for the other signal and reference layers is 1oz HVLP3. The dielectric layer adjacent to the reference layer above uses prepreg material, and the dielectric layer adjacent to the reference layer below uses core board material.

[0138] The main routing area containing the high-speed channel can be located in the fifth signal layer L5. The reference layers adjacent to the fifth signal layer L5 include the fourth reference layer L4 and the sixth reference layer L6. The signal layers adjacent to the fifth signal layer L5 include the third signal layer L3 and the seventh signal layer L7. The third signal layer L3, the fourth reference layer L4, the sixth reference layer L6, and the seventh signal layer L7 are hollowed out, so that the orthographic projection of the first trace of the high-speed channel on the circuit board is located inside the orthographic projection of the hollowed-out area on the circuit board. The high-speed channel can connect across layers to the second reference layer L2 and the eighth reference layer L8 to reduce the transmission loss of the high-speed channel, thereby reducing the transmission loss of the circuit board.

[0139] Table 3 shows the link loss evaluation table for the 224G switching system under the second design.

[0140] In the second design, the via fragment length of the 224G switching system circuit board is designed to be 4 mil, and the main wiring area of ​​the circuit board is designed with a cut-out area and cross-layer routing. As shown in Table 3, the chip package loss is 3.7 dB. The connector and cable loss is 15 dB. The wiring length of the main wiring area of ​​the PCB is 4 inches, and the wiring length of the fan-out area of ​​the PCB is 1 inch. The wiring loss of the fan-out area of ​​the PCB is 2.37 dB.

[0141] By designing a hollowed-out area and routing traces across layers, the wiring loss in the main wiring area of ​​the PCB was reduced from 1.5dB / inch to 0.95dB / inch.

[0142] In the second design, the via loss of the 224G switching system is 1dB. By routing the traces across layers, the estimated link loss is reduced from 44.14dB to 39.74dB. The second design effectively improves the link margin. Link margin represents the "redundancy space" between the actual performance of the link and the minimum performance required for normal operation.

[0143] As shown in Table 3, connector and cable losses account for 40% of the overall loss, making them the main source of link loss. Connector losses are 4.26 dB, making them the primary source of loss for both connectors and cables.

[0144] Connector losses can be improved. For example... Figure 7C As shown, reducing the size of the connector pad stub from 27 mil to 10 mil reduces loss by 1.6 dB / inch, compared to 2.65 dB for the connector itself. With two connectors included, the loss improvement is 3.2 dB.

[0145] Table 4 shows the link loss evaluation table for the 224G switching system under the third design.

[0146] In the third design, the via fragment length of the 224G switching system circuit board is designed to be 4 mil. The main wiring area of ​​the circuit board is designed with a cutout area and cross-layer routing. The size of the connection pad fragment is designed to be 10 mil. As shown in Table 4, the chip package loss is 3.7 dB. The connector and cable loss is 11.8 dB. The wiring length of the main wiring area of ​​the PCB is 4 inches, and the wiring length of the fan-out area of ​​the PCB is 1 inch. The wiring loss of the fan-out area of ​​the PCB is 2.37 dB.

[0147] By designing a hollowed-out area and routing traces across layers, the wiring loss in the main wiring area of ​​the PCB was reduced from 1.5dB / inch to 0.95dB / inch.

[0148] In the third design, the 224G switching system's channel has a via loss of 1dB and a connector and cable loss of 11.8dB. By routing the cables across layers, the estimated link loss is reduced from 44.14dB to 36.54dB. The third design further effectively improves the link margin.

[0149] Table 3

[0150]

[0151] Table 4

[0152]

[0153] In the design of high-speed links in 224G switching systems, ensuring impedance control of the signal link is crucial. The core requirement is that the characteristic impedance of the transmission line must remain consistent from the driver to the receiver. Even minute impedance fluctuations can trigger signal reflections, leading to waveform distortion and timing issues. The characteristic impedance deviation of the transmission line must be controlled within ±5% or even less. In circuit board routing, impedance discontinuities can affect signal integrity. When a transmission line experiences a sudden change in line width, the distributed inductance and capacitance on the line change abruptly, disrupting impedance uniformity. Vias connecting different signal layers, with their complex three-dimensional structures, introduce parasitic inductance and capacitance. Right-angle designs at transmission line corners can easily generate concentrated parasitic capacitance, causing a local impedance drop at the corner. 45° bevels or even better, rounded traces can be used as alternatives. Rounded traces provide a smooth impedance transition, with the machining accuracy deviation of the radius limited to ≤0.5 mil. Through collaborative design and manufacturing, high-speed signal transmission is guaranteed throughout the entire high-speed link's signal transmission path.

[0154] For cross-layer routing designs on circuit boards, more routing layers are needed. Therefore, the physical depth of the vias connecting different signal layers increases, altering the via's electrical characteristics. From an equivalent circuit model perspective, vias inherently exhibit capacitive impedance, typically displaying low impedance characteristics. However, as the depth of the vias increases, their inductive impedance also increases, exceeding the capacitive impedance and resulting in an impedance discontinuity.

[0155] Optimize the impedance of the connecting vias in the link. Control the impedance of the connecting vias to be no more than 100 ohms ±5%. For example, control the via length to be approximately 65 mil, and control the length of the via stub to be <= 4 mil. The longer the via stub, the lower the resonant point of the connecting via will appear. It is necessary to ensure that the resonant point does not appear within the 53 GHz frequency range.

[0156] Figure 10 A schematic diagram showing the simulation results of the connection via according to an embodiment of this application is illustrated.

[0157] like Figure 10 As shown in section (a), the link can effectively handle UHF signals from a lower lower frequency limit up to 55 GHz, with a return loss better than -15 dB below 55 GHz. Return loss represents how much signal power is reflected back and can be used to measure the strength of the reflected signal. -15 dB is a commonly used engineering threshold. Figure 10 As shown in section (b), the link can effectively handle ultra-high frequency signals from a low lower frequency limit to up to 59 GHz. The link attenuation does not exceed 1 dB across the entire frequency range. Figure 10 As shown in section (c), the link can effectively handle ultra-high frequency signals from a lower lower limit frequency to up to 53 GHz. The far-end crosstalk below 53 GHz is better than -57 dB. Far-end crosstalk refers to crosstalk measured at the far end of the link where the interfering signal travels in the same direction as the main signal. The return loss, bandwidth, and far-end crosstalk of the 224G switching system link all meet the design requirements.

[0158] Figure 11 A flowchart illustrating the operation of an optimized design method for a high-speed link in a 224G switching system according to an embodiment of this application is shown.

[0159] like Figure 11 As shown, the optimization design method for the high-speed link of the 224G switching system includes operations S1110 to S1160.

[0160] In operation S1110, the positions of multiple first differential via pairs, multiple second differential via pairs, and multiple connecting vias are determined.

[0161] For high-speed links in 224G switching systems, identify the via areas that need optimization in BGA solder ball areas or other areas with dense vias.

[0162] In operation S1120, adjust the via depth of the first differential via pair, the second differential via pair, and the connecting via.

[0163] When operating S1130, adjust the size of the remaining segment connecting the pads.

[0164] In operation S1140, determine the layer of the main cabling area.

[0165] Based on the circuit board stack-up and board material, via impedance, connector impedance, and the layer of the main wiring area, in operation S1150, determine whether the loss of the simulated cross via meets the link requirements. If the loss of the simulated cross via does not meet the link requirements, return to operation S1120. If the loss of the simulated cross via meets the link requirements, execute operation S1160.

[0166] In operation S1160, the circuit board stack-up and board material, the first differential via pair, the second differential via pair, the via depth of the connecting vias, the dimensions of the connecting pad remnants, and the layer of the main wiring area are determined.

[0167] The link requirements for high-speed links in a 224G switching system refer to meeting the requirements of encapsulation technology specifications.

[0168] The finalized circuit board stack-up and board material, first differential via pair, second differential via pair, via depth of connecting vias, dimensions of connecting pad remnants, and layers of the main wiring area are incorporated into the circuit board design for fabrication.

[0169] Based on the circuit board design, the circuit board data is used as the film for etching the copper foil layer of the circuit board. The traces of each intermediate layer of the circuit board are exposed, developed, and etched. After etching, a surface polypropylene (PP) layer and copper foil are added to the core board of each intermediate layer, followed by lamination, drilling, copper plating, and further etching of the surface copper foil to complete the circuit board trace fabrication.

[0170] For high-speed signals in high-speed links of 224G switching systems, when data rates are in the 53GHz band, the core of transmission loss is the skin effect, with a skin depth on the order of approximately 0.3 micrometers. The vast majority of the current is confined to an extremely thin space on the surface of the conductor. Skin depth represents the surface thickness through which high-frequency alternating current can effectively penetrate and flow in the copper foil traces of a circuit board. Since high-frequency alternating current is concentrated on the copper foil surface of the circuit board, reducing the surface roughness of the transmission lines can mitigate signal attenuation. The surface roughness of the transmission lines needs to be <0.1μm. Scratches, dents, or uneven thickness generated during electroplating on the transmission line surface increase conductor loss and insertion loss, and also exacerbate phase noise. In circuit board manufacturing, using high-precision electrochemical polishing or ultra-flat copper foil processes to smooth the transmission line surface can create an ideal transmission channel for high-speed signals in the high-speed links of 224G switching systems.

[0171] For high-speed signals in the high-speed links of 224G switching systems, the interlayer alignment and stack-up accuracy control of circuit boards require strict control of interlayer offset in multilayer boards. This offset must be limited to a very small range, such as less than 25 micrometers, to ensure power integrity and maintain the expected electromagnetic field distribution. Even slight variations in dielectric thickness directly alter the capacitance of transmission lines, thus affecting their characteristic impedance. Dielectric thickness deviations must be controlled, for example, to <±3%. Furthermore, while the linewidth tolerance of 100G circuit boards is acceptable at ±10μm, the linewidth tolerance of 224G switching system circuit boards needs to be controlled within ±5μm, or ±3μm, to prevent impedance deviations exceeding ±5Ω. The design target for impedance deviation is typically 50Ω ±10%. The etching process demands high precision; for example, the concentration and temperature of the etching solution must be controlled in real-time in a closed-loop manner, with dynamic fine-tuning of parameters such as the concentration, temperature, and spray pressure of the etching solution.

[0172] During via fabrication, in addition to the via fragment being controlled to within 4mil, the increased number of traces leads to many buried / blind via designs, increasing the difficulty of circuit board fabrication. At the same time, the roughness of the via wall needs to be controlled; for example, a via wall roughness of ≤0.5μm can prevent increased conductor loss.

[0173] The manufacturing challenge of circuit boards for high-speed links in 224G switching systems lies in maintaining signal integrity at ultra-high frequencies. Besides design optimization, the manufacturing process requires optimization across multiple dimensions, including materials, processes, and testing. For example, low-loss substrates can be used, and low-roughness copper foil can be employed. High-precision etching, drilling, and lamination processes are also crucial. Furthermore, ultra-high-resolution testing methods are essential. The goal is to balance reliability and cost during the optimized design and manufacturing process.

[0174] Those skilled in the art will understand that the features described in the various embodiments of this application can be combined and / or combined in various ways, even if such combinations or combinations are not explicitly described in this application. In particular, the features described in the various embodiments of this application can be combined and / or combined in various ways without departing from the spirit and teachings of this application. All such combinations and / or combinations fall within the scope of this application.

[0175] The embodiments of this application have been described above. However, these embodiments are merely illustrative and not intended to limit the scope of this application. Although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination. Without departing from the scope of this application, those skilled in the art can make various substitutions and modifications, all of which should fall within the scope of this application.

Claims

1. A circuit board, characterized in that, The circuit board includes: A plurality of first differential via pairs penetrate at least a portion of the circuit board and are connected to a signal transmission channel in the circuit board, the plurality of first differential via pairs being arranged in a first array; Multiple second differential via pairs penetrate at least a portion of the circuit board and are connected to a signal receiving channel in the circuit board. The multiple second differential via pairs are arranged in a second array, which is located on one side of the first array along the row direction. The signal transmitting channel is used to transmit differential signals; the signal receiving channel is used to receive differential signals. Among them, the angle between the extended centerlines of adjacent first differential via pairs and second differential via pairs in the row direction is in the range of 60 degrees to 120 degrees; The angle between the centerline extensions of adjacent first differential via pairs in the row direction and the angle between the centerline extensions of adjacent second differential via pairs in the row direction are both within the range of 60 degrees to 120 degrees.

2. The circuit board according to claim 1, characterized in that, The centerlines of the first differential via pair in the same column are parallel to each other, and the centerlines of the second differential via pair in the same column are parallel to each other.

3. The circuit board according to claim 1, characterized in that, The circuit board also includes multiple grounding vias, with the first differential via pair and the second differential via pair each surrounded by grounding vias.

4. The circuit board according to claim 3, characterized in that, At least two columns of grounding vias are provided between the first array and the second array.

5. The circuit board according to claim 3, characterized in that, At least one column of grounding vias is provided between two adjacent columns of first differential via pairs and between two adjacent columns of second differential via pairs.

6. The circuit board according to claim 1, characterized in that, The circuit board also includes multiple differential pads, which are respectively connected to multiple first differential via pairs and second differential via pairs, for connecting multiple first differential via pairs and multiple second differential via pairs to chips outside the circuit board. The spacing between adjacent differential pads is in the range of 0.5mm to 1.5mm.

7. The circuit board according to claim 1, characterized in that, In a direction parallel to the circuit board, the circuit board includes a main wiring area and a fan-out area located on one side of the main wiring area. The signal transmission channel and the signal reception channel each include a first trace located in the main wiring area and a second trace located in the fan-out area. The first trace is connected to the corresponding first differential via pair or second differential via pair via the second trace. The first array is located on the side of the fan-out area away from the main wiring area, and the second array is located on the side of the first array away from the fan-out area.

8. The circuit board according to claim 7, characterized in that, In a direction perpendicular to the circuit board, the circuit board includes multiple signal layers, multiple reference layers alternately disposed with the multiple signal layers, and a dielectric layer located between adjacent signal layers and reference layers. Signal transmission channels and signal reception channels are located in at least one of the multiple signal layers. At least one of the signal transmission channel and the signal reception channel is a high-speed channel, said high-speed channel being used to transmit signals at a data rate of 224Gbps; In the main routing area, the reference layer and signal layer adjacent to the signal layer where the first trace of the high-speed channel is located include a cut-out area, and the orthographic projection of the first trace of the high-speed channel on the circuit board at least partially overlaps with the orthographic projection of the cut-out area on the circuit board.

9. The circuit board according to claim 8, characterized in that, The orthographic projection of the first trace of the high-speed channel on the circuit board is located inside the orthographic projection of the cutout area on the circuit board.

10. The circuit board according to claim 8, characterized in that, The ratio of the gap width between the orthographic projection of the first trace of the high-speed channel on the circuit board and the orthographic projection of the cutout area on the circuit board to the width of the first trace of the high-speed channel is in the range of 20% to 40%.

11. The circuit board according to claim 8, characterized in that, The media layers on both sides of the excavated area are in contact with each other in the excavated area.

12. The circuit board according to claim 8, characterized in that, The medium layer on one side of the hollowed-out area includes a prepreg material, and the medium layer on the other side of the hollowed-out area includes a core board material. In the hollowed-out area, the medium layer including the prepreg material collapses toward the medium layer including the core board material.

13. The circuit board according to claim 8, characterized in that, The first trace and the second trace each include differential trace pairs. The differential trace pairs of the first trace are connected to the corresponding first differential via pairs or second differential via pairs through the differential trace pairs of the second trace.

14. The circuit board according to claim 8, characterized in that, The circuit board also includes a connection via that connects to the high-speed channel. The connection via electrically connects the first and second traces of the high-speed channel or connects the first or second trace to other components. At least one of the first differential via pair, the second differential via pair, and the connection via that connects to the high-speed channel has a via depth in the range of 55 mil to 75 mil and a via fragment length of less than 4 mil. The via fragment is the part of the via that does not play an effective connection role.

15. The circuit board according to claim 8, characterized in that, The circuit board also has connection pads. The first trace of the high-speed channel is connected to the connection pads via connection vias. The connection pads are used to connect to the pins of connectors outside the circuit board. When the connection pad is connected to the connector pin, the size of the connection pad remnant is in the range of 5 mil to 15 mil. The connection pad remnant is the part of the connection pad that does not play an effective connection role between the connection via and the connector. The size of the connection pad remnant is the length of the connection pad remnant in the extension direction of the connection pad.

16. A circuit assembly, characterized in that, include: The circuit board as described in any one of claims 1 to 15; as well as The chip is located on the circuit board and is electrically connected to the signal transmission and signal reception channels on the circuit board.

17. The circuit assembly according to claim 16, characterized in that, The chip is connected to the signal transmission and signal reception channels on the circuit board via multiple differential pads.

18. The circuit assembly according to claim 16, characterized in that, The circuit assembly is a switch motherboard, network card, or general-purpose baseboard.

19. An electronic device, characterized in that, include: The circuit assembly as described in claim 16; as well as A connector, one end of which is connected to a pad on a circuit board in a circuit assembly, and the other end of which is connected to another component in an electronic device other than the circuit assembly.

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