Gallium nitride power device and method of manufacturing the same

Abstract

The application discloses a gallium nitride power device and a preparation method thereof, and relates to the technical field of semiconductors. The gallium nitride power device comprises a substrate, a buffer layer, a GaN channel layer, an AlGaN barrier layer, an insulating dielectric layer, a source electrode, a drain electrode and a gate electrode. A U-shaped groove is formed in the AlGaN barrier layer, and the bottom arc radius of the U-shaped groove is optimized to be larger than the radius determined by geometric constraints and electric field uniformity constraints after the insulating dielectric layer is laid. The preparation method iteratively optimizes the etching process by using a field coupling adaptive gradient method, detects the damage and roughness of the etching surface in real time as feedback, dynamically adjusts the etching parameters, and thus accurately forms the U-shaped groove of the optimization design. The application effectively suppresses the electric field peak in the gate region through the synergistic innovation of structure optimization and preparation process, improves the breakdown voltage and reliability of the device, and ensures the high precision and consistency of the device preparation.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more specifically, to a gallium nitride power device and its fabrication method. Background Technology

[0002] Gallium nitride (GaN), as a representative of third-generation wide-bandgap semiconductors, has shown great potential in the fabrication of high-power, high-frequency, and high-efficiency power devices due to its superior physical properties such as high breakdown field strength, high electron saturation velocity, and high thermal conductivity. GaN-based enhancement-mode high electron mobility transistors (E-mode HEMTs), with their normally-off characteristics, have become a focus of research and application in power management, electric vehicles, and communication base stations—applications requiring high security.

[0003] One of the mainstream technical approaches to achieving enhancement-mode operation is to etch grooves into the AlGaN barrier layer beneath the gate. By precisely controlling the groove depth, the depletion state of the two-dimensional electron gas (2DEG) in the channel can be effectively controlled, thereby achieving a positive threshold voltage. However, traditional grooved gate structures, especially rectangular or V-shaped grooves with sharp corners, are prone to generating severe electric field concentration effects at the corners of the grooves during device operation. These electric field spikes not only significantly reduce the actual breakdown voltage of the device, making it far below the material's theoretical limit, but also induce thermal carrier effects, leading to reliability problems such as increased gate leakage current and threshold voltage drift, seriously affecting the long-term operational stability and lifespan of the device.

[0004] To mitigate this issue, the industry has attempted to employ U-shaped or arc-shaped groove structures. While U-shaped grooves theoretically smooth the electric field distribution, their performance is highly dependent on precise control of the groove geometry. In existing fabrication processes, dry etching techniques (such as reactive ion etching) are typically used to form the grooves in a single pass. This type of "open-loop" etching process lacks real-time feedback and correction mechanisms, making it extremely sensitive to fluctuations in process parameters. Therefore, even small deviations during the etching process can lead to significant differences between the final groove depth, width, and bottom curvature and the design values, making it difficult to guarantee process consistency within and between batches. More seriously, the high-energy ion bombardment during dry etching inevitably introduces plasma damage to the semiconductor surface, creating defect states that further degrade the interface quality between the gate dielectric and the semiconductor, impairing the device's electrical performance.

[0005] Therefore, designing an optimized groove structure that can fundamentally suppress electric field spikes and developing an advanced manufacturing method that can realize the structure with high precision, high quality and high repeatability are key technical challenges that urgently need to be solved in the field of GaN power devices. Summary of the Invention

[0006] This invention aims to address the electric field spike problem in the grooved gate structure of existing gallium nitride (GaN) power devices, as well as the technical shortcomings of traditional fabrication processes that make it difficult to accurately and effectively control the groove morphology. Specifically, this invention strives to provide a GaN power device structure that optimizes the electric field distribution, improves the device's breakdown voltage and reliability, and provides a high-precision, adaptive fabrication method to achieve this structure.

[0007] To solve the above problems, the technical solution adopted by the present invention is as follows:

[0008] In a first aspect, the present invention provides a gallium nitride power device, comprising:

[0009] Substrate;

[0010] A buffer layer, a GaN channel layer, and an AlGaN barrier layer with a U-shaped groove on the upper surface are sequentially disposed on the substrate;

[0011] An insulating dielectric layer covering the upper surface of the AlGaN barrier layer having the U-shaped groove;

[0012] The source and drain are respectively disposed on the AlGaN barrier layer on opposite sides of the U-shaped groove;

[0013] The gate is disposed within the U-shaped groove and electrically isolated by the insulating dielectric layer;

[0014] Among them, the bottom arc radius of the U-shaped groove after the insulating dielectric layer is laid is taken as the maximum bottom arc radius value that satisfies the chord length radius constraint condition and the electric field uniformity constraint condition.

[0015] When a conduction voltage is applied to the gate, a 2DEG is formed in the GaN channel layer as a conductive channel.

[0016] In a second aspect, the present invention provides a method for fabricating the gallium nitride power device described in the first aspect, comprising:

[0017] A substrate is provided, and a buffer layer, a GaN channel layer, and an AlGaN barrier layer are sequentially grown on the substrate;

[0018] A U-shaped groove is formed on the AlGaN barrier layer using an iterative etching method. The iterative etching steps include:

[0019] a) Etch the AlGaN barrier layer based on a set of initial etching parameters;

[0020] b) Detect the etching surface quality parameters of the etched surface, wherein the etching surface quality parameters include at least the thickness of the etched surface damage layer and the etched surface roughness;

[0021] c) Based on the etched surface quality parameters, establish a fitness function, and use the field-coupled adaptive gradient method to update a new set of etching parameters according to the fitness function, including:

[0022] A fitness function is established based on the etched surface quality parameters;

[0023] By combining the gradient of the influence of etching parameters on the fitness function, the covariance matrix describing the variation law of each etching parameter is updated;

[0024] The influence gradient is corrected based on the covariance matrix to decouple the coupling relationship between the etching parameters and obtain the corrected influence gradient.

[0025] The etching parameters are updated based on the corrected influence gradient to obtain the new etching parameters;

[0026] d) Repeat steps a) to c) based on the new etching parameters until the U-shaped groove is formed;

[0027] An insulating dielectric layer is deposited on the inner surface of the U-shaped groove and on the AlGaN barrier layer;

[0028] It forms the source, drain, and gate.

[0029] Compared with the prior art, the beneficial effects of the present invention are:

[0030] (1) The electric field distribution is optimized by creating a U-shaped groove on the upper surface of the AlGaN barrier layer and laying an insulating dielectric layer. The bottom arc radius of the U-shaped groove is designed to satisfy the maximum value of the chord length radius constraint and the electric field uniformity constraint, ensuring that the curvature of the bottom is not too sharp, making the bottom of the groove smoother, which helps the electric field to spread naturally, avoids the electric field intensity from being excessively concentrated in the local area, ensures that the electric field distribution at the bottom of the groove is more uniform, effectively suppresses the formation of electric field peaks, thereby significantly improving the breakdown voltage of the device, making it closer to the intrinsic limit of the material, and enhancing the robustness of the device in high-voltage application environments.

[0031] (2) The laid insulating dielectric layer provides additional electrical isolation, reduces current leakage, and ensures uniform electric field distribution, thereby improving the device's conductivity and high-voltage withstand capability. Because electric field spikes are effectively suppressed, device degradation phenomena such as gate leakage and threshold voltage drift caused by hot carrier effects are significantly alleviated. Simultaneously, the high-quality etched surface reduces the density of interface trap states, further enhancing device stability. Therefore, the device prepared in this invention has a longer lifespan and more stable operating performance.

[0032] (3) The iterative etching method proposed in this invention introduces a closed-loop feedback mechanism of "etching-detection-optimization". By quantifying the damage and roughness of the etched surface in real time and dynamically adjusting the process parameters using a field-coupled adaptive gradient algorithm, it overcomes the defects of low precision and poor consistency in traditional "one-time" etching processes. This method can achieve nanometer-level precise control over the groove depth, width, and critical bottom arc radius, while minimizing plasma damage and ensuring a high-quality gate dielectric / semiconductor interface. The adaptive etching method of this invention can actively compensate for potential fluctuations in the process, ensuring a high degree of consistency in the final device structure. Both the uniformity within the wafer and the repeatability between different batches are greatly improved, which is crucial for large-scale, low-cost commercial production and can significantly improve product yield.

[0033] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, embodiments of the present invention are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0034] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0035] Figure 1 This is a schematic diagram of the structure of a gallium nitride power device provided in an embodiment of the present invention;

[0036] Figure 2 This is a schematic diagram of a gate structure provided in an embodiment of the present invention;

[0037] Figure 3 This is a schematic diagram of a structure including an AlGaN barrier layer and an insulating dielectric layer provided by an embodiment of the present invention;

[0038] Figure 4 This is a schematic flowchart of a gallium nitride power device fabrication method provided in an embodiment of the present invention.

[0039] Explanation of reference numerals in the attached figures: 1. Substrate; 2. Buffer layer; 3. GaN channel layer; 4. AlGaN barrier layer; 5. Insulating dielectric layer; 6. U-shaped groove; 7. Surface of AlGaN barrier layer; 8. Gate root. Detailed Implementation

[0040] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are some embodiments of the present invention, but not all embodiments.

[0041] like Figure 1 The diagram shown is a schematic representation of an enhanced gallium nitride power device provided in an embodiment of the present invention.

[0042] This device employs a stacked structure, comprising, from bottom to top, a substrate, a buffer layer, a GaN channel layer, an AlGaN barrier layer, and an insulating dielectric layer above it. A U-shaped groove is etched into the surface of the AlGaN barrier layer, and the gate G is placed within the groove; the source S and drain D are located on opposite sides of the U-shaped groove. The U-shaped groove, through precise design of its opening width and bottom curvature, effectively regulates the electric field distribution and suppresses electric field spikes. When a voltage is applied to the gate, a two-dimensional electron gas (2DEG) is formed at the interface between the GaN channel layer and the AlGaN barrier layer, serving as an electron conduction channel, thereby achieving efficient current control and device conduction. In the figure, d1 < d2 indicates that the gate is close to the source, which is beneficial for improving switching speed and control performance. This structure as a whole improves the device's reliability, conductivity, and high-voltage withstand capability.

[0043] like Figure 2 The diagram shows a schematic representation of a gate structure provided in an embodiment of the present invention.

[0044] The portion extending below the gate into the U-shaped groove is called the "gate root." This structural design allows the gate to penetrate deep into the AlGaN barrier layer, thereby enabling more direct control of the switching on and off of the two-dimensional electron gas (2DEG) in the channel. Extending the gate root to the bottom of the groove helps enhance gate control capability, improve device switching efficiency and modulation performance, and, combined with the rounded bottom structure, effectively suppresses electric field spikes, improving device reliability and breakdown resistance.

[0045] like Figure 3 The diagram shows a schematic representation of the structure provided in this embodiment of the invention, which has a U-shaped groove on the surface of an AlGaN barrier layer and is covered with an insulating dielectric layer.

[0046] The U-shaped groove has a rounded bottom, which helps to ensure the uniformity of the electric field distribution, suppress electric field spikes, and improve the breakdown voltage and stability of the device. Figure 3 The radius 'r' marked in the figure represents the bottom arc radius of the U-shaped groove after the insulating dielectric layer is applied. The U-shaped groove is covered with an insulating dielectric layer on both the inside and the surface to isolate the electrode from the AlGaN barrier layer, prevent leakage, and enhance the gate's control over the channel.

[0047] The gallium nitride power device provided in this invention includes: a substrate, a buffer layer, a GaN channel layer, an AlGaN barrier layer, an insulating dielectric layer, a source (S), a drain (D), and a gate (G). The AlGaN barrier layer has a U-shaped groove on its upper surface, forming an AlGaN barrier layer surface with a U-shaped groove. The insulating dielectric layer is laid flat on the AlGaN barrier layer surface. The source and drain are disposed on opposite sides of the AlGaN barrier layer, and the gate is disposed in the U-shaped groove after the insulating dielectric layer is laid, forming an optimized AlGaN barrier layer. The opening width of the U-shaped groove after the insulating dielectric layer is laid is related to the thickness and width of the AlGaN barrier layer. The depth of the U-shaped groove after the insulating dielectric layer is laid is related to the thickness of the AlGaN barrier layer. The bottom arc radius of the U-shaped groove after the insulating dielectric layer is taken as the maximum bottom arc radius value satisfying both the chord length radius constraint and the electric field uniformity constraint, to suppress electric field spikes. A substrate, a buffer layer, a GaN channel layer, and an optimized AlGaN barrier layer are stacked sequentially. When a turn-on voltage is applied to the gate, a 2DEG (Dielectric Deposition Gate) is formed in the GaN channel layer to serve as a conductive channel.

[0048] In gallium nitride (GaN) power devices, the substrate is typically made of highly conductive materials (such as silicon, sapphire, or aluminum nitride) to provide mechanical support and facilitate heat transfer. A buffer layer reduces lattice mismatch between the substrate and the GaN material, preventing stress problems caused by lattice differences. The buffer layer commonly uses aluminum nitride (AlN) or gallium nitride (GaN) and acts as a transition layer. The GaN channel layer, located above the buffer layer, is a channel for electron flow. GaN has very high electron mobility, providing efficient current transport and ensuring efficient operation of the device at high power and high frequency. The AlGaN barrier layer and the GaN channel layer form a heterojunction, which generates a two-dimensional electron gas (2DEG), giving GaN power devices excellent conductivity and low power consumption. The AlGaN layer also acts as a shield, enhancing the device's breakdown voltage. An insulating dielectric layer, typically composed of silicon nitride (SiN) or aluminum oxide (Al2O3), sits atop the AlGaN barrier layer. It provides electrical isolation, prevents leakage current between the source and gate, and helps optimize gate control performance. The source and drain are the device's input and output terminals, responsible for current flow. The gate controls the device's switching; adjusting the gate voltage controls the formation of the two-dimensional electron gas (2DEG) and the opening of conductive channels. A U-shaped groove is located on the AlGaN barrier layer surface to optimize the electric field distribution. By adjusting the opening width, depth, and bottom radius of the U-shaped groove, electric field spikes can be effectively suppressed, ensuring a uniform electric field distribution and reducing the risk of breakdown and overheating during device operation.

[0049] Specifically, by optimizing the U-shaped groove structure of the AlGaN barrier layer and the insulating dielectric layer, the stability and reliability of the device are significantly improved. The opening width and depth of the U-shaped groove are precisely matched with the geometry of the AlGaN barrier layer, which helps to achieve uniform electric field distribution and avoids the electric field spike problem commonly found in traditional designs. In particular, the radius of the arc at the bottom of the U-shaped groove is optimized to satisfy the maximum value of the electric field uniformity and chord length radius constraints, ensuring a smooth transition of the electric field within the device and suppressing the risk of overheating and breakdown caused by electric field concentration.

[0050] Alternatively, as another implementation method, the formula for calculating the opening width of the U-shaped groove after laying the insulating dielectric layer is as follows:

[0051]

[0052]

[0053] in, This indicates the opening width of the U-shaped groove after the insulating dielectric layer has been laid. This indicates the opening width of the U-shaped groove before the insulating dielectric layer is laid. Indicates the thickness of the insulating dielectric layer. This indicates the angle at which the insulating dielectric layer extends inside the U-shaped groove. Indicates the thickness of the AlGaN barrier layer. The width of the AlGaN barrier layer is represented by tan, and the tangent function is represented by tan. This indicates the inclination angle of the sidewall of the U-shaped groove before laying the insulating dielectric layer, which is related to the etching process.

[0054] It should be noted that the formula for calculating the opening width of the U-shaped groove after laying the insulating dielectric layer is one implementation method. Implementing this method does not affect the implementation of the basic scheme described above, and the opening width can also be obtained in other ways. By using the above formula to calculate the opening width of the U-shaped groove, the influence of the thickness and tilt angle of the insulating dielectric layer on the groove opening width can be considered more accurately. Specifically, by combining the thickness of the insulating dielectric layer with the tilt angle, the change in the groove opening can be calculated more precisely, thereby effectively compensating for dimensional changes caused by the dielectric layer. This calculation method ensures that the geometric dimensions of the groove opening meet the design requirements, avoids the problem of uneven electric field caused by dimensional mismatch, optimizes the electric field distribution, and contributes to the stable operation of the device.

[0055] Alternatively, as another implementation method, the formula for calculating the depth of the U-shaped groove after laying the insulating dielectric layer is as follows:

[0056]

[0057] in, This indicates the depth of the U-shaped groove after the insulating dielectric layer has been laid.

[0058] It should be noted that the formula for calculating the depth of the U-shaped groove after laying the insulating dielectric layer is one implementation method. Implementing this method does not affect the implementation of the basic scheme described above, and the depth can also be obtained in other ways. The calculation method for the depth of the U-shaped groove after laying the insulating dielectric layer simplifies the calculation of the groove depth and keeps the groove depth within a reasonable range. By setting the depth to one-third of the AlGaN barrier layer thickness, a suitable groove depth can be ensured without increasing additional complexity, thereby effectively optimizing the electric field distribution. An appropriate groove depth helps reduce the occurrence of electric field spikes and avoids electric field inhomogeneity caused by grooves that are too deep or too shallow.

[0059] More specifically, gallium nitride (GaN) power devices effectively improve the electric field distribution by optimizing the U-shaped groove structure of the AlGaN barrier layer and laying an insulating dielectric layer. The opening width and depth of the U-shaped groove are precisely calculated to accommodate the thickness and tilt angle of the insulating dielectric layer, thereby avoiding electric field inhomogeneity caused by size mismatch. In particular, the optimized design of the bottom arc radius ensures a smooth transition of the electric field within the device, suppressing electric field spikes and reducing the risk of overheating and breakdown.

[0060] In this embodiment of the invention, the electric field distribution is optimized by creating a U-shaped groove on the upper surface of the AlGaN barrier layer and laying an insulating dielectric layer. The bottom radius of the U-shaped groove is designed to satisfy the maximum value of the chord length radius constraint and the electric field uniformity constraint, ensuring that the curvature at the bottom is not too sharp, making the bottom of the groove smoother. This facilitates the natural expansion of the electric field, avoids excessive concentration of electric field intensity in local areas, ensures a more uniform electric field distribution at the bottom of the groove, and prevents the formation of electric field peaks. Furthermore, the laid insulating dielectric layer provides additional electrical isolation, reduces current leakage, and ensures a uniform electric field distribution, thereby improving the device's conductivity and high-voltage withstand capability. This optimized structural design ensures the long-term stability and high efficiency of gallium nitride power devices in high-power, high-frequency applications. Especially under high-voltage operating environments, it avoids problems such as overheating and breakdown, improving the overall performance and reliability of the device.

[0061] In one possible implementation, the substrate is one or more of a silicon substrate, a sapphire substrate, and an aluminum nitride substrate.

[0062] Understandably, choosing silicon, sapphire, or aluminum nitride substrates as the substrate material for gallium nitride power devices allows for optimization of device performance based on different application requirements.

[0063] In one possible implementation, the buffer layer includes an aluminum nitride buffer layer and a gallium nitride buffer layer.

[0064] Understandably, choosing aluminum nitride (Anitride) and gallium nitride (GaN) buffer layers as buffer layers for GaN power devices can effectively alleviate lattice mismatch between the substrate and the GaN layer. Aluminum nitride has high thermal conductivity and a low expansion coefficient, making it suitable for reducing stress. Meanwhile, the GaN buffer layer provides higher interface quality, improving the crystal quality and conductivity of the GaN layer.

[0065] In one possible implementation, the thicknesses of both the source and drain are the same as the stack thicknesses of the AlGaN barrier layer and the insulating dielectric layer.

[0066] It should be noted that the thickness of the source and drain electrodes is the same as the stack thickness of the AlGaN barrier layer and the insulating dielectric layer. This design ensures good contact between the source / drain electrodes and the AlGaN layer and insulating dielectric layer, avoiding interface resistance caused by thickness mismatch and guaranteeing stable current transmission. Furthermore, uniform thickness helps improve device uniformity, reduce heat buildup, and enhance the device's stability and reliability at high power.

[0067] In one possible implementation, the radius of the bottom arc of the U-shaped groove is calculated as follows:

[0068]

[0069] in, The radius of the bottom arc is represented by , and h represents the depth of the U-shaped groove after the insulating dielectric layer is laid. This indicates the width of the U-shaped groove opening after the insulating dielectric layer has been laid. Indicates the safety factor. This indicates the GaN breakdown field strength. This indicates the maximum operating voltage of the gallium nitride power device, where max represents the maximum value.

[0070] It should be noted that the calculation method for the bottom arc radius of the U-shaped groove is one implementation method. Implementing this method does not affect the implementation of the basic scheme above. The bottom arc radius of the U-shaped groove can also be obtained by other methods. This calculation method for the bottom arc radius can optimize the design of the U-shaped groove while considering electric field uniformity and device safety. The first term in the formula... Based on the groove depth and opening width, the radius of the arc is designed to effectively disperse the electric field and avoid electric field spikes. The second item... Based on the maximum operating voltage and the breakdown field strength of GaN, combined with a safety factor, it is ensured that the device will not break down due to electric field concentration under high voltage. By taking the maximum value, the design ensures that both electric field uniformity and breakdown safety are taken into account, thereby improving the reliability of the device and avoiding problems such as overheating and breakdown caused by excessive electric field.

[0071] Optionally, the safety factor can be set to 0.8.

[0072] In one possible implementation, the distance between the gate root and the source of the gate is a first distance. The distance between the gate root and the drain of the gate is a second distance. The first distance is less than the second distance.

[0073] It should be noted that this constraint is... Figure 1 In this design, d1 is less than d2. The first distance between the gate root and the source is less than the second distance between the gate root and the drain. This design optimizes the device's switching characteristics and current control. The shorter first distance helps to form a conductive path faster, improving turn-on speed. The longer second distance reduces the interaction of electric fields between the gate and the drain, reducing leakage current, thereby enhancing device performance stability, reducing potential interference during switching, and improving overall efficiency.

[0074] Specifically, this gallium nitride power device improves electric field uniformity and overall performance through optimization of the U-groove structure, insulating dielectric layer, and other key design aspects. The precise design of the U-groove, combined with optimized bottom radius, effectively suppresses electric field spikes, reduces the risk of overheating and breakdown, and enhances device stability and reliability. The gate design optimizes switching characteristics and current control, further improving device performance.

[0075] Reference manual attached Figure 4 The diagram shows a flow chart of a gallium nitride power device fabrication method according to an embodiment of the present invention. The specific fabrication method is as follows:

[0076] S1: Prepare the substrate.

[0077] Specifically, the substrate fabrication process involves selecting a suitable substrate material (such as silicon, sapphire, or aluminum nitride), followed by surface cleaning and treatment to remove impurities and oxide layers, ensuring a smooth and flat surface. After cleaning with chemical solvents and ultrasonic waves, the substrate is typically heated to an appropriate temperature to provide a stable foundation for the subsequent growth of buffer layers and GaN channel layers.

[0078] S2: A buffer layer, a GaN channel layer, and an AlGaN barrier layer are grown sequentially on the substrate.

[0079] Specifically, a buffer layer, typically aluminum nitride (AlN) or gallium nitride (GaN), is first grown on the substrate to alleviate lattice mismatch between the substrate and the GaN material. Next, a GaN channel layer, which serves as a channel for electron flow, is grown on the buffer layer; high-quality GaN thin films are typically grown using metal-organic chemical vapor deposition (MOCVD). Finally, an AlGaN barrier layer is grown to form a heterojunction structure, generating a two-dimensional electron gas (2DEG) and enhancing the device's conductivity.

[0080] S3: Combine field coupling adaptive gradient method to optimize etching parameters, etch the AlGaN barrier layer to generate U-shaped grooves on the upper surface of the AlGaN barrier layer.

[0081] It should be noted that by optimizing etching parameters using the field-coupled adaptive gradient method, etching conditions can be automatically adjusted based on electric field simulation feedback, precisely controlling the morphology and dimensions of the U-shaped groove. This method can effectively form opening width, depth, and bottom arc radius that meet design requirements, significantly improving electric field uniformity and suppressing electric field spikes, thereby enhancing device reliability and performance consistency.

[0082] In one possible implementation, S3 specifically includes:

[0083] S301: Define the opening area of ​​the U-shaped groove according to the opening width.

[0084] S302: Combining the depth of the U-shaped groove and the radius of the bottom arc, the AlGaN barrier layer is subjected to a first coarse etching using a dry etching method according to the first etching size and first etching parameters. The first etching size includes the first etching width, the first etching depth, and the first etching bottom arc radius. The first etching width is smaller than the opening width, the first etching depth is smaller than the depth of the U-shaped groove, and the first etching bottom arc radius is smaller than the bottom arc radius of the U-shaped groove. The first etching parameters include the RF power, the etching gas ratio, and the etching temperature.

[0085] S303: Detect the quality parameters of the etched surface, including the thickness of the etched surface damage layer and the roughness of the etched surface.

[0086] Specifically, the thickness of the damaged layer on the etched surface can be detected using transmission electron microscopy (TEM) or secondary ion mass spectrometry (SIMS). By observing the lattice distortion or elemental distribution of the material, the thickness of the damaged layer can be determined. For the surface roughness of the etched surface, it can be precisely measured using atomic force microscopy (AFM) to obtain surface roughness parameters.

[0087] S304: If the thickness of the etched surface damage layer is less than the preset etched surface damage layer thickness and the etched surface roughness is less than the preset etched surface roughness, update the etch size once, and update the etch parameters once using the etched surface quality parameters as the fitness function through the field coupling adaptive gradient method, and return to step S302.

[0088] It should be noted that in the updated etching dimensions, each dimension is larger than the previous etching dimensions, but smaller than the opening width, the depth of the U-shaped groove, and the radius of the bottom arc of the U-shaped groove.

[0089] In one possible implementation, step S304, which uses the etched surface quality parameters as the fitness function and updates the etched parameters once using the gradient descent method, specifically includes:

[0090] S3041: Establish a fitness function based on the etched surface quality parameters.

[0091] The fitness function is as follows:

[0092]

[0093] Where D represents the thickness of the etched surface damage layer. R represents the preset thickness of the etched surface damage layer, and R represents the surface roughness. This indicates the preset surface roughness for etching. This represents the fitness function value.

[0094] It should be noted that those skilled in the art can set the preset thickness of the etched surface damage layer and the preset roughness of the etched surface according to actual needs, and this invention does not limit these settings.

[0095] The fitness function evaluates the quality of the etching process by quantifying the ratio of the damaged layer thickness and surface roughness to a preset standard. A smaller fitness value indicates better surface quality and a more successful etching process. By establishing a fitness function based on etched surface quality parameters, the impact of surface damage and roughness during etching can be quantified, etching quality can be monitored in real time, and precise data can be provided for optimizing etching parameters. This method allows for more precise control of the etching process, avoiding the increase in interface states or current leakage caused by excessive damage or excessive surface roughness, thereby improving the performance and reliability of gallium nitride power devices.

[0096] S3042: Combining the gradient of the influence of the etching parameter vector on the fitness function, the covariance matrix describing the change law of the etching parameters in one step is updated by the exponential moving average method.

[0097] For example, below is another implementation method where the update formula for the covariance matrix can be specifically as follows:

[0098]

[0099] in, and Let represent the covariance matrices at time step t and time step t-1, respectively. This represents the forgetting factor that controls the weights of historical data; the subscript T indicates transpose. This represents the gradient of the effect of the etching parameter vector on the fitness function.

[0100] Wherein, the covariance matrix is ​​a vector describing the etching parameters. The covariance matrix is ​​a 3×3 symmetric matrix, where P, G, and T represent RF power, etching gas ratio, and etching temperature, respectively. The specific formula for the covariance matrix is ​​as follows: ,in, and These represent the calculation of variance and the calculation of covariance, respectively. ,in, This indicates the partial derivative.

[0101] The covariance matrix update formula can take other forms, and the form described in this invention is not unique. Furthermore, the implementation of this update formula does not affect the implementation of the basic scheme described above. The exponential moving average method is a weighted averaging approach that emphasizes "new data" but does not completely ignore "old data." The covariance matrix is ​​a 3×3 symmetric matrix representing the variance and covariance relationship between the three key etching parameters. Updating the covariance matrix using the exponential moving average method dynamically captures the changing trends of etching parameters and their coupling relationships, avoiding instability caused by relying on single measurements. This method, while preserving historical etching behavior patterns, promptly reflects changes in the current gradient, helping to form a smooth response to the etching system state. This makes parameter optimization more stable, robust, and convergent, further improving the accuracy and consistency of etching morphology control.

[0102] S3043: Based on the covariance matrix, perform gradient correction on the influence gradient to obtain the corrected influence gradient, thereby decoupling the coupling relationship between each primary etching parameter.

[0103] The revised formula for calculating the gradient effect is as follows:

[0104]

[0105] in, This represents the inverse square root matrix of the covariance matrix at time step t. Indicates the influence of gradient. This indicates that the gradient is affected by the correction.

[0106] Specifically, the covariance matrix describes the relationships and couplings between the various etching parameters. The square root of the covariance matrix is ​​used to map the gradient direction to a "decoupled" space. This eliminates coupling effects between different parameters, making updates to each parameter more independent and efficient. The gradient direction is "corrected" by multiplying the original gradient by the square root inverse of the covariance matrix. Specifically, the square root inverse of the covariance matrix projects the original gradient into a "decoupled" feature space, thus avoiding gradient direction shifts caused by strong coupling between parameters.

[0107] It should be noted that by using the inverse square root matrix of the covariance matrix to correct the influencing gradient, the coupling relationship between etching parameters can be effectively decoupled. This avoids strong coupling between parameters from interfering with the optimization process, making the adjustment of each etching parameter more independent and precise, avoiding gradient direction deviation, thereby accelerating the convergence of the optimization process and improving the stability and control accuracy of the etching process.

[0108] S3044: Determine whether the modulus of the correction effect gradient is less than the preset modulus of the correction effect gradient. If so, update each first-order etching parameter by combining the random perturbation and the correction effect gradient. Otherwise, update each first-order etching parameter according to the correction effect gradient.

[0109] As another implementation method, the update formula is as follows:

[0110]

[0111] in, and Let represent the etching parameter vectors at time step t and time step t+1, respectively. Indicates the learning rate. Indicates standard Gaussian noise. This represents the disturbance intensity coefficient. This indicates that the correction affects the gradient modulus. express traces, This indicates that the preset correction affects the gradient modulus.

[0112] Specifically, the update formula can take other forms, and the form described in this invention is not unique. Furthermore, the implementation of this update formula does not affect the implementation of the basic scheme described above. When the correction effect gradient modulus is too small or the optimization gets stuck in the saddle point region, introducing random perturbations can break the stagnation state, helping the etching parameters escape the local stable region and continue to converge towards the global optimum. This mechanism enhances the robustness of the optimization process, avoids getting stuck in non-convergent regions, and improves the flexibility of etching control and the accuracy and consistency of the final etching morphology.

[0113] It should be noted that those skilled in the art can set the preset magnitude of the gradient influence according to actual needs, and this invention does not limit this. Specifically, during the optimization process, when the corrected gradient modulus is less than the preset magnitude of the gradient influence, it indicates that the optimization process may have entered a saddle point region, at which point the change in the objective function, i.e., the fitness function value, is close to stagnation. A saddle point is a very special point; it is where the gradient of the objective function is zero, but it is neither a local minimum nor a local maximum. That is to say, the update has stalled. At this point, random perturbation is introduced to help the model escape the saddle point and continue moving towards the optimal solution.

[0114] In practical applications, firstly, by establishing a fitness function centered on the thickness and roughness of the surface damage layer, the etched surface quality is quantified into an optimizable objective. Next, the influence of the etching parameter gradient on the fitness function is calculated, and the covariance matrix of the etching parameters is updated in real time using the exponential moving average method to dynamically capture parameter change trends and their coupling relationships. In S3043, the inverse square root of the covariance matrix is ​​used to decouple and correct the gradient, avoiding gradient shift and making the adjustment of each etching parameter more independent and accurate. Finally, if the corrected gradient modulus is less than a preset threshold (potentially falling into a saddle point), a Gaussian random perturbation is introduced to help escape the stagnation interval and continue converging towards the global optimum. This process achieves adaptive iterative optimization of etching parameters, possessing dynamic feedback adjustment capabilities, resistance to local extrema interference, and high convergence efficiency, significantly improving the accuracy of etching morphology control and the consistency and reliability of device fabrication.

[0115] S305: Calculate the remaining etching dimension between the current etching dimension and the corresponding U-shaped groove dimension.

[0116] S306: Based on the current etching parameters, etch a U-shaped groove according to the remaining etching dimensions to obtain a U-shaped groove.

[0117] It should be noted that the entire process constitutes a complete process for the precise etching of the U-shaped groove. First, the target morphology area of ​​the U-shaped groove is defined according to the predetermined opening width. Next, combining the depth of the target groove and the bottom radius, dry etching technology is used to perform preliminary etching of the AlGaN barrier layer, setting the first etching dimensions (width, depth, bottom radius) and etching parameters (RF power, etching gas ratio, etching temperature). Subsequently, the thickness and roughness of the damaged layer on the etched surface are detected by means of transmission electron microscopy (TEM), secondary ion mass spectrometry (SIMS), or atomic force microscopy (AFM) to evaluate the etching quality. In S304, if both the damage and roughness are below the preset threshold, the first etching dimensions are updated, and the etched surface quality parameters are used as a fitness function. The etching parameters are optimized using the field-coupled adaptive gradient method, and the process returns to S302 for iterative etching. Finally, the remaining etching amount is calculated, and the remaining etching is completed based on the latest parameters, ultimately forming a U-shaped groove that meets the design requirements.

[0118] This etching process, combining step-by-step iteration with surface quality monitoring, enables precise control over the morphology of the U-shaped groove, ensuring that the groove size gradually approaches the target structure and avoiding damage caused by over-etching in one go. Simultaneously, by continuously optimizing etching parameters using a field-coupled adaptive gradient method, etching conditions can be dynamically adjusted to minimize surface roughness and damage layer thickness, improve interface quality, and suppress electric field spikes. This significantly improves device reliability, electric field control capability, and process consistency, achieving precise control over the groove geometry and enhancing electric field uniformity and device performance.

[0119] S4: Deposit an insulating dielectric layer on the surface of the U-shaped groove.

[0120] Specifically, atomic layer deposition (ALD) or chemical vapor deposition (CVD) methods are typically used to deposit an insulating dielectric layer, such as silicon nitride (SiN) or aluminum oxide (Al2O3), on the etched U-shaped grooves. The deposition process requires precise control of temperature, gas flow rate, and deposition rate to ensure that the insulating dielectric layer uniformly covers the inner walls and bottom of the grooves, avoiding voids or uneven thickness, ensuring effective electric field isolation and gate control performance, thereby providing a good insulating foundation for subsequent electrode formation.

[0121] S5: Perform electrode fabrication, wherein the electrodes include source, drain and gate.

[0122] Specifically, electrode fabrication typically involves three main steps: patterning, metal deposition, and annealing. First, a patterned mask for the source, drain, and gate electrodes is formed on the device surface using photolithography. Then, metal materials (such as multilayer metals like Ti / Al / Ni / Au) are deposited using methods such as electron beam evaporation or sputtering to form the electrodes. Finally, rapid thermal annealing (RTA) is performed to enhance the ohmic contact performance between the metal and GaN material, ensuring current injection efficiency and device conduction characteristics.

[0123] S6: Deposit a passivation layer on the electrode to obtain a gallium nitride power device.

[0124] Specifically, passivation layer deposition typically employs plasma-enhanced chemical vapor deposition (PECVD) or atomic layer deposition (ALD) techniques to cover the formed source, drain, and gate electrodes with a passivation layer made of materials such as silicon nitride (SiN) or silicon oxide (SiO2). This process requires precise control of temperature, gas ratio, and deposition rate to ensure uniform coverage of the passivation layer across the electrode surfaces and edges, as well as the device surface, preventing the intrusion of environmental moisture, oxidation, or impurities. Simultaneously, it enhances the device's electrostatic discharge (ESD) immunity and long-term reliability, thus completing the fabrication of the entire gallium nitride power device.

[0125] In one possible implementation, the passivation layer is specifically a silicon nitride passivation layer.

[0126] In practical applications, the fabrication process of gallium nitride (GaN) power devices is systematically completed through six key steps, from substrate preparation to final device formation, demonstrating meticulous craftsmanship and highly coordinated processes. First, silicon, sapphire, or aluminum nitride is selected as the substrate. After cleaning and pretreatment, a smooth surface is ensured, laying the foundation for the growth of the heterostructure. Subsequently, a buffer layer, a GaN channel layer, and an AlGaN barrier layer are grown sequentially on the substrate to form a high-quality heterojunction structure, providing conditions for the subsequent formation of a two-dimensional electron gas (2DEG). Using a field-coupled adaptive gradient method, etching parameters are precisely controlled to etch U-shaped grooves with optimized morphology, significantly improving the electric field distribution, suppressing electric field spikes, and enhancing device stability. A high-quality insulating dielectric layer is deposited within the groove to ensure gate control capability. Then, the source, drain, and gate electrodes are precisely fabricated, and thermal annealing achieves good ohmic contact, enhancing conductivity. Finally, a passivation layer is deposited to encapsulate the electrodes, preventing environmental interference and improving device lifetime. The fabrication process has comprehensive advantages such as high structural precision, excellent electric field control, good thermal stability, strong conductivity, and high reliability, making it suitable for high-power, high-frequency, and high-stability scenarios.

[0127] In this embodiment of the invention, the electric field distribution is optimized by creating a U-shaped groove on the upper surface of the AlGaN barrier layer and laying an insulating dielectric layer. The bottom radius of the U-shaped groove is designed to satisfy the maximum value of the chord length radius constraint and the electric field uniformity constraint, ensuring that the curvature at the bottom is not too sharp, making the bottom of the groove smoother. This facilitates the natural expansion of the electric field, avoids excessive concentration of electric field intensity in local areas, ensures a more uniform electric field distribution at the bottom of the groove, and prevents the formation of electric field peaks. Furthermore, the laid insulating dielectric layer provides additional electrical isolation, reduces current leakage, and ensures a uniform electric field distribution, thereby improving the device's conductivity and high-voltage withstand capability. This optimized structural design ensures the long-term stability and high efficiency of gallium nitride power devices in high-power, high-frequency applications. Especially under high-voltage operating environments, it avoids problems such as overheating and breakdown, improving the overall performance and reliability of the device.

[0128] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A gallium nitride power device, characterized in that, include: Substrate; A buffer layer, a GaN channel layer, and an AlGaN barrier layer with a U-shaped groove on the upper surface are sequentially disposed on the substrate; An insulating dielectric layer covering the upper surface of the AlGaN barrier layer having the U-shaped groove; The source and drain are respectively disposed on the AlGaN barrier layer on opposite sides of the U-shaped groove; The gate is disposed within the U-shaped groove and electrically isolated by the insulating dielectric layer; Specifically, the bottom radius of the U-shaped groove after the insulating dielectric layer is laid. Its value is taken as the maximum bottom arc radius value that satisfies the chord length radius constraint and the electric field uniformity constraint, that is: Where h represents the depth of the U-shaped groove after the insulating dielectric layer is laid. This indicates the width of the U-shaped groove opening after the insulating dielectric layer has been laid. Indicates the safety factor. This indicates the GaN breakdown field strength. This indicates the maximum operating voltage of the gallium nitride power device; max indicates the maximum value. When a conduction voltage is applied to the gate, a 2DEG is formed in the GaN channel layer as a conductive channel.

2. The gallium nitride power device according to claim 1, characterized in that, The substrate is one of a silicon substrate, a sapphire substrate, and an aluminum nitride substrate.

3. The gallium nitride power device according to claim 1, characterized in that, The buffer layer includes either an aluminum nitride buffer layer or a gallium nitride buffer layer.

4. The gallium nitride power device according to claim 1, characterized in that, The thicknesses of the source and drain electrodes are the same as the stack thicknesses of the AlGaN barrier layer and the insulating dielectric layer.

5. The gallium nitride power device according to claim 1, characterized in that, The distance between the gate and the source is less than the distance between the gate and the drain.

6. A method for fabricating the gallium nitride power device according to any one of claims 1 to 5, characterized in that, include: A substrate is provided, and a buffer layer, a GaN channel layer, and an AlGaN barrier layer are sequentially grown on the substrate; A U-shaped groove is formed on the AlGaN barrier layer using an iterative etching method. The iterative etching steps include: a) Etch the AlGaN barrier layer based on a set of initial etching parameters; b) Detect the etching surface quality parameters of the etched surface, wherein the etching surface quality parameters include at least the thickness of the etched surface damage layer and the etched surface roughness; c) Based on the etched surface quality parameters, establish a fitness function, and use the field-coupled adaptive gradient method to update a new set of etching parameters according to the fitness function, including: A fitness function is established based on the etched surface quality parameters; By combining the gradient of the influence of etching parameters on the fitness function, the covariance matrix describing the variation law of each etching parameter is updated; The influence gradient is corrected based on the covariance matrix to decouple the coupling relationship between the etching parameters and obtain the corrected influence gradient. The etching parameters are updated based on the corrected influence gradient to obtain new etching parameters; d) Repeat steps a) to c) based on the new etching parameters until the U-shaped groove is formed; An insulating dielectric layer is deposited on the inner surface of the U-shaped groove and on the AlGaN barrier layer; It forms the source, drain, and gate.

7. The preparation method according to claim 6, characterized in that, The step of updating the etching parameters based on the corrected influence gradient further includes: determining whether the modulus of the corrected influence gradient is less than a preset threshold; if so, updating the etching parameters by combining random perturbation and the corrected influence gradient.

8. The preparation method according to claim 6, characterized in that, The etching parameters include radio frequency power, etching gas ratio, and etching temperature.

9. The preparation method according to claim 6, characterized in that, Also includes: After the source, drain and gate are formed, a silicon nitride passivation layer is deposited thereon.

Images