Array substrate, preparation method of array substrate and display panel

Abstract

The invention discloses an array substrate, a preparation method of the array substrate and a display panel, the array substrate comprises a substrate and a driving circuit layer, the driving circuit layer comprises a first conductive structure, a first insulating layer, a second conductive layer, a first planarization layer and a third conductive layer, and the first conductive structure is arranged on one side of the substrate; the first insulating layer is arranged on the side, away from the substrate, of the first conductive structure; the second conductive layer is arranged on the side, away from the substrate, of the first insulating layer, the second conductive layer comprises a signal line, the signal line is electrically connected with the first conductive structure through the first via hole, a concave part is formed in the side, away from the substrate, of the signal line, and the orthographic projection of the concave part on the substrate and the orthographic projection of the first via hole on the substrate are at least partially overlapped; the first planarization layer is arranged on the side, away from the substrate, of the second conductive layer, covers at least part of the signal line and fills at least part of the sunken part; the third conductive layer is arranged on the side, away from the substrate, of the first planarization layer.

Description

Technical Field

[0001] This application belongs to the field of display technology, and in particular relates to an array substrate, a method for preparing the array substrate, and a display panel. Background Technology

[0002] Organic light-emitting diode (OLED) and flat panel display devices based on light-emitting diode (LED) technologies are widely used in various consumer electronics products such as mobile phones, televisions, laptops, and desktop computers due to their advantages such as high image quality, energy saving, thin body and wide range of applications, becoming the mainstream of display devices.

[0003] However, the performance of the array substrate in current OLED display products needs to be improved. Summary of the Invention

[0004] The purpose of this application is to provide an array substrate, a method for fabricating the array substrate, and a display panel that can improve the performance of the array substrate.

[0005] A first aspect of this application provides an array substrate, including a substrate and a driving circuit layer. The driving circuit layer includes a first conductive structure, a first insulating layer, a second conductive layer, a first planarization layer, and a third conductive layer. The first conductive structure is disposed on one side of the substrate. The first insulating layer is disposed on the side of the first conductive structure facing away from the substrate. The second conductive layer is disposed on the side of the first insulating layer facing away from the substrate. The second conductive layer includes a signal line, which is electrically connected to the first conductive structure through a first via. A recess is formed on the side of the signal line facing away from the substrate, and the orthographic projection of the recess onto the substrate and the orthographic projection of the first via onto the substrate at least partially overlap. The first planarization layer is disposed on the side of the second conductive layer facing away from the substrate, covering at least a portion of the signal line and filling at least a portion of the recess. The third conductive layer is disposed on the side of the first planarization layer facing away from the substrate.

[0006] In some embodiments, the first planarization layer is disposed as a single layer; Preferably, there are multiple signal lines, which are arranged at intervals. Preferably, the first planarization layer comprises an organic insulating material.

[0007] In some embodiments, the first planarization layer includes a filler portion that fills at least a portion of the recess and covers the portion of the signal line located within the first via. Preferably, the array substrate further includes a seventh insulating layer that covers the portion of the signal line exposed relative to the filling portion; Preferably, the seventh insulating layer also covers the filling portion; Preferably, the filling portion comprises an organic insulating material; Preferably, the seventh insulating layer comprises an inorganic insulating material.

[0008] In some embodiments, the driving circuit layer further includes a transistor, the transistor including a source and a drain, at least one of the source and drain being located in a third conductive layer; Preferably, the third conductive layer is electrically connected to the first conductive structure through a second via, wherein the second via penetrates at least the first planarization layer and the first insulating layer.

[0009] In some embodiments, the first conductive structure includes a plurality of sub-layers, which are stacked in a direction away from the substrate, adjacent sub-layers are insulated from each other, and signal lines are electrically connected to at least one sub-layer through a first via. Preferably, the first conductive structure includes at least one of a first active sublayer, a first metal sublayer, a second metal sublayer, a third metal sublayer, a second active sublayer, and a fourth metal sublayer.

[0010] In some embodiments, the first conductive structure includes a first active sublayer and a first metal sublayer disposed on the side of the first active sublayer away from the substrate. The first metal sublayer includes a first gate, and the orthographic projection of the first gate on the substrate at least partially overlaps with the orthographic projection of the first active sublayer on the substrate. Preferably, the first metal sublayer further includes a first capacitor plate; Preferably, the first gate is reused as a first capacitor plate; Preferably, the array substrate further includes a second insulating layer, which is stacked between the first active sublayer and the first metal sublayer.

[0011] In some embodiments, a portion of the signal lines are electrically connected to the first active sublayer via a first via, wherein the corresponding first via penetrates at least the first insulating layer and the second insulating layer; and / or, Some signal lines are electrically connected to the first metal sublayer through the first via, and the corresponding first via at least penetrates the first insulating layer; Preferably, the signal line electrically connected to the first active sublayer forms the source or drain of the transistor corresponding to the first active sublayer; Preferably, the third conductive layer is electrically connected to the first active sublayer through the second via, and the corresponding second via at least penetrates the first planarization layer, the first insulating layer and the second insulating layer; Preferably, a connecting electrode is provided between the third conductive layer and the first active sublayer, and the third conductive layer is electrically connected to the first active sublayer through the connecting electrode.

[0012] In some embodiments, the first conductive structure further includes a second metal sublayer disposed on the side of the first metal sublayer facing away from the substrate. The second metal sublayer includes a second capacitor plate, and the orthographic projection of the first capacitor plate on the substrate and the orthographic projection of the second capacitor plate on the substrate at least partially overlap. Preferably, the array substrate further includes a third insulating layer, which is stacked between the first metal sublayer and the second metal sublayer; Preferably, the third conductive layer is electrically connected to the first active sublayer through the second via, and the corresponding second via at least penetrates the first planarization layer, the first insulating layer, the second insulating layer and the third insulating layer; Preferably, some signal lines are electrically connected to the second metal sublayer through a first via, and the corresponding first via at least penetrates the first insulating layer.

[0013] In some embodiments, the first conductive structure further includes a third metal sublayer disposed on the side of the second metal sublayer facing away from the substrate. The third metal sublayer includes a third capacitor plate, and the orthographic projection of the third capacitor plate on the substrate at least partially overlaps with the orthographic projection of the second capacitor plate on the substrate. Preferably, the third metal sublayer further includes a connecting electrode, and the third conductive layer is electrically connected to the first active sublayer through the connecting electrode; Preferably, the array substrate further includes a fourth insulating layer disposed between the second metal sublayer and the third metal sublayer; Preferably, the second via used to connect the third conductive layer and the first active sublayer also penetrates the fourth insulating layer.

[0014] In some embodiments, the first conductive structure further includes a second active sublayer and a fourth metal sublayer disposed on the side of the second active sublayer facing away from the substrate. The fourth metal sublayer includes a second gate, and the orthographic projection of the second gate on the substrate at least partially overlaps with the orthographic projection of the second active sublayer on the substrate. Preferably, the array substrate further includes a fifth insulating layer, which is disposed between the second active sublayer and the fourth metal sublayer; Preferably, the second active sublayer is located on the side of the third metal sublayer facing away from the substrate, and the array substrate further includes a sixth insulating layer disposed between the third metal sublayer and the second active sublayer.

[0015] In some embodiments, some signal lines are electrically connected to the second active sublayer through a first via, and the corresponding first via penetrates at least the first insulating layer and the fifth insulating layer. Preferably, the signal line electrically connected to the second active sublayer forms the source or drain of the transistor corresponding to the second active sublayer.

[0016] A second aspect of this application provides a method for fabricating an array substrate, comprising: A first conductive structure is formed on one side of the substrate; A first insulating layer is formed on the side of the first conductive structure away from the substrate, and at least a portion of the first insulating layer is formed with a first via. A second conductive layer is formed on the side of the first insulating layer away from the substrate. The second conductive layer includes a signal line. The signal line is electrically connected to the first conductive structure through a first via. A recess is formed on the side of the signal line away from the substrate. The orthographic projection of the recess onto the substrate and the orthographic projection of the first via onto the substrate at least partially overlap. A first planarization layer is formed on the side of the second conductive layer away from the substrate. The first planarization layer covers at least a portion of the signal line and fills at least a portion of the recess. A third conductive layer is formed on the side of the first planarization layer that is away from the substrate.

[0017] In some embodiments, the step of forming a first planarization layer on the side of the second conductive layer away from the substrate includes: A first planarization material layer is formed on the side of the second conductive layer that is away from the substrate; The first planarization material layer is patterned to form the first planarization layer; Preferably, the substrate includes a first region and a second region, the first region being used for the display area corresponding to the display panel, and the second region being used for the non-display area corresponding to the display panel; The steps of patterning the first planarization material layer to form the first planarization layer include: The first planarization material layer is patterned, and the first planarization material layer in the second region is removed to form a first planarization layer located in the first region. Preferably, the step of patterning the first planarization material layer includes: The first planarization material layer is patterned, the first planarization material layer in the second region is removed, and the first planarization material layer in the first region is retained. The first planarization material layer in the first region is patterned to form the first planarization layer; Preferably, in the step of patterning the first planarization material layer in the first region to form the first planarization layer, the first planarization layer is disposed as a single layer in the first region, or... The first planarization layer includes a filler portion that fills at least a portion of the recess and covers the portion of the signal line located within the first via. Preferably, in the step of patterning the first planarization material layer in the first region to form a first planarization layer, and wherein the first planarization layer is disposed as a single layer in the first region, A second via is also formed, which at least penetrates the first planarization layer and the first insulating layer to expose a portion of the first conductive structure; Preferably, after forming the second via, the method further includes: A third conductive layer is formed on the side of the first planarization layer away from the substrate, and the third conductive layer is electrically connected to the first conductive structure through a second via.

[0018] A third aspect of this application provides a display panel comprising an array substrate according to any one of the above methods or an array substrate formed by the above-described preparation method.

[0019] In some embodiments, the display panel further includes an isolation structure and a light-emitting unit. The isolation structure is disposed on one side of the array substrate and forms an isolation opening. The isolation structure includes a first isolation portion and a second isolation portion stacked in a direction away from the array substrate. The second isolation portion protrudes into the isolation opening relative to the first isolation portion. At least a portion of the light-emitting unit is located within the isolation opening. Preferably, the display panel includes a display area, and the orthographic projection of the first planarization layer of the array substrate onto the substrate is located in the display area.

[0020] This application provides an array substrate, a method for fabricating the array substrate, and a display panel. The array substrate includes a substrate and a driving circuit layer. The driving circuit layer includes a first conductive structure, a first insulating layer, a second conductive layer, a first planarization layer, and a third conductive layer. The first conductive structure is disposed on one side of the substrate. The first insulating layer is disposed on the side of the first conductive structure facing away from the substrate. The second conductive layer is disposed on the side of the first insulating layer facing away from the substrate. The second conductive layer includes a signal line, which is electrically connected to the first conductive structure through a first via. A recess is formed on the side of the signal line facing away from the substrate. The orthographic projection of the recess onto the substrate and the orthographic projection of the first via onto the substrate at least partially overlap. The first planarization layer is disposed on the side of the second conductive layer facing away from the substrate. The first planarization layer covers at least a portion of the signal line and fills at least a portion of the recess. Therefore, when the third conductive layer is subsequently fabricated, the first planarization layer can effectively insulate the signal line and the third conductive layer at the recess, reducing the risk of the third conductive layer and the signal line contacting and short-circuiting in the recess, thus helping to improve the performance of the array substrate. Attached Figure Description

[0021] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the embodiments of this application will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1 A cross-sectional schematic diagram of an array substrate provided in some embodiments of this application; Figure 2This is another cross-sectional schematic diagram of the array substrate provided in some embodiments of this application; Figure 3 A cross-sectional schematic diagram of a display panel provided in some embodiments of this application; Figure 4 This is a schematic diagram of the pixel circuit structure provided in some embodiments of this application; Figure 5 This is a schematic diagram of the pixel circuit provided in some other embodiments of this application; Figure 6 A cross-sectional schematic diagram from another perspective of the array substrate provided in some embodiments of this application; Figure 7 A flowchart illustrating a method for fabricating an array substrate according to some embodiments of this application; Figure 8 Another flowchart illustrating a method for fabricating an array substrate provided in some embodiments of this application; Figure 9 Another flowchart illustrating a method for fabricating an array substrate provided in some embodiments of this application; Figure 10 Top view of a display panel provided in some embodiments of this application; Figure 11 A cross-sectional schematic diagram of a display panel provided in some embodiments of this application; Figure 12 Another cross-sectional schematic diagram of a display panel provided in some embodiments of this application; Figure 13 This is a schematic diagram of the structure of the light-emitting layer of a display panel provided in some embodiments of this application.

[0023] The attached icons are numbered as follows: Display panel 1000; array substrate 100; substrate 10; driving circuit layer 11; first conductive structure 13; first active sublayer 131; first metal sublayer 132; first gate 1321; first capacitor plate 1322; second metal sublayer 133; second capacitor plate 1331; third metal sublayer 134; third capacitor plate 1341; second active sublayer 135; fourth metal sublayer 136; second gate 1361; first insulating layer 14; second conductive layer 15; signal line 151; first planarization layer 16; first sub-section 161; second sub-section 162; filling section 163; third conductive layer 17; transistor 18; source 181; drain 182; seventh insulating layer 19; second planarization layer 20; second insulating layer 21; connecting electrode 22; third insulating layer 23; fourth insulating layer 24; fifth insulating layer 25; sixth insulating layer 26; shielding layer 27. First via K1; Recessed portion K2; Second via K3; Third via K4; Isolation structure 200; isolation opening 210; first isolation opening 210a; second isolation opening 210b; third isolation opening 210c; first isolation section 220; second isolation section 230; Light-emitting unit 300; first light-emitting unit 300a; second light-emitting unit 300b; third light-emitting unit 300c; first electrode 310; light-emitting layer 320; second electrode 330; Pixel definition layer 400; Pixel limiting part 410; Pixel opening 420; Display area AA; Non-display area NA; Electron blocking layer (EBL); Electron injection layer (EIL); Luminescent material layer (EML); Electron transport layer (ETL); Hole blocking layer (HBL); Hole transport layer (HTL); Pixel PX; Scan signal Scan; Sub-pixel SPX; First sub-pixel SPX1; Second sub-pixel SPX2; Sub-pixel SPX2; Third sub-pixel SPX3; Sub-pixel SPX3; First transistor T1; Second transistor T2; Third transistor T3; Fourth transistor T4; Fifth transistor T5; First capacitor C1; Second capacitor C2; First scan signal line S1; Second scan signal line S2; Third scan signal line S3. Detailed Implementation

[0024] The embodiments of this application will be described in further detail below with reference to the accompanying drawings and examples. The detailed description of the following embodiments and the accompanying drawings are used to illustrate the principles of this application by way of example, but should not be used to limit the scope of this application, that is, this application is not limited to the described embodiments.

[0025] In the description of this application, it should be noted that, unless otherwise stated, "a plurality of" means two or more; the terms "upper," "lower," "left," "right," "inner," and "outer," etc., indicating orientation or positional relationships, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on this application. Furthermore, the terms "first," "second," and "third," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance. "Vertical" is not vertical in the strict sense, but within the allowable tolerance range. "Parallel" is not parallel in the strict sense, but within the allowable tolerance range.

[0026] In this application, the reference to "embodiment" means that a specific feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a mutually exclusive, independent, or alternative embodiment. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described in this application can be combined with other embodiments.

[0027] The directional terms used in the following description refer to the directions shown in the figures and are not intended to limit the specific structure of this application. It should also be noted in the description of this application that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a direct connection or an indirect connection through an intermediate medium. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0028] In some array substrates, an insulating layer is typically provided between the signal line and the underlying conductive layer. This insulating layer may have vias, through which the signal line can be electrically connected to the corresponding conductive layer. However, after the signal line extends to the via, a recess corresponding to the via is usually formed above the signal line. This can cause the insulating layer above the signal line to easily break at the recess, leading to the conductive layer above the signal line coming into contact with the signal line at the break point, thus causing a short circuit.

[0029] To address at least some of the aforementioned problems, this application provides an array substrate, a method for fabricating the array substrate, and a display panel. The structure of the array substrate will be described below with reference to the accompanying drawings.

[0030] refer to Figure 1 and Figure 2The first aspect of this application provides an array substrate 100, which includes a substrate 10 and a driving circuit layer 11. The driving circuit layer 11 includes a first conductive structure 13, a first insulating layer 14, a second conductive layer 15, a first planarization layer 16, and a third conductive layer 17. The first conductive structure 13 is disposed on one side of the substrate 10. The first insulating layer 14 is disposed on the side of the first conductive structure 13 away from the substrate 10. The second conductive layer 15 is disposed on the side of the first insulating layer 14 away from the substrate 10. The second conductive layer 15 includes a signal line 151, which is electrically connected to the first conductive structure 13 through a first via K1. A recess K2 is formed on the side of the signal line 151 away from the substrate 10. The orthographic projection of the recess K2 on the substrate 10 and the orthographic projection of the first via K1 on the substrate 10 at least partially overlap. The first planarization layer 16 is disposed on the side of the second conductive layer 15 away from the substrate 10. The first planarization layer 16 covers at least a portion of the signal line 151 and fills at least a portion of the recess K2. The third conductive layer 17 is disposed on the side of the first planarization layer 16 away from the substrate 10.

[0031] The substrate 10 can be a rigid substrate 10 made of materials such as glass or plastic, or a flexible substrate 10 made of materials such as polyethersulfone (PES), polyacrylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyarylate, polyimide (PI), polycarbonate (PC) or cellulose acetate propionate (CAP).

[0032] The driving circuit layer 11 contains a driving circuit for controlling the light emission of the light-emitting unit 300. The driving circuit layer 11 may include conductive layers and insulating layers, among other film layers. Specifically, the driving circuit layer 11 may include a first conductive structure 13, a first insulating layer 14, a second conductive layer 15, a first planarization layer 16, and a third conductive layer 17. The patterning of these film layers forms the driving circuit for controlling the light emission of the light-emitting unit 300. Figure 3 Transistor 18 of the drive circuit is shown.

[0033] The first conductive structure 13 may be a single-layer structure, or the first conductive structure 13 may be a composite film layer composed of metal sublayers, semiconductor sublayers and other film layers. This embodiment does not limit this.

[0034] The first insulating layer 14 covers the first conductive structure 13, which may include at least one of inorganic and organic materials.

[0035] The second conductive layer 15 is disposed on the side of the first insulating layer 14 away from the substrate 10, and the first conductive structure 13 and the second conductive layer 15 can be insulated through the first insulating layer 14.

[0036] The second conductive layer 15 includes a signal line 151, which can be electrically connected to the first conductive structure 13 through a first via K1. A portion of the signal line 151 can be located inside the first via K1 and electrically connected to the first conductive structure 13 exposed through the first via K1, while another portion can be located outside the first via K1 for transmitting signals.

[0037] It should be noted that the first via K1 penetrates at least the first insulating layer 14. Furthermore, when the first conductive structure 13 is composed of multiple film layers, and the signal line 151 is electrically connected to one of the film layers in the first conductive structure 13, the first via K1 also penetrates the other film layers above that film layer.

[0038] It is known that a portion of the signal line 151 located within the first via K1 may be located on the bottom surface of the first via K1, covering the first conductive structure 13 exposed through the first via K1. Furthermore, another portion of the signal line 151 located within the first via K1 may be located on the sidewall surface of the first via K1. Therefore, the two portions of the signal line 151 can jointly define a recessed portion K2, which is located on the side of the signal line 151 facing away from the substrate 10 and corresponds to the first via K1.

[0039] Optionally, a portion of the orthographic projection of the recessed portion K2 on the substrate 10 may overlap with the orthographic projection of the first via K1 on the substrate 10, while another portion may be misaligned with the orthographic projection of the first via K1 on the substrate 10. Alternatively, the orthographic projection of the recessed portion K2 on the substrate 10 may be located within the orthographic projection of the first via K1 on the substrate 10.

[0040] The first planarization layer 16 is disposed on the side of the second conductive layer 15 facing away from the substrate 10. The first planarization layer 16 can be formed using an insulating material, for example, an organic insulating material. The first planarization layer 16 covers at least a portion of the signal line 151 and fills at least a portion of the recess K2. Therefore, when the third conductive layer 17 is subsequently fabricated, the first planarization layer 16 can effectively insulate the signal line 151 and the third conductive layer 17 in the recess K2, reducing the risk of the third conductive layer 17 and the signal line 151 contacting and short-circuiting in the recess K2, which helps to improve the performance of the array substrate 100.

[0041] Furthermore, since the first planarization layer 16 can fill at least part of the recess K2 to reduce the height difference of the recess K2, the risk of the third conductive layer 17 breaking in the recess K2 can be reduced during the subsequent fabrication of the third conductive layer 17, which helps to improve the continuity of the third conductive layer 17.

[0042] In some alternative embodiments, the third conductive layer 17 can be used to transmit ELVDD signals. It is understood that when the third conductive layer 17 is used to transmit ELVDD signals, the coverage area of ​​the third conductive layer 17 in the array substrate 100 is relatively large, thereby helping to improve the crosstalk problem of the display panel 1000.

[0043] In this embodiment, since the first planarization layer 16 can cover at least a portion of the signal line 151 and fill at least a portion of the recess K2, when the third conductive layer 17 with a larger coverage area is subsequently prepared, the third conductive layer 17 is less likely to come into contact with the signal line 151 in the recess K2 and cause a short circuit, thereby helping to improve the performance of the display panel 1000.

[0044] Optionally, the array substrate 100 may also include scan lines that provide scan signals Scan and data lines that provide data signals Data to the driving circuit.

[0045] refer to Figure 4 The driving circuit includes a first transistor T1, a second transistor T2, and a first capacitor C1. The first transistor T1 can be a driving transistor, the second transistor T2 can be a data transistor, and the first capacitor C1 can be a storage capacitor. The source of the second transistor T2 is connected to the data line providing the data signal "Data", the gate of the second transistor T2 is connected to the scan line providing the scan signal "Scan", the drain of the second transistor T2 is connected to the gate of the first transistor T1, the two ends of the first capacitor C1 are respectively connected to the gate and the source of the first transistor T1, and the drain of the first transistor T1 is connected to the light-emitting unit 300. Figure 3 This is one implementation of the driving circuit; the driving circuit of this application is not limited to this one. Figure 3 The 2T1C driving circuit shown can also be other driving circuits, such as 5T2C, 7T1C, 8T1C driving circuits, etc.

[0046] See Figure 5 The driving circuit can also be a 5T2C circuit. For example, the driving circuit also includes a second capacitor C2, a third transistor T3, a fourth transistor T4, and a fifth transistor T5.

[0047] Optionally, the multiple transistors in the driving circuit may include driving transistors, switching transistors, initialization transistors, anode reset transistors, gate reset transistors, etc., and there are various ways to set and connect the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, and the fifth transistor T5.

[0048] In some optional embodiments, the first transistor T1 is a driving transistor. One of the source and drain of the first transistor T1 is connected to the driving voltage signal line VDD, and the other is connected to the fifth transistor T5. The fifth transistor T5 is a light-emitting control transistor. One of the source and drain of the fifth transistor T5 is connected to the first transistor T1, and the other is connected to the light-emitting unit 300. The gate of the fifth transistor T5 is connected to the light-emitting control signal line, which can be used to control the on / off state of the fifth transistor T5, thereby controlling the on / off state of the circuit between the first transistor T1 and the light-emitting unit 300, and controlling the light emission of the light-emitting unit 300. During the use of the array substrate, the first transistor T1 can always remain in a conducting state, and the on / off state of the light-emitting unit 300 is controlled by the on / off state of the fifth transistor T5.

[0049] Optionally, the second transistor T2 is a gate reset transistor, one of the source and drain of the second transistor T2 is connected to the first transistor T1, and the gate of the second transistor T2 can be used to connect to the first scan signal line S1.

[0050] Optionally, the third transistor T3 is an anode reset transistor. One of the source and drain of the third transistor T3 is used to connect to the light-emitting unit 300, and the other is used to connect to the voltage reference signal line. The gate of the third transistor T3 can be used to connect to the third scan signal line S3. When the third scan signal line S3 inputs a control signal to the gate of the third transistor T3, the third transistor T3 is turned on, and the voltage reference signal can be transmitted to the light-emitting unit 300 through the third transistor T3, thereby realizing the anode reset function.

[0051] Optionally, one of the source and drain of the fourth transistor T4 is used to connect to the data signal line Data or the initialization signal line, and the other is used to connect to the plate of the first capacitor C1. The gate of the fourth transistor T4 can be used to connect to the second scan signal line S2. When the data signal line Data and the fourth transistor T4 are turned on, the fourth transistor T4 acts as a switching transistor. When the fourth transistor T4 is used to transmit the initialization signal, the fourth transistor T4 acts as an initialization transistor. Multiplexing the initialization transistor and the switching transistor simplifies the pixel circuit structure.

[0052] Please continue reading. Figure 1 In some embodiments, the first planarization layer 16 is provided as a single layer.

[0053] The first planarization layer 16 can not only fill the recess K2 and cover the signal line 151 inside the first via K1, but it can also extend outside the recess K2 and cover the signal line 151 outside the first via K1. Optionally, the first planarization layer 16 can also cover the first insulating layer 14 that is not covered by the signal line 151.

[0054] In these embodiments, by setting the first planarization layer 16 as a single layer, the first planarization layer 16 can not only fill the recess K2, but also effectively insulate the signal line 151 and the third conductive layer 17, without the need to set other insulating film layers between the signal line 151 and the third conductive layer 17, which helps to simplify the film layer structure in the array substrate 100 and reduce the thickness of the array substrate 100.

[0055] Preferably, there are multiple signal lines 151, which are arranged at intervals and can be used to transmit one or more signals in the array substrate 100.

[0056] Please continue reading. Figure 1 Preferably, the first planarization layer 16 includes a first sub-part 161 and a second sub-part 162, the first sub-part 161 covering the signal line 151 and filling at least a portion of the recess K2, and the second sub-part 162 covering the portion of the first insulating layer 14 exposed relative to the signal line 151.

[0057] It is known that when multiple signal lines 151 are arranged at intervals, each signal line 151 can be electrically connected to the first conductive structure 13 through the first via K1, and part of the first insulating layer 14 can be exposed through the gap between two adjacent signal lines 151.

[0058] Therefore, in these embodiments, the first planarization layer 16 includes a first sub-part 161 and a second sub-part 162. The first sub-part 161 covers each signal line 151 and fills at least a portion of the recess K2 corresponding to each signal line 151, thereby reducing the risk that the subsequently prepared third conductive layer 17 will come into contact with the corresponding signal line 151 at each recess K2 and short-circuit. The second sub-part 162 covers a portion of the first insulating layer 14 relative to the signal line 151. That is, the second sub-part 162 can be located in the region corresponding to the gap between two adjacent signal lines 151, covering the first insulating layer 14 exposed through the gap. On the one hand, this helps to improve the insulation performance between each signal line 151 and the third conductive layer 17. On the other hand, the connection between the first insulating layer 14 and the first planarization layer 16 also helps to improve the stability of the first planarization layer 16 and reduce the risk of the first planarization layer 16 collapsing or peeling.

[0059] It should be noted that there can be multiple first sub-parts 161, which are arranged at intervals and correspond one-to-one with multiple signal lines 151. The second sub-part 162 can be located between any two adjacent first sub-parts 161 to cover the first insulating layer 14 corresponding to the gap between two adjacent signal lines 151.

[0060] Preferably, the side surface of the first sub-part 161 facing away from the substrate 10 is flush with the side surface of the second sub-part 162 facing away from the substrate 10, which helps to improve the flatness of the side surface of the first planarization layer 16 facing away from the substrate 10 and improve the preparation yield of subsequent films such as the third conductive layer 17.

[0061] Preferably, the first planarization layer 16 comprises an organic insulating material. The organic insulating material has good leveling and insulating properties, enabling the formation of a flat first planarization layer 16. This allows subsequent layers such as the third conductive layer 17 to be formed on a relatively flat surface, thereby improving the fabrication yield. Furthermore, the organic insulating material also possesses good flexibility and external force buffering properties.

[0062] Please continue reading. Figure 2 In some embodiments, the first planarization layer 16 includes a filler portion 163 that fills at least a portion of the recess K2 and covers the portion of the signal line 151 located within the first via K1. The filler portion 163 effectively insulates the signal line 151 and the corresponding third conductive layer 17 within the first via K1 in the recess K2, thereby reducing the risk of the third conductive layer 17 and the signal line 151 coming into contact and short-circuiting within the recess K2.

[0063] Please continue reading. Figure 2 Preferably, the array substrate 100 further includes a seventh insulating layer 19, which covers the portion of the signal line 151 exposed relative to the filling portion 163.

[0064] It is understood that the filling portion 163 covers the portion of the signal line 151 located inside the first via K1, while the portion of the signal line 151 located outside the first via K1 is exposed because it is not covered by the filling portion 163. Therefore, in this embodiment, the seventh insulating layer 19 covers the portion of the signal line 151 exposed relative to the filling portion 163, thereby insulating the signal line 151 located outside the first via K1 and the third conductive layer 17, reducing the risk of the signal line 151 contacting the third conductive layer 17 and short-circuiting.

[0065] Optionally, the thickness of the seventh insulating layer 19 is less than the thickness of the filling portion 163, thereby reducing the thickness of the array substrate 100 while ensuring that the signal line 151 is insulated from the third conductive layer 17.

[0066] Preferably, the seventh insulating layer 19 also covers the filler portion 163, which helps to further reduce the risk of the third conductive layer 17 and the signal line 151 coming into contact and short-circuiting in the recess K2.

[0067] Preferably, the seventh insulating layer 19 also covers the portion of the first insulating layer 14 exposed relative to the signal line 151.

[0068] Specifically, when multiple signal lines 151 are arranged at intervals, the first insulating layer 14 is exposed in the gap between two adjacent signal lines 151. Therefore, in this embodiment, the first insulating layer 14 exposed relative to the signal line 151 is covered by the seventh insulating layer 19. On the one hand, this helps to improve the insulation performance between each signal line 151 and the third conductive layer 17. On the other hand, the connection between the first insulating layer 14 and the seventh insulating layer 19 is equivalent to covering the signal line 151 and the filling portion 163 from both sides in the thickness direction of the substrate 10. Therefore, it also helps to improve the stability of the structure such as the signal line 151 and the filling portion 163, and reduces the risk of the signal line 151 and the filling portion 163 collapsing or peeling off.

[0069] Preferably, the seventh insulating layer 19 is provided as a single layer, which helps to improve the insulation performance and stability of the seventh insulating layer 19.

[0070] Preferably, the filling portion 163 comprises an organic insulating material. The organic insulating material has good leveling and insulating properties, which helps to improve the filling effect of the filling portion 163 on the recessed portion K2.

[0071] Preferably, the seventh insulating layer 19 comprises an inorganic insulating material. Using an inorganic insulating material to prepare the seventh insulating layer 19 allows for a thinner and lighter design while maintaining its insulating properties. This reduces the overall thickness of the array substrate 100 and also reduces the difficulty of connecting the third conductive layer 17 to the vias in the underlying film layer, thus improving the production efficiency of the array substrate 100.

[0072] Please continue reading. Figure 3 In some embodiments, the driving circuit layer 11 further includes a transistor 18, which includes a source 181 and a drain 182, at least one of which is located in the third conductive layer 17.

[0073] Specifically, the driving circuit layer 11 includes a driving circuit for driving the light-emitting unit 300 to emit light. Figure 4 A transistor 18 in a driving circuit is shown. The transistor 18 includes a source 181 and a drain 182, at least one of which is located in a third conductive layer 17; that is, at least one of the source 181 and drain 182 can be formed during the fabrication of the third conductive layer 17. Specifically, during the fabrication of the third conductive layer 17, at least one of the source 181 and drain 182 can be formed by patterning a third conductive material layer.

[0074] See Figure 6Preferably, the third conductive layer 17 is electrically connected to the first conductive structure 13 through the second via K3, and the second via K3 at least penetrates the first planarization layer 16 and the first insulating layer 14.

[0075] The third conductive layer 17 is electrically connected to the first conductive structure 13 through the second via K3 to transmit signals. Exemplarily, the first conductive structure 13 may include a first active sublayer 131, and in the third conductive layer 17, at least one of the source 181 and drain 182 may be electrically connected to the first active sublayer 131 in the first conductive structure 13 through the second via K3 to form a... Figure 4 At least a portion of the transistor 18 shown.

[0076] Please continue reading. Figure 3 and Figure 6 Preferably, the array substrate 100 further includes a second planarization layer 20, which is disposed on the side of the third conductive layer 17 away from the substrate 10.

[0077] The second planarization layer 20 can make the surface of the third conductive layer 17 facing away from the substrate 10 flat, that is, make the surface of the array substrate 100 flat, thereby helping to prepare the light-emitting unit 300 and other film structures of the display panel 1000, and improving the preparation yield and preparation difficulty of the film structure.

[0078] Please continue reading. Figure 3 Preferably, the second planarization layer 20 has a third via K4, which is used to electrically connect the first electrode 310 of the display panel 1000 to the third conductive layer 17. The third via K4 can penetrate the second planarization layer 20, exposing a portion of the third conductive layer 17 on the side of the second planarization layer 20 facing the substrate 10. For example, it can expose one of the source electrode 181 and the drain electrode 182 in the third conductive layer 17, so that the first electrode 310, which is subsequently fabricated, can be electrically connected to this portion of the third conductive layer 17 via the third via K4, so that the driving circuit of the driving circuit layer 11 can drive the light-emitting unit 300 to emit light.

[0079] In some embodiments, the first conductive structure 13 includes a plurality of sub-layers, which are stacked in a direction away from the substrate, and adjacent sub-layers are insulated from each other. The signal line 151 is electrically connected to at least one sub-layer through a first via K1.

[0080] Specifically, in the first conductive structure 13, each sublayer can be made of conductive material, and by patterning these sublayers, a part of the driving circuit can be formed. An insulating layer can be provided between two adjacent sublayers to insulate them from each other.

[0081] The number of signal lines 151 and first vias K1 can be multiple. Multiple signal lines 151 can be electrically connected to a sublayer through multiple first vias K1, or multiple signal lines 151 can be electrically connected to multiple sublayers through multiple first vias K1. This embodiment does not limit this.

[0082] It should be noted that if signal line 151 is electrically connected to the sublayer furthest from substrate 10 among the multiple sublayers, then the corresponding first via K1 penetrates the first insulating layer 14. If signal line 151 is electrically connected to other sublayers besides the aforementioned furthest sublayer, then the corresponding first via K1 needs to penetrate the first insulating layer 14 and other film layers above the corresponding sublayer, so that a portion of the corresponding sublayer is exposed through the corresponding first via K1.

[0083] Please continue reading. Figure 1 and Figure 2 Preferably, the first conductive structure 13 includes at least one of a first active sublayer 131, a first metal sublayer 132, a second metal sublayer 133, a third metal sublayer 134, a second active sublayer 135, and a fourth metal sublayer 136.

[0084] The first active sublayer 131, the first metal sublayer 132, the second metal sublayer 133, the third metal sublayer 134, the second active sublayer 135, and the fourth metal sublayer 136 are arranged sequentially in a direction away from the substrate 10, and adjacent sublayers are insulated from each other. If the first conductive structure 13 includes at least one of the aforementioned sublayers, then the signal line 151 can be electrically connected to at least one of the aforementioned sublayers through the first via K1, and the third conductive layer 17 can be electrically connected to at least one of the aforementioned sublayers through the second via K3. For example, when the first conductive structure 13 includes the first active sublayer 131, the signal line 151 can be electrically connected to the first active sublayer 131 through the first via K1, and the third conductive layer 17 can be electrically connected to the first active sublayer 131 through the second via K3.

[0085] Please continue reading. Figure 1 and Figure 2 In some embodiments, the first conductive structure 13 includes a first active sublayer 131 and a first metal sublayer 132 disposed on the side of the first active sublayer 131 away from the substrate 10. The first metal sublayer 132 includes a first gate 1321, and the orthographic projection of the first gate 1321 on the substrate 10 at least partially overlaps with the orthographic projection of the first active sublayer 131 on the substrate 10.

[0086] The first active sublayer 131 may include a semiconductor material and may be connected to the source 181 and the drain 182. The first gate 1321 is disposed on the first metal sublayer 132 and is located on the side of the first active sublayer 131 away from the substrate 10. The first gate 1321, the first active sublayer 131, and the source 181 and drain 182 connected to the first active sublayer 131 may together constitute a transistor 18.

[0087] Optionally, the orthogonal projection of the first gate 1321 on the substrate 10 may be located within the orthogonal projection of the first active sublayer 131 on the substrate 10.

[0088] Please continue reading. Figure 1 and Figure 2 Preferably, the first metal sublayer 132 further includes a first capacitor plate 1322. The first capacitor plate 1322 and the first gate 1321 are disposed in the same layer and made of the same material, and can be formed by the same process, which helps to reduce the fabrication difficulty of the array substrate 100 and improve the production efficiency of the array substrate 100.

[0089] Preferably, the first gate 1321 is reused as the first capacitor plate 1322. The first capacitor plate 1322 is obtained by reusing the first gate 1321, which can simplify the structure of the driving circuit, reduce the distribution area of ​​the driving circuit, and improve the performance of the display panel 1000.

[0090] Please continue reading. Figure 1 and Figure 2 Preferably, the array substrate 100 further includes a second insulating layer 21, which is stacked between the first active sub-layer 131 and the first metal sub-layer 132. The second insulating layer 21 can serve as a gate insulating layer, which on the one hand insulates the first active sub-layer 131 and the first gate 1321, achieving electrical isolation between the first active sub-layer 131 and the first gate 1321; on the other hand, the second insulating layer 21 allows the gate electric field to penetrate and act on the first active sub-layer 131, so as to form a channel.

[0091] In some embodiments, a portion of the signal line 151 is electrically connected to the first active sublayer 131 through a first via K1. The corresponding first via K1 at least penetrates the first insulating layer 14 and the second insulating layer 21. This corresponding first via K1 is used to conduct the first active sublayer 131 and the corresponding signal line 151. The first via K1 can penetrate all the film layers between the first active sublayer 131 and the second conductive layer 15 where the signal line 151 is located, so that a portion of the first active sublayer 131 is exposed in the corresponding first via K1. Therefore, when the signal line 151 extends into the corresponding first via K1, it can be electrically connected to the exposed first active sublayer 131 to transmit a signal to the first active sublayer 131 or to transmit the signal of the first active sublayer 131 outward.

[0092] Furthermore, in this embodiment, a portion of the first planarization layer 16 may be provided in the recessed portion K2 formed on the side of the signal line 151 that is electrically connected to the first active sublayer 131 away from the substrate 10. This portion of the first planarization layer 16 can achieve insulation between the corresponding signal line 151 and the third conductive layer 17 in the recessed portion K2, thereby reducing the risk of the third conductive layer 17 contacting the signal line 151 and short-circuiting.

[0093] Please continue reading. Figure 1 and Figure 2 In some embodiments, a portion of the signal line 151 is electrically connected to the first metal sublayer 132 through a first via K1, and the corresponding first via K1 at least penetrates the first insulating layer 14. This corresponding first via K1 serves to connect the first metal sublayer 132 and the corresponding signal line 151. The first via K1 can penetrate the entire film layer between the first metal sublayer 132 and the second conductive layer 15 where the signal line 151 is located, exposing a portion of the first metal sublayer 132 within the corresponding first via K1. When the signal line 151 extends into the corresponding first via K1, it can be electrically connected to the exposed first metal sublayer 132 to transmit signals to or from the first metal sublayer 132.

[0094] It should be noted that the aforementioned signal lines 151 used for electrical connection with the first metal sublayer 132 can be electrically connected to the first gate 1321, or they can be electrically connected to the first capacitor plate 1322. Alternatively, there can be multiple signal lines 151 used for electrical connection with the first metal sublayer 132, with some signal lines 151 electrically connected to the first gate 1321 and others electrically connected to the first capacitor plate 1322. This embodiment does not impose any limitations on this.

[0095] Furthermore, in this embodiment, a portion of the first planarization layer 16 may be provided in the recessed portion K2 formed on the side of the signal line 151 that is electrically connected to the first metal sublayer 132 away from the substrate 10. This portion of the first planarization layer 16 can achieve insulation between the corresponding signal line 151 and the third conductive layer 17 in the recessed portion K2, thereby reducing the risk of the third conductive layer 17 contacting the signal line 151 and short-circuiting.

[0096] Preferably, the signal line 151 electrically connected to the first active sub-layer 131 forms the source 181 or drain 182 of the transistor 18 corresponding to the first active sub-layer 131, for transferring charge carriers.

[0097] It is understood that the same first active sub-layer 131 can be electrically connected to the third conductive layer 17 and a portion of the signal line 151 simultaneously. In this case, one of the third conductive layer 17 and the portion of the signal line 151 can serve as the source 181 of the same transistor 18, while the other serves as the drain 182 of the corresponding transistor 18. Alternatively, the third conductive layer 17 and the signal line 151 can serve as the source 181 and / or drain 182 of different transistors 18. This embodiment does not impose any limitations on this.

[0098] Please continue reading. Figure 6 Preferably, the third conductive layer 17 is electrically connected to the first active sublayer 131 through a second via K3. The corresponding second via K3 penetrates at least the first planarization layer 16, the first insulating layer 14, and the second insulating layer 21. This corresponding second via K3 can penetrate all the film layers between the third conductive layer 17 and the first active sublayer 131, exposing a portion of the first active sublayer 131 in the corresponding second via K3. When the third conductive layer 17 extends into the corresponding second via K3, it can be electrically connected to the first active sublayer 131. The third conductive layer 17 may include the source 181 and / or drain 182 of the transistor 18 corresponding to the first active sublayer 131, which is electrically connected to the first active sublayer 131 through the second via K3 to transfer charge carriers.

[0099] Please continue reading. Figure 6 Preferably, a connecting electrode 22 is provided between the third conductive layer 17 and the first active sub-layer 131, and the third conductive layer 17 is electrically connected to the first active sub-layer 131 through the connecting electrode 22. In the thickness direction of the substrate 10, the connecting electrode 22 can be located between the third conductive layer 17 and the first active sub-layer 131. The arrangement of the connecting electrode 22 is equivalent to dividing the corresponding second via K3 into two sub-vias. The third conductive layer 17 is electrically connected to the connecting electrode 22 through one of the sub-vias, and the connecting electrode 22 is electrically connected to the first active sub-layer 131 through the other sub-via. This arrangement helps to reduce the depth of the corresponding second via K3, reduces the fabrication difficulty of the corresponding second via K3, and thus helps to improve the production efficiency of the array substrate 100.

[0100] Please continue reading. Figure 1 and Figure 2 In some embodiments, the first conductive structure 13 further includes a second metal sublayer 133 disposed on the side of the first metal sublayer 132 away from the substrate 10. The second metal sublayer 133 includes a second capacitor plate 1331. The orthographic projection of the first capacitor plate 1322 on the substrate 10 and the orthographic projection of the second capacitor plate 1331 on the substrate 10 at least partially overlap.

[0101] The second metal sublayer 133 is disposed on the side of the first metal sublayer 132 away from the substrate 10 and is insulated from the first metal sublayer 132. The second metal sublayer 133 includes a second capacitor plate 1331, and the orthographic projection of the first capacitor plate 1322 on the substrate 10 and the orthographic projection of the second capacitor plate 1331 on the substrate 10 at least partially overlap, and the two can jointly form a capacitor in the driving circuit.

[0102] Optionally, the orthographic projection of the first capacitor plate 1322 on the substrate 10 can coincide with the orthographic projection of the second capacitor plate 1331 on the substrate 10, which helps to improve the performance of the capacitor.

[0103] Please continue reading. Figure 1 and Figure 2 Preferably, the array substrate 100 further includes a third insulating layer 23, which is stacked between the first metal sublayer 132 and the second metal sublayer 133 to insulate the first metal sublayer 132 and the second metal sublayer 133 from each other.

[0104] Optionally, the third insulating layer 23 may include organic or inorganic materials.

[0105] Preferably, the third conductive layer 17 is electrically connected to the first active sublayer 131 through the second via K3, and the corresponding second via K3 penetrates at least the first planarization layer 16, the first insulating layer 14, the second insulating layer 21, and the third insulating layer 23. In the thickness direction of the substrate 10, the first planarization layer 16, the first insulating layer 14, the second insulating layer 21, and the third insulating layer 23 are all located between the third conductive layer 17 and the first active sublayer 131. Therefore, the second via K3, which is used to connect the third conductive layer 17 and the first active sublayer 131, penetrates the first planarization layer 16, the first insulating layer 14, the second insulating layer 21, and the third insulating layer 23, allowing the first active sublayer 131 to be exposed in the corresponding second via K3.

[0106] Please continue reading. Figure 1 and Figure 2 Preferably, a portion of the signal line 151 is electrically connected to the second metal sublayer 133 through a first via K1, and the corresponding first via K1 at least penetrates the first insulating layer 14. This corresponding first via K1 is used to connect the signal line 151 and the second metal sublayer 133. The first via K1 can penetrate all the film layers between the second metal sublayer 133 and the second conductive layer 15 where the signal line 151 is located, and it at least penetrates the first insulating layer 14 to expose a portion of the second metal sublayer 133. When the signal line 151 extends into the corresponding first via K1, the signal line 151 can be electrically connected to the second metal sublayer 133 exposed in the corresponding first via K1 to transmit a signal.

[0107] For example, some signal lines 151 can be electrically connected to the second capacitor plate 1331 of the second metal sublayer 133 through the first via K1 to transmit signals.

[0108] Furthermore, in this embodiment, a portion of the first planarization layer 16 may be provided in the recessed portion K2 formed on the side of the signal line 151 that is electrically connected to the second metal sublayer 133 away from the substrate 10. This portion of the first planarization layer 16 can achieve insulation between the corresponding signal line 151 and the third conductive layer 17 in the recessed portion K2, thereby reducing the risk of the third conductive layer 17 contacting the signal line 151 and short-circuiting.

[0109] Please continue reading. Figure 1 and Figure 2 In some embodiments, the first conductive structure 13 further includes a third metal sublayer 134 disposed on the side of the second metal sublayer 133 away from the substrate. The third metal sublayer 134 includes a third capacitor plate 1341, and the orthographic projection of the third capacitor plate 1341 on the substrate at least partially overlaps with the orthographic projection of the second capacitor plate 1331 on the substrate.

[0110] The third metal sublayer 134 is disposed on the side of the second metal sublayer 133 facing away from the substrate 10 and is insulated from the second metal sublayer 133. The third metal sublayer 134 includes a third capacitor plate 1341, the orthographic projection of the third capacitor plate 1341 on the substrate at least partially overlaps with the orthographic projection of the second capacitor plate 1331 on the substrate. Therefore, the third capacitor plate 1341 and the second capacitor plate 1331 can together form another capacitor in the driving circuit.

[0111] It is understood that, in the embodiments of this application, the second capacitor plate 1331 can be used as a common capacitor plate in the driving circuit, and it forms different capacitances with the first capacitor plate 1322 and the third capacitor plate 1341 respectively, thereby helping to simplify the structure of the array substrate 100.

[0112] Preferably, the third metal sublayer 134 further includes Figure 6 As shown in the diagram, the third conductive layer 17 is electrically connected to the first active sublayer 131 via the connecting electrode 22.

[0113] In this embodiment, the connection electrode 22 for connecting the third conductive layer 17 and the first active sub-layer 131 is located in the third metal sub-layer 134. That is, the connection electrode 22 and the third capacitor plate 1341 can be formed in the same process, which helps to simplify the fabrication process of the array substrate 100 and reduce the fabrication difficulty of the array substrate 100.

[0114] Please continue reading. Figure 1 and Figure 2Preferably, the array substrate 100 further includes a fourth insulating layer 24, which is disposed between the second metal sublayer 133 and the third metal sublayer 134 to insulate the second metal sublayer 133 and the third metal sublayer 134.

[0115] Optionally, the fourth insulating layer 24 may include organic or inorganic materials.

[0116] Preferably, the second via K3 used to connect the third conductive layer 17 and the first active sublayer 131 also penetrates the fourth insulating layer 24.

[0117] Specifically, the fourth insulating layer 24 is located between the third conductive layer 17 and the first active sub-layer 131. Therefore, the second via K3, which is used to connect the third conductive layer 17 and the first active sub-layer 131, passes through the fourth insulating layer 24, so that the first active sub-layer 131 is exposed in the corresponding second via K3.

[0118] Please continue reading. Figure 1 and Figure 2 In some embodiments, the first conductive structure 13 further includes a second active sublayer 135 and a fourth metal sublayer 136 disposed on the side of the second active sublayer 135 away from the substrate 10. The fourth metal sublayer 136 includes a second gate 1361, and the orthographic projection of the second gate 1361 on the substrate at least partially overlaps with the orthographic projection of the second active sublayer 135 on the substrate 10.

[0119] The second active sublayer 135 may include a semiconductor material and may be connected to the source 181 and the drain 182. The second gate 1361 is disposed on the fourth metal sublayer 136, which is located on the side of the second active sublayer 135 away from the substrate 10. The second gate 1361, the second active sublayer 135, and the source 181 and drain 182 connected to the second active sublayer 135 may together constitute a transistor 18.

[0120] Optionally, the orthogonal projection of the second gate 1361 onto the substrate 10 may be located within the orthogonal projection of the second active sublayer 135 onto the substrate 10.

[0121] Preferably, the array substrate 100 further includes a fifth insulating layer 25, which is disposed between the second active sub-layer 135 and the fourth metal sub-layer 136. The fifth insulating layer 25 can serve as a gate insulating layer, on the one hand is to insulate the second active sub-layer 135 and the second gate 1361, thereby achieving electrical isolation between the second active sub-layer 135 and the second gate 1361, and on the other hand, the fifth insulating layer 25 allows the gate electric field to penetrate and act on the second active sub-layer 135, so as to form a channel.

[0122] Optionally, the fifth insulating layer 25 may include organic or inorganic materials.

[0123] Preferably, the second active sublayer 135 is located on the side of the third metal sublayer 134 away from the substrate 10. The array substrate 100 further includes a sixth insulating layer 26, which is disposed between the third metal sublayer 134 and the second active sublayer 135 to achieve insulation between the third metal sublayer 134 and the second active sublayer 135.

[0124] Optionally, the sixth insulating layer 26 may include organic or inorganic materials.

[0125] In some embodiments, a portion of the signal line 151 is electrically connected to the second active sublayer 135 through a first via K1, wherein the corresponding first via K1 penetrates at least the first insulating layer 14 and the fifth insulating layer 25. This corresponding first via K1 is used to conduct the second active sublayer 135 and the corresponding signal line 151. The first via K1 can penetrate all the film layers between the second active sublayer 135 and the second conductive layer 15 where the signal line 151 is located, exposing a portion of the second active sublayer 135 within the corresponding first via K1. Therefore, when the signal line 151 extends into the corresponding first via K1, it can be electrically connected to the exposed second active sublayer 135 to transmit signals to or to the second active sublayer 135.

[0126] Furthermore, in this embodiment, a portion of the first planarization layer 16 may be provided in the recessed portion K2 formed on the side of the signal line 151 that is electrically connected to the second active sublayer 135 away from the substrate 10. This portion of the first planarization layer 16 can achieve insulation between the corresponding signal line 151 and the third conductive layer 17 in the recessed portion K2, thereby reducing the risk of the third conductive layer 17 contacting the signal line 151 and short-circuiting.

[0127] Preferably, the signal line 151 electrically connected to the second active sublayer 135 forms the source 181 or drain 182 of the transistor 18 corresponding to the second active sublayer 135, for transferring charge carriers.

[0128] Optionally, the second active sublayer 135 can be electrically connected to two signal lines 151, which can serve as the source 181 and drain 182 of the transistor 18 corresponding to the second active sublayer 135. Alternatively, the second active sublayer 135 can be electrically connected to a signal line 151 and a third conductive layer 17, respectively, whereby one of the signal line 151 and the third conductive layer 17 can serve as the source 181 of the transistor 18 corresponding to the second active sublayer 135, and the other can serve as the drain 182 of the corresponding transistor 18.

[0129] Please continue reading. Figure 1 and Figure 2In some optional embodiments, the array substrate 100 further includes a shielding layer 27 disposed on the side of the driving circuit layer 11 facing the substrate 10. The shielding layer 27 is insulated from the driving circuit layer 11. The shielding layer 27 can be used to shield the charge in the substrate 10 to reduce the risk that the charge in the substrate 10 will affect the performance of the driving circuit.

[0130] Optionally, the shielding layer 27 may include a metallic material to improve the charge shielding effect.

[0131] Please see Figure 7 The second aspect of this application provides a method for fabricating an array substrate 100, comprising: S10. A first conductive structure 13 is formed on one side of the substrate 10.

[0132] S20. A first insulating layer 14 is formed on the side of the first conductive structure 13 away from the substrate 10, and at least a portion of the first via K1 is formed in the first insulating layer 14.

[0133] S30. A second conductive layer 15 is formed on the side of the first insulating layer 14 away from the substrate 10. The second conductive layer 15 includes a signal line 151. The signal line 151 is electrically connected to the first conductive structure 13 through a first via K1. A recessed portion K2 is formed on the side of the signal line 151 away from the substrate 10. The orthographic projection of the recessed portion K2 on the substrate 10 and the orthographic projection of the first via K1 on the substrate 10 at least partially overlap.

[0134] S40. A first planarization layer 16 is formed on the side of the second conductive layer 15 away from the substrate 10. The first planarization layer 16 covers at least a portion of the signal line 151 and fills at least a portion of the recess K2.

[0135] S50, a third conductive layer 17 is formed on the side of the first planarization layer 16 away from the substrate 10.

[0136] In these embodiments, a first conductive structure 13 is first formed on one side of the substrate 10, and then a first insulating layer 14 is formed on the side of the first conductive structure 13 away from the substrate 10. The first insulating layer 14 has at least a portion of a first via K1. Then, a second conductive layer 15 is formed on the side of the first insulating layer 14 away from the substrate 10. The second conductive layer 15 includes a signal line 151. The signal line 151 can be electrically connected to the first conductive structure 13 through the first via K1. A recess K2 is formed on the side of the signal line 151 away from the substrate 10. The orthographic projection of the recess K2 on the substrate 10 and the orthographic projection of the first via K1 on the substrate 10 at least partially overlap. Subsequently, a first planarization layer 16 is formed on the side of the second conductive layer 15 away from the substrate 10, such that the first planarization layer 16 covers at least a portion of the signal line 151 and fills at least a portion of the recess K2. Finally, a third conductive layer 17 is formed on the side of the first planarization layer 16 away from the substrate 10. In this process, the arrangement of the first planarization layer 16 can effectively insulate the signal line 151 and the third conductive layer 17 in the recess K2, reducing the risk of the third conductive layer 17 and the signal line 151 coming into contact and short-circuiting in the recess K2, which helps to improve the performance of the array substrate 100.

[0137] Please see Figure 8 In some embodiments, the step of forming a first planarization layer 16 on the side of the second conductive layer 15 facing away from the substrate 10 includes: S41. A first planarization material layer is formed on the side of the second conductive layer 15 away from the substrate 10. The first planarization material layer may include an organic material with good leveling ability, so that the first planarization layer 16 has a flat surface.

[0138] S42. The first planarization material layer is patterned to form the first planarization layer 16.

[0139] In these embodiments, the first planarization material layer can be patterned by processes such as etching and exposure development to form a first planarization layer 16 with a specific pattern.

[0140] Preferably, the substrate 10 includes a first region and a second region, the first region corresponding to the display area AA of the display panel 1000, and the second region corresponding to the non-display area NA of the display panel 1000. The second region may be disposed around the first region.

[0141] The step of patterning the first planarization material layer to form the first planarization layer 16 includes: The first planarization material layer is patterned, and the first planarization material layer in the second region is removed to form the first planarization layer 16 located in the first region.

[0142] In these embodiments, the first planarization layer 16 is formed in the first region. On the one hand, the arrangement of the first planarization layer 16 can reduce the risk of the third conductive layer 17 coming into contact with the signal line 151 and short-circuiting in the first region. On the other hand, since the first planarization layer 16 is not formed in the second region, its space occupation in the second region can be reduced, which helps to improve the space utilization of the second region of the array substrate 100.

[0143] Please see Figure 9 Preferably, the step of patterning the first planarization material layer includes: S421. Pattern the first planarization material layer, remove the first planarization material layer in the second region, and retain the first planarization material layer in the first region.

[0144] S422. The first planarization material layer in the first region is patterned to form the first planarization layer 16.

[0145] In these embodiments, the first planarization material layer can be patterned twice by processes such as etching and exposure development to form a first planarization layer 16 with a specific pattern.

[0146] In some embodiments, in the step of patterning a first planarization material layer in a first region to form a first planarization layer 16, the first planarization layer 16 is disposed as a single layer in the first region.

[0147] The first planarization layer 16, which is integrally disposed in the first region, can not only fill the recess K2, but also effectively insulate the signal line 151 and the third conductive layer 17 without the need to provide other insulating film layers between the signal line 151 and the third conductive layer 17. This helps to simplify the film layer structure in the array substrate 100 and reduce the thickness of the array substrate 100.

[0148] In other embodiments, in the step of patterning the first planarization material layer in the first region to form the first planarization layer 16, the first planarization layer 16 includes a filling portion 163, which fills at least a portion of the recess K2 and covers the portion of the signal line 151 located within the first via K1.

[0149] The filling portion 163 can effectively insulate the signal line 151 located within the first via K1 and the corresponding third conductive layer 17 within the recess K2, thereby reducing the risk of the third conductive layer 17 and the signal line 151 coming into contact and short-circuiting within the recess K2. Furthermore, in this embodiment, the first planarization layer 16 is not required in areas of the array substrate 100 other than the recess K2, thus helping to reduce the thickness of the array substrate 100.

[0150] Optionally, after patterning the first planarization material layer in the first region to form a first planarization layer 16, and the first planarization layer 16 including a filling portion 163 that fills at least a portion of the recess K2 and covers the portion of the signal line 151 located within the first via K1, the method further includes: A seventh insulating layer 19 is formed on the side of the first planarization layer 16 facing away from the substrate 10. The seventh insulating layer 19 can cover the portion of the signal line 151 exposed relative to the fill portion 163. The seventh insulating layer 19 can insulate the signal line 151 located outside the first via K1 and the third conductive layer 17, reducing the risk of the signal line 151 contacting the third conductive layer 17 and short-circuiting.

[0151] Preferably, in the step of patterning the first planarization material layer in the first region to form a first planarization layer 16, and wherein the first planarization layer 16 is disposed as a single layer in the first region, A second via K3 is also formed, which at least penetrates the first planarization layer 16 and the first insulating layer 14 to expose a portion of the first conductive structure 13. This is used to provide electrical connection between the third conductive layer 17 and the first conductive structure 13.

[0152] Preferably, after forming the second via K3, the method further includes: A third conductive layer 17 is formed on the side of the first planarization layer 16 away from the substrate 10. The third conductive layer 17 is electrically connected to the first conductive structure 13 through the second via K3.

[0153] Specifically, the first conductive structure 13 may include a first active sublayer 131, and the driving circuit layer 11 may include a transistor 18. The transistor 18 includes a source 181 and a drain 182, and at least one of the source 181 and the drain 182 may be located in the third conductive layer 17. In the third conductive layer 17, at least one of the source 181 and the drain 182 may be electrically connected to the first active sublayer 131 in the first conductive structure 13 through a second via K3 to form at least a portion of the transistor 18.

[0154] Preferably, after forming the third conductive layer 17 on the side of the first planarization layer 16 opposite to the substrate 10, the method further includes: A second planarization layer 20 is formed on the side of the third conductive layer 17 that is away from the substrate 10.

[0155] The second planarization layer 20 can make the surface of the third conductive layer 17 facing away from the substrate 10 flat, that is, make the surface of the array substrate 100 flat, thereby helping to prepare the light-emitting unit 300 and other film structures of the display panel 1000, and improving the preparation yield and preparation difficulty of the film structure.

[0156] Please see Figure 10 and Figure 11 A third aspect of this application provides a display panel 1000, including an array substrate 100 as described above or an array substrate 100 formed by the above-described preparation method. Since this display panel 1000 employs all the technical solutions of all the above embodiments, it possesses at least all the beneficial effects brought about by the technical solutions of the above embodiments, which will not be elaborated upon here.

[0157] The display panel 1000 provided in this application embodiment can be an organic light-emitting diode (OLED) display panel 1000, or it can be other types of display panels 1000, such as a micro light-emitting diode (Micro-LED) or a quantum light-emitting diode (QLED) display panel 1000.

[0158] like Figure 10 As shown, the display panel 1000 includes a display area AA with display function and a non-display area NA.

[0159] The display area AA of the display panel 1000 can be rectangular, square, circular, oval, or other shapes.

[0160] The display area AA includes a plurality of pixels PX arranged in the X and Y directions. Each pixel PX includes a plurality of sub-pixels SPX displaying different colors. In some embodiments, a pixel PX includes a first sub-pixel SPX1, a second sub-pixel SPX2, and a third sub-pixel SPX3. For example, the first sub-pixel SPX1 is a blue sub-pixel SPX2, the second sub-pixel SPX2 is a green sub-pixel SPX2, and the third sub-pixel SPX3 is a red sub-pixel SPX3. In some embodiments, in addition to sub-pixels SPX1, SPX2, and SPX3, a pixel PX also includes sub-pixels SPX that emit white or other colors of light.

[0161] Sub-pixel SPX includes a pixel PX circuit and a light-emitting unit 300 driven by the pixel PX circuit to emit light of the corresponding color. The first sub-pixel SPX1 includes a first light-emitting unit 300a, the second sub-pixel SPX2 includes a second light-emitting unit 300b, and the third sub-pixel SPX3 includes a third light-emitting unit 300c. One pixel PX circuit drives at least one light-emitting unit 300 to emit light. For example, the display area AA includes a normal display area AA and a light-transmitting display area AA. The light-transmitting display area AA is a display area AA set for a corresponding sensor and having light-transmitting properties, while the normal display area AA is a display area AA not set for a corresponding sensor. In the normal display area AA, one pixel PX circuit drives one light-emitting unit 300 to emit light, and in the light-transmitting display area AA, one pixel PX circuit drives one or more light-emitting units 300 to emit light.

[0162] In one implementation, reference Figure 11 The display panel 1000 includes an array substrate 100, an isolation structure 200, and multiple light-emitting units 300.

[0163] In some embodiments, the isolation structure 200 is disposed on one side of the array substrate 100, and the isolation structure 200 surrounds and forms an isolation opening 210. The isolation structure 200 includes a first isolation portion 220 and a second isolation portion 230 stacked in a direction away from the array substrate 100. The second isolation portion 230 protrudes into the isolation opening 210 relative to the first isolation portion 220. At least a portion of the light-emitting unit 300 is disposed in the isolation opening 210.

[0164] Please see Figure 12 The isolation structure 200 can be enclosed to form multiple isolation openings 210, including multiple first isolation openings 210a, multiple second isolation openings 210b, and multiple third isolation openings 210c. Multiple light-emitting units 300 include multiple first light-emitting units 300a, multiple second light-emitting units 300b, and multiple third light-emitting units 300c. The first light-emitting units 300a are positioned corresponding to the first isolation openings 210a, the second light-emitting units 300b are positioned corresponding to the second isolation openings 210b, and the third light-emitting units 300c are positioned corresponding to the third isolation openings 210c.

[0165] In one embodiment, one light-emitting unit 300 is correspondingly disposed with one isolation opening 210. For example, a first light-emitting unit 300a is correspondingly disposed with a first isolation opening 210a, a second light-emitting unit 300b is correspondingly disposed with a second isolation opening 210b, and a third light-emitting unit 300c is correspondingly disposed with a third isolation opening 210c. At least a portion of the first light-emitting unit 300a is disposed within the corresponding first isolation opening 210a, at least a portion of the second light-emitting unit 300b is disposed within the corresponding second isolation opening 210b, and at least a portion of the third light-emitting unit 300c is disposed within the corresponding third isolation opening 210c. In another embodiment, multiple light-emitting units 300 are correspondingly disposed with one isolation opening 210. For example, multiple light-emitting devices with the same emission color are corresponding to one isolation opening 210.

[0166] Optionally, the first light-emitting unit 300a, the second light-emitting unit 300b, and the third light-emitting unit 300c emit light of different colors respectively; the first light-emitting unit 300a, the second light-emitting unit 300b, and the third light-emitting unit 300c each include a first electrode 310, a light-emitting layer 320, and a second electrode 330 stacked together.

[0167] The second electrodes 330 of the first light-emitting unit 300a, the second light-emitting unit 300b, and the third light-emitting unit 300c respectively cover the corresponding light-emitting layer 320. The second electrodes 330 are electrically connected to the isolation structure 200. For example, the second electrodes 330 are connected to the first isolation portion 220 of the isolation structure 200.

[0168] The first electrode 310 can be an anode, and the second electrode 330 can be a cathode. The first electrode 310 of each light-emitting unit 300 can be connected to the driving circuit through a via, so that the driving circuit drives the light-emitting unit 300 to emit light.

[0169] The isolation structure 200 includes a first isolation portion 220 and a second isolation portion 230 stacked along a direction away from the array substrate 100 (i.e., the Z direction). The width of the second isolation portion 230 is greater than the width of the first isolation portion 220. As a result, the two ends of the second isolation portion 230 protrude from the sides of the first isolation portion 220. This shape of the isolation structure 200 is also referred to as a pendant shape. The pendant isolation structure 200 can separate the light-emitting material into independent light-emitting units 300 in subsequent processes, thereby eliminating the need for a precision mask and helping to reduce the production cost of the display panel 1000.

[0170] The first isolation portion 220 and the second isolation portion 230 are made of different materials, and the etching rate of the second isolation portion 230 can be lower than the etching rate of the first isolation portion 220.

[0171] Optionally, the first electrode 310 may include a multilayer structure, such as a reflective layer and a pair of conductive oxide layers covering the upper and lower surfaces of the reflective layer, respectively. The reflective layer can be formed, for example, using silver, a metallic material with excellent light reflectivity. Each conductive oxide layer can be formed, for example, from a transparent conductive oxide such as ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), or IGZO (Indium Gallium Zinc Oxide). The second electrode 330 is formed, for example, from a metallic material such as an alloy of magnesium and silver (MgAg).

[0172] Please see Figure 13 The light-emitting layer 320 of at least one of the light-emitting devices in the first light-emitting unit 300a, the second light-emitting unit 300b, and the third light-emitting unit 300c includes a hole injection layer HIL, a hole transport layer HTL, an electron blocking layer EBL, a light-emitting material layer EML, a hole blocking layer HBL, an electron transport layer ETL, and an electron injection layer EIL stacked along a direction away from the array substrate 100 (i.e., the Z direction). The light-emitting layer 320 may include a single light-emitting material layer EML, or a stacked light-emitting structure including multiple light-emitting material layers EML.

[0173] In order for the light-emitting layer 320 to emit light, a pixel PX voltage is provided to the first electrode 310 and a common voltage is provided to the second electrode 330, forming a potential difference between the first electrode 310 and the second electrode 330, causing the light-emitting layer 320 disposed between the first electrode 310 and the second electrode 330 to emit light. In one embodiment, if a potential difference is formed between the first electrode 310 and the second electrode 330 of the first light-emitting unit 300a, the light-emitting material layer EML of the light-emitting layer 320 emits blue light; if a potential difference is formed between the first electrode 310 and the second electrode 330 of the second light-emitting unit 300b, the light-emitting material layer EML of the light-emitting layer 320 emits green light; and if a potential difference is formed between the first electrode 310 and the second electrode 330 of the third light-emitting unit 300c, the light-emitting material layer EML of the light-emitting layer 320 emits red light.

[0174] In this configuration, the pixel PX voltage of the first electrode 310 is provided by the pixel PX circuit, and the common voltage of the second electrode 330 is provided by the isolation structure 200. Specifically, the second electrode 330 is electrically connected to the isolation structure 200, and the common voltage is supplied to the second electrode 330 by providing the isolation structure 200. That is, the isolation structure 200 has the function of supplying a common voltage to the second electrode 330.

[0175] Preferably, the orthographic projection of the first planarization layer 16 of the array substrate 100 onto the substrate 10 is located in the display area AA, thereby reducing the space occupied by the first planarization layer 16 in the non-display area NA and helping to improve the space utilization of the non-display area NA.

[0176] In some embodiments, the display panel 1000 may further include a pixel definition layer 400, which includes a pixel defining portion 410 and a plurality of pixel openings 420 formed by the pixel defining portion 410. The pixel openings 420 communicate with the isolation openings 210. At least some of the light-emitting units 300 are located in the corresponding pixel openings 420. The pixel definition layer 400 is made of an inorganic material, such as an inorganic insulating material made of at least one of silicon nitride, silicon oxide, and silicon oxynitride.

[0177] A fourth aspect of this application provides a display device including a display panel 1000 according to any of the above embodiments. Since this display device employs all the technical solutions of all the above embodiments, it possesses at least all the beneficial effects brought about by the technical solutions of the above embodiments, which will not be elaborated upon here.

[0178] The display device can be any device with display function, such as mobile devices such as mobile phones, tablets, laptops, handheld computers, in-vehicle electronic devices, wearable devices, ultra-mobile personal computers (UMPCs), netbooks, or personal digital assistants (PDAs), as well as non-mobile devices such as personal computers (PCs), televisions (TVs), ATMs, or self-service machines.

[0179] While the embodiments disclosed in this application are as described above, the content is merely for the purpose of facilitating understanding of this application and is not intended to limit the invention. Any person skilled in the art to which this application pertains may make any modifications and changes in form and detail of the implementation without departing from the spirit and scope disclosed in this application; however, the scope of protection of this application shall still be determined by the scope defined in the appended claims.

[0180] The above description is merely a specific embodiment of this application. Those skilled in the art will clearly understand that, for the sake of convenience and brevity, substitutions for other connection methods described above can be made by referring to the corresponding processes in the foregoing method embodiments, and will not be repeated here. It should be understood that the scope of protection of this application is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in this application, and these modifications or substitutions should all be covered within the scope of protection of this application.

Claims

1. An array substrate, characterized in that, It includes a substrate and a driving circuit layer, the driving circuit layer including: A first conductive structure is disposed on one side of the substrate; A first insulating layer is disposed on the side of the first conductive structure opposite to the substrate; A second conductive layer is disposed on the side of the first insulating layer away from the substrate. The second conductive layer includes a signal line, which is electrically connected to the first conductive structure through a first via. A recess is formed on the side of the signal line away from the substrate. The orthographic projection of the recess onto the substrate and the orthographic projection of the first via onto the substrate at least partially overlap. A first planarization layer is disposed on the side of the second conductive layer opposite to the substrate. The first planarization layer covers at least a portion of the signal line and fills at least a portion of the recess. A third conductive layer is disposed on the side of the first planarization layer opposite to the substrate.

2. The array substrate according to claim 1, characterized in that, The first planarization layer is a single, continuous layer. Preferably, there are multiple signal lines, and the multiple signal lines are arranged at intervals; Preferably, the first planarization layer comprises an organic insulating material.

3. The array substrate according to claim 1, characterized in that, The first planarization layer includes a filling portion that fills at least a portion of the recess and covers the portion of the signal line located within the first via. Preferably, the array substrate further includes a seventh insulating layer that covers the portion of the signal line exposed relative to the filling portion; Preferably, the seventh insulating layer further covers the filling portion; Preferably, the filling portion comprises an organic insulating material; Preferably, the seventh insulating layer comprises an inorganic insulating material.

4. The array substrate according to any one of claims 1-3, characterized in that, The driving circuit layer further includes a transistor, which includes a source and a drain, and at least one of the source and drain is located in the third conductive layer. Preferably, the third conductive layer is electrically connected to the first conductive structure through a second via, wherein the second via at least penetrates the first planarization layer and the first insulating layer.

5. The array substrate according to claim 4, characterized in that, The first conductive structure includes multiple sub-layers, which are stacked in a direction away from the substrate. Adjacent sub-layers are insulated from each other, and the signal line is electrically connected to at least one sub-layer through the first via. Preferably, the first conductive structure includes at least one of a first active sublayer, a first metal sublayer, a second metal sublayer, a third metal sublayer, a second active sublayer, and a fourth metal sublayer.

6. The array substrate according to claim 5, characterized in that, The first conductive structure includes a first active sublayer and a first metal sublayer disposed on the side of the first active sublayer facing away from the substrate. The first metal sublayer includes a first gate, and the orthographic projection of the first gate on the substrate at least partially overlaps with the orthographic projection of the first active sublayer on the substrate. Preferably, the first metal sublayer further includes a first capacitor plate; Preferably, the first gate is reused as the first capacitor plate; Preferably, the array substrate further includes a second insulating layer, which is stacked between the first active sublayer and the first metal sublayer.

7. The array substrate according to claim 6, characterized in that, Some of the signal lines are electrically connected to the first active sublayer through the first via, and the corresponding first via at least penetrates the first insulating layer and the second insulating layer; and / or, Some of the signal lines are electrically connected to the first metal sublayer through the first via, and the corresponding first via at least penetrates the first insulating layer; Preferably, the signal line electrically connected to the first active sublayer forms the source or drain of the transistor corresponding to the first active sublayer; Preferably, the third conductive layer is electrically connected to the first active sublayer through the second via, and the corresponding second via at least penetrates the first planarization layer, the first insulating layer, and the second insulating layer; Preferably, a connecting electrode is provided between the third conductive layer and the first active sublayer, and the third conductive layer is electrically connected to the first active sublayer through the connecting electrode.

8. The array substrate according to claim 6, characterized in that, The first conductive structure further includes a second metal sublayer disposed on the side of the first metal sublayer facing away from the substrate. The second metal sublayer includes a second capacitor plate. The orthographic projection of the first capacitor plate on the substrate and the orthographic projection of the second capacitor plate on the substrate at least partially overlap. Preferably, the array substrate further includes a third insulating layer, which is stacked between the first metal sublayer and the second metal sublayer; Preferably, the third conductive layer is electrically connected to the first active sublayer through the second via, and the corresponding second via at least penetrates the first planarization layer, the first insulating layer, the second insulating layer and the third insulating layer; Preferably, a portion of the signal lines are electrically connected to the second metal sublayer through the first via, and the corresponding first via at least penetrates the first insulating layer.

9. The array substrate according to claim 8, characterized in that, The first conductive structure further includes a third metal sublayer disposed on the side of the second metal sublayer facing away from the substrate. The third metal sublayer includes a third capacitor plate, and the orthographic projection of the third capacitor plate on the substrate at least partially overlaps with the orthographic projection of the second capacitor plate on the substrate. Preferably, the third metal sublayer further includes a connecting electrode, and the third conductive layer is electrically connected to the first active sublayer through the connecting electrode; Preferably, the array substrate further includes a fourth insulating layer disposed between the second metal sublayer and the third metal sublayer; Preferably, the second via used to connect the third conductive layer and the first active sublayer also penetrates the fourth insulating layer.

10. The array substrate according to claim 5, characterized in that, The first conductive structure further includes a second active sublayer and a fourth metal sublayer disposed on the side of the second active sublayer facing away from the substrate. The fourth metal sublayer includes a second gate, and the orthographic projection of the second gate on the substrate at least partially overlaps with the orthographic projection of the second active sublayer on the substrate. Preferably, the array substrate further includes a fifth insulating layer, which is disposed between the second active sub-layer and the fourth metal sub-layer; Preferably, the second active sublayer is located on the side of the third metal sublayer facing away from the substrate, and the array substrate further includes a sixth insulating layer disposed between the third metal sublayer and the second active sublayer.

11. The array substrate according to claim 10, characterized in that, Some of the signal lines are electrically connected to the second active sublayer through the first via, and the corresponding first via at least penetrates the first insulating layer and the fifth insulating layer; Preferably, the signal line electrically connected to the second active sublayer forms the source or drain of the transistor corresponding to the second active sublayer.

12. A method for fabricating an array substrate, characterized in that, include: A first conductive structure is formed on one side of the substrate; A first insulating layer is formed on the side of the first conductive structure opposite to the substrate, and the first insulating layer has at least a portion of a first via. A second conductive layer is formed on the side of the first insulating layer away from the substrate. The second conductive layer includes a signal line. The signal line is electrically connected to the first conductive structure through the first via. A recess is formed on the side of the signal line away from the substrate. The orthographic projection of the recess on the substrate and the orthographic projection of the first via on the substrate at least partially overlap. A first planarization layer is formed on the side of the second conductive layer opposite to the substrate. The first planarization layer covers at least a portion of the signal line and fills at least a portion of the recess. A third conductive layer is formed on the side of the first planarization layer that is away from the substrate.

13. The preparation method according to claim 12, characterized in that, The step of forming a first planarization layer on the side of the second conductive layer opposite to the substrate includes: A first planarization material layer is formed on the side of the second conductive layer that is away from the substrate; The first planarization material layer is patterned to form the first planarization layer; Preferably, the substrate includes a first region and a second region, the first region being used for the display area of ​​the corresponding display panel, and the second region being used for the non-display area of ​​the corresponding display panel; The step of patterning the first planarization material layer to form the first planarization layer includes: The first planarization material layer is patterned, and the first planarization material layer in the second region is removed to form the first planarization layer located in the first region. Preferably, the step of patterning the first planarization material layer includes: The first planarization material layer is patterned, the first planarization material layer in the second region is removed, and the first planarization material layer in the first region is retained; The first planarization material layer in the first region is patterned to form the first planarization layer; Preferably, in the step of patterning the first planarization material layer in the first region to form the first planarization layer, the first planarization layer is disposed as a single layer in the first region, or... The first planarization layer includes a filling portion that fills at least a portion of the recess and covers the portion of the signal line located within the first via. Preferably, in the step of patterning the first planarization material layer in the first region to form the first planarization layer, and wherein the first planarization layer is disposed as a single layer in the first region, A second via is also formed, which at least penetrates the first planarization layer and the first insulating layer to expose a portion of the first conductive structure; Preferably, after forming the second via, the method further includes: A third conductive layer is formed on the side of the first planarization layer opposite to the substrate, and the third conductive layer is electrically connected to the first conductive structure through the second via.

14. A display panel, characterized in that, The array substrate includes the array substrate as described in any one of claims 1-11 or the array substrate prepared by the preparation method described in claim 12 or 13.

15. The display panel according to claim 14, characterized in that, The display panel also includes: An isolation structure is disposed on one side of the array substrate, the isolation structure encloses and forms an isolation opening, the isolation structure includes a first isolation portion and a second isolation portion stacked in a direction away from the array substrate, the second isolation portion protruding into the isolation opening relative to the first isolation portion; A light-emitting unit, at least a portion of which is located within the isolation opening; Preferably, the display panel includes a display area, and the orthographic projection of the first planarization layer of the array substrate onto the substrate is located in the display area.

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