Analog-to-digital (AD) converter, imaging apparatus, and control method of AD converter

Abstract

The present invention increases the speed of a successive comparison type AD converter while suppressing an increase in circuit size. An AD (analog-to-digital) converter is provided with a first DAC (digital-to-analog converter), a second DAC, and a comparison unit. The first DAC has a capacitor that holds a first input signal during a first sampling period. The second DAC has a capacitor that holds a second input signal during a second sampling period. The comparison unit is connected to the first DAC and the second DAC.

Description

TECHNICAL FIELD

[0001] The present technology relates to an AD converter. More specifically, the present technology relates to a successive approximation type AD converter, an imaging device, and a control method of an AD converter. BACKGROUND

[0002] A successive approximation type register analog-digital converter (SAR ADC) is widely used in various electronic devices due to its high resolution and low power consumption. For example, an AD converter of a time-interleaved manner equipped with a plurality of SAR ADCs that perform sampling at different times has been proposed (for example, see Non-Patent Literature 1).

[0003] LIST OF CITATIONS

[0004] NON-PATENT LITERATURE

[0005] Non-Patent Literature 1: Yuan Zhou et al., A 12-b 1-GS / s 31.5-mW Time- Interleaved SAR ADC With Analog HPF-Assisted Skew Calibration and Randomly Sampling Reference ADC, IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 54, NO. 8, AUGUST 2019. SUMMARY

[0006] PROBLEMS TO BE SOLVED BY THE INVENTION

[0007] The above related technology adopts a time-interleaved manner to improve the speed of AD conversion. However, the above related technology requires a plurality of SAR ADCs, which results in an increase in circuit size compared to a case where the time-interleaved manner is not adopted. When only one SAR ADC is provided, the circuit size can be reduced, but the speed improvement cannot be achieved using the time-interleaved manner. As described above, the above related technology has difficulty in achieving speed improvement while suppressing an increase in circuit size.

[0008] The present technology is proposed in view of such a situation, and therefore an object of the present technology is to improve the speed of a successive approximation type AD converter while suppressing an increase in circuit size.

[0009] SOLUTION TO PROBLEM

[0010] The present technology has been made in order to solve the above problems, and according to a first aspect of the present technology, there is provided an AD converter and a control method of an AD converter, the AD converter including: a first digital-to-analog converter (DAC) having a capacitor that holds a first input signal during a first sampling period; a second DAC connected in parallel to the first DAC and having a capacitor that holds a second input signal during a second sampling period; and a comparison unit connected to the first DAC and the second DAC. This brings about an effect of suppressing an increase in circuit size while achieving an improvement in speed.

[0011] Further, in the first aspect, a single-ended-differential conversion circuit that converts the first single-ended signal to a first differential signal and converts the second single-ended signal to a second differential signal, a first sample-and-hold switch that supplies the first differential signal as the first input signal to the first DAC during the first sampling period, and a second sample-and-hold switch that supplies the second differential signal as the second input signal to the second DAC during the second sampling period can be further included. This brings about an effect of AD-converting differential signals.

[0012] Further, in the first aspect, a first sample-and-hold switch that supplies the first single-ended signal as the first input signal to the first DAC during the first sampling period, a second sample-and-hold switch that supplies the second single-ended signal as the second input signal to the second DAC during the second sampling period, a shared DAC, a first single-ended-differential conversion circuit that converts the first input signal to a differential signal and supplies the differential signal to the first DAC and the shared DAC during an interval between an end of the first sampling period and a start of the second sampling period, and a second single-ended-differential conversion circuit that converts the second input signal to a differential signal and supplies the differential signal to the second DAC and the shared DAC during an interval between an end of the second sampling period and a start of the first sampling period can be further included. This brings about an effect of reducing the number of DACs.

[0013] Further, in the first aspect, a first sample-and-hold switch that supplies the first single-ended signal and a reference signal as the first input signal to the first DAC during the first sampling period, and a second sample-and-hold switch that supplies the second single-ended signal and the reference signal as the second input signal to the second DAC during the second sampling period can be further included.

[0014] Further, in the first aspect, a logic circuitry can be included which generates a second control signal based on a comparison result of the comparison unit during a first sampling period and generates a first control signal based on a comparison result of the comparison unit during a second sampling period, wherein the first DAC generates a pair of first analog signals based on the first control signal and the first input signal during the second sampling period, the second DAC generates a pair of second analog signals based on the second control signal and the second input signal during the first sampling period, and the comparison unit sequentially compares the pair of first analog signals and the pair of second analog signals. This brings an effect of performing sampling and AD conversion in parallel.

[0015] Further, in the first aspect, a first enable switch can be included which supplies the pair of first analog signals to the comparison unit during the second sampling period, and a second enable switch can be included which supplies the pair of second analog signals to the comparison unit during the first sampling period. This brings an effect of being able to switch signals input to the comparison unit.

[0016] Further, in the first aspect, the first DAC can supply the pair of first analog signals to the comparison unit, the second DAC can supply the pair of second analog signals to the comparison unit, and the comparison unit can select either the pair of second analog signals or the pair of first analog signals according to a predetermined enable signal and compare them. This brings an effect of reducing switches on the input side of the comparison unit.

[0017] Further, in the first aspect, a third DAC can be included which is connected in parallel to the first DAC and the second DAC and has a capacitor which holds a third input signal during a third sampling period.

[0018] Further, according to a second aspect of the present technology, there is provided an imaging device including: a pixel array unit including a plurality of pixels each outputting a pixel signal; and an AD converter inputting the pixel signal from the pixel array unit, wherein the AD converter includes: a first DAC having a capacitor which holds a first input signal during a first sampling period; a second DAC connected in parallel to the first DAC and having a capacitor which holds a second input signal during a second sampling period, and a comparison unit connected to the first DAC and the second DAC. This brings an effect of suppressing an increase in circuit size when improving an AD conversion speed in an imaging device. BRIEF DESCRIPTION OF DRAWINGS

[0019] Figure 1 is a block diagram showing a configuration example of an imaging device according to the first embodiment of the present technology.

[0020] Figure 2 is a block diagram showing a configuration example of a solid-state imaging device according to the first embodiment of the present technology.

[0021] Figure 3 is a block diagram showing a configuration example of a pixel according to the first embodiment of the present technology.

[0022] Figure 4 is a block diagram showing a configuration example of a column signal processing unit according to the first embodiment of the present technology.

[0023] Figure 5 is a block diagram showing a configuration example of a column signal processing unit according to the first embodiment of the present technology, which further includes a sample-and-hold circuit and a column amplifier.

[0024] Figure 6 is a block diagram showing a configuration example of a SAR ADC according to the first embodiment of the present technology.

[0025] Figure 7 is a block diagram showing a configuration example of a control unit according to the first embodiment of the present technology.

[0026] Figure 8 is a circuit diagram showing a configuration example of a comparison unit according to the first embodiment of the present technology.

[0027] Figure 9 is a timing chart showing an operation example of a SAR ADC according to the first embodiment of the present technology.

[0028] Figure 10 shows an example of a block diagram and a timing chart of a SAR ADC according to a first comparative example.

[0029] Figure 11 is a block diagram showing a configuration example of an AD converter according to a second comparative example.

[0030] Figure 12 is a timing chart showing an operation example of an AD converter according to the second comparative example.

[0031] Figure 13 is a flowchart showing an operation example of a solid-state imaging device according to the first embodiment of the present technology.

[0032] Figure 14 is a block diagram showing a configuration example of a SAR ADC according to the second embodiment of the present technology.

[0033] Figure 15 is a block diagram showing a configuration example of a control unit according to the second embodiment of the present technology.

[0034] Figure 16 is a timing chart showing an operation example of a SAR ADC according to the second embodiment of the present technology.

[0035] Figure 17This is a block diagram illustrating a configuration example of a SARADC according to a third embodiment of the present technology.

[0036] Figure 18 This is a block diagram illustrating a configuration example of a SARADC where CDAC control is unilateral according to a third embodiment of the present technology.

[0037] Figure 19 This is a block diagram illustrating a configuration example of a SARADC according to a fourth embodiment of the present technology.

[0038] Figure 20 This is a block diagram illustrating an example configuration of a control unit according to a fourth embodiment of the present technology.

[0039] Figure 21 This is a circuit diagram illustrating an example configuration of a comparison unit according to the fourth embodiment of the present technology.

[0040] Figure 22 This is a block diagram illustrating an example of the configuration of a column signal processing unit according to a fifth embodiment of the present technology.

[0041] Figure 23 This is a block diagram illustrating a configuration example of a SARADC according to a fifth embodiment of the present technology.

[0042] Figure 24 This is a timing diagram illustrating an operational example of a SARADC according to a fifth embodiment of the present technology. Detailed Implementation

[0043] The following describes the form (hereinafter referred to as the implementation scheme) used to implement this technology. The description will be given in the following order.

[0044] 1. First implementation scheme (an example of two systems' DACs connected in parallel)

[0045] 2. Second implementation scheme (an example in which the DACs of the two systems are connected in parallel and perform single-ended to differential conversion after sampling)

[0046] 3. Third implementation scheme (an example in which the DACs of the two systems are connected in parallel and configured for single-ended input)

[0047] 4. Fourth implementation scheme (an example in which the DACs of the two systems are connected in parallel and the enable switch on the input side of the comparator unit is eliminated)

[0048] 5. Fifth Implementation Scheme (Example of three systems with DACs connected in parallel)

[0049] <1. First Implementation Plan>

[0050] [Example of Imaging Device Configuration]

[0051] Figure 1 This is a block diagram illustrating an example configuration of an imaging device 100 according to a first embodiment of the present technology. The imaging device 100 is a device for capturing image data and includes an optical system 110, a solid-state imaging element 200, an image processing unit 120, a memory 130, an imaging control unit 140, and a monitor 150. Possible examples of the imaging device 100 include Internet of Things (IoT) cameras, vehicle cameras, etc.

[0052] The optical system 110 collects light from the subject and directs the light to the solid-state imaging element 200. The optical system 110 includes at least one optical lens.

[0053] The solid-state imaging element 200 captures image data under the control of the imaging control unit 140. The solid-state imaging element 200 supplies the captured image data to the image processing unit 120 via signal line 209.

[0054] The imaging control unit 140 controls the solid-state imaging element 200. The imaging control unit 140 supplies signals such as a vertical synchronization signal instructing image capture timing and a signal for controlling exposure time to the solid-state imaging element 200 via signal line 149. Furthermore, for example, when an operation to start image capture is performed (such as pressing the shutter button), the imaging control unit 140 begins supplying the vertical synchronization signal.

[0055] Image processing unit 120 performs predetermined image processing on image data, such as depigmentation and white balance adjustment. Image processing unit 120 supplies the processed image data to memory 130 and monitor 150 via signal lines 128 and 129. Memory 130 stores the image data. Monitor 150 displays the image data.

[0056] [Example of solid-state imaging element configuration]

[0057] Figure 2 This is a block diagram illustrating an example of the configuration of a solid-state imaging element 200 according to a first embodiment of the present technology. The solid-state imaging element 200 includes a sensor chip 201 and a circuit chip 202 stacked on the sensor chip 201.

[0058] The sensor chip 201 includes a pixel array unit 220, which comprises a plurality of pixels 230 arranged in a two-dimensional grid pattern. Furthermore, the circuit chip 202 includes a vertical drive circuit 210, a column signal processing unit 240, a timing control circuit 250, and an output circuit 260.

[0059] The vertical drive circuit 210 drives the pixel 230 to output pixel signals to the column signal processing unit 240. The column signal processing unit 240 performs AD conversion processing on the pixel signals for each column and supplies the resulting data to the output circuit 260. The output circuit 260 performs correlated double sampling (CDS) processing, etc., on the data received from the column signal processing unit 240 and outputs the resulting data to the image processing unit 120. Furthermore, in addition to CDS processing, the output circuit 260 also performs autofocus (AF) processing as needed to detect focus based on the contrast of the image data.

[0060] The timing control circuit 250 controls the operation timing of each of the vertical drive circuit 210, column signal processing unit 240 and output circuit 260 synchronously with the vertical synchronization signal.

[0061] Note that in the solid-state imaging element 200, the above-mentioned circuit is configured on two stacked chips, but the technology is not limited to this configuration, and the circuit can be configured on a single semiconductor chip.

[0062] [Example of pixel circuit configuration]

[0063] Figure 3 This is a circuit diagram illustrating an example of the configuration of pixel 230 according to a first embodiment of the present technology. Pixel 230 includes a photodiode 231, a transmission transistor 232, a reset transistor 233, a floating diffusion layer 234, an amplification transistor 235, and a selection transistor 236.

[0064] The photodiode 231 converts received light into electrical charge. The photodiode 231 is disposed on the back side of the semiconductor substrate, opposite to the front side of the circuitry. This type of solid-state imaging element is called a back-illuminated solid-state imaging element. Note that a front-illuminated configuration with the photodiode 231 disposed on the front side can also be used instead of a back-illuminated configuration.

[0065] The transfer transistor 232 transfers charge from the photodiode 231 to the floating diffusion layer 234 according to the transfer signal TRG received from the vertical drive circuit 210. The floating diffusion layer 234 accumulates the transferred charge and generates a voltage corresponding to the accumulated charge level.

[0066] Reset transistor 233 extracts charge from floating diffusion layer 234 to reset the charge level based on reset signal RST received from vertical drive circuit 210. Amplification transistor 235 amplifies the voltage of floating diffusion layer 234. Selection transistor 236 outputs the amplified voltage signal as pixel signal AIN to column signal processing unit 240 via vertical signal line VSL based on selection signal SEL received from vertical drive circuit 210.

[0067] Note that the circuit configuration of pixel 230 is not limited to the configuration shown in the figure; it can be used as long as it can generate pixel signals through photoelectric conversion.

[0068] [Example of a column signal processing unit]

[0069] Figure 4 This is a block diagram illustrating an example configuration of a column signal processing unit 240 according to a first embodiment of the present invention. Furthermore, in the column signal processing unit 240, one SARADC 300 is configured for each group of vertical signal lines. Assuming four SARADCs 300 and 4×C (where C is an integer) columns, each SARADC 300 is connected to C columns. Additionally, a vertical signal line VSL is configured for each column, and a switch 243 is configured for each column to open and close the path between the corresponding SARADC 300 and the vertical signal line VSL. For example, vertical signal lines VSL_1 and VSL_5 are connected to the first SARADC 300 via switch 243.

[0070] For example, whenever a row is selected, the vertical drive circuit 210 outputs the pixel signal AIN for the selected row. The timing control circuit 250 controls the four corresponding switches 243 to be closed, inputting the corresponding VSL signals to the SARADC 300. Pixel signals input to the SARADC 300 on odd-numbered lines (e.g., signals from vertical signal line VSL_1) are denoted as AIN1, and pixel signals input on even-numbered lines (e.g., signals from vertical signal line VSL_5) are denoted as AIN2. The SARADC 300 sequentially performs AD conversion on AIN1 and AIN2, and outputs the resulting signals as the digital signal DOUT to the output circuit 260.

[0071] Note that although four SARADC 300s are configured in the diagram, the actual number of SARADC 300s is arbitrary and not limited to four. Furthermore, as... Figure 5 As shown, a sample-and-hold circuit 241 and a column amplifier 242 can be further configured for each column. In this case, the sample-and-hold circuit 241 performs sampling and holding on the pixel signal AIN received from the corresponding vertical signal line VSL, the column amplifier 242 amplifies the pixel signal AIN received from the sample-and-hold circuit 242, and supplies the amplified pixel signal AIN to the switch 243.

[0072] [Example of SARADC configuration]

[0073] Figure 6This is a block diagram illustrating an example configuration of a SARADC 300 according to a first embodiment of the present invention. The SARADC 300 includes a single-ended to differential conversion circuit 340, sample-and-hold switches 311, 312, 321, and 322, and enable switches 313, 314, 323, and 324. Furthermore, the SARADC 300 also includes capacitor digital-to-analog converters (CDACs) 411, 412, 421, and 422, and a control unit 500. Note that the SARADC 300 is an example of the AD converter described in the claims.

[0074] In the following text, the CDACs 411 and 412 for AD conversion of pixel signal AIN1 and the control unit 500 are referred to as the "first system". Furthermore, the CDACs 421 and 422 for AD conversion of pixel signal AIN2 and the control unit 500 are referred to as the "second system". The control unit 500 is shared between the first system and the second system.

[0075] The pixel signal AIN (AIN1 or AIN2), as a single-ended signal, is input from pixel array unit 220 to single-ended differential conversion circuit 340 via vertical signal line VSL. Single-ended differential conversion circuit 340 converts the pixel signal AIN into a differential signal. The differential signal contains a positive signal AINp and a negative signal AINn. The differential signals corresponding to AIN1 are represented as AINp1 and AINn1, and the differential signals corresponding to AIN2 are represented as AINp2 and AINn2. Furthermore, the capacitor shown by the dashed line in the figure represents the parasitic capacitance caused by the wiring load of the vertical signal line VSL.

[0076] Note that pixel signal AIN1 is an example of the first single-ended signal described in the claims, and pixel signal AIN2 is an example of the second single-ended signal described in the claims.

[0077] The sample-and-hold switch 311 opens and closes the path between the single-ended to differential converter circuit 340 and the CDAC 411 of the first system according to the control signal SH_SW1 received from the timing control circuit 250. The control signal SH_SW1 is a signal indicating the sampling period of the first system; for example, during the sampling period, the control signal SH_SW1 is controlled to be high. During the sampling period of the first system, the sample-and-hold switch 311 inputs the positive signal AINp1 as an input signal to the CDAC 411.

[0078] The sample-and-hold switch 312 opens and closes the path between the single-ended to differential converter circuit 340 and the CDAC 412 of the first system according to the control signal SH_SW1. During the sampling period of the first system, the sample-and-hold switch 312 inputs the negative signal AINn1 as an input signal to the CDAC 412.

[0079] The sample-and-hold switch 321 opens and closes the path between the single-ended to differential converter circuit 340 and the CDAC 421 of the second system according to the control signal SH_SW2 received from the timing control circuit 250. The control signal SH_SW2 is a signal indicating the sampling period of the second system; for example, during the sampling period, the control signal SH_SW2 is controlled to be high. The sampling period of the second system does not overlap with the sampling period of the first system. During the sampling period of the second system, the sample-and-hold switch 321 inputs the positive signal AINp2 as an input signal to the CDAC 421.

[0080] The sample-and-hold switch 322 opens and closes the path between the single-ended to differential converter circuit 340 and the CDAC 422 of the second system according to the control signal SH_SW2. During the sampling period of the second system, the sample-and-hold switch 322 inputs the negative signal AINn2 as an input signal to the CDAC 422.

[0081] CDACs 411, 412, 421, and 422 generate analog signals through digital-to-analog (DA) conversion and also serve as capacitors to hold the input signal.

[0082] CDACs 411 and 412 hold the input signals AINp1 and AINn1 received from sample-and-hold switches 311 and 312. Subsequently, by turning on enable switches 313 and 314 corresponding to AD1_EN, the control unit 500 performs a comparison operation and supplies control signals CTLp1 and CTLn1 based on the comparison result to CDACs 411 and 421, performing an AD conversion on AIN1. CDAC 411 outputs the positive differential signal INP1, and CDAC 412 outputs the negative differential signal INN1. Control signals CTLp1 and CTLn1 are digital signals, while INP1 and INN1 are analog signals.

[0083] Note that CDACs 411 and 412 are examples of the first DACs described in the claims. AINp1 and AINn1 are examples of the first input signals described in the claims. INP1 and INN1 are examples of a pair of first analog signals described in the claims. Control signals CTLp1 and CTLn1 are examples of the first control signals described in the claims.

[0084] CDACs 421 and 422 hold the input signals AINp2 and AINn2 received from sample-and-hold switches 321 and 322. Subsequently, by turning on enable switches 323 and 324 corresponding to AD2_EN, the control unit 500 performs a comparison operation and supplies control signals CTLp2 and CTLn2 based on the comparison result to CDACs 421 and 422, performing an AD conversion on AIN2. CDAC 421 outputs the positive differential signal INP2, and CDAC 422 outputs the negative differential signal INN2. Control signals CTLp2 and CTLn2 are digital signals, while INP2 and INN2 are analog signals.

[0085] Note that CDACs 421 and 422 are examples of the second DACs described in the claims. AINp2 and AINn2 are examples of the second input signals described in the claims. INP2 and INN2 are examples of a pair of second analog signals described in the claims. Control signals CTLp2 and CTLn2 are examples of the second control signals described in the claims.

[0086] Enable switch 313 opens and closes the path between CDAC 411 and control unit 500 based on the enable signal AD1_EN received from timing control circuit 250. Enable signal AD1_EN indicates the period during which successive comparisons of the differential signal are performed in the first system. For example, during the sampling period of the second system, enable signal AD1_EN is controlled to be high to perform successive comparisons in the first system during this period. Enable switch 313 allows the positive signal INP1 to be supplied from CDAC 411 to control unit 500 during the sampling period of the second system.

[0087] Enable switch 314 opens and closes the path between CDAC 412 and control unit 500 according to the enable signal AD1_EN. Enable switch 314 allows the negative signal INN1 to be supplied from CDAC 412 to control unit 500 during the sampling period of the second system.

[0088] Enable switch 323 opens and closes the path between CDAC 421 and control unit 500 based on the enable signal AD2_EN received from timing control circuit 250. Enable signal AD2_EN indicates the period during which successive comparisons of the differential signal are performed in the second system. For example, during the sampling period of the first system, enable signal AD2_EN is controlled to be high to enable successive comparisons in the second system during this period. Enable switch 323 allows the positive signal INP2 to be supplied from CDAC 421 to control unit 500 during the sampling period of the first system.

[0089] Enable switch 324 opens and closes the path between CDAC 422 and control unit 500 according to the enable signal AD2_EN. Enable switch 324 allows the negative signal INN2 to be supplied from CDAC 422 to control unit 500 during the sampling period of the first system.

[0090] Control unit 500 compares the positive signal INP (INP1 or INP2) with the negative signal INN (INN1 or INN2) and controls the level of the reference signal based on the comparison result. Control unit 500 generates control signals CTLp1 and CTLn1 based on the comparison result between the positive and negative signals INP1, and supplies control signals CTLp1 and CTLn1 to CDACs 411 and 412. Furthermore, control unit 500 generates control signals CTLp2 and CTLn2 based on the comparison result between the positive and negative signals INP2, and supplies control signals CTLp2 and CTLn2 to CDACs 421 and 422.

[0091] As described above, the sampling period of the first system does not overlap with the sampling period of the second system. Successive comparisons of the first system are performed during the sampling period of the second system, and successive comparisons of the second system are performed during the sampling period of the first system. Therefore, CDACs 411 and 412 generate INP1 and INN1 during the sampling period of the second system based on AINp1 and AINn1 held during the sampling period of the first system and control signals CTLp1 and CTLn1.

[0092] On the other hand, CDACs 421 and 422 generate INP2 and INN2 during the sampling period of the first system based on AINp2 and AINn2 held during the sampling period of the second system and control signals CTLp2 and CTLn2.

[0093] Furthermore, the control unit 500 generates control signals CTLp2 and CTLn2 during the sampling period of the first system based on the comparison result between INP2 and INN2 of the second system. Additionally, the control unit 500 generates control signals CTLp1 and CTLn1 during the sampling period of the second system based on the comparison result between INP1 and INN1 of the first system.

[0094] Note that the SARADC 300 shown in the figure can also be used in circuits other than the solid-state imaging element 200, such as communication circuits in Internet of Things (IoT) systems. However, in this case, input signal errors caused by timing errors in the switching between the sample-and-hold switches of the first and second systems may cause problems. On the other hand, when the SARADC 300 is used in a solid-state imaging element 200 such as a CMOS image sensor (CIS), the VSL signal does not have frequency-dependent characteristics, so timing errors do not cause significant problems.

[0095] Figure 7 This is a block diagram illustrating an example configuration of a control unit 500 according to a first embodiment of the present invention. The control unit 500 includes a comparison unit 510, AND gates 551, 552, 561 and 562, and SAR logic circuitry 580.

[0096] The comparison unit 510 compares the positive signal INP (INP1 or INP2) with the negative signal INN (INN1 or INN2) synchronously with the clock signal CLK, and supplies the comparison result to the SAR logic circuit 580.

[0097] SAR logic circuit 580 stores the comparison result received from comparison unit 510 and controls the level of the reference signal based on the comparison result. SAR logic circuit 580 updates the level of the reference signal using a successive comparison method, so that the outputs of CDAC 411 (or CDAC 421) and CDAC 412 (or CDAC 422) are balanced. SAR logic circuit 580 generates control signals CTLp and CTLn for updating and outputs them to the respective AND gates. Furthermore, assuming that SARADC 300 has an M-bit resolution (where M is an integer), successive comparisons are performed M times. SAR logic circuit 580 holds the comparison results of M times and supplies a bit string containing bits indicating the comparison results as a digital signal DOUT to the output circuit.

[0098] Note that SAR logic circuit 580 is an example of the logic circuit described in the claims.

[0099] Assuming each control signal CTLp and CTLn has K bits (where K is an integer), then each of the AND gates 551, 552, 561, and 562 consists of K bits. For clarity, the AND gates corresponding to the second and subsequent bits are omitted from the diagram.

[0100] The k-th AND gate 551 (where k is an integer from 1 to K) outputs the logical AND of the k-th bit of the control signal CTLp and the enable signal AD1_EN as the k-th bit of CTLp1 to CDAC 411.

[0101] The k-th AND gate 552 outputs the logical AND of the k-th bit of the control signal CTLn and the enable signal AD1_EN as the k-th bit of CTLn1 to CDAC 412.

[0102] The k-th AND gate 561 outputs the logical AND of the k-th bit of the control signal CTLp and the enable signal AD2_EN as the k-th bit of CTLp2 to CDAC 421.

[0103] The k-th AND gate 562 outputs the logical AND of the k-th bit of the control signal CTLn and the enable signal AD2_EN as the k-th bit of CTLn2 to CDAC 422.

[0104] [Example of the structure of a comparison unit]

[0105] Figure 8 This is a block diagram illustrating an example configuration of a comparison unit 510 according to a first embodiment of the present invention. The comparison unit 510 includes p-channel metal-oxide-semiconductor (pMOS) transistors 531 and 532, n-channel MOS (nMOS) transistors 511, 512 and 513, and a latch 550.

[0106] pMOS transistors 531 and 532 are connected in parallel with the node at the power supply potential VDD.

[0107] A positive signal INP is input to the gate of nMOS transistor 511, and the drain of nMOS transistor 511 is connected to pMOS transistor 531. A negative signal INN is input to the gate of nMOS transistor 512, and the drain of nMOS transistor 512 is connected to pMOS transistor 532. The sources of nMOS transistors 511 and 512 are commonly connected to nMOS transistor 513. nMOS transistor 513 is interposed between the node commonly connected to nMOS transistors 511 and 512 and the node at ground.

[0108] In addition, the clock signal CLK is input to the gates of pMOS transistors 531 and 532 and the gate of nMOS transistor 513.

[0109] The node connecting pMOS transistor 531 and nMOS transistor 511 is connected to the positive input terminal of latch 550, and the node connecting pMOS transistor 532 and nMOS transistor 512 is connected to the negative input terminal of latch 550. Latch 550 outputs output signals OUTP and OUTN to SAR logic circuit 580, representing the comparison result of the input differential signals.

[0110] Using the circuit shown in the figure, the positive signal INP and the negative signal INN are compared synchronously with the clock signal CLK.

[0111] [SARADC Operation Example]

[0112] Figure 9 This is a timing diagram illustrating an operational example of the SARADC 300 according to a first embodiment of the present technology. During the first system sampling period from time T1 to time T2, the timing control circuit 250 sets the control signal SH_SW1 to a high level. Furthermore, during this period, the timing control circuit 250 sets the enable signal AD2_EN to a high level. On the other hand, the control signal SH_SW2 and the enable signal AD1_EN are controlled to a low level.

[0113] Through this control, CDACs 411 and 412 of the first system sample and hold the input signals. Meanwhile, comparison unit 510 performs successive comparisons of the second system synchronously with clock signal CLK. During this period, for example, pixel signals from vertical signal lines VSL_1 to VSL_4 are read out.

[0114] The timing control circuit 250 sets the control signal SH_SW2 to a high level during the sampling period of the second system from time T3 to time T4, which immediately follows time T2. Furthermore, the timing control circuit 250 sets the enable signal AD1_EN to a high level during this period. On the other hand, the control signal SH_SW1 and the enable signal AD2_EN are controlled to a low level at time T2.

[0115] Through this control, the CDACs 421 and 422 of the second system sample and hold the input signals. Meanwhile, the comparison unit 510 performs successive comparisons of the first system synchronously with the clock signal CLK. During this period, for example, the pixel signals of the vertical signal lines VSL_5 to VSL_8 are read out.

[0116] Similarly, after time T4, sampling of the first system and sampling of the second system are performed alternately. Furthermore, successive comparisons of the second system are performed during the sampling period of the first system, and successive comparisons of the first system are performed during the sampling period of the second system.

[0117] Here, we assume that the configuration of only one CDAC system is provided as the first comparative example.

[0118] Figure 10 Examples of block diagrams and timing diagrams of a SARADC according to a first comparative example are shown. In the figure, a is a block diagram showing a configuration example of the SARADC according to the first comparative example, and b is a timing diagram showing an operational example of the SARADC according to the first comparative example.

[0119] As shown in Figure a, in the first comparative example, only one system including CDAC 411 and 412 is configured.

[0120] In this scenario, as shown in Figure b, sampling and successive comparisons are performed alternately. For example, during the sampling period from time T1 to time T2, CDACs 411 and 412 sample the input signal. Then, successive comparisons are performed during the period from time T2 to time T5. Subsequently, during the sampling period from time T5 to time T6, CDACs 411 and 412 sample the next input signal. Then, successive comparisons are performed after time T6.

[0121] As shown in Figure b, in a first comparative example of a CDAC-based system, AD conversion cannot be performed on the image signal of another column during the sampling period of the pixel signal of one column. On the other hand, in a first embodiment, while the first system is sampling the pixel signal of one column, the second system can perform AD conversion on the image signal of another column. This makes the AD conversion faster than in the first comparative example.

[0122] Furthermore, in the first comparative example, the blocks operating during the sampling phase and the blocks operating during the successive comparison phase are different, resulting in a change in the IR voltage drop. This change may have different effects on surrounding circuitry, leading to an increase in streaking. On the other hand, in the first embodiment, the sampling block and the successive comparison block operate simultaneously, which prevents changes in the IR voltage drop and allows for a reduction in streaking.

[0123] Next, we will consider the configuration using a time-interleaved approach as a second comparative example, in which multiple SARADCs are configured within the AD converter and sampling is performed at different times.

[0124] Figure 11 This is a block diagram illustrating a configuration example of the AD converter according to the second comparative example. In the second comparative example, at least two SARADCs and switching circuits 271 and 272 are configured in the AD converter.

[0125] Switching circuit 271 selects one of the multiple SARADCs 300 and connects the input terminal of the selected SARADC 300 to the vertical signal line VSL. Switching circuit 272 selects one of the multiple SARADCs 300 and connects the output terminal of the selected SARADC 300 to the output circuit 260.

[0126] Each SARADC 300 includes a single-ended to differential converter circuit 340, sample-and-hold switches 311 and 312, CDACs 411 and 412, and a control unit 500. The control unit 500 includes a comparator unit 510 and SAR logic circuitry 580.

[0127] Figure 12 This is a timing diagram illustrating an operational example of the AD converter according to the second comparison example. As shown, multiple SARADC 300s perform sampling at different times and perform successive comparisons after sampling. For example, in the case of four systems, the sampling periods of each system differ by one-quarter of the period of the control signal SH_SW used for sampling.

[0128] According to the time-interleaving method shown in the figure, during the sampling of pixel signals in one column, the AD converter can perform AD conversion on image signals in another column. This makes the AD conversion faster than the first comparison example. However, it requires not only the CDAC but also the comparator unit 510 and the SAR logic circuit 580 to be configured in each SARADC 300, resulting in an increase in circuit size. For example, a configuration of SARADC 300 including two systems requires four CDACs, two comparator units, and two SAR logic circuits.

[0129] On the other hand, in the first embodiment, in order to connect the CDACs of the two systems in parallel with the comparator unit 510, only four CDACs, one comparator unit, and one SAR logic circuit need to be configured. Compared with the second comparison example, this allows for an increase in the size of the suppression circuit.

[0130] [Operational Example of a Solid-State Imaging Element]

[0131] Figure 13 This is a flowchart illustrating an operational example of the solid-state imaging element 200 according to a first embodiment of the present technology. For example, operation begins when a predetermined application for capturing image data is performed.

[0132] The vertical drive circuit 210 selects a row. The column signal processing unit 240 drives four pixels within the row to output pixel signals (step S901). The first system of each of the four SARADCs 300 samples the pixel signals of the four pixels, and the second system performs AD conversion on the image signals of the first four pixels (step S902). Note that when driving the initial four pixels, there are no first four pixels, so only sampling is performed in step S902. When driving the last four pixels, only AD conversion is performed in step S902.

[0133] Solid-state imaging element 200 determines whether all rows have been read out (step S903). If all rows have been read out in solid-state imaging element 200 (step S903: Yes), solid-state imaging element 100 performs various types of image processing as needed and ends the imaging process.

[0134] On the other hand, if the reading of all rows has not been completed (step S903: No), the timing control circuit 250 uses switch 243 to drive the next four pixels and output pixel signals (step S904). The first system performs AD conversion on the sampled pixel signals, and the second system samples the newly output pixel signals (step S905).

[0135] Then, repeat step S901 and subsequent steps.

[0136] Note that when capturing multiple image data consecutively, steps S901 to S905 are repeated synchronously with the vertical synchronization signal.

[0137] As described above, according to the first embodiment of this technology, compared to the second comparative example, the CDACs 411 and 412 of the first system and the CDACs 421 and 422 of the second system are connected in parallel with the comparator unit 510, thereby allowing for an increase in the size of the suppression circuit. Furthermore, the first system holds the input signal during the first sampling period, and the second system holds the input signal during the first sampling period, thereby achieving a faster AD conversion than the first comparative example.

[0138] <2. Second Implementation Plan>

[0139] In the first embodiment described above, the SARADC 300 converts the single-ended signal into a differential signal before sampling. The SARADC 300 according to the second embodiment differs from that according to the first embodiment in that the single-ended signal is converted into a differential signal after sampling.

[0140] Figure 14 This is a block diagram illustrating a configuration example of a SARADC 300 according to a second embodiment of the present invention. In the SARADC 300 according to the second embodiment, single-ended to differential conversion circuits 341 and 342 are provided instead of single-ended to differential conversion circuit 340. Furthermore, CDAC 430 is provided instead of CDAC 412 and 422. In addition, sample-and-hold switches 312 and 322 and enable switches 314 and 324 are eliminated, and enable switches 315, 316, 317, 325, 326, and 327 are added. Furthermore, an OR (logic OR) gate 351 and an enable switch 352 are added.

[0141] CDAC 430 is shared between the first and second systems. Note that CDAC 430 is an example of a shared DAC as described in the claims.

[0142] The input terminals of sample-and-hold switches 311 and 321 are connected via switch 243 to corresponding vertical signal lines VSL (e.g., VSL_1 and VSL_5). The sample-and-hold switch 311 of the first system supplies the pixel signal (single-ended signal) AIN1 from the vertical signal line VSL to the CDAC 411 according to the control signal SH_SW1. The CDAC 411 holds the pixel signal AIN1. Note that the pixel signal AIN1 is an example of the first single-ended signal described in the claims.

[0143] When the enable signal IN_EN1 received from the timing control circuit 250 is at a high level, the enable switch 315 of the first system supplies the pixel signal AIN1 held by CDAC 411 to the single-ended to differential conversion circuit 341.

[0144] The single-ended differential converter circuit 341 of the first system converts the pixel signal AIN1 of the first system into a differential signal containing AINp1 and AINn1, and supplies the differential signal to enable switches 316 and 317. Note that the single-ended differential converter circuit 341 is an example of the first single-ended differential converter circuit described in the claims.

[0145] When the enable signal OUT_EN1 received from the timing control circuit 250 is high, the enable switch 316 of the first system supplies a positive signal AINp1 to the CDAC 411. When the enable signal EN1_OUT1 is high, the enable switch 317 of the first system supplies a negative signal AINn1 to the CDAC 430.

[0146] The first system's CDAC 411 maintains the positive signal AINp1 of the first system, generates a positive signal INP1 based on the positive signal AINp1 and the control signal CTLp1 received from the control unit 500, and supplies the positive signal INP1 to the enable switch 313. The CDAC 430 maintains the negative signal AINn1 of the first system, generates a negative signal INN based on the negative signal AINn1 and the control signal CTLn received from the control unit 500, and supplies the negative signal INN to the enable switch 352.

[0147] When the enable signal AD1_EN is high, the enable switch 313 of the first system supplies the positive signal INP1 from CDAC 411 to the control unit 500.

[0148] On the other hand, the sample-and-hold switch 321 of the second system supplies the pixel signal (single-ended signal) AIN2 from the vertical signal line VSL to the CDAC 421 according to the control signal SH_SW2. The CDAC 421 holds the pixel signal AIN2. Note that the pixel signal AIN2 is an example of the second single-ended signal described in the claims.

[0149] When the enable signal IN_EN2 received from the timing control circuit 250 is at a high level, the enable switch 325 of the second system supplies the pixel signal AIN2 held by CDAC 421 to the single-ended to differential conversion circuit 342.

[0150] The single-ended differential converter circuit 342 of the second system converts the pixel signal AIN2 of the second system into a differential signal containing AINp2 and AINn2, and supplies the differential signal to enable switches 326 and 327. Note that the single-ended differential converter circuit 342 is an example of the second single-ended differential converter circuit described in the claims.

[0151] When the enable signal OUT_EN2 received from the timing control circuit 250 is high, the enable switch 326 of the second system supplies a positive signal AINp2 to the CDAC 421. When the enable signal EN_OUT2 is high, the enable switch 327 of the second system supplies a negative signal AINn2 to the CDAC 430.

[0152] The second system's CDAC 421 maintains the positive signal AINp2 of the second system, generates a positive signal INP2 based on the positive signal AINp2 and the control signal CTLp2 received from the control unit 500, and supplies the positive signal INP2 to the enable switch 323. The CDAC 430 maintains the negative signal AINn2 of the second system, generates a negative signal INN based on the negative signal AINn2 and the control signal CTLn from the control unit 500, and supplies the negative signal INN to the enable switch 352.

[0153] When the enable signal AD2_EN is high, the enable switch 323 of the second system supplies the positive signal INP2 from CDAC 421 to the control unit 500.

[0154] OR gate 351 outputs a logical OR of enable signals AD1_EN and AD2_EN to enable switch 352. When the signal received from OR gate 351 is high, enable switch 352 supplies the negative signal INN from CDAC 430 to control unit 500.

[0155] Note that in the figure, the first system and the second system share the CDAC on the negative side, but the CDACs of the first system and the second system can be configured on the negative side, and the first system and the second system can share a single CDAC on the positive side.

[0156] Figure 15 This is a block diagram illustrating an example configuration of a control unit 500 according to a second embodiment of the present technology. In the control unit 500 of the second embodiment, the negative-side AND gates 552 and 562 are eliminated.

[0157] Figure 16 This is a timing diagram illustrating an operational example of the SARADC 300 according to a second embodiment of the present technology. The timing control circuit 250 sets the control signal SH_SW1 high during the sampling period of the first system from time T1 to time T2. As a result, sampling of the first system is performed. Furthermore, the timing control circuit 250 sets the enable signal AD2_EN high during the period from time T1 until immediately preceding time T4. During this period, successive comparisons of the second system are performed during the sampling period of the first system.

[0158] Furthermore, the timing control circuit 250 sets the enable signal IN_EN1 to a high level during the pulse period starting from time T2, and sets the enable signal OUT_EN1 to a high level during the pulse period starting from time T3. As a result, the single-ended signal of the first system is converted into a differential signal and output.

[0159] Then, the timing control circuit 250 sets the control signal SH_SW2 to a high level during the sampling period of the second system from time T4 to time T5. As a result, sampling of the second system is performed. Furthermore, the timing control circuit 250 sets the enable signal AD1_EN to a high level from time T4 until immediately preceding time T7. During this period, successive comparisons of the first system are performed during the sampling period of the second system.

[0160] Furthermore, the timing control circuit 250 sets the enable signal IN_EN2 to a high level during the pulse period starting from time T5, and sets the enable signal OUT_EN2 to a high level during the pulse period starting from time T6. As a result, the single-ended signal of the second system is converted into a differential signal and output.

[0161] As shown in the figure, the single-ended-differential conversion of the first system is performed during the interval between the end of the sampling period of the first system and the beginning of the sampling period of the second system. Similarly, as shown in the figure, the single-ended-differential conversion of the second system is performed during the interval between the end of the sampling period of the second system and the beginning of the sampling period of the first system. As described above, by allowing the single-ended-differential conversion to be performed at a timed interval outside the sampling period, the number of CDACs on the negative side can be reduced to one, such as... Figure 14 As shown.

[0162] As described above, according to the second embodiment of the present technology, single-ended to differential conversion circuits 341 and 342 convert single-ended signals into differential signals after sampling, thereby reducing the circuit size by reducing the number of CDACs on the negative side to one.

[0163] <3. Third Implementation Plan>

[0164] In the first embodiment described above, the SARADC 300 converts the single-ended signal into a differential signal before sampling; however, this configuration makes it difficult to further reduce the circuit size. The SARADC 300 according to the third embodiment differs from that according to the first embodiment in that the single-ended signal is retained and not converted into a differential signal.

[0165] Figure 17 This is a block diagram illustrating a configuration example of a SARADC 300 according to a third embodiment of the present invention. The SARADC 300 according to the third embodiment differs from that according to the first embodiment in that it does not include a single-ended to differential conversion circuit 340.

[0166] Furthermore, the input terminals of sample-and-hold switches 311 and 321 are connected via switch 243 to the corresponding multiple vertical signal lines (such as VSL_1 and VSL_5). Sample-and-hold switch 311 supplies the pixel signal (single-ended signal) AIN1 to the CDAC 411 of the first system according to the control signal SH_SW1. Sample-and-hold switch 321 supplies the pixel signal (single-ended signal) AIN2 to the CDAC 421 of the second system according to the control signal SH_SW2.

[0167] Furthermore, a reference signal REF, which is a constant single-ended signal, is input to the input terminals of sample-and-hold switches 312 and 322. The reference signal REF is generated by a base reference signal generation circuit (not shown), such as a DAC. Sample-and-hold switch 312 supplies the reference signal REF (single-ended signal) to the CDAC 412 of the first system according to the control signal SH_SW1. Sample-and-hold switch 322 supplies the reference signal REF to the CDAC 422 of the second system according to the control signal SH_SW2.

[0168] As shown in the figure, sample-and-hold switches 311 and 312 supply pixel signal AIN1 and reference signal REF to the first system, and sample-and-hold switches 321 and 322 supply pixel signal AIN2 and reference signal REF2 to the second system. This control reduces the need for single-ended to differential conversion circuit 340.

[0169] Note that, as Figure 18 As shown, the negative-side CDAC can also be replaced by capacitors 441 and 442. In the figure, the negative-side CDAC is replaced by capacitors 441 and 442, or the positive-side VDAC can be replaced.

[0170] As described above, according to the third embodiment of the present technology, sample and hold switches 311, 312, 321 and 322 supply pixel signals and reference signals REF corresponding to each system, thereby allowing the reduction of single-ended to differential conversion circuit 340.

[0171] <4. Fourth Implementation Plan>

[0172] In the first embodiment described above, enable switches 313, 314, 323, and 324 are inserted into the input side of the comparator unit 510; however, when these switches are controlled, the on-resistance introduces corresponding noise. The SARADC300 according to the fourth embodiment differs from that according to the first embodiment in that noise is reduced by eliminating the switches on the input side of the comparator unit 510.

[0173] Figure 19 This is a block diagram illustrating a configuration example of a SARADC 300 according to a fourth embodiment of the present invention. The SARADC 300 according to the fourth embodiment differs from that according to the first embodiment in that enable switches 313, 314, 323, and 324 are omitted.

[0174] Figure 20 This is a block diagram illustrating an example configuration of a control unit 500 according to a fourth embodiment of the present technology. As shown, INP1, INN1, INP2, and INN2 from CDACs 411, 412, 421, and 422 are input to the comparison unit 510 in the control unit 500.

[0175] Figure 21 This is a circuit diagram illustrating an example configuration of the comparison unit 510 according to a fourth embodiment of the present invention. The comparison unit 510 according to the fourth embodiment also includes enable switches 514, 515, 524 and 525, nMOS transistors 521, 522 and 523, and AND gates 516 and 526.

[0176] Enable switch 514 opens and closes the path between pMOS transistor 531 and nMOS transistor 511 based on the enable signal AD1_EN. When the enable signal AD1_EN is high, enable switch 514 returns to the closed state. Enable switch 515 opens and closes the path between pMOS transistor 532 and nMOS transistor 512 based on the enable signal AD1_EN. When the enable signal AD1_EN is high, enable switch 515 returns to the closed state.

[0177] In addition, the connection point between pMOS transistor 531 and enable switch 514, and the connection point between pMOS transistor 532 and enable switch 515, are connected to the positive and negative input terminals of latch 550.

[0178] AND gate 516 supplies the clock signal CLK and the enable signal AD1_EN to the gate of nMOS transistor 513 via a logic AND operation.

[0179] The connection configuration of nMOS transistors 521, 522, and 523 is similar to that of nMOS transistors 511, 512, and 513.

[0180] Enable switch 524 opens and closes the path between pMOS transistor 531 and nMOS transistor 521 based on the enable signal AD2_EN. When the enable signal AD2_EN is high, enable switch 524 turns to the closed state. Enable switch 525 opens and closes the path between pMOS transistor 532 and nMOS transistor 522 based on the enable signal AD2_EN. When the enable signal AD2_EN is high, enable switch 525 turns to the closed state.

[0181] In addition, the connection point between pMOS transistor 531 and enable switch 524, and the connection point between pMOS transistor 532 and enable switch 525, are connected to the positive and negative input terminals of latch 550.

[0182] AND gate 526 supplies the clock signal CLK and the enable signal AD2_EN to the gate of nMOS transistor 523 via a logic AND operation.

[0183] As shown in the figure, the comparison unit 510 selects and compares any one of INP1 and INN1, or INP2 and INN2, based on the enable signal. This allows the enable switch 313 on the input side to be deactivated.

[0184] Note that the second or third implementation scheme can be applied to the fourth implementation scheme.

[0185] As described above, according to the fourth embodiment of this technology, the enable switch 313 on the input side of the comparator unit 510 is eliminated, thereby reducing the impact of noise caused by the on-resistance of the switch.

[0186] <5. Fifth Implementation Plan>

[0187] In the first embodiment described above, two CDAC systems are configured within the SARADC 300. However, with this configuration, the parasitic capacitance caused by the wiring load of the vertical signal line VSL is larger, resulting in a longer settling time. The extended settling time increases the required sampling period, leading to a decrease in the AD conversion speed. The SARADC 300 according to the fifth embodiment differs from that according to the first embodiment in that it suppresses the decrease in AD conversion speed by configuring at least three CDAC systems within the CDAC.

[0188] Figure 22This is a block diagram illustrating an example configuration of the column signal processing unit 240 according to a fifth embodiment of the present technology. Also in the fifth embodiment, similar to the first embodiment, one SARADC 300 is configured for each group of vertical signal lines.

[0189] In addition, each SARADC 300 is equipped with three system CDACs. Column C corresponding to each SARADC 300 is classified into three groups: first, second, and third. Let's assume the first group of pixel signals is denoted as AIN1, the second group as AIN2, and the third group as AIN3. For example, AIN1 is output from vertical signal line VSL_1, AIN2 from vertical signal line VSL_5, and AIN3 from vertical signal line VSL_9.

[0190] Figure 23 This is a block diagram illustrating a configuration example of a SARADC 300 according to a fifth embodiment of the present invention. The SARADC 300 according to the fifth embodiment differs from that according to the first embodiment in that it further includes CDACs 431 and 432, sample-and-hold switches 331 and 332, and enable switches 333 and 334. Furthermore, the control unit 500 also includes AND gates 571 and 572. CDACs 431 and 432 are referred to as the CDACs of the "third system".

[0191] The single-ended differential converter 340 converts the pixel signal AIN3 into a differential signal containing a positive signal AINp3 and a negative signal AINn3. The sample-and-hold switch 331 opens and closes the path between the single-ended differential converter 340 and the CDAC 431 of the third system according to the control signal SH_SW3 received from the timing control circuit 250. The control signal SH_SW3 is a signal indicating the sampling period of the third system; for example, during the sampling period, the control signal SH_SW3 is controlled to be high. During the sampling period of the third system, the sample-and-hold switch 331 inputs the positive signal AINp3 as an input signal to the CDAC 431.

[0192] The sample-and-hold switch 332 opens and closes the path between the single-ended to differential converter circuit 340 and the CDAC 432 of the third system according to the control signal SH_SW3. During the sampling period of the third system, the sample-and-hold switch 332 inputs the negative signal AINn3 as an input signal to the CDAC 432.

[0193] CDACs 431 and 432 hold the input signals AINp3 and AINn3 received from sample-and-hold switches 331 and 332. Then, CDACs 431 and 432 internally generate differential reference signals based on control signals CTLp3 and CTLn3 received from control unit 500, and output the difference between the reference signal and AINp3 and AINn3 to enable switches 333 and 334. CDAC 431 outputs the positive differential signal INP3, and CDAC 432 outputs the negative differential signal INN3. Control signals CTLp3 and CTLn3 are digital signals, while INP3 and INN3 are analog signals.

[0194] Note that CDAC 431 and 432 are examples of the third digital-to-analog converters described in the claims. AINp3 and AINn3 are examples of the third input signals described in the claims.

[0195] Enable switch 333 opens and closes the path between CDAC 431 and control unit 500 based on the enable signal AD3_EN received from timing control circuit 250. Enable signal AD3_EN indicates the period during which successive comparisons of the differential signal are performed in the third system. For example, during a predetermined period within the sampling period of the first system, enable signal AD3_EN is controlled to be high to perform successive comparisons in the third system. When enable signal AD3_EN is high, enable switch 333 supplies the positive signal INP3 from CDAC 431 to control unit 500.

[0196] Enable switch 334 opens and closes the path between CDAC 432 and control unit 500 according to enable signal AD3_EN. When enable signal AD3_EN is high, enable switch 334 supplies the negative signal INN3 from CDAC 432 to control unit 500.

[0197] Assuming each control signal CTLp3 and CTLn3 has K bits, then each of AND gates 571 and 572 consists of K bits. For clarity, the AND gates corresponding to the second and subsequent bits are omitted from the diagram.

[0198] The k-th AND gate 571 outputs the logical AND of the k-th bit of the control signal CTLp and the enable signal AD3_EN as the k-th bit of CTLp3 to CDAC 431.

[0199] The k-th AND gate 572 outputs the logical AND of the k-th bit of the control signal CTLn and the enable signal AD3_EN as the k-th bit of CTLn3 to CDAC 432.

[0200] Note that each SARADC 300 includes three CDAC systems, or may include four or more. Assuming the number of systems is S (where S is an integer), in... Figure 22 In this configuration, one SARADC 300 can be configured for each S column. As the number of systems increases, the number of SARADC 300s can be reduced, thereby reducing the chip area.

[0201] Figure 24 This is a timing diagram illustrating an operational example of a SARADC 300 according to a fifth embodiment of the present technology.

[0202] The timing control circuit 250 sets the control signal SH_SW1 to a high level during the first system sampling period from time T1 to time T3. Furthermore, the timing control circuit 250 sets the enable signal AD2_EN to a high level during the period immediately following time T1 and immediately preceding time T2. Additionally, the timing control circuit 250 sets the enable signal AD3_EN to a high level during the period immediately following time T2 and immediately preceding time T3.

[0203] This control enables successive comparisons of the second and third systems to be performed during the sampling period of the first system.

[0204] Furthermore, the sampling period of the first system partially overlaps with that of the second system. During the sampling period of the second system, from time T2 to time T4, the timing control circuit 250 sets the control signal SH_SW2 to a high level. During this sampling period, the timing control circuit 250 also sets the enable signal AD1_EN to a high level from immediately following time T3 to immediately preceding time T4.

[0205] This control enables successive comparisons of not only the third system but also the first system to be performed during the sampling period of the second system.

[0206] Furthermore, the sampling period of the second system partially overlaps with that of the third system. During the sampling period of the third system, from time T3 to time T5, the timing control circuit 250 sets the control signal SH_SW3 to a high level. During this sampling period, the timing control circuit 250 also sets the enable signal AD2_EN to a high level from immediately following time T4 to immediately preceding time T5.

[0207] This control enables successive comparisons of not only the first system but also the second system to be performed during the sampling period of the third system.

[0208] Repeat the above control. As shown in the figure, by successively comparing the other two systems during the sampling period of one of the three systems, the decrease in AD conversion speed can be suppressed even during a longer settling time.

[0209] Note that each of the second, third, and fourth implementation schemes can be applied to the fifth implementation scheme.

[0210] As described above, according to the fifth embodiment of the present technology, a CDAC with three systems is configured, and during the sampling period of one of the three systems, successive comparisons of the other two systems are performed, thereby allowing suppression of the reduction in AD conversion speed.

[0211] Note that the above embodiments are merely examples illustrating this technology, and the matters in the embodiments correspond to the matters specified in the claims. Similarly, the matters specified in the claims correspond to the matters with the same names in the embodiments of this technology. Note that this technology is not limited to the embodiments and can be implemented by various modifications to the embodiments without departing from the essential points of this technology.

[0212] Note that the effects described in this manual are for illustrative purposes only and are not intended to be limiting; other effects can also be achieved.

[0213] Note that this technology may also have the following configurations.

[0214] (1) An analog-to-digital (AD) converter, comprising:

[0215] A first digital-to-analog converter (DAC) has a capacitor that holds a first input signal during a first sampling period;

[0216] A second DAC, connected in parallel with the first DAC, and having a capacitor that holds the second input signal during the second sampling period; and

[0217] The comparator unit is connected to the first DAC and the second DAC.

[0218] (2) The AD converter according to (1) above further includes:

[0219] A single-ended to differential converter circuit that converts a first single-ended signal into a first differential signal and a second single-ended signal into a second differential signal;

[0220] A first sample-and-hold switch supplies a first differential signal as a first input signal to a first DAC during a first sampling period; and

[0221] The second sample and hold switch supplies the second differential signal as the second input signal to the second DAC during the second sampling period.

[0222] (3) The AD converter according to (1) above further includes:

[0223] A first sample and hold switch supplies a first single-ended signal as a first input signal to a first DAC during a first sampling period;

[0224] The second sample and hold switch supplies the second single-ended signal as the second input signal to the second DAC during the second sampling period;

[0225] Shared DAC;

[0226] A first single-ended differential converter circuit converts a first input signal into a differential signal during the interval between the end of a first sampling period and the beginning of a second sampling period, and supplies the differential signal to a first DAC and the shared DAC; and

[0227] The second single-ended differential converter circuit converts the second input signal into a differential signal during the interval between the end of the second sampling period and the beginning of the first sampling period, and supplies the differential signal to the second DAC and the shared DAC.

[0228] (4) The AD converter according to (1) above further includes:

[0229] A first sample-and-hold switch, which supplies a first single-ended signal and a reference signal as first input signals to a first DAC during a first sampling period; and

[0230] The second sample and hold switch supplies the second single-ended signal and the reference signal as the second input signal to the second DAC during the second sampling period.

[0231] (5) The AD converter according to any one of (1) to (4) above further includes:

[0232] A logic circuit that generates a second control signal based on the comparison result of the comparison unit during a first sampling period, and generates a first control signal based on the comparison result of the comparison unit during a second sampling period, wherein...

[0233] During the second sampling period, the first DAC generates a pair of first analog signals based on the first control signal and the first input signal.

[0234] During the first sampling period, the second DAC generates a pair of second analog signals based on the second control signal and the second input signal, and

[0235] The comparison unit sequentially compares the pair of first analog signals and the pair of second analog signals.

[0236] (6) The AD converter according to (5) above further includes:

[0237] A first enable switch supplies the pair of first analog signals to the comparison unit during the second sampling period; and

[0238] A second enable switch supplies the pair of second analog signals to the comparison unit during the first sampling period.

[0239] (7) The AD converter according to (5) above, wherein

[0240] The first DAC supplies the pair of first analog signals to the comparison unit.

[0241] The second DAC supplies the pair of second analog signals to the comparison unit, and

[0242] The comparison unit selects and compares either the pair of second analog signals or the pair of first analog signals according to a predetermined enable signal.

[0243] (8) The AD converter according to any one of (1) to (7) above further includes:

[0244] The third DAC is connected in parallel with the first and second DACs and has a capacitor that holds the third input signal during the third sampling period.

[0245] (9) An imaging device, comprising:

[0246] A pixel array unit, comprising multiple pixels, each outputting a pixel signal; and

[0247] An AD converter is input to a pixel signal from the pixel array unit, wherein

[0248] The AD converter includes:

[0249] A first DAC has a capacitor that holds a first input signal during a first sampling period;

[0250] The second DAC, which is connected in parallel with the first DAC, has a capacitor that holds the second input signal during the second sampling period, and

[0251] The comparator unit is connected to the first DAC and the second DAC.

[0252] (10) A control method for an AD converter, comprising:

[0253] The first input signal is maintained during the first sampling period by a first DAC having a capacitor;

[0254] The second input signal is maintained during the second sampling period by a second DAC having a capacitor and connected in parallel with the first DAC; and

[0255] The comparison unit is connected to the first DAC and the second DAC to compare a pair of analog signals.

[0256] List of reference numerals

[0257] 100 imaging device

[0258] 110 Optical System

[0259] 120 Image Processing Unit

[0260] 130 memory

[0261] 140 Imaging Control Unit

[0262] 150 monitors

[0263] 200 solid-state imaging elements

[0264] 201 sensor chip

[0265] 202 circuit chip

[0266] 210 Vertical Drive Circuit

[0267] 220 pixel array unit

[0268] 230 pixels

[0269] 231 photodiode

[0270] 232 Transmission Transistor

[0271] 233 reset transistor

[0272] 234 Floating Diffusion Layer

[0273] 235 Amplifying Transistor

[0274] 236 Select Transistor

[0275] 240 signal processing units

[0276] 241 Sample and Hold Circuit

[0277] 242 column amplifier

[0278] 243 switch

[0279] 250 timing control circuit

[0280] 260 output circuit

[0281] 271, 272 switching circuit

[0282] 300SARADC

[0283] 311, 312, 321, 322, 331, 332 Sample and Hold Switches

[0284] Enable switches 313~317, 323~327, 333, 334, 352, 514, 515, 524, 525

[0285] 340, 341, 342 Single-ended to Differential Conversion Circuits

[0286] 351OR (Logical OR) gate

[0287] 411, 412, 421, 422, 430, 431, 432CDAC

[0288] 441, 442 capacitors

[0289] 500 control unit

[0290] 510 Comparison Unit

[0291] 511~513, 521~523 nMOS transistors

[0292] 516, 526, 551, 552, 561, 562, 571, 572 AND (Logical AND) gates

[0293] 531, 532 pMOS transistors

[0294] 550 latch

[0295] 580SAR Logic Circuit

Claims

1. An analog-to-digital (AD) converter, comprising: A first digital-to-analog converter (DAC) has a capacitor that holds a first input signal during a first sampling period; The second DAC is connected in parallel with the first DAC and has a capacitor that holds the second input signal during the second sampling period; and The comparator unit is connected to the first DAC and the second DAC.

2. The AD converter according to claim 1, further comprising: A single-ended to differential converter circuit that converts a first single-ended signal into a first differential signal and a second single-ended signal into a second differential signal; A first sample-and-hold switch supplies a first differential signal as a first input signal to a first DAC during a first sampling period; and The second sample and hold switch supplies the second differential signal as the second input signal to the second DAC during the second sampling period.

3. The AD converter according to claim 1, further comprising: A first sample and hold switch supplies a first single-ended signal as a first input signal to a first DAC during a first sampling period; The second sample and hold switch supplies the second single-ended signal as the second input signal to the second DAC during the second sampling period; Shared DAC; A first single-ended differential converter circuit converts a first input signal into a differential signal during the interval between the end of a first sampling period and the beginning of a second sampling period, and supplies the differential signal to a first DAC and the shared DAC. and The second single-ended differential converter circuit converts the second input signal into a differential signal during the interval between the end of the second sampling period and the beginning of the first sampling period, and supplies the differential signal to the second DAC and the shared DAC.

4. The AD converter according to claim 1, further comprising: A first sample and hold switch supplies a first single-ended signal and a reference signal as a first input signal to a first DAC during a first sampling period; and The second sample and hold switch supplies the second single-ended signal and the reference signal as the second input signal to the second DAC during the second sampling period.

5. The AD converter according to claim 1, further comprising: A logic circuit that generates a second control signal based on the comparison result of the comparison unit during a first sampling period, and generates a first control signal based on the comparison result of the comparison unit during a second sampling period, wherein... During the second sampling period, the first DAC generates a pair of first analog signals based on the first control signal and the first input signal. During the first sampling period, the second DAC generates a pair of second analog signals based on the second control signal and the second input signal, and The comparison unit sequentially compares the pair of first analog signals and the pair of second analog signals.

6. The AD converter according to claim 5, further comprising: A first enable switch supplies the pair of first analog signals to the comparison unit during the second sampling period; and A second enable switch supplies the pair of second analog signals to the comparison unit during the first sampling period.

7. The AD converter according to claim 5, wherein The first DAC supplies the pair of first analog signals to the comparison unit. The second DAC supplies the pair of second analog signals to the comparison unit, and The comparison unit selects and compares either the pair of second analog signals or the pair of first analog signals according to a predetermined enable signal.

8. The AD converter according to claim 1, further comprising: The third DAC is connected in parallel with the first and second DACs and has a capacitor that holds the third input signal during the third sampling period.

9. An imaging device, comprising: A pixel array unit, which includes multiple pixels, with each pixel outputting a pixel signal; and An AD converter is input to a pixel signal from the pixel array unit, wherein The AD converter includes: A first DAC has a capacitor that holds a first input signal during a first sampling period; The second DAC, which is connected in parallel with the first DAC, has a capacitor that holds the second input signal during the second sampling period, and The comparator unit is connected to the first DAC and the second DAC.

10. A control method for an AD converter, comprising: The first input signal is maintained during the first sampling period by a first DAC having a capacitor; The second input signal is maintained during the second sampling period by a second DAC having a capacitor and being connected in parallel with the first DAC; and The comparison unit is connected to the first DAC and the second DAC to compare a pair of analog signals.

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