A method and generator of random instruction sequences and a verification system

Abstract

The application provides a random instruction sequence generation method, a generator and a verification system. N instances are created according to a microinstruction quantity parameter in a target test case. Instruction slot identifiers and a target instruction library corresponding to each instance are determined according to an instruction slot quantity. Matching instructions of the instances are determined according to the target instruction library. Register allocation is performed according to the matching instructions of each instance, each register information in the microinstruction corresponding to the instance is determined, and corresponding assembly instructions are obtained. An assembly instruction file is generated according to the sorting number corresponding to each instance and all the assembly instructions. The assembly instruction file comprises a random instruction sequence composed of the assembly instructions according to the sorting number corresponding to the instance and the instruction slot identifier corresponding to each assembly instruction. The random instruction sequence matched with a very long instruction word architecture processor can be generated, various test scenes can be simulated, and the verification of the very long instruction word architecture processor can be completed.

Description

Technical Field

[0001] This invention relates to the field of chip verification, and more specifically, to a method and generator for generating random instruction sequences and a verification system. Background Technology

[0002] With the rapid development of artificial intelligence and high-performance computing, processor architectures face increasingly higher demands for parallel computing. Very Long Instruction Word (VLIW) architecture, due to its high parallelism and simple hardware implementation, is widely used in the field of dedicated processors. VLIW is an explicit parallel instruction computing architecture that packages multiple instructions that can be executed in parallel into a very long instruction word. Unlike traditional superscalar processors, VLIW shifts the complexity of instruction scheduling from hardware to the compiler, thus simplifying processor design.

[0003] In the process of verifying processors with very long instruction word (VLT) architecture, a large number of random instruction sequences are required. How to generate random instruction sequences that match the VLT architecture to complete the processor verification has become a difficult problem of concern to those skilled in the art. Summary of the Invention

[0004] The purpose of this invention is to provide a method, generator, and verification system for generating random instruction sequences to improve the above-mentioned problems.

[0005] To achieve the above objectives, the technical solutions adopted in the embodiments of the present invention are as follows:

[0006] In a first aspect, embodiments of the present invention provide a method for generating a random instruction sequence, the method comprising:

[0007] Based on the number of microinstructions in the target test case, N instances are created, where the target test case is any test case in the test case set, N matches the number of microinstructions parameter, and the initially created instances are blank microinstructions;

[0008] The instruction slot identifier corresponding to each instance is determined based on the number of instruction slots, wherein the number of instruction slots is the number of instruction slots in the processor to be verified using a very long instruction word architecture, and the instruction slot identifier is the identifier of the target instruction slot in the processor to be verified used to process the microinstruction corresponding to the instance.

[0009] The target instruction library is determined based on the instruction slot identifier of the instance, wherein the target instruction library includes the processable microinstructions corresponding to the target instruction slot in the target test case;

[0010] The matching instruction for the instance is determined based on the target instruction library;

[0011] Register allocation is performed based on the matching instruction for each instance, and the register information in the microinstruction corresponding to the instance is determined to obtain the corresponding assembly instruction.

[0012] An assembly instruction file is generated based on the sort number corresponding to each instance and all assembly instructions. The assembly instruction file includes a random instruction sequence composed of the assembly instructions according to the sort number corresponding to the instance and an instruction slot identifier corresponding to each assembly instruction.

[0013] Secondly, embodiments of the present invention provide a random instruction sequence generator, which is used in the above-described random instruction sequence generation method.

[0014] Thirdly, embodiments of the present invention provide a verification system, the verification system including a compilation unit, a conversion unit, a RISC-V isa simulator, a comparison unit, and the above-mentioned random instruction sequence generator;

[0015] The output of the random instruction sequence generator is connected to the input of the compilation unit. The output of the compilation unit is connected to the input of the conversion unit and the input of the RISC-Visa simulator. The output of the RISC-Visa simulator is connected to the first input of the comparison unit. The output of the conversion unit is used to connect to the input of the processor to be verified using a very long instruction word architecture. The second input of the comparison unit is used to connect to the output of the processor to be verified.

[0016] Optionally, the random instruction sequence generator is used to transmit the generated assembly instruction file to the compilation unit;

[0017] The compilation unit is used to combine the linker script to convert the assembly instruction file into a first type of file, and transmit the first type of file to the conversion unit and the RISC-V isa simulator;

[0018] The first type of file is the recognizable executable file corresponding to the RISC-V isa simulator;

[0019] The conversion unit is used to convert the first type of file into a second type of file and transmit the second type of file to the processor to be verified, wherein the second type of file is a recognizable executable file corresponding to the processor to be verified;

[0020] The RISC-V isa simulator is used to execute the first type of file and transmit the corresponding first execution result to the comparison unit;

[0021] The processor to be verified is used to execute the second type of file and transmit the corresponding second execution result to the comparison unit;

[0022] The comparison unit is used to compare the first execution result and the second execution result to determine the verification result of the processor to be verified.

[0023] Compared to existing technologies, the random instruction sequence generation method, generator, and verification system provided in this invention create N instances based on the number of microinstructions in the target test case; determine the instruction slot identifier corresponding to each instance based on the number of instruction slots; determine the target instruction library based on the instruction slot identifier of the instance; determine the matching instructions for the instance based on the target instruction library; perform register allocation based on the matching instructions for each instance, determine the register information of each microinstruction corresponding to the instance, and obtain the corresponding assembly instructions; generate an assembly instruction file based on the sorting number corresponding to each instance and all assembly instructions. The assembly instruction file includes a random instruction sequence composed of assembly instructions according to the sorting number corresponding to the instance and the instruction slot identifier corresponding to each assembly instruction. This can generate random instruction sequences that match processors with very long instruction word (VLS) architectures, simulate various test scenarios, and be used to verify VLS processors, ensuring verification efficiency and accuracy.

[0024] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0025] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0026] Figure 1 This is a flowchart illustrating the random instruction sequence generation method provided in an embodiment of the present invention.

[0027] Figure 2 This is a schematic diagram of the structure of the verification system provided in an embodiment of the present invention. Detailed Implementation

[0028] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0029] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0030] It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. Furthermore, in the description of this invention, terms such as "first," "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0031] The following detailed description of some embodiments of the present invention is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0032] This invention provides a method for generating random instruction sequences, applied to a random instruction sequence generator. Please refer to [link / reference]. Figure 1 The random instruction sequence generation methods include S100 to S600, which are described in detail below.

[0033] S100: Create N instances based on the number of microinstructions in the target test case.

[0034] The target test case is any test case in the test case set. N matches the number of microinstructions parameter. N and the number of microinstructions parameter can be equal. The initially created instance is a blank microinstruction. Each instance corresponds to a sort number idx.

[0035] Optionally, the number of micro-instructions in the target test case can be obtained from the script file (yaml file) (instr_cnt parameter). The number of micro-instructions is usually large, such as 1200 or 2000.

[0036] S200 determines the instruction slot identifier corresponding to each instance based on the number of instruction slots.

[0037] The instruction slot number refers to the number of instruction slots in the processor to be verified that adopts a very long instruction word architecture, and the instruction slot identifier refers to the identifier of the target instruction slot in the processor to be verified that is used to process the microinstruction corresponding to the instance.

[0038] S300 determines the target instruction library based on the instruction slot identifier of the instance.

[0039] The target instruction library includes the processable microinstructions corresponding to the target instruction slots in the target test cases.

[0040] S400 determines the matching instruction for the instance based on the target instruction library.

[0041] Optionally, the instruction name of the matching instruction for the instance can be determined based on the target instruction library.

[0042] S500 allocates registers based on the matching instruction for each instance, determines the register information in the microinstruction corresponding to the instance, and obtains the corresponding assembly instruction.

[0043] S600 generates an assembly instruction file based on the sort number corresponding to each instance and all assembly instructions.

[0044] The assembly instruction file includes a random instruction sequence composed of assembly instructions arranged according to their instance order numbers and an instruction slot identifier for each assembly instruction. The instruction slot identifier is used for instruction allocation in subsequent processors to be verified.

[0045] In the random instruction sequence generation method provided in this embodiment of the invention, a random instruction sequence matching the processor with a very long instruction word (VLTB) architecture can be generated to simulate various test scenarios and to complete the verification of the VLTB ​​processor, so as to ensure verification efficiency and accuracy.

[0046] Based on the preceding text, regarding the content of S200, this embodiment of the invention also provides an optional implementation, please refer to the following. S200, determining the instruction slot identifier corresponding to each instance according to the number of instruction slots, includes: S201 and S202, which are described in detail below.

[0047] S201, through the very long word instruction creation (setup_allowed_instr) function, obtains the remainder of the sort number corresponding to the instance divided by the number of instruction slots.

[0048] S202, determine the instruction slot identifier corresponding to the instance based on the remainder corresponding to the instance.

[0049] For example, if there are 4 instruction slots, the corresponding sequence numbers of the instances are 1, 2, 3, 4, 5, 6, 7, 8... The instance with sequence number 1 has a remainder of 1, and its corresponding instruction slot identifier is the identifier of the 1st instruction slot; the instance with sequence number 2 has a remainder of 2, and its corresponding instruction slot identifier is the identifier of the 2nd instruction slot; the instance with sequence number 3 has a remainder of 3, and its corresponding instruction slot identifier is the identifier of the 3rd instruction slot; the instance with sequence number 4 has a remainder of 0, and its corresponding instruction slot identifier is the identifier of the 4th instruction slot, and so on. This will not be elaborated further here.

[0050] When the number of concurrent operation registers (vlmul parameter) in the target test case is less than or equal to the target threshold (which can be, but is not limited to, 2 or 1), regarding the content of S400, this embodiment of the invention also provides an optional implementation, please refer to the following. S400, determining the matching instruction of the instance according to the target instruction library, includes: S401, which is described in detail below.

[0051] S401 uses the random instruction generation function (randomize_instr function) to randomly select an executable microinstruction from the target instruction library as the matching instruction for the instance.

[0052] Optionally, the types of instructions that can be placed in the instruction slot can be adjusted according to the specific implementation of the hardware microarchitecture. For example, the execution unit of a branch instruction is in the first instruction slot, so a branch instruction can only be placed in the first instruction slot.

[0053] Based on the premise that the number of concurrent operation registers (vlmul parameter) in the target test case is less than or equal to the target threshold, this embodiment of the invention also provides an optional implementation regarding the content of S500, please refer to the following. S500, register allocation is performed according to the matching instruction of each instance to determine the register information in the microinstruction corresponding to the instance in order to obtain the corresponding assembly instructions, including: S501, S502 and S503, which are described in detail below.

[0054] S501 divides N instances into multiple instance groups, with each instance group containing instances of the instruction slot number.

[0055] S502, determine the instruction type of each instance in the instance group, where the instruction type of the instance is the type of the matching instruction of the instance.

[0056] S503, under the supervision of instance group constraints, determines the register type of each register in each instance based on the instruction type of each instance in the instance group, and then determines the register information of each instance in the instance group to obtain the corresponding assembly instruction.

[0057] Among them, the instance group constraint conditions include at least the first instance group sub-condition. The first instance group sub-condition is that there are no read-after-write conflicts, write-after-read conflicts, or write-after-write conflicts in the vector registers and floating-point registers of any two instances in the same instance group, and there are no write-after-write conflicts in the integer registers.

[0058] Optionally, the register randomization function (randomize_gpr function) is called to randomize all register addresses corresponding to the register type, thereby determining the register information for each instance in the instance group.

[0059] When the number of concurrently operated registers (vlmul parameter) in the target test case is greater than the target threshold, for example, the number of concurrently operated registers is 4 or 8, this embodiment of the invention also provides an optional implementation regarding the content of S400, please refer to the following. S400, determining the matching instruction of the instance according to the target instruction library, includes: S411, S412, S413, S414 and S415, which are described in detail below.

[0060] S411 divides N instances into multiple instance groups.

[0061] Each instance group includes instances of the instruction slots, and the partitioning result includes at least 4 instance groups.

[0062] S412 divides multiple instance groups into multiple instance bundles, with each instance bundle containing 4 instance groups.

[0063] S413, classify instances in the instance bundle and determine the category of each instance in each instance group within the instance bundle.

[0064] The instance is classified as either a first-class instance or a second-class instance. The instance classification result satisfies the instance bundle constraint condition, which includes a first instance bundle sub-condition and a second instance bundle condition. The first instance bundle sub-condition is that each instance group includes at least one first-class instance and at least one second-class instance. The second instance bundle condition is that the instruction slots corresponding to the first-class instances in different instance groups are different.

[0065] S414, For the first type of instance, the random instruction generation function (randomize_instr function) is used to randomly select an executable microinstruction from the target instruction library corresponding to the first type of instance as the matching instruction for the first type of instance.

[0066] S415, for the second type of instance, the random instruction generation function (randomize_instr function) is used to randomly select an executable microinstruction from the non-vector register operation instruction library as the matching instruction for the second type of instance.

[0067] The non-vector register operation instruction library includes non-vector register operation instructions in the target test cases. Non-vector register operation instructions are instructions that do not require operation on vector registers, and can be, but are not limited to, Nop instructions, integer instructions, and floating-point instructions.

[0068] The data hazard problem is solved by randomly selecting an executable microinstruction from the non-vector register operation instruction library as the matching instruction for the second type of instance.

[0069] When the number of concurrent operation registers (vlmul parameter) in the target test case is greater than the target threshold and the number of instruction slots is 4, this embodiment of the invention also provides an optional implementation method for the content in S413, please refer to the following. S413, classify instances in the instance bundle, and determine the category of each instance in each instance group in the instance bundle, including: S413A, S413B, S413C, S413D and S413E, which are described in detail below.

[0070] S413A, obtain the remainder when the sort number corresponding to each instance group is divided by 4.

[0071] S413B, when the remainder corresponding to the instance group is 1, the first instance in the instance group is determined to be a first-class instance, and the other instances in the instance group are second-class instances;

[0072] S413C, when the remainder corresponding to the instance group is 2, the second instance in the instance group is determined to be a first-class instance, and the other instances in the instance group are second-class instances.

[0073] S413D, when the remainder of the instance group is 3, the third instance in the instance group is determined to be a first-class instance, and the other instances in the instance group are second-class instances.

[0074] S413E, when the remainder corresponding to the instance group is 4, the 4th instance in the instance group is determined to be a first-class instance, and the other instances in the instance group are second-class instances.

[0075] When the number of concurrent operation registers (vlmul parameter) in the target test case is greater than the target threshold and the number of instruction slots is 8, this embodiment of the invention also provides an optional implementation method for the content in S413, please refer to the following. S413, classify instances in the instance bundle, and determine the category of each instance in each instance group in the instance bundle, including: S413F, S413G, S413H, S413I and S413J, which are described in detail below.

[0076] S413F: Obtain the remainder when the sort number corresponding to each instance group is divided by 4.

[0077] S413G: When the remainder corresponding to the instance group is 1, the first and fifth instances in the instance group are determined to be first-class instances, and the other instances in the instance group are second-class instances.

[0078] S413H, when the remainder corresponding to the instance group is 2, the second and sixth instances in the instance group are determined to be first-class instances, and the other instances in the instance group are second-class instances.

[0079] S413I, when the remainder corresponding to the instance group is 3, the 3rd and 7th instances in the instance group are determined to be first-class instances, and the other instances in the instance group are second-class instances.

[0080] S413J: When the remainder of the instance group is 4, the 4th and 8th instances in the instance group are determined to be first-class instances, and the other instances in the instance group are second-class instances.

[0081] When the number of concurrently operated registers (vlmul parameter) in the target test case exceeds the target threshold, this embodiment of the invention also provides an optional implementation method for the content in S500, please refer to the following. S500, register allocation is performed according to the matching instruction of each instance to determine the register information in the microinstruction corresponding to the instance in order to obtain the corresponding assembly instructions, including: S511 and S512, which are described in detail below.

[0082] S511, determine the instruction type of each instance in the instance group, where the instruction type of the instance is the type of the matching instruction of the instance.

[0083] S512, under the supervision of instance group constraints, determines the register type of each register in each instance according to the instruction type of each instance in the instance group, and then determines the register information of each instance in each instance in the instance group to obtain the corresponding assembly instructions.

[0084] The instance group constraint includes at least the first instance group sub-condition, which states that in any two instances within the same instance group, there are no read-after-write conflicts, write-after-read conflicts, or write-after-write conflicts in the vector registers and floating-point registers, and there are no write-after-write conflicts in the integer registers.

[0085] It's important to note that Very Long Instruction Word (VLE) architectures allow multiple operations to be executed in parallel within a single instruction. Unlike traditional instruction set architectures (such as RISC and CISC), VLE architectures improve parallel processing capabilities by packaging multiple instructions into a single long instruction. This design relies on the intelligence of the compiler, which is responsible for packaging instructions and scheduling them at compile time, rather than dynamically scheduling them at runtime.

[0086] Instruction packing is the process of combining multiple instructions into a single long instruction. Each instruction typically corresponds to a functional unit, such as the arithmetic logic unit (ALU) or a load / store unit.

[0087] In a Very Long Instruction Word (VLTB) architecture, long instructions are divided into multiple "slots." Each slot can contain an operation or instruction. Each slot typically points to a specific functional unit, and the processor executes them in parallel based on the contents of the instruction slots.

[0088] Optionally, the Very Long Instruction Word (VLE) architecture has four instruction slots, which can execute four different instructions in the same cycle. The execution unit of the branch instruction is in slot 0 (i.e., the first instruction slot), so the branch instruction can only be placed in slot 0.

[0089] Very Long Instruction Word (VLE) architecture is based on the RISC-V instruction set. Specific RISC-V instructions are inserted into each slot to form long instructions adapted to the hardware architecture. The random instruction generator is compatible with all instructions in the RISC-V instruction set and has been constrained to address instruction register hazards caused by the VLE architecture.

[0090] This invention also provides a random instruction sequence generator, which is used to execute the above-described random instruction sequence generation method.

[0091] This invention provides a verification system, please refer to... Figure 2 , Figure 2 This is a schematic diagram of the structure of a verification system provided in an embodiment of the present invention. The verification system includes a compilation unit (RISC-V Compiler), a conversion unit, a RISC-V isa simulator, a comparison unit (checker), and the aforementioned random instruction sequence generator (RSG).

[0092] The RISC-V isa simulator is a RISC-V instruction set simulator, and the Spike simulator can be used. The Spike simulator is a trace-driven simulator. It only considers the implementation of the instruction set, without considering the execution time of the instructions. Spike achieves instruction-level simulation by simulating the hardware and software behavior during the actual code execution process, providing golden instruction execution results.

[0093] The output of the random instruction sequence generator is connected to the input of the compilation unit. The output of the compilation unit is connected to the input of the conversion unit and the input of the RISC-V isa simulator. The output of the RISC-V isa simulator is connected to the first input of the comparison unit. The output of the conversion unit is used to connect to the input of the processor to be verified (RVC) using a very long instruction word architecture. The second input of the comparison unit is used to connect to the output of the processor to be verified.

[0094] The random instruction sequence generator is used to transmit the generated assembly instruction file (main.s) to the compilation unit.

[0095] The compilation unit is used to combine the link script to convert the assembly instruction file into a first-class file, and then transmit the first-class file to the conversion unit and the RISC-V isa simulator.

[0096] The first type of file is the recognizable executable file (main.elf) corresponding to the RISC-V isa simulator.

[0097] The conversion unit is used (via the objcopy tool) to convert the first type of file into the second type of file and transmit the second type of file to the processor to be verified, wherein the second type of file is the recognizable executable file (main.bin or main.hex) corresponding to the processor to be verified.

[0098] The RISCV isa simulator is used to execute the first type of file and transmit the corresponding first execution result (DPI-C) to the comparison unit.

[0099] The processor to be verified is used to execute the second type of file and transmit the corresponding second execution result (Monitor) to the comparison unit.

[0100] The comparison unit is used to compare the first execution result and the second execution result to determine the verification result of the processor to be verified.

[0101] In summary, the random instruction sequence generation method, generator, and verification system provided by this invention create N instances based on the number of microinstructions in the target test case; determine the instruction slot identifier corresponding to each instance based on the number of instruction slots; determine the target instruction library based on the instruction slot identifier of the instance; determine the matching instructions for the instance based on the target instruction library; perform register allocation based on the matching instructions for each instance, determine the register information of each microinstruction corresponding to the instance, and obtain the corresponding assembly instructions; generate an assembly instruction file based on the sorting number corresponding to each instance and all assembly instructions. The assembly instruction file includes a random instruction sequence composed of assembly instructions according to the sorting number corresponding to the instance and the instruction slot identifier corresponding to each assembly instruction. This can generate random instruction sequences that match processors with very long instruction word (VLS) architectures, simulate various test scenarios, and be used to verify VLS processors, ensuring verification efficiency and accuracy.

[0102] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

[0103] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the invention can be implemented in other specific forms without departing from its spirit or essential characteristics. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within the present invention. No reference numerals in the claims should be construed as limiting the scope of the claims.

Claims

1. A method for generating a random instruction sequence, characterized in that, The method includes: Based on the number of microinstructions in the target test case, N instances are created, where the target test case is any test case in the test case set, N matches the number of microinstructions parameter, and the initially created instances are blank microinstructions; The instruction slot identifier corresponding to each instance is determined based on the number of instruction slots, wherein the number of instruction slots is the number of instruction slots in the processor to be verified using a very long instruction word architecture, and the instruction slot identifier is the identifier of the target instruction slot in the processor to be verified used to process the microinstruction corresponding to the instance. The target instruction library is determined based on the instruction slot identifier of the instance, wherein the target instruction library includes the processable microinstructions corresponding to the target instruction slot in the target test case; The matching instruction for the instance is determined based on the target instruction library; Register allocation is performed based on the matching instruction for each instance, and the register information in the microinstruction corresponding to the instance is determined to obtain the corresponding assembly instruction. An assembly instruction file is generated based on the sort number corresponding to each instance and all assembly instructions. The assembly instruction file includes a random instruction sequence composed of the assembly instructions according to the sort number corresponding to the instance and an instruction slot identifier corresponding to each assembly instruction.

2. The random instruction sequence generation method as described in claim 1, characterized in that, The step of determining the instruction slot identifier corresponding to each instance based on the number of instruction slots includes: The function is created by using a very long word instruction to obtain the remainder when the sort number corresponding to the instance is divided by the number of instruction slots. The instruction slot identifier corresponding to the instance is determined based on the remainder corresponding to the instance.

3. The random instruction sequence generation method as described in claim 1, characterized in that, When the number of concurrently operated registers in the target test case is less than or equal to a target threshold, determining the matching instruction for the instance based on the target instruction library includes: Using a random instruction generation function, an executable microinstruction is randomly selected from the target instruction library and used as the matching instruction for the instance.

4. The random instruction sequence generation method as described in claim 3, characterized in that, The process of allocating registers based on the matching instruction for each instance, determining the register information in the microinstruction corresponding to the instance, and obtaining the corresponding assembly instruction includes: Divide the N instances into multiple instance groups, and each instance group includes the number of instances in the instruction slot; Determine the instruction type of each instance in the instance group, wherein the instruction type of the instance is the type of the matching instruction of the instance; Under the supervision of instance group constraints, the register type of each register in each instance is determined according to the instruction type of each instance in the instance group, and then the register information of each instance in the instance group is determined to obtain the corresponding assembly instructions. The instance group constraint includes at least a first instance group sub-condition, which states that in any two instances within the same instance group, there are no read-after-write conflicts, write-after-read conflicts, or write-after-write conflicts in the vector registers and floating-point registers, and there are no write-after-write conflicts in the integer registers.

5. The random instruction sequence generation method as described in claim 1, characterized in that, When the number of registers operated simultaneously in the target test case is greater than a target threshold, determining the matching instruction for the instance based on the target instruction library includes: Divide the N instances into multiple instance groups, and each instance group includes the number of instances in the instruction slot; The plurality of instance groups are divided into a plurality of instance bundles, each instance bundle comprising 4 of the instance groups; The instance bundle is classified to determine the category of each instance in each instance group within the instance bundle; The instance is classified as either a first-class instance or a second-class instance. The instance classification result satisfies the instance bundle constraint condition, which includes a first instance bundle sub-condition and a second instance bundle condition. The first instance bundle sub-condition is that each instance group includes at least one first-class instance and at least one second-class instance. The second instance bundle condition is that the instruction slots corresponding to the first-class instances in different instance groups are different. For the first type of instance, an executable microinstruction is randomly selected from the target instruction library corresponding to the first type of instance using a random instruction generation function, and used as the matching instruction for the first type of instance; For the second type of instance, an executable microinstruction is randomly selected from the non-vector register operation instruction library using a random instruction generation function, and used as the matching instruction for the second type of instance.

6. The random instruction sequence generation method as described in claim 5, characterized in that, When the number of instruction slots is 4, the step of classifying the instance bundle to determine the category of each instance in each instance group within the instance bundle includes: Get the remainder when the sort number corresponding to each instance group is divided by 4; When the remainder corresponding to the instance group is 1, the first instance in the instance group is determined to be the first type of instance, and the other instances in the instance group are the second type of instance; When the remainder corresponding to the instance group is 2, the second instance in the instance group is determined to be the first type of instance, and the other instances in the instance group are the second type of instance; When the remainder corresponding to the instance group is 3, the third instance in the instance group is determined to be the first type of instance, and the other instances in the instance group are the second type of instance; When the remainder corresponding to the instance group is 4, the 4th instance in the instance group is determined to be the first type of instance, and the other instances in the instance group are the second type of instance.

7. The random instruction sequence generation method as described in claim 5, characterized in that, The process of allocating registers based on the matching instruction for each instance, determining the register information in the microinstruction corresponding to the instance, and obtaining the corresponding assembly instruction includes: Determine the instruction type of each instance in the instance group, wherein the instruction type of the instance is the type of the matching instruction of the instance; Under the supervision of instance group constraints, the register type of each register in each instance is determined according to the instruction type of each instance in the instance group, and then the register information of each instance in the instance group is determined to obtain the corresponding assembly instructions. The instance group constraint includes at least a first instance group sub-condition, which states that in any two instances within the same instance group, there are no read-after-write conflicts, write-after-read conflicts, or write-after-write conflicts in the vector registers and floating-point registers, and there are no write-after-write conflicts in the integer registers.

8. A verification system, characterized in that, The verification system includes a compilation unit, a conversion unit, a RISC-V isa simulator, a comparison unit, and a random instruction sequence generator, wherein the random instruction sequence generator is used to execute the random instruction sequence generation method according to any one of claims 1-7; The output of the random instruction sequence generator is connected to the input of the compilation unit. The output of the compilation unit is connected to the input of the conversion unit and the input of the RISC-V isa simulator. The output of the RISC-V isa simulator is connected to the first input of the comparison unit. The output of the conversion unit is used to connect to the input of the processor to be verified using a very long instruction word architecture. The second input of the comparison unit is used to connect to the output of the processor to be verified.

9. The verification system as described in claim 8, characterized in that, The random instruction sequence generator is used to transmit the generated assembly instruction file to the compilation unit; The compilation unit is used to combine the linker script to convert the assembly instruction file into a first type of file, and transmit the first type of file to the conversion unit and the RISC-V isa simulator; The first type of file is the recognizable executable file corresponding to the RISC-V isa simulator; The conversion unit is used to convert the first type of file into a second type of file and transmit the second type of file to the processor to be verified, wherein the second type of file is a recognizable executable file corresponding to the processor to be verified; The RISC-V isa simulator is used to execute the first type of file and transmit the corresponding first execution result to the comparison unit; The processor to be verified is used to execute the second type of file and transmit the corresponding second execution result to the comparison unit; The comparison unit is used to compare the first execution result and the second execution result to determine the verification result of the processor to be verified.

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