Zero-voltage turn-on circuit and zero-voltage turn-on method for switching transistor in switching power supply

Abstract

The application discloses a zero-voltage opening circuit and a zero-voltage opening method of a switching tube in a switching power supply, and belongs to the technical field of circuits. In a critical conduction mode, when a low-side power tube is turned off, a rising zero-voltage opening circuit compares a switching node voltage with an input voltage or compares the switching node voltage with an output voltage under the control of a low-side gate drive voltage; when the switching node voltage is equal to the input voltage or the output voltage, a high level is output to a high-side gate drive end, and a high-side power tube is controlled by the high level to realize zero-voltage opening; in the critical conduction mode, when the high-side power tube is turned off, a falling zero-voltage opening circuit compares an induced voltage with a pull-up resistor voltage under the control of a high-side gate drive voltage; when the induced voltage is equal to the pull-up resistor voltage, a high level is output to the low-side gate drive end, and the low-side power tube is controlled by the high level to realize zero-voltage opening; and the induced voltage is equal to the pull-up resistor voltage plus the switching node voltage. The application can reduce transmission delay.

Description

Technical Field

[0001] This application relates to the field of circuit technology, and in particular to a zero-voltage turn-on circuit and method for a switching transistor in a switching power supply. Background Technology

[0002] The trend towards higher frequencies and higher efficiency in switching power supplies has transformed zero-voltage switching (ZVS) technology from an optional technology into an essential one for high-power and high-frequency applications. This is because traditional hard-switching technology leads to significant overlap losses during the turn-on phase, reducing system efficiency, a drawback that is particularly pronounced in high-power and high-frequency applications.

[0003] Boundary Conduction Mode (BCM) is a technique that utilizes the zero-voltage turn-on characteristic of inductor current valleys to achieve Zero-Switching Switching (ZVS). The key to achieving ZVS in BCM is precisely controlling the valley turn-on time, i.e., turning on when the drain-source voltage of the power transistor drops to zero, at which point switching losses are minimized. This requires precise detection of the lowest point of the power transistor's source-drain voltage. However, for zero-voltage turn-on of the high-side power transistor, detection needs to be performed on the rising edge of the switching node. Since the switching node is in the high-voltage domain at this time, traditional detection methods first detect the switching node voltage in the low-voltage domain and then use a level shifter to convert the obtained signal to the high-voltage domain. Because of the need for high-voltage and low-voltage domain conversion, this implementation method introduces additional propagation delay. Summary of the Invention

[0004] This application provides a zero-voltage turn-on circuit and method for a switching transistor in a switching power supply, to solve the problem of large transmission delay when the switching node in the high-voltage domain cannot be directly detected. The technical solution is as follows:

[0005] According to a first aspect of this application, a zero-voltage turn-on circuit for a switching transistor in a switching power supply is provided. The zero-voltage turn-on circuit includes a rising edge zero-voltage turn-on circuit and a falling edge zero-voltage turn-on circuit. The switching power supply includes a high-side power transistor and a low-side power transistor.

[0006] The first input terminal of the rising edge zero voltage turn-on circuit is connected to the input voltage terminal or the output voltage terminal. The second input terminal of the rising edge zero voltage turn-on circuit is connected to the low-side gate drive voltage terminal of the low-side power transistor. The third input terminal of the rising edge zero voltage turn-on circuit is connected to the switching node. The fourth input terminal of the rising edge zero voltage turn-on circuit is connected to the low-side turn-on signal terminal of the low-side power transistor. The output terminal of the rising edge zero voltage turn-on circuit is connected to the high-side gate drive terminal of the high-side power transistor.

[0007] The first input terminal of the falling edge zero voltage enable circuit is connected to the high-side gate drive voltage terminal of the high-side power transistor, the second input terminal of the falling edge zero voltage enable circuit is connected to the switching node, the third input terminal of the falling edge zero voltage enable circuit is connected to the low-side turn-on signal terminal, and the output terminal of the falling edge zero voltage enable circuit is connected to the low-side gate drive terminal of the low-side power transistor.

[0008] In critical conduction mode, when the low-side power transistor is turned off, the parasitic capacitance corresponding to the high-side power transistor is charged by the inductor current in the switching power supply, so that the switching node voltage of the switching node continues to rise during the dead time interval. The rising edge zero voltage turn-on circuit is used to compare the switching node voltage with the input voltage or compare the switching node voltage with the output voltage under the control of the low-side gate drive voltage. When it is determined that the switching node voltage is equal to the input voltage or the output voltage, a high level is output to the high-side gate drive terminal to control the high-side power transistor to achieve zero voltage turn-on.

[0009] In critical conduction mode, when the high-side power transistor is turned off, the parasitic capacitance corresponding to the low-side power transistor is discharged by the inductor current in the switching power supply, so that the switching node voltage of the switching node continues to decrease during the dead time interval. The falling edge zero-voltage turn-on circuit is used to compare the induced voltage with the pull-up resistor voltage under the control of the high-side gate drive voltage. When it is determined that the induced voltage is equal to the pull-up resistor voltage, a high level is output to the low-side gate drive terminal to control the low-side power transistor to achieve zero-voltage turn-on through the high level. The induced voltage is equal to the sum of the pull-up resistor voltage and the switching node voltage.

[0010] In one possible implementation, the rising edge zero-voltage turn-on circuit includes a rising edge detection module, a level conversion module, a first comparator, a high-side drive and level conversion module, and a first inverter;

[0011] The first input terminal of the rising edge detection module serves as the first input terminal of the rising edge zero-voltage enable circuit. The second input terminal of the rising edge detection module is connected to the output terminal of the level conversion module. The input terminal of the level conversion module serves as the second input terminal of the rising edge zero-voltage enable circuit. The third input terminal of the rising edge detection module serves as the third input terminal of the rising edge zero-voltage enable circuit. The first output terminal of the rising edge detection module is connected to the negative input terminal of the first comparator. The second output terminal of the rising edge detection module is connected to the positive input terminal of the first comparator. The output terminal of the first comparator is connected to the first input terminal of the high-side drive and level conversion module. The second input terminal of the high-side drive and level conversion module is connected to the output terminal of the first inverter. The input terminal of the first inverter serves as the fourth input terminal of the rising edge zero-voltage enable circuit. The output terminal of the high-side drive and level conversion module serves as the output terminal of the rising edge zero-voltage enable circuit.

[0012] In one possible implementation, the rising edge detection module includes a first to a fourth power transistor, a first current source, and a second current source;

[0013] The drain of the first power transistor serves as the first input terminal of the rising edge detection module. The gates of the first to fourth power transistors are connected together and serve as the second input terminal of the rising edge detection module. The source of the first power transistor is connected to the source of the second power transistor. The drain of the second power transistor is connected to the output terminal of the first current source and serves as the first output terminal of the rising edge detection module. The input terminal of the first current source is connected to the input terminal of the second current source. The output terminal of the second current source is connected to the drain of the third power transistor and serves as the second output terminal of the rising edge detection module. The source of the third power transistor is connected to the source of the fourth power transistor. The drain of the fourth power transistor serves as the third input terminal of the rising edge detection module.

[0014] In one possible implementation, the level conversion module includes a second inverter and a first level converter;

[0015] The input terminal of the second inverter serves as the input terminal of the level conversion module, and the output terminal of the second inverter is connected to the first level converter. The output terminal of the first level converter serves as the output terminal of the level conversion module.

[0016] In one possible implementation, the falling edge zero-voltage turn-on circuit includes a falling edge detection module, a second level converter, a second comparator, and a low-side drive and delay matching module;

[0017] The input terminal of the second level converter serves as the first input terminal of the falling edge zero-voltage enable circuit. The output terminal of the second level converter is connected to the first input terminal of the falling edge detection module. The second input terminal of the falling edge detection module serves as the second input terminal of the falling edge zero-voltage enable circuit. The first output terminal of the falling edge detection module is connected to the negative input terminal of the second comparator. The second output terminal of the falling edge detection module is connected to the positive input terminal of the second comparator. The output terminal of the second comparator is connected to the first input terminal of the low-side drive and delay matching module. The second input terminal of the low-side drive and delay matching module serves as the third input terminal of the falling edge zero-voltage enable circuit. The output terminal of the low-side drive and delay matching module serves as the output terminal of the falling edge zero-voltage enable circuit.

[0018] In one possible implementation, the falling edge detection module includes a fifth to eighth power transistor, a third current source, a fourth current source, a first pull-up resistor, a second pull-up resistor, and a third inverter;

[0019] The drain of the fifth power transistor serves as the second input terminal of the falling edge detection module. The source of the fifth power transistor is connected to the source of the sixth power transistor. The gate of the fifth power transistor is connected to the gate of the sixth power transistor and then connected to the output terminal of the third inverter. The input terminal of the third inverter is connected to the gates of the seventh and eighth power transistors and then serves as the first input terminal of the falling edge detection module. The drain of the seventh power transistor is connected to the drain of the sixth power transistor and the first terminal of the first pull-up resistor. The source of the seventh power transistor is connected to the drain of the eighth power transistor. The source of the eighth power transistor is grounded.

[0020] The second end of the first pull-up resistor is connected to the output end of the third current source and serves as the first output end of the falling edge detection module. The input end of the third current source is connected to the input end of the fourth current source. The output end of the fourth current source is connected to the first end of the second pull-up resistor and serves as the second output end of the falling edge detection module. The second end of the second pull-up resistor is grounded.

[0021] In one possible implementation, the switching power supply is a boost converter circuit;

[0022] The boost converter circuit includes a high-side power transistor, a low-side power transistor, and an inductor. The zero-voltage turn-on circuit includes a rising-edge zero-voltage turn-on circuit and a falling-edge zero-voltage turn-on circuit. The high-side power transistor corresponds to the rising-edge zero-voltage turn-on circuit, and the low-side power transistor corresponds to the falling-edge zero-voltage turn-on circuit.

[0023] The first end of the inductor is connected to the input voltage terminal, the second end of the inductor is connected to the switching node, and the parasitic capacitance is formed between the second end of the inductor and ground.

[0024] In the rising edge zero voltage turn-on circuit, the first input terminal is connected to the output voltage terminal.

[0025] In one possible implementation, the switching power supply is a buck converter circuit;

[0026] The buck converter circuit includes a high-side power transistor, a low-side power transistor, and an inductor. The zero-voltage turn-on circuit includes a rising-edge zero-voltage turn-on circuit and a falling-edge zero-voltage turn-on circuit. The high-side power transistor corresponds to the rising-edge zero-voltage turn-on circuit, and the low-side power transistor corresponds to the falling-edge zero-voltage turn-on circuit.

[0027] The first end of the inductor is connected to the switching node, the second end of the inductor is connected to the output voltage terminal, and the parasitic capacitance is formed between the first end of the inductor and ground.

[0028] In the rising edge zero voltage turn-on circuit, the first input terminal is connected to the input voltage terminal.

[0029] In one possible implementation, the switching power supply is a buck-boost converter circuit;

[0030] The buck-boost converter circuit includes two high-side power transistors, two low-side power transistors, and an inductor. The zero-voltage turn-on circuit includes two rising-edge zero-voltage turn-on circuits and two falling-edge zero-voltage turn-on circuits. Each high-side power transistor corresponds to one rising-edge zero-voltage turn-on circuit, and each low-side power transistor corresponds to one falling-edge zero-voltage turn-on circuit.

[0031] The first end of the inductor is connected to a switching node, the second end of the inductor is connected to another switching node, and a parasitic capacitance is formed between the first end of the inductor and ground, and another parasitic capacitance is formed between the second end of the inductor and ground.

[0032] In a rising-edge zero-voltage turn-on circuit connected to the first terminal of the inductor, the first input terminal is connected to the input voltage terminal.

[0033] In a rising-edge zero-voltage turn-on circuit connected to the second terminal of the inductor, the first input terminal is connected to the output voltage terminal.

[0034] According to a second aspect of this application, a zero-voltage switching method for a high-voltage power supply is provided for use in a zero-voltage switching circuit as described above, the method comprising:

[0035] In critical conduction mode, when the low-side power transistor is turned off, the parasitic capacitance corresponding to the high-side power transistor is charged by the inductor current in the switching power supply, so that the switching node voltage of the switching node continues to rise during the dead time interval. The rising edge zero voltage turn-on circuit compares the switching node voltage with the input voltage or compares the switching node voltage with the output voltage under the control of the low-side gate drive voltage. When it is determined that the switching node voltage is equal to the input voltage or the output voltage, it outputs a high level to the high-side gate drive terminal, so as to control the high-side power transistor to achieve zero voltage turn-on through the high level.

[0036] In critical conduction mode, when the high-side power transistor is turned off, the parasitic capacitance corresponding to the low-side power transistor is discharged by the inductor current in the switching power supply, so that the switching node voltage of the switching node continues to decrease during the dead time interval. The falling edge zero-voltage turn-on circuit compares the induced voltage with the pull-up resistor voltage under the control of the high-side gate drive voltage. When it is determined that the induced voltage is equal to the pull-up resistor voltage, it outputs a high level to the low-side gate drive terminal, so as to control the low-side power transistor to achieve zero-voltage turn-on through the high level. The induced voltage is equal to the sum of the pull-up resistor voltage and the switching node voltage.

[0037] The beneficial effects of the technical solution provided in this application include at least the following:

[0038] In critical conduction mode, when the low-side power transistor is turned off, the rising edge zero-voltage turn-on circuit can output a high level to the high-side gate drive terminal when it determines that the switching node voltage is equal to the input voltage or the output voltage. This high level controls the high-side power transistor to achieve zero-voltage turn-on, meaning that the switching node voltage is detected directly in the high-voltage domain without the need for high-voltage and low-voltage domain switching, thereby reducing transmission delay. Attached Figure Description

[0039] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0040] Figure 1 This is a block diagram of the zero-voltage turn-on circuit of the switching transistor in a switching power supply provided by related technologies;

[0041] Figure 2 This is a structural block diagram of a zero-voltage turn-on circuit for a switching transistor in a switching power supply provided in one embodiment of this application;

[0042] Figure 3This is a structural block diagram of the zero-voltage turn-on circuit of the switching transistor in a boost converter circuit provided in one embodiment of this application;

[0043] Figure 4 This is a structural block diagram of the zero-voltage turn-on circuit of the switching transistor in a buck converter circuit provided in one embodiment of this application;

[0044] Figure 5 This is a structural block diagram of the zero-voltage turn-on circuit of the switching transistor in a buck-boost converter circuit provided in one embodiment of this application;

[0045] Figure 6 This is a schematic diagram of the dead time provided in one embodiment of this application;

[0046] Figure 7 This is a flowchart of a zero-voltage start-up method for a high-voltage power supply provided in one embodiment of this application. Detailed Implementation

[0047] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the implementation methods of this application will be further described in detail below with reference to the accompanying drawings.

[0048] like Figure 2 The diagram illustrates a structural block diagram of a zero-voltage turn-on circuit for a switching transistor in a switching power supply according to an embodiment of this application. This zero-voltage turn-on circuit for the switching transistor in the switching power supply may include a rising-edge zero-voltage turn-on circuit and a falling-edge zero-voltage turn-on circuit. The switching power supply includes a high-side power transistor and a low-side power transistor. The high-side power transistor corresponds to the rising-edge zero-voltage turn-on circuit, and the low-side power transistor corresponds to the falling-edge zero-voltage turn-on circuit.

[0049] In this embodiment, the switching power supply can be a boost converter, a buck converter, or a buck-boost converter. Different switching power supplies correspond to zero-voltage turn-on circuits with different structures.

[0050] First, the switching power supply is a boost converter circuit:

[0051] like Figure 3 As shown, the boost converter circuit includes a high-side power transistor M. D A low-side power transistor M C A zero-voltage turn-on circuit with an inductor L, including a rising-edge zero-voltage turn-on circuit and a falling-edge zero-voltage turn-on circuit, and a high-side power transistor M. D Corresponding to the zero-voltage turn-on circuit on the rising edge, the low-side power transistor M C This corresponds to a zero-voltage turn-on circuit on the falling edge.

[0052] (1) Zero voltage turn-on circuit on rising edge

[0053] The first input terminal and output voltage terminal V of the rising edge zero voltage turn-on circuit OUT Connected, the second input terminal of the rising edge zero-voltage turn-on circuit is connected to the low-side gate drive voltage terminal V of the low-side power transistor. GC Connected, the third input terminal of the rising edge zero-voltage turn-on circuit is connected to the switching node V. SW2 Connect the fourth input terminal of the rising edge zero-voltage turn-on circuit to the low-side turn-on signal terminal V of the low-side power transistor. C_ON Connected, the output terminal of the rising edge zero voltage turn-on circuit is connected to the high-side gate drive terminal V of the high-side power transistor. D Connected.

[0054] In this embodiment, the rising edge zero-voltage enable circuit includes a rising edge detection module, a level conversion module, a first comparator CMP2, a high-side drive and level conversion module, and a first inverter N1; the first input terminal of the rising edge detection module serves as the first input terminal and output voltage terminal V of the rising edge zero-voltage enable circuit. OUT The rising edge detection module's second input terminal is connected to the level conversion module's output terminal. The level conversion module's input terminal serves as the second input terminal of the rising edge zero-voltage enable circuit and is connected to the low-side gate drive voltage terminal V. GC Connected, the third input terminal of the rising edge detection module serves as the third input terminal of the rising edge zero-voltage turn-on circuit and is connected to the switching node V. SW2 Connected, the first output of the rising edge detection module is connected to the negative input V of the first comparator CMP2. S_OUT The second output of the rising edge detection module is connected to the positive input V of the first comparator CMP2. S_SW2 Connected, the output terminal V of the first comparator CMP2 RZC2 The high-side drive and level conversion module's first input is connected to the high-side drive and level conversion module's second input, which is connected to the output of the first inverter N1. The input of the first inverter N1 serves as the fourth input of the rising-edge zero-voltage turn-on circuit and is connected to the low-side turn-on signal V. C_ON Connected, the output of the high-side drive and level conversion module serves as the output of the rising-edge zero-voltage turn-on circuit and the high-side gate drive terminal V. D Connected. High-side gate drive terminal V D After being converted by the gate driver, it is converted into a high-side power transistor M. D drive signal V GD .

[0055] The rising edge detection module includes a first power transistor M. L5 Second power transistor M L6 Third power transistor M L7 Fourth power transistor ML8 First current source I REF3 Second current source I REF4 First power transistor M L5 The drain of the transistor serves as the first input terminal of the rising edge detection module, and the first power transistor M... L5 Second power transistor M L6 Third power transistor M L7 and the fourth power transistor M L8 After being connected to the gate, it serves as the second input terminal of the rising edge detection module. The first power transistor M L5 The source and the second power transistor M L6 The source of the second power transistor M is connected to the source. L6 The drain and the first current source I REF3 After being connected to the output terminal, it serves as the first output terminal of the rising edge detection module, and the first current source I... REF3 The input terminal is connected to the second current source I. REF4 The input terminal is connected to the second current source I. REF4 The output terminal is connected to the third power transistor M L7 The drain of the transistor is connected to serve as the second output terminal of the rising edge detection module, and the third power transistor M... L7 The source and the fourth power transistor M L8 The source is connected to the fourth power transistor M. L8 The drain of [the device] serves as the third input terminal of the rising edge detection module. The first current source I [is used in this module]. REF3 With the second current source I REF4 same.

[0056] The level conversion module includes a second inverter N2 and a first level converter; the input terminal of the second inverter N2 serves as the input terminal of the level conversion module, the output terminal of the second inverter N2 is connected to the first level converter, and the output terminal of the first level converter serves as the output terminal of the level conversion module.

[0057] In critical conduction mode, and the low-side power transistor M C When turned off, the high-side power transistor M D The corresponding parasitic capacitance C SW2 The forward inductor current I in the switching power supply L Charge to make the switching node voltage V of the switching node. SW2 The rising edge continues to rise during the dead time interval, and the zero-voltage turn-on circuit is used to drive the low-side gate voltage V. GC Under the control of the comparison switch node voltage V SW2 With output voltage V OUT In determining the switching node voltage V SW2 Equal to output voltage V OUT At that time, drive the high-side gate terminal V DOutput a high level to control the high-side power transistor M. D Achieve zero-voltage startup.

[0058] That is, in the low-side power transistor M C During the turn-off period, the gate drive signal V GC Lower, thus turning on M L5 ~M L8 (These are high-voltage NMOS transistors used for voltage isolation). Thus, the output voltage V OUT and switching node voltage V SW2 They were detected as V S_OUT and V S_SW2 This operation is performed directly in the high-voltage domain. In critical conduction mode, due to C... SW2 The forward inductor current I L Charging, switching node voltage V SW2 The voltage rises continuously during the dead time interval. The rising edge triggers a zero-voltage turn-on circuit (buck side) that compares V. S_OUT and V S_SW2 When V S_OUT =V S_SW2 When, it indicates V SW2 equals V OUT The first comparator CMP2 will output signal V RZC2 The high-side gate drive signal V flips from low to high. D It becomes high. Therefore, the high-side power transistor M... D At the zero-crossing point on the rising edge (high-side power transistor M) D Drain-source voltage V DSD When the voltage is 0V, it is turned on, realizing the high-side power transistor M. D Zero-voltage start-up.

[0059] (2) Zero-voltage turn-on circuit on falling edge

[0060] The first input terminal of the falling-edge zero-voltage turn-on circuit is connected to the high-side gate drive voltage terminal V of the high-side power transistor. GD Connected, the second input terminal of the zero-voltage turn-on circuit on the falling edge is connected to the switching node V. SW2 Connected, the third input terminal of the zero-voltage turn-on circuit on the falling edge is connected to the turn-on signal terminal V. C_ON Connected, the output terminal of the zero-voltage-on circuit on the falling edge is connected to the low-side gate drive terminal V of the low-side power transistor. C Connected.

[0061] In this embodiment, the falling edge zero-voltage enable circuit includes a falling edge detection module, a second level converter, a second comparator CMP4, and a low-side drive and delay matching module; the input terminal of the second level converter serves as the first input terminal of the falling edge zero-voltage enable circuit and the high-side gate drive voltage terminal V.GD The output of the second level converter is connected to the first input of the falling edge detection module, and the second input of the falling edge detection module serves as the second input of the falling edge zero-voltage turn-on circuit and is connected to the switching node V. SW2 Connected, the first output of the falling edge detection module is connected to the negative input V of the second comparator CMP4. SNS2 Connected, the second output of the falling edge detection module is connected to the positive input V of the second comparator CMP4. RLS2 Connected, the output terminal V of the second comparator CMP4 FZC2 The second input of the low-side drive and delay matching module is connected to the first input terminal of the low-side drive and delay matching module, and serves as the third input terminal of the falling-edge zero-voltage turn-on circuit and the turn-on signal terminal V. C_ON Connected, the output of the low-side drive and delay matching module serves as the output of the falling-edge zero-voltage turn-on circuit and is connected to the low-side gate drive terminal V. C Connected.

[0062] The falling edge detection module includes the fifth power transistor M. L13 The sixth power transistor M L14 Seventh power transistor M L15 Eighth power transistor M L16 Third current source I REF7 Fourth current source I REF8 First pull-up resistor R LS1 Second pull-up resistor R LS2 And the third inverter N3; the fifth power transistor M L13 The drain of the transistor serves as the second input terminal of the falling edge detection module, and the fifth power transistor M... L13 The source and the sixth power transistor M L14 The source is connected to the fifth power transistor M. L13 The gate of the sixth power transistor M L14 The gate of the transistor is connected to the output of the third inverter N3, and the input of the third inverter N3 is connected to the seventh power transistor M. L15 and the eighth power transistor M L16 After its gate is connected, it serves as the first input terminal of the falling edge detection module, and the seventh power transistor M L15 The drains of the transistors are respectively connected to the sixth power transistor M. L14 The drain and the first pull-up resistor R LS1 The first terminal is connected, and the seventh power transistor M L15 The source and the eighth power M L16 The drain of the eighth power transistor M is connected. L16 The source is grounded; the first pull-up resistor R LS1 The second terminal and the third current source I REF7 After being connected to the output terminal, it serves as the first output terminal of the falling edge detection module, and the third current source I...REF7 The input terminal is connected to the fourth current source I. REF8 The input terminal is connected to the fourth current source I. REF8 The output terminal is connected to the second pull-up resistor R LS2 The first terminal is connected and serves as the second output terminal of the falling edge detection module, with the second pull-up resistor R LS2 The second end is grounded.

[0063] Among them, the third current source I REF7 With the fourth current source I REF8 The same, and the first pull-up resistor R LS1 With the second pull-up resistor R LS2 same.

[0064] In this embodiment, the first terminal of the inductor L is connected to the input voltage terminal V. IN Connected, the second terminal of the inductor is connected to the switching node V. SW2 The inductor L is connected, and a parasitic capacitance C is formed between the second terminal of the inductor L and ground. SW2 .

[0065] In critical conduction mode, and the high-side power transistor is turned off M D At that time, the low-side power transistor M C The corresponding parasitic capacitance C SW2 The negative inductor current I in the switching power supply L Discharge to reduce the switching node voltage V at the switching node. SW2 The voltage continues to drop during the dead time interval, and the zero-voltage turn-on circuit on the falling edge is used to drive the high-side gate voltage V. GD Under the control of the comparison induced voltage V SNS2 With pull-up resistor voltage V RLS2 In determining the induced voltage V SNS2 Equal to the pull-up resistor voltage V RLS2 At that time, drive the low-side gate terminal V C Output a high level to control the low-side power transistor M. C To achieve zero-voltage start-up, the induced voltage V SNS2 Equal to the pull-up resistor voltage V RLS2 With the switching node voltage V SW2 sum.

[0066] That is, in the high-side power transistor M D During the turn-off period, in critical conduction mode, the parasitic capacitance C SW2 Negative inductor current I L Discharge, switching node voltage V SW2 The descent begins. At the falling edge, zero voltage turns on the circuit M. L13 and M L14 To detect the switching node voltage V SW2 And the induced voltage VSNS2 equals V SW2 +V RLS1 The voltage of the analog ground AGND is connected through the second pull-up resistor R. LS2 The voltage V is shifted up to the pull-up resistor voltage. RLS2 This is to accommodate the input common-mode range of the second comparator CMP4. The second comparator CMP4 compares the induced voltage V. SNS2 and pull-up resistor voltage V RLS2 When V SNS2 =V RLS2 This indicates the voltage V at the switching node. SW2 When the voltage drops below 0V, the second comparator CMP4 will output signal V. FZC2 Set to high level, at which time the low-side gate drive signal V C It becomes high. Therefore, the low-side power transistor M... C At the zero-crossing point of this falling edge (low-side power transistor M) C Drain-source voltage V DSC When the voltage is 0V, it is turned on, realizing the low-side power transistor M. C Zero-voltage turn-on. Wherein, the pull-up resistor voltage V... RLS2 =I REF8 *R LS2 = V RLS1 =I REF7 *R LS1 .

[0067] Second, the switching power supply is a step-down converter circuit:

[0068] like Figure 4 As shown, the buck converter circuit includes a high-side power transistor M. A A low-side power transistor M B A zero-voltage turn-on circuit with an inductor L, including a rising-edge zero-voltage turn-on circuit and a falling-edge zero-voltage turn-on circuit, and a high-side power transistor M. A Corresponding to the zero-voltage turn-on circuit on the rising edge, the low-side power transistor M B This corresponds to a zero-voltage turn-on circuit on the falling edge.

[0069] (1) Zero voltage turn-on circuit on rising edge

[0070] The first input terminal and the input voltage terminal V of the rising edge zero voltage turn-on circuit IN Connected, the second input terminal of the rising edge zero-voltage turn-on circuit is connected to the low-side gate drive voltage terminal V of the low-side power transistor. GB Connected, the third input terminal of the rising edge zero-voltage turn-on circuit is connected to the switching node V. SW1 Connect the fourth input terminal of the rising edge zero-voltage turn-on circuit to the low-side turn-on signal terminal V of the low-side power transistor. B_ONConnected, the output terminal of the rising edge zero voltage turn-on circuit is connected to the high-side gate drive terminal V of the high-side power transistor. A Connected.

[0071] In this embodiment, the rising edge zero-voltage enable circuit includes a rising edge detection module, a level conversion module, a first comparator CMP1, a high-side drive and level conversion module, and a first inverter N4; the first input terminal of the rising edge detection module serves as the first input terminal and input voltage terminal V of the rising edge zero-voltage enable circuit. IN The rising edge detection module's second input terminal is connected to the level conversion module's output terminal. The level conversion module's input terminal serves as the second input terminal of the rising edge zero-voltage enable circuit and is connected to the low-side gate drive voltage terminal V. GB Connected, the third input terminal of the rising edge detection module serves as the third input terminal of the rising edge zero-voltage turn-on circuit and is connected to the switching node V. SW1 Connected, the first output of the rising edge detection module is connected to the negative input V of the first comparator CMP1. S_IN The second output of the rising edge detection module is connected to the positive input V of the first comparator CMP1. S_SW1 Connected, the output terminal V of the first comparator CMP1 RZC1 The high-side drive and level conversion module's first input is connected to the high-side drive and level conversion module's second input, which is connected to the output of the first inverter N4. The input of the first inverter N4 serves as the fourth input of the rising-edge zero-voltage turn-on circuit and is connected to the low-side turn-on signal V. B_ON Connected, the output of the high-side drive and level conversion module serves as the output of the rising-edge zero-voltage turn-on circuit and the high-side gate drive terminal V. A Connected. High-side gate drive terminal V A After being converted by the gate driver, it is converted into a high-side power transistor M. A drive signal V GA .

[0072] The rising edge detection module includes a first power transistor M. L1 Second power transistor M L2 Third power transistor M L3 Fourth power transistor M L4 First current source I REF1 Second current source I REF2 First power transistor M L1 The drain of the transistor serves as the first input terminal of the rising edge detection module, and the first power transistor M... L1 Second power transistor M L2 Third power transistor M L3 and the fourth power transistor M L4 After being connected to the gate, it serves as the second input terminal of the rising edge detection module. The first power transistor M L1The source and the second power transistor M L2 The source of the second power transistor M is connected to the source. L2 The drain and the first current source I REF1 After being connected to the output terminal, it serves as the first output terminal of the rising edge detection module, and the first current source I... REF1 The input terminal is connected to the second current source I. REF2 The input terminal is connected to the second current source I. REF2 The output terminal is connected to the third power transistor M L3 The drain of the transistor is connected to serve as the second output terminal of the rising edge detection module, and the third power transistor M... L3 The source and the fourth power transistor M L4 The source is connected to the fourth power transistor M. L4 The drain of [the device] serves as the third input terminal of the rising edge detection module. The first current source I [is used in this module]. REF1 With the second current source I REF2 same.

[0073] The level conversion module includes a second inverter N5 and a first level converter; the input terminal of the second inverter N5 serves as the input terminal of the level conversion module, the output terminal of the second inverter N2 is connected to the first level converter, and the output terminal of the first level converter serves as the output terminal of the level conversion module.

[0074] In critical conduction mode, and the low-side power transistor M B When turned off, the high-side power transistor M A The corresponding parasitic capacitance C SW1 The negative inductor current I in the switching power supply L Charge to make the switching node voltage V of the switching node. SW1 The rising edge continues to rise during the dead time interval, and the zero-voltage turn-on circuit is used to drive the low-side gate voltage V. GB Under the control of the comparison switch node voltage V SW1 With input voltage V IN In determining the switching node voltage V SW1 Equal to input voltage V IN At that time, drive the high-side gate terminal V A Output a high level to control the high-side power transistor M. A Achieve zero-voltage startup.

[0075] That is, in the low-side power transistor M B During the turn-off period, the gate drive signal V GB Lower, thus turning on M L1 ~M L4 (These are high-voltage NMOS transistors used for voltage isolation). Thus, the input voltage V... IN and switching node voltage V SW1 They were detected as VS_IN and V S_SW1 This operation is performed directly in the high-voltage domain. In critical conduction mode, due to C... SW1 Negative inductor current I L Charging, switching node voltage V SW1 The voltage rises continuously during the dead time interval. The rising edge triggers a zero-voltage turn-on circuit (buck side) that compares V. S_IN and V S_SW1 When V S_IN =V S_SW1 When, it indicates V SW1 equals V IN The first comparator CMP1 will output signal V RZC1 The high-side gate drive signal V flips from low to high. A It becomes high. Therefore, the high-side power transistor M... A At the zero-crossing point on the rising edge (high-side power transistor M) A Drain-source voltage V DSA When the voltage is 0V, it is turned on, realizing the high-side power transistor M. A Zero-voltage start-up.

[0076] (2) Zero-voltage turn-on circuit on falling edge

[0077] The first input terminal of the falling-edge zero-voltage turn-on circuit is connected to the high-side gate drive voltage terminal V of the high-side power transistor. GA Connected, the second input terminal of the zero-voltage turn-on circuit on the falling edge is connected to the switching node V. SW1 Connected, the third input terminal of the zero-voltage turn-on circuit on the falling edge is connected to the turn-on signal terminal V. B_ON Connected, the output terminal of the zero-voltage-on circuit on the falling edge is connected to the low-side gate drive terminal V of the low-side power transistor. B Connected.

[0078] In this embodiment, the falling edge zero-voltage enable circuit includes a falling edge detection module, a second level converter, a second comparator CMP3, and a low-side drive and delay matching module; the input terminal of the second level converter serves as the first input terminal of the falling edge zero-voltage enable circuit and the high-side gate drive voltage terminal V. GA The output of the second level converter is connected to the first input of the falling edge detection module, and the second input of the falling edge detection module serves as the second input of the falling edge zero-voltage turn-on circuit and is connected to the switching node V. SW1 Connected, the first output of the falling edge detection module is connected to the negative input V of the second comparator CMP3. SNS1 The second output of the falling edge detection module is connected to the positive input V of the second comparator CMP3. RLS1 Connected, the output terminal V of the second comparator CMP3 FZC1The second input of the low-side drive and delay matching module is connected to the first input terminal of the low-side drive and delay matching module, and serves as the third input terminal of the falling-edge zero-voltage turn-on circuit and the turn-on signal terminal V. B_ON Connected, the output of the low-side drive and delay matching module serves as the output of the falling-edge zero-voltage turn-on circuit and is connected to the low-side gate drive terminal V. B Connected.

[0079] The falling edge detection module includes the fifth power transistor M. L9 The sixth power transistor M L10 Seventh power transistor M L11 Eighth power transistor M L12 Third current source I REF5 Fourth current source I REF6 First pull-up resistor R LS3 Second pull-up resistor R LS4 And the third inverter N6; the fifth power transistor M L9 The drain of the transistor serves as the second input terminal of the falling edge detection module, and the fifth power transistor M... L9 The source and the sixth power transistor M L10 The source is connected to the fifth power transistor M. L9 The gate of the sixth power transistor M L10 The gate of the transistor is connected to the output of the third inverter N6, and the input of the third inverter N6 is connected to the seventh power transistor M. L11 and the eighth power transistor M L12 After its gate is connected, it serves as the first input terminal of the falling edge detection module, and the seventh power transistor M L11 The drains of the transistors are respectively connected to the sixth power transistor M. L10 The drain and the first pull-up resistor R LS3 The first terminal is connected, and the seventh power transistor M L11 The source and the eighth power M L12 The drain of the eighth power transistor M is connected. L12 The source is grounded; the first pull-up resistor R LS3 The second terminal and the third current source I REF5 After being connected to the output terminal, it serves as the first output terminal of the falling edge detection module, and the third current source I... REF5 The input terminal is connected to the fourth current source I. REF6 The input terminal is connected to the fourth current source I. REF6 The output terminal is connected to the second pull-up resistor R LS4 The first terminal is connected and serves as the second output terminal of the falling edge detection module, with the second pull-up resistor R LS4 The second end is grounded.

[0080] Among them, the third current source I REF5 With the fourth current source I REF6The same, and the first pull-up resistor R LS3 With the second pull-up resistor R LS4 same.

[0081] In this embodiment, the first end of the inductor L is connected to the switch node V. SW1 Connected, the second terminal of inductor L is connected to the output voltage terminal V. OUT The inductor L is connected, and a parasitic capacitance C is formed between the first terminal of the inductor L and ground. SW1 .

[0082] In critical conduction mode, and the high-side power transistor is turned off M A At that time, the low-side power transistor M B The corresponding parasitic capacitance C SW1 The forward inductor current I in the switching power supply L Discharge to reduce the switching node voltage V at the switching node. SW1 The voltage continues to drop during the dead time interval, and the zero-voltage turn-on circuit on the falling edge is used to drive the high-side gate voltage V. GA Under the control of the comparison induced voltage V SNS1 With pull-up resistor voltage V RLS1 In determining the induced voltage V SNS1 Equal to the pull-up resistor voltage V RLS1 At that time, drive the low-side gate terminal V B Output a high level to control the low-side power transistor M. B To achieve zero-voltage start-up, the induced voltage V SNS1 Equal to the pull-up resistor voltage V RLS1 With the switching node voltage V SW1 sum.

[0083] That is, in the high-side power transistor M A During the turn-off period, in critical conduction mode, the parasitic capacitance C SW1 The forward inductor current I L Discharge, switching node voltage V SW1 The voltage begins to drop. At the falling edge, the zero-voltage turn-on circuit activates the fifth power transistor M. L9 and the sixth power transistor M L10 To detect the switching node voltage V SW1 And the induced voltage V SNS1 equals V SW1 +V RLS3 The voltage of the analog ground AGND is connected through the second pull-up resistor R. LS4 The voltage V is shifted up to the pull-up resistor voltage. RLS1 This is to accommodate the input common-mode range of the second comparator CMP3. The second comparator CMP3 compares the induced voltage V. SNS1 and pull-up resistor voltage V RLS1 When V SNS1 =VRLS1 This indicates the voltage V at the switching node. SW1 When the voltage drops below 0V, the second comparator CMP3 will output signal V. FZC1 Set to high level, at which time the low-side gate drive signal V B It becomes high. Therefore, the low-side power transistor M... B At the zero-crossing point of this falling edge (low-side power transistor M) B Drain-source voltage V DSB When the voltage is 0V, it is turned on, realizing the low-side power transistor M. B Zero-voltage turn-on. Wherein, the pull-up resistor voltage V... RLS1 =I REF6 *R LS4 = V RLS3 =I REF5 *R LS3 .

[0084] Third, the switching power supply is a step-up / step-down conversion circuit:

[0085] like Figure 5 As shown, the buck-boost converter circuit includes two high-side power transistors M A and M D Two low-side power transistors M B and M C An inductor L has a zero-voltage turn-on circuit consisting of two rising-edge zero-voltage turn-on circuits and two falling-edge zero-voltage turn-on circuits. Each high-side power transistor corresponds to one rising-edge zero-voltage turn-on circuit, and each low-side power transistor corresponds to one falling-edge zero-voltage turn-on circuit. Figure 5 Middle, high-side power transistor M A Corresponding to the zero-voltage turn-on circuit on the rising edge of the buck side (left side), the high-side power transistor M D Corresponding to the zero-voltage turn-on circuit on the rising edge of the boost side (right side), the low-side power transistor M B Corresponding to the falling edge zero-voltage turn-on circuit on the buck side (left side), the low-side power transistor M C The circuit that turns on at the falling edge corresponds to the boost side (right side).

[0086] The first terminal of the inductor L is connected to a switching node V SW1 Connected, the second terminal of the inductor is connected to another switching node V. SW2 The inductor L is connected, and a parasitic capacitance C is formed between the first terminal of the inductor L and ground. SW1 Another parasitic capacitance C is formed between the second terminal of the inductor and ground. SW2 .

[0087] In the rising-edge zero-voltage turn-on circuit connected to the first terminal of inductor L, the first input terminal is connected to the input voltage terminal V. INConnected. That is, the first input terminal of the zero-voltage turn-on circuit on the rising edge of the buck side (left side) is connected to the input voltage terminal V. IN Connected.

[0088] In the rising-edge zero-voltage turn-on circuit connected to the second terminal of inductor L, the first input terminal and the output voltage terminal V OUT Connected. That is, the first input terminal of the zero-voltage turn-on circuit on the rising edge of the boost side (right side) is connected to the output voltage terminal V. OUT Connected.

[0089] The rising edge zero-voltage turn-on circuit and the falling edge zero-voltage turn-on circuit on the boost side (right side) are related to... Figure 3 The boost converter circuit shown is the same, so it will not be described again here.

[0090] The rising edge zero-voltage turn-on circuit and the falling edge zero-voltage turn-on circuit on the buck side (left side) are related to... Figure 4 The step-down converter circuit shown is the same, so it will not be described again here.

[0091] In this embodiment, the four power transistors M A ~ M D It could be a gallium nitride (GaN) power transistor. Because GaN power transistors lack a body diode, an excessively long dead time leads to high reverse conduction losses, which is more pronounced in GaN power transistors; conversely, with an excessively short dead time, the GaN power transistor will experience high reverse conduction losses at V0. DS It is turned on before it drops to zero, parasitic capacitance C SW1 and C SW2 It will be rapidly charged or discharged, resulting in additional switching charge loss. In this embodiment, V is directly detected. SW1 and V SW2 The proposed dual-edge zero-voltage turn-on circuit, utilizing both rising and falling edges, helps generate an ideal dead time, thus enabling the four power transistors M... A ~ M D Zero-voltage turn-on, such as Figure 6 As shown.

[0092] In summary, the zero-voltage turn-on circuit for the switching transistor in the switching power supply provided in this application embodiment, under critical conduction mode and when the low-side power transistor is turned off, can output a high level to the high-side gate drive terminal when it is determined that the switching node voltage is equal to the input voltage or the output voltage. This high level controls the high-side power transistor to achieve zero-voltage turn-on, that is, the switching node voltage is detected directly in the high-voltage domain without the need for high-voltage and low-voltage domain conversion, thereby reducing transmission delay.

[0093] like Figure 7The diagram illustrates a flowchart of a zero-voltage turn-on method for a high-voltage power supply according to an embodiment of this application. The zero-voltage turn-on method for the high-voltage power supply includes:

[0094] Step 701: In critical conduction mode, when the low-side power transistor is turned off, the parasitic capacitance corresponding to the high-side power transistor is charged by the inductor current in the switching power supply, so that the switching node voltage of the switching node continues to rise during the dead time interval. The rising edge zero-voltage turn-on circuit compares the switching node voltage with the input voltage or compares the switching node voltage with the output voltage under the control of the low-side gate drive voltage. When it is determined that the switching node voltage is equal to the input voltage or the output voltage, a high level is output to the high-side gate drive terminal to control the high-side power transistor to achieve zero-voltage turn-on.

[0095] by Figure 3 Taking the example of the low-side power transistor M, we can illustrate this further. C During the turn-off period, the gate drive signal V GC Lower, thus turning on M L5 ~M L8 (These are high-voltage NMOS transistors used for voltage isolation). Thus, the output voltage V OUT and switching node voltage V SW2 They were detected as V S_OUT and V S_SW2 This operation is performed directly in the high-voltage domain. In critical conduction mode, due to C... SW2 The forward inductor current I L Charging, switching node voltage V SW2 The voltage rises continuously during the dead time interval. The rising edge triggers a zero-voltage turn-on circuit (buck side) that compares V. S_OUT and V S_SW2 When V S_OUT =V S_SW2 When, it indicates V SW2 equals V OUT The first comparator CMP2 will output signal V RZC2 The high-side gate drive signal V flips from low to high. D It becomes high. Therefore, the high-side power transistor M... D At the zero-crossing point on the rising edge (high-side power transistor M) D Drain-source voltage V DSD When the voltage is 0V, it is turned on, realizing the high-side power transistor M. D Zero-voltage start-up.

[0096] by Figure 4 Taking the example of the low-side power transistor M, we can illustrate this further. B During the turn-off period, the gate drive signal V GB Lower, thus turning on M L1 ~M L4(These are high-voltage NMOS transistors used for voltage isolation). Thus, the input voltage V... IN and switching node voltage V SW1 They were detected as V S_IN and V S_SW1 This operation is performed directly in the high-voltage domain. In critical conduction mode, due to C... SW1 Negative inductor current I L Charging, switching node voltage V SW1 The voltage rises continuously during the dead time interval. The rising edge triggers a zero-voltage turn-on circuit (buck side) that compares V. S_IN and V S_SW1 When V S_IN =V S_SW1 When, it indicates V SW1 equals V IN The first comparator CMP1 will output signal V RZC1 The high-side gate drive signal V flips from low to high. A It becomes high. Therefore, the high-side power transistor M... A At the zero-crossing point on the rising edge (high-side power transistor M) A Drain-source voltage V DSA When the voltage is 0V, it is turned on, realizing the high-side power transistor M. A Zero-voltage start-up.

[0097] Step 702: In the critical conduction mode, when the high-side power transistor is turned off, the parasitic capacitance corresponding to the low-side power transistor is discharged by the inductor current in the switching power supply, so that the switching node voltage of the switching node continues to decrease during the dead time interval. The falling edge zero-voltage turn-on circuit compares the induced voltage with the pull-up resistor voltage under the control of the high-side gate drive voltage. When it is determined that the induced voltage is equal to the pull-up resistor voltage, a high level is output to the low-side gate drive terminal to control the low-side power transistor to achieve zero-voltage turn-on. The induced voltage is equal to the sum of the pull-up resistor voltage and the switching node voltage.

[0098] by Figure 3 Taking the example of the high-side power transistor M, we can illustrate this further. D During the turn-off period, in critical conduction mode, the parasitic capacitance C SW2 Negative inductor current I L Discharge, switching node voltage V SW2 The descent begins. At the falling edge, zero voltage turns on the circuit M. L13 and M L14 To detect the switching node voltage V SW2 And the induced voltage V SNS2 equals V SW2 +V RLS1 The voltage of the analog ground AGND is connected through the second pull-up resistor R. LS2The voltage V is shifted up to the pull-up resistor voltage. RLS2 This is to accommodate the input common-mode range of the second comparator CMP4. The second comparator CMP4 compares the induced voltage V. SNS2 and pull-up resistor voltage V RLS2 When V SNS2 =V RLS2 This indicates the voltage V at the switching node. SW2 When the voltage drops below 0V, the second comparator CMP4 will output signal V. FZC2 Set to high level, at which time the low-side gate drive signal V C It becomes high. Therefore, the low-side power transistor M... C At the zero-crossing point of this falling edge (low-side power transistor M) C Drain-source voltage V DSC When the voltage is 0V, it is turned on, realizing the low-side power transistor M. C Zero-voltage turn-on. Wherein, the pull-up resistor voltage V... RLS2 =I REF8 *R LS2 = V RLS1 =I REF7 *R LS1 .

[0099] by Figure 4 Taking the example of the high-side power transistor M, we can illustrate this further. A During the turn-off period, in critical conduction mode, the parasitic capacitance C SW1 The forward inductor current I L Discharge, switching node voltage V SW1 The voltage begins to drop. At the falling edge, the zero-voltage turn-on circuit activates the fifth power transistor M. L9 and the sixth power transistor M L10 To detect the switching node voltage V SW1 And the induced voltage V SNS1 equals V SW1 +V RLS3 The voltage of the analog ground AGND is connected through the second pull-up resistor R. LS4 The voltage V is shifted up to the pull-up resistor voltage. RLS1 This is to accommodate the input common-mode range of the second comparator CMP3. The second comparator CMP3 compares the induced voltage V. SNS1 and pull-up resistor voltage V RLS1 When V SNS1 =V RLS1 This indicates the voltage V at the switching node. SW1 When the voltage drops below 0V, the second comparator CMP3 will output signal V. FZC1 Set to high level, at which time the low-side gate drive signal V B It becomes high. Therefore, the low-side power transistor M... B At the zero-crossing point of this falling edge (low-side power transistor M)B Drain-source voltage V DSB When the voltage is 0V, it is turned on, realizing the low-side power transistor M. B Zero-voltage turn-on. Wherein, the pull-up resistor voltage V... RLS1 =I REF6 *R LS4 =V RLS3 =I REF5 *R LS3 .

[0100] In summary, the zero-voltage turn-on method for high-voltage power supplies provided in this application embodiment, under critical conduction mode and when the low-side power transistor is turned off, the rising edge zero-voltage turn-on circuit can output a high level to the high-side gate drive terminal when it is determined that the switching node voltage is equal to the input voltage or the output voltage, so as to control the high-side power transistor to achieve zero-voltage turn-on through the high level. That is, the switching node voltage is directly detected in the high-voltage domain without the need for high-voltage domain and low-voltage domain conversion, thereby reducing the transmission delay.

[0101] Those skilled in the art will understand that all or part of the steps of the above embodiments can be implemented by hardware or by a program instructing related hardware. The program can be stored in a computer-readable storage medium, such as a read-only memory, a disk, or an optical disk.

[0102] The above description is not intended to limit the embodiments of this application. Any adjustments, equivalent substitutions, improvements, etc., made within the spirit and principles of the embodiments of this application should be included within the protection scope of the embodiments of this application.

Claims

1. A zero-voltage turn-on circuit for a switching transistor in a switching power supply, characterized in that, The zero-voltage turn-on circuit includes a rising edge zero-voltage turn-on circuit and a falling edge zero-voltage turn-on circuit, and the switching power supply includes a high-side power transistor and a low-side power transistor. The first input terminal of the rising edge zero voltage turn-on circuit is connected to the input voltage terminal or the output voltage terminal. The second input terminal of the rising edge zero voltage turn-on circuit is connected to the low-side gate drive voltage terminal of the low-side power transistor. The third input terminal of the rising edge zero voltage turn-on circuit is connected to the switching node. The fourth input terminal of the rising edge zero voltage turn-on circuit is connected to the low-side turn-on signal terminal of the low-side power transistor. The output terminal of the rising edge zero voltage turn-on circuit is connected to the high-side gate drive terminal of the high-side power transistor. The first input terminal of the falling edge zero voltage enable circuit is connected to the high-side gate drive voltage terminal of the high-side power transistor, the second input terminal of the falling edge zero voltage enable circuit is connected to the switching node, the third input terminal of the falling edge zero voltage enable circuit is connected to the low-side turn-on signal terminal, and the output terminal of the falling edge zero voltage enable circuit is connected to the low-side gate drive terminal of the low-side power transistor. In critical conduction mode, when the low-side power transistor is turned off, the parasitic capacitance corresponding to the high-side power transistor is charged by the inductor current in the switching power supply, so that the switching node voltage of the switching node continues to rise during the dead time interval. The rising edge zero voltage turn-on circuit is used to compare the switching node voltage with the input voltage or compare the switching node voltage with the output voltage under the control of the low-side gate drive voltage. When it is determined that the switching node voltage is equal to the input voltage or the output voltage, a high level is output to the high-side gate drive terminal to control the high-side power transistor to achieve zero voltage turn-on. In critical conduction mode, when the high-side power transistor is turned off, the parasitic capacitance corresponding to the low-side power transistor is discharged by the inductor current in the switching power supply, so that the switching node voltage of the switching node continues to decrease during the dead time interval. The falling edge zero voltage turn-on circuit is used to compare the induced voltage and the pull-up resistor voltage under the control of the high-side gate drive voltage. When it is determined that the induced voltage is equal to the pull-up resistor voltage, a high level is output to the low-side gate drive terminal to control the low-side power transistor to achieve zero voltage turn-on through the high level. The induced voltage is equal to the sum of the pull-up resistor voltage and the switching node voltage. The rising edge zero-voltage enable circuit includes a rising edge detection module, a level conversion module, a first comparator, a high-side drive and level conversion module, and a first inverter. The first input terminal of the rising edge detection module serves as the first input terminal of the rising edge zero-voltage enable circuit. The second input terminal of the rising edge detection module is connected to the output terminal of the level conversion module. The input terminal of the level conversion module serves as the second input terminal of the rising edge zero-voltage enable circuit. The third input terminal of the rising edge detection module serves as the third input terminal of the rising edge zero-voltage enable circuit. The first output terminal of the rising edge detection module is connected to the negative input terminal of the first comparator. The second output terminal of the rising edge detection module is connected to the positive input terminal of the first comparator. The output terminal of the first comparator is connected to the first input terminal of the high-side drive and level conversion module. The second input terminal of the high-side drive and level conversion module is connected to the output terminal of the first inverter. The input terminal of the first inverter serves as the fourth input terminal of the rising edge zero-voltage enable circuit. The output terminal of the high-side drive and level conversion module serves as the output terminal of the rising edge zero-voltage enable circuit.

2. The zero-voltage turn-on circuit for the switching transistor in the switching power supply according to claim 1, characterized in that, The rising edge detection module includes a first to a fourth power transistor, a first current source, and a second current source; The drain of the first power transistor serves as the first input terminal of the rising edge detection module. The gates of the first to fourth power transistors are connected together and serve as the second input terminal of the rising edge detection module. The source of the first power transistor is connected to the source of the second power transistor. The drain of the second power transistor is connected to the output terminal of the first current source and serves as the first output terminal of the rising edge detection module. The input terminal of the first current source is connected to the input terminal of the second current source. The output terminal of the second current source is connected to the drain of the third power transistor and serves as the second output terminal of the rising edge detection module. The source of the third power transistor is connected to the source of the fourth power transistor. The drain of the fourth power transistor serves as the third input terminal of the rising edge detection module.

3. The zero-voltage turn-on circuit for the switching transistor in the switching power supply according to claim 1, characterized in that, The level conversion module includes a second inverter and a first level converter; The input terminal of the second inverter serves as the input terminal of the level conversion module, and the output terminal of the second inverter is connected to the first level converter. The output terminal of the first level converter serves as the output terminal of the level conversion module.

4. The zero-voltage turn-on circuit for the switching transistor in the switching power supply according to claim 1, characterized in that, The falling edge zero-voltage turn-on circuit includes a falling edge detection module, a second level converter, a second comparator, and a low-side drive and delay matching module. The input terminal of the second level converter serves as the first input terminal of the falling edge zero-voltage enable circuit. The output terminal of the second level converter is connected to the first input terminal of the falling edge detection module. The second input terminal of the falling edge detection module serves as the second input terminal of the falling edge zero-voltage enable circuit. The first output terminal of the falling edge detection module is connected to the negative input terminal of the second comparator. The second output terminal of the falling edge detection module is connected to the positive input terminal of the second comparator. The output terminal of the second comparator is connected to the first input terminal of the low-side drive and delay matching module. The second input terminal of the low-side drive and delay matching module serves as the third input terminal of the falling edge zero-voltage enable circuit. The output terminal of the low-side drive and delay matching module serves as the output terminal of the falling edge zero-voltage enable circuit.

5. The zero-voltage turn-on circuit for the switching transistor in the switching power supply according to claim 4, characterized in that, The falling edge detection module includes a fifth to eighth power transistor, a third current source, a fourth current source, a first pull-up resistor, a second pull-up resistor, and a third inverter; The drain of the fifth power transistor serves as the second input terminal of the falling edge detection module. The source of the fifth power transistor is connected to the source of the sixth power transistor. The gate of the fifth power transistor is connected to the gate of the sixth power transistor and then connected to the output terminal of the third inverter. The input terminal of the third inverter is connected to the gates of the seventh and eighth power transistors and then serves as the first input terminal of the falling edge detection module. The drain of the seventh power transistor is connected to the drain of the sixth power transistor and the first terminal of the first pull-up resistor. The source of the seventh power transistor is connected to the drain of the eighth power transistor. The source of the eighth power transistor is grounded. The second end of the first pull-up resistor is connected to the output end of the third current source and serves as the first output end of the falling edge detection module. The input end of the third current source is connected to the input end of the fourth current source. The output end of the fourth current source is connected to the first end of the second pull-up resistor and serves as the second output end of the falling edge detection module. The second end of the second pull-up resistor is grounded.

6. The zero-voltage turn-on circuit for the switching transistor in the switching power supply according to any one of claims 1 to 5, characterized in that, The switching power supply is a boost converter circuit; The boost converter circuit includes a high-side power transistor, a low-side power transistor, and an inductor. The zero-voltage turn-on circuit includes a rising-edge zero-voltage turn-on circuit and a falling-edge zero-voltage turn-on circuit. The high-side power transistor corresponds to the rising-edge zero-voltage turn-on circuit, and the low-side power transistor corresponds to the falling-edge zero-voltage turn-on circuit. The first end of the inductor is connected to the input voltage terminal, the second end of the inductor is connected to the switching node, and the parasitic capacitance is formed between the second end of the inductor and ground. In the rising edge zero voltage turn-on circuit, the first input terminal is connected to the output voltage terminal.

7. The zero-voltage turn-on circuit for the switching transistor in a switching power supply according to any one of claims 1 to 5, characterized in that, The switching power supply is a step-down converter circuit; The buck converter circuit includes a high-side power transistor, a low-side power transistor, and an inductor. The zero-voltage turn-on circuit includes a rising-edge zero-voltage turn-on circuit and a falling-edge zero-voltage turn-on circuit. The high-side power transistor corresponds to the rising-edge zero-voltage turn-on circuit, and the low-side power transistor corresponds to the falling-edge zero-voltage turn-on circuit. The first end of the inductor is connected to the switching node, the second end of the inductor is connected to the output voltage terminal, and the parasitic capacitance is formed between the first end of the inductor and ground. In the rising edge zero voltage turn-on circuit, the first input terminal is connected to the input voltage terminal.

8. The zero-voltage turn-on circuit for the switching transistor in a switching power supply according to any one of claims 1 to 5, characterized in that, The switching power supply is a step-up / step-down converter circuit; The buck-boost converter circuit includes two high-side power transistors, two low-side power transistors, and an inductor. The zero-voltage turn-on circuit includes two rising-edge zero-voltage turn-on circuits and two falling-edge zero-voltage turn-on circuits. Each high-side power transistor corresponds to one rising-edge zero-voltage turn-on circuit, and each low-side power transistor corresponds to one falling-edge zero-voltage turn-on circuit. The first end of the inductor is connected to a switching node, the second end of the inductor is connected to another switching node, and a parasitic capacitance is formed between the first end of the inductor and ground, and another parasitic capacitance is formed between the second end of the inductor and ground. In a rising-edge zero-voltage turn-on circuit connected to the first terminal of the inductor, the first input terminal is connected to the input voltage terminal. In a rising-edge zero-voltage turn-on circuit connected to the second terminal of the inductor, the first input terminal is connected to the output voltage terminal.

9. A method for zero-voltage switching of a high-voltage power supply, characterized in that, For use in a zero-voltage turn-on circuit as described in any one of claims 1 to 8, the method comprises: In critical conduction mode, when the low-side power transistor is turned off, the parasitic capacitance corresponding to the high-side power transistor is charged by the inductor current in the switching power supply, so that the switching node voltage of the switching node continues to rise during the dead time interval. The rising edge zero voltage turn-on circuit compares the switching node voltage with the input voltage or compares the switching node voltage with the output voltage under the control of the low-side gate drive voltage. When it is determined that the switching node voltage is equal to the input voltage or the output voltage, it outputs a high level to the high-side gate drive terminal, so as to control the high-side power transistor to achieve zero voltage turn-on through the high level. In critical conduction mode, when the high-side power transistor is turned off, the parasitic capacitance corresponding to the low-side power transistor is discharged by the inductor current in the switching power supply, so that the switching node voltage of the switching node continues to decrease during the dead time interval. The falling edge zero-voltage turn-on circuit compares the induced voltage with the pull-up resistor voltage under the control of the high-side gate drive voltage. When it is determined that the induced voltage is equal to the pull-up resistor voltage, it outputs a high level to the low-side gate drive terminal, so as to control the low-side power transistor to achieve zero-voltage turn-on through the high level. The induced voltage is equal to the sum of the pull-up resistor voltage and the switching node voltage.

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