Semiconductor process chamber and thin film deposition process

Abstract

The application provides a semiconductor process chamber and a thin film deposition process, and relates to the technical field of semiconductors.The semiconductor process chamber comprises a chamber body, a bearing assembly and a shielding assembly, the shielding assembly comprises a driving structure, a first shielding ring and a second shielding ring, the first shielding ring comprises a plurality of arc-shaped shielding segments along the circumference thereof, the driving structure is connected to each shielding segment and is configured to drive the radial movement of the shielding segments, the first shielding ring, the second shielding ring and a wafer are coaxially arranged, and the second shielding ring is configured to have an inner diameter greater than that of the first shielding ring, and the semiconductor process chamber can continuously perform two deposition cycles, and in the first deposition cycle and the second deposition cycle, the first shielding structure and the second shielding structure formed by the film layers deposited on the first shielding ring, the second shielding ring and the corresponding inner wall of the ring successively shield the edge dead zone of the wafer.The semiconductor process chamber can reduce the opening cleaning and maintenance frequency of the semiconductor process chamber, improve the maintenance convenience and the production capacity.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more particularly to a semiconductor process chamber and thin film deposition process. Background Technology

[0002] Thin film deposition is an important process in the fabrication of semiconductor devices. During thin film deposition, the back side of the wafer must be kept clean to ensure wafer quality and reduce contact contamination from metrology tools and other equipment.

[0003] In related technologies, some process chambers have a shielding ring with an inner diameter less than or equal to the wafer diameter placed above the wafer. This shields the wafer edge to reduce deposition contamination on the back side of the wafer during thin film deposition. However, during thin film deposition, the inner wall of the shielding ring also deposits a film layer. As the process progresses, the film thickness gradually increases, and the shielding area on the wafer edge also increases. When the shielding area is large enough to exceed the ineffective area of ​​the wafer edge, it significantly affects the plasma distribution within the process chamber, thus affecting the uniformity of the thin film deposited on the front side of the wafer. Based on this, the process chambers in related technologies generally determine the duration of the deposition cycle (PK life) based on the thin film deposition rate. After each deposition cycle, the process chamber needs to be shut down and the shielding ring needs to be disassembled, cleaned, and replaced to ensure the uniformity of the thin film deposited on the front side of the wafer. However, this operation also increases the maintenance cost of the process chamber and reduces its throughput. Summary of the Invention

[0004] The purpose of this invention is to provide a semiconductor process chamber and a thin film deposition process to solve the technical problem in related technologies that the thin film deposition process requires shutdown and opening of the chamber to disassemble, clean, and replace the shielding ring after each deposition cycle, resulting in high maintenance costs and low production capacity of the process chamber.

[0005] To address the above problems, the present invention provides a semiconductor process chamber, comprising:

[0006] The chamber body has an internal cavity;

[0007] A carrier component is disposed within the cavity, and the carrier component is configured to carry a wafer.

[0008] The shielding assembly includes a drive structure disposed on the chamber body and a first shielding ring and a second shielding ring disposed in the chamber. The first shielding ring includes a plurality of arc-shaped shielding segments along its circumference. The drive structure is connected to each of the shielding segments and is configured to drive the shielding segments to move radially away from the axis of the first shielding ring.

[0009] The first shielding ring, the second shielding ring, and the wafer are coaxially arranged and configured such that the inner diameter of the second shielding ring is larger than the inner diameter of the first shielding ring, and two consecutive deposition cycles can be performed. In the first deposition cycle, the first shielding structure formed by the film deposited on the first shielding ring and its inner wall shields the invalid edge region of the wafer. In the second deposition cycle, the second shielding structure formed by the film deposited on the second shielding ring and its inner wall shields the invalid edge region of the wafer.

[0010] Optionally, the difference between the diameter of the wafer and the inner diameter of the first shielding ring is 0 to 1 mm;

[0011] The second shielding ring is located above the first shielding ring. The difference between the inner diameter of the second shielding ring and the diameter of the wafer is 2d1. The thickness of the film deposited on the inner wall of the second shielding ring in the first deposition cycle is d2. The difference between d2 and d1 is 0 to 0.5 mm.

[0012] Alternatively, the second shielding ring is located below the first shielding ring, and the inner diameter of the second shielding ring is smaller than the diameter of the wafer.

[0013] Optionally, the second shielding ring is located above the first shielding ring, and the outer edge of the second shielding ring is surrounded by an upwardly extending side panel, the top of which is connected to the chamber body.

[0014] Optionally, the upper region of the cavity sidewall of the cavity is surrounded by an overlapping seat, and the top edge of the side panel is provided with a top flange, which overlaps the overlapping seat.

[0015] Optionally, the outer diameter of the first shielding ring is larger than the outer diameter of the second shielding ring.

[0016] Optionally, the carrier assembly includes a base and a deposition ring disposed on top of the base. The deposition ring includes a receiving boss located in an annular shape and a shielding edge surrounding the bottom end of the receiving boss, and the outer diameter of the shielding edge is larger than the diameter of the wafer.

[0017] Optionally, the outer diameter of the shielding edge is larger than the outer diameter of the second shielding ring.

[0018] Optionally, in the connecting ends of two adjacent shielding sections, one of them has an upper connecting groove and a lower connecting step, and the other has an upper connecting step and a lower connecting groove. The upper connecting step is inserted into the upper connecting groove, and the lower connecting step is inserted into the lower connecting groove.

[0019] Optionally, the driving structure includes a plurality of driving elements, each of which is connected to one of the blocking segments and configured to drive the corresponding blocking segment to move radially away from the axis of the first blocking ring.

[0020] The present invention also provides a thin film deposition process employing the above-mentioned semiconductor process chamber, the thin film deposition process comprising:

[0021] First deposition step: thin film deposition is performed on the wafer supported on the support substrate for a first preset time, wherein the first shielding ring and the film deposited on its inner wall form a first shielding structure, and the second shielding ring and the film deposited on its inner wall form a second shielding structure.

[0022] Adjustment step: Adjust the blocking section of the first blocking structure to move radially away from its axis until it avoids the area within the ring formed by the second blocking structure;

[0023] Second deposition step: Perform thin film deposition on the wafer supported on the substrate for a second preset time.

[0024] The semiconductor process chamber provided by this invention includes a shielding assembly comprising a second shielding ring and a first shielding ring that is spliced ​​together and capable of outward expansion. Considering the rate at which a film layer accumulates on the inner wall of the shielding assembly during the wafer deposition process, the relationship between the inner diameters of the first and second shielding rings and the wafer diameter is determined. This allows the semiconductor process chamber to effectively shield the wafer, prevent film deposition on the back side of the wafer, and ensure uniformity of the film deposition on the front side. It can then perform two consecutive deposition cycles before requiring a shutdown to open the chamber for cleaning and replacement of the shielding assembly. This doubles the deposition process time compared to related technologies, thereby reducing the frequency of chamber cleaning and maintenance, improving the ease of maintenance and production capacity of the process chamber, and reducing the waste of target materials.

[0025] The thin film deposition process provided by this invention uses the aforementioned semiconductor process chamber. While ensuring that the shielding component effectively shields the wafer, the back side of the wafer is not deposited with thin film, and the uniformity of the thin film deposited on the front side of the wafer is guaranteed, it can continuously perform two deposition cycles before needing to stop the machine to open the chamber for disassembly, cleaning, and replacement of the shielding component. Compared with the deposition process in related technologies, the deposition process time is doubled, thereby reducing the frequency of opening the semiconductor process chamber for cleaning and maintenance, improving the maintenance convenience and production capacity of the process chamber, and reducing the waste of target material resources. Attached Figure Description

[0026] To more clearly illustrate the technical solutions in the specific embodiments or related technologies of the present invention, the drawings used in the description of the specific embodiments or related technologies will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0027] Figure 1 This is a schematic diagram of the interior of a semiconductor process chamber in related technologies;

[0028] Figure 2 This is a schematic diagram of the interior of a semiconductor process chamber provided in an embodiment of the present invention;

[0029] Figure 3 A schematic diagram showing the initial relative orientation of the wafer, the first shielding ring, and the second shielding ring in a semiconductor process chamber provided for an embodiment of the present invention;

[0030] Figure 4 A schematic diagram showing the relative orientation of the wafer, the first shielding ring, and the second shielding ring after the first deposition cycle of the thin film deposition process in a semiconductor process chamber provided in an embodiment of the present invention.

[0031] Figure 5 A schematic diagram showing the relative orientation of the wafer, the first shielding ring, and the second shielding ring in a semiconductor process chamber provided in an embodiment of the present invention after the second deposition cycle of the thin film deposition process;

[0032] Figure 6 A schematic diagram showing the connection between the first shielding ring and the driving structure in a semiconductor process chamber provided in an embodiment of the present invention;

[0033] Figure 7 A schematic diagram showing the connection between the first shielding ring and the driving structure in a semiconductor process chamber provided in an embodiment of the present invention after the first deposition cycle of the thin film deposition process;

[0034] Figure 8 A schematic diagram of the connection between two adjacent shielding sections in a semiconductor process chamber provided for an embodiment of the present invention;

[0035] Figure 9 This is a schematic flowchart of a thin film deposition process according to an embodiment of the present invention.

[0036] Explanation of reference numerals in the attached figures:

[0037] 10-Wafer; 11-Deposition area; 12-Edge ineffective area; 100-Cavity body; 110-Cavity; 120-Cavity sidewall; 200-Supporting component; 210-Base; 220-Deposition ring; 221-Receiving boss; 222-Shielding edge; 300-Shielding component; 30A-First shielding structure; 30B-Second shielding structure; 30C-Inner liner; 310-Drive structure; 311-Driver; 31 2-Connecting rod; 320-First shielding ring; 321-Shielding section; 321a-Upper connecting groove; 321b-Lower connecting step; 321c-Upper connecting step; 321d-Lower connecting groove; 330-Second shielding ring; 340-First shielding film layer; 350-Second shielding film layer; 360-Side panel; 370-Top flange; 380-Overlap seat; 400-Target material; 500-Magnetron; 600-Shielding plate. Detailed Implementation

[0038] The technical solution of the present invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0039] In the description of this invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing the invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0040] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0041] Figure 1 This is a schematic diagram of the internal structure of a semiconductor process chamber in related technologies. For example... Figure 1As shown, the semiconductor process chamber includes a chamber body 100 that forms an internal cavity 110. A base 210 is provided in the lower region of the cavity 110, and a deposition ring 220 is provided on the top of the base 210. A liner 30C (Shield) is provided in the upper region of the cavity 110. A first shielding ring 320 is attached to the inner side of the liner 30C, and the bottom flange of the liner 30C serves as a second shielding ring 330. In use, wafer 10 is supported on the central region of the top surface of deposition ring 220. Wafer 10 includes a deposition area 11 located in the center where a thin film needs to be deposited and an edge ineffective area 12 located at the edge of wafer 10. The first shielding ring 320 is approximately coaxially arranged with wafer 10, and the inner diameter of the first shielding ring 320 is less than or equal to the diameter of wafer 10. When the base 210 drives deposition ring 220 and wafer 10 to move upward, the deposition position is reached when the edge of deposition ring 220 pushes up the first shielding ring 320. The first shielding ring 320 is located above wafer 10 and can shield the outer periphery of wafer 10 to prevent deposits from descending to the back of wafer 10 and causing deposition contamination.

[0042] Subsequently, a thin film deposition process is performed on wafer 10, and the duration of the deposition cycle is determined according to the thin film deposition rate. As the thin film deposition proceeds, while the deposition region 11 of wafer 10 is deposited to form a thin film, a film layer is also deposited on the inner wall of the first shielding ring 320, and the film layer thickness gradually increases. Consequently, the inner diameter of the first shielding structure 30A formed by the film layer deposited on the first shielding ring 320 and its inner wall gradually decreases, correspondingly shielding the edge invalid region 12, and the shielding area gradually increases. At the end of one deposition cycle, the shielding area of ​​the first shielding structure 30A on the edge invalid region 12 is close to the inner ring boundary of the edge invalid region 12. During this deposition cycle, the shielding area of ​​the first shielding structure 30A on the edge of wafer 10 is small, and its impact on the plasma distribution within the cavity 110 is minimal. To ensure uniform film deposition in the front deposition area 11 of wafer 10, if film deposition continues, the first shielding structure 30A will shield the edge of wafer 10 beyond the edge ineffective region 12, significantly affecting the plasma distribution within the cavity 110. This results in the uniformity of the film deposition in the deposition area 11 of wafer 10 being affected. Therefore, after one deposition cycle, it is necessary to shut down the process chamber and open it to disassemble, clean, and replace process components such as the first shielding ring 320. Subsequently, the cleaned first shielding ring 320 is reinstalled into the cavity body 100, and the next deposition cycle continues. This ensures the uniformity of the film deposition in the front deposition area 11 of wafer 10. However, the frequent shutdowns and openings of the process cavity, as well as the frequent disassembly and replacement of the first shielding ring 320, also lead to higher maintenance costs and lower production capacity for the process cavity.

[0043] This embodiment provides a semiconductor process chamber with a shielding assembly 300 including a second shielding ring 330 and a first shielding ring 320 that is spliced ​​together and capable of outward expansion. Considering the speed at which a film layer accumulates on the inner wall of the shielding assembly 300 during the deposition of a thin film onto the wafer 10, the relationship between the inner diameters of the first and second shielding rings 320 and the diameter of the wafer 10 is set. This allows the semiconductor process chamber to effectively shield the wafer 10 with the shielding assembly 300, ensuring that the back side of the wafer 10 is not deposited with a film and that the uniformity of the film deposited on the front side of the wafer 10 is guaranteed. Furthermore, the chamber can continuously perform two deposition cycles before needing to stop and open the chamber for cleaning and replacement of the shielding assembly 300. This doubles the deposition process time compared to related technologies, thereby reducing the frequency of opening the semiconductor process chamber for cleaning and maintenance, improving the ease of maintenance and production capacity of the process chamber, and reducing the waste of target material 400 resources. The semiconductor process chamber provided by this embodiment will be further described in detail below with reference to the accompanying drawings.

[0044] This invention provides a semiconductor process chamber, such as... Figure 2 As shown, the device includes a chamber body 100, a support assembly 200, and a shielding assembly 300. The chamber body 100 has a cavity 110 inside. The support assembly 200 is disposed within the cavity 110 and is configured to support a wafer 10. The shielding assembly 300 includes a drive structure 310 disposed in the chamber body 100 and a first shielding ring 320 and a second shielding ring 330 disposed within the cavity 110. The first shielding ring 320 includes multiple arc-shaped shielding segments 321 along its circumference. The drive structure 310 is connected to each shielding segment 321 and is configured to drive the shielding segments 321 radially away from the first shielding ring. The ring 320 moves along its axis; wherein the first shielding ring 320, the second shielding ring 330 and the wafer 10 are coaxially arranged and configured such that: the inner diameter of the second shielding ring 330 is larger than the inner diameter of the first shielding ring 320, and two deposition cycles can be performed continuously, wherein, in the first deposition cycle, the first shielding structure 30A formed by the film deposited on the first shielding ring 320 and its inner wall shields the edge invalid region 12 of the wafer 10; in the second deposition cycle, the second shielding structure 30B formed by the film deposited on the second shielding ring 330 and its inner wall shields the edge invalid region 12 of the wafer 10.

[0045] In the semiconductor process chamber provided in this embodiment of the invention, initially, as... Figure 1 , Figure 3 and Figure 6As shown, the first shielding ring 320 is in a spliced ​​state under the constraint of the driving component. The first shielding ring 320 and the second shielding ring 330 are arranged sequentially in the height direction and are coaxially arranged. When a thin film deposition process is required, the wafer 10 is transferred and carried on the bearing surface at the top of the bearing component 200. The first shielding ring 320 and the second shielding ring 330 are located above the wafer 10, and the first shielding ring 320, the second shielding ring 330 and the wafer 10 are coaxially arranged. The inner diameter of the first shielding ring 320 is smaller than the inner diameter of the second shielding ring 330. At the same time, the inner diameter of the first shielding ring 320 is less than or equal to the diameter of the wafer 10 and greater than the diameter of the inner ring boundary of the invalid region 12 at the edge of the wafer 10.

[0046] This embodiment also provides a thin film deposition process. Using the above-mentioned semiconductor process chamber, on the basis of ensuring that the shielding component 300 effectively shields the wafer 10, that the back side of the wafer 10 is not deposited with thin film, and that the uniformity of the thin film deposited on the front side of the wafer 10 is guaranteed, it is possible to continuously perform two deposition cycles before stopping the machine to open the chamber for disassembly, cleaning and replacement of the shielding component 300. Figure 9 This is a schematic flowchart of a thin film deposition process according to an embodiment of the present invention. Specifically, the thin film deposition process includes:

[0047] S102 First deposition step: Thin film deposition is performed on the wafer 10 supported on the support base 210 for a first preset time, wherein the film deposited on the first shielding ring 320 and its inner wall forms a first shielding structure 30A, and the film deposited on the second shielding ring 330 and its inner wall forms a second shielding structure 30B.

[0048] The semiconductor process chamber enters the first deposition cycle. During this deposition cycle, the first shielding ring 320 effectively shields the edge invalid region 12 of the wafer 10 to reduce deposition contamination caused by deposits reaching the back side of the wafer 10. As the thin film deposition of the front deposition region 11 of the wafer 10 proceeds, the top surface and inner wall of the first shielding ring 320 are simultaneously deposited to form the first shielding film layer 340. The thickness of the first shielding film layer 340 gradually increases, causing the inner diameter of the first shielding structure 30A formed by the first shielding ring 320 and the first shielding film layer 340 to gradually decrease. The shielding area of ​​the edge invalid region 12 of the wafer 10 gradually increases until the shielding area of ​​the first shielding structure 30A of the edge invalid region 12 of the wafer 10 approaches the inner ring boundary of the edge invalid region 12. The deposition time reaches the first preset duration, and the first deposition cycle ends.

[0049] In the first deposition cycle, the second shielding ring 330 can be located above or below the first shielding ring 320, such as... Figure 4As shown, when the second shielding ring 330 is above the first shielding ring 320, the top surface and inner wall of the second shielding ring 330 are simultaneously deposited to form a second shielding film 350, and the second shielding ring 330 and the second shielding film 350 together form the second shielding structure 30B; when the second shielding ring 330 is below the first shielding ring 320, the second shielding ring 330 is not deposited to form a film, and the second shielding ring 330 serves as the second shielding structure 30B. At the end of the first deposition cycle, the inner diameter of the second shielding structure 30B is less than or equal to the diameter of the wafer 10 and greater than the diameter of the inner ring boundary of the edge invalid region 12.

[0050] S104 Adjustment step: Adjust the blocking section 321 of the first blocking structure 30A to move radially away from its axis until it avoids the area within the ring formed by the second blocking structure 30B.

[0051] Then, adjustment steps are performed, such as... Figure 5 and Figure 7 As shown, the adjustment drive structure 310 drives multiple blocking segments 321 of the first blocking ring 320 to move radially away from the axis of the second blocking ring 330 until the radial distance between each blocking segment 321 and the axis of the second blocking ring 330 is greater than the inner radius of the second blocking structure 30B. That is, each blocking segment 321 moves radially to the area outside the inner wall of the second blocking structure 30B, avoiding the inner area enclosed by the second blocking structure 30B.

[0052] S106 Second deposition step: Perform thin film deposition on the wafer 10 supported on the support base 210 for a second preset time.

[0053] Continue with the second deposition step, such as Figure 5 As shown, the semiconductor process chamber enters the second deposition cycle. In this deposition cycle, the second shielding structure 30B effectively shields the edge invalid region 12 of the wafer 10 to further reduce the deposition contamination caused by the deposits reaching the back side of the wafer 10. As the thin film is deposited on the front side of the wafer 10, the front side and inner ring wall of the second shielding structure 30B are also continuously deposited to form the second shielding film layer 350. The shielding area of ​​the second shielding structure 30B on the edge invalid region 12 gradually increases until the shielding area of ​​the second shielding structure 30B on the edge invalid region 12 approaches the inner ring boundary of the edge invalid region 12. The deposition time reaches the second preset duration, and the second deposition cycle ends.

[0054] Subsequently, the semiconductor process chamber is shut down and opened, the shielding component 300 is disassembled, removed, cleaned, and replaced. This ensures that the shielding component 300 effectively shields the wafer 10, prevents the deposition of thin film on the back side of the wafer 10, and guarantees the uniformity of the deposition film on the front side of the wafer 10. It allows for two consecutive deposition cycles before the chamber needs to be shut down and the shielding component 300 needs to be disassembled, cleaned, and replaced. This doubles the deposition process time compared to related technologies, thereby reducing the frequency of opening, cleaning, and maintenance of the semiconductor process chamber, improving the ease of maintenance and production capacity of the process chamber, and reducing the waste of target material 400 resources.

[0055] Specifically, such as Figure 2 As shown, a target material 400 is provided in the upper region of the cavity 110, and a magnetron 500 is provided above the target material 400. The magnetron 500 applies an action to the target material 400, causing a deposit to form below the target material 400 and deposit downwards onto the deposition region 11 of the wafer 10 to form a thin film. A shielding disk 600 may also be provided in the lower region of the cavity 110.

[0056] In embodiments of the present invention, such as Figure 8 As shown, in the connecting ends of two adjacent blocking segments 321, one has an upper connecting groove 321a at the top and a lower connecting step 321b at the bottom, while the other has an upper connecting step 321c at the top and a lower connecting groove 321d at the bottom. The upper connecting step 321c is inserted into the upper connecting groove 321a, and the lower connecting step 321b is inserted into the lower connecting groove 321d. The upper connecting step 321c and the lower connecting step 321b are arranged to overlap vertically, resulting in overlapping areas in both the radial and circumferential directions. During adjustment, the drive structure 310 drives each blocking segment 321 to move radially towards the cavity sidewall 120 of the corresponding area. This causes adjacent blocking segments 321 to move away from each other at a certain angle. Within the adjustable range, although the corresponding upper connecting step 321c and lower connecting step 321b move away from each other, they still have overlapping areas, allowing for adjustment of the radial... Each shielding segment 321, even as its size increases, remains a closed ring. This ensures that while the first shielding ring 320 can be radially adjusted to avoid obstructing the second shielding ring 330, the circumferential shielding of the first shielding ring 320 is maintained. Consequently, the leakage of light through the gap between two adjacent shielding segments 321 during the second deposition cycle is reduced. This ensures the isolation between the upper and lower cavities, reduces the deposition contamination caused by upper cavity deposits entering the lower cavity and affecting the cavity wall and the outer wall of the support assembly 200, and ensures the ease of maintenance and production capacity of the semiconductor process chamber.

[0057] Specifically, in the embodiments of the present invention, such as Figure 6 and Figure 7As shown, the drive structure 310 includes multiple drive members 311, each connected to one of the blocking sections 321, configured to drive the corresponding blocking section 321 to move radially away from the axis of the first blocking ring 320. The number of drive members 311 is equal to the number of blocking rings. Each drive member 311 is connected to the cavity sidewall 120 of the chamber body 100. The multiple drive members 311 are arranged circumferentially along the cavity sidewall 120 and are respectively connected to one of the blocking sections 321 at the circumferential center position. During the adjustment step, each drive member 311 operates synchronously and drives the multiple blocking sections 321 to move synchronously outward along their radial direction, thereby achieving synchronous drive of the multiple blocking sections 321. Specifically, the drive member 311 can be a linear motor, and the drive end of the drive member 311 is connected to the corresponding blocking section 321 through a connecting rod 312.

[0058] In this embodiment of the invention, the difference between the diameter of the wafer 10 and the inner diameter of the first shielding ring 320 is 0-1 mm. At the start of the first deposition cycle, the first shielding ring 320 shields the edge ineffective region 12 radially by 0-0.5 mm. This ensures effective shielding of the wafer 10 edge by the first shielding ring 320 during the early stages of the first deposition cycle, preventing deposition contamination of the back side of the wafer 10. Furthermore, it ensures a large radial distance between the inner wall of the first shielding ring 320 and the inner ring boundary of the edge ineffective region 12. This guarantees a longer first preset duration for the first deposition cycle and reduces the occurrence of the shielding range of the first shielding film layer 340 deposited on the first shielding ring 320 exceeding the inner ring boundary at the end of the first deposition cycle. Consequently, it further ensures the uniformity of the thin film deposited on the front side of the wafer 10, ensures the yield of semiconductor devices fabricated in the semiconductor process chamber, and further reduces the frequency of opening and cleaning maintenance of the semiconductor process chamber, improving the ease of maintenance and productivity of the process chamber.

[0059] In this embodiment of the invention, the second shielding ring 330 may be located above or below the first shielding ring 320. When the second shielding ring 330 is located above the first shielding ring 320, the difference between the inner diameter of the second shielding ring 330 and the diameter of the wafer 10 is 2d1, and the thickness of the film deposited on the inner wall of the second shielding ring 330 in the first deposition cycle is d2, and the difference between d2 and d1 is 0 to 0.5 mm.

[0060] In the first deposition cycle, the second shielding ring 330 is located above the first shielding ring 320. As the thin film deposition proceeds in the deposition region 11 of wafer 10, the top surface and inner wall of the second shielding ring 330 are simultaneously deposited with film to form the second shielding structure 30B. The first shielding ring 320 extends radially inward, and the top surface and inner wall of the second shielding ring 330 are also simultaneously deposited with film to form the first shielding structure 30A. The inner diameter of the first shielding structure 30A is always smaller than the inner diameter of the second shielding structure 30B. The first shielding structure 30A maintains its position relative to the edge of wafer 10. Effective shielding of edge ineffective region 12; at the end of the first deposition cycle, the inner wall of the first shielding structure 30A is close to the inner ring boundary of the edge ineffective region 12, and the inner diameter of the second shielding structure 30B is 2d2 smaller than the inner diameter of the first shielding ring 320. Since the inner diameter of the second shielding ring 330 is larger than the diameter of the wafer 10, and the radial distance d1 between the inner wall of the second shielding ring 330 and the outer edge of the wafer 10 is 0-0.5mm smaller than d2, the shielding range of the second shielding structure 30B on the edge ineffective region 12 in the radial direction is 0-0.5mm.

[0061] Correspondingly, at the beginning of the second deposition cycle, the second shielding structure 30B has a radial shielding range of 0-0.5 mm for the edge invalid region 12. This ensures effective shielding of the wafer 10 edge by the second shielding structure 30B during the early stage of the second deposition cycle, preventing deposition contamination of the back side of the wafer 10. Furthermore, it ensures a large radial distance between the inner wall of the second shielding structure 30B and the inner ring boundary of the edge invalid region 12. This guarantees a longer second preset duration for the second deposition cycle and reduces the occurrence of the second shielding film layer 350 deposited on the second shielding ring 330 exceeding the inner ring boundary at the end of the second deposition cycle. This further ensures the uniformity of the thin film deposited on the front side of the wafer 10, guarantees the yield of semiconductor devices fabricated in the semiconductor process chamber, and further reduces the frequency of opening and cleaning maintenance of the semiconductor process chamber, improving the ease of maintenance and productivity of the process chamber.

[0062] When the second shielding ring 330 is located below the first shielding ring 320, the inner diameter of the second shielding ring 330 is smaller than the diameter of the wafer 10, while the inner diameter of the second shielding ring 330 is larger than the inner diameter of the first shielding ring 320. During the first deposition cycle, as the thin film deposition proceeds in the deposition region 11 of wafer 10, the top surface and inner wall of the first shielding ring 320 are simultaneously deposited with a first shielding film layer 340 to form a first shielding structure 30A. The second shielding ring 330 is shielded by the first shielding ring 320 and no film layer is formed. At the end of the first deposition cycle, the inner wall of the first shielding structure 30A is close to the inner ring boundary of the edge invalid region 12. The second shielding ring 330 maintains its initial state and provides radial shielding to the edge invalid region 12 with a shielding range of less than 0.5 mm. Correspondingly, at the beginning of the second deposition cycle, the radial shielding range of the second shielding ring 330 to the edge invalid region 12 is less than 0.5 mm. This can further ensure the uniformity of the thin film deposited on the front side of wafer 10, ensure the yield of semiconductor devices fabricated in the semiconductor process chamber, and further reduce the frequency of opening and cleaning maintenance of the semiconductor process chamber, thereby improving the maintenance convenience and productivity of the process chamber.

[0063] In this embodiment of the invention, when the second shielding ring 330 is located above the first shielding ring 320, an upwardly extending side plate 360 ​​is provided around the outer edge of the second shielding ring 330, and the top end of the side plate 360 ​​is connected to the cavity body 100. The second shielding ring 330 and the side plate 360 ​​together form the liner 30C. During thin film deposition, the liner 30C, the first shielding ring 320, and the wafer 10 together divide the cavity 110 into an upper cavity and a lower cavity. The side plate 360 ​​can also provide a barrier protection for the cavity sidewall 120 of the upper cavity. Thus, while achieving the effective shielding effect of the second shielding ring 330 on the invalid region 12 at the edge of the wafer 10 during the second deposition cycle, the functionality of the second shielding ring 330 is improved, and the contamination caused by the thin film deposition on the cavity sidewall 120 and the support component 200 is reduced. Consequently, the maintenance convenience and production capacity of the semiconductor process cavity are further improved.

[0064] In embodiments of the present invention, such as Figure 2 As shown, the upper region of the cavity sidewall 120 of the cavity 110 is surrounded by a mounting base 380, and the top edge of the side panel 360 is provided with a top flange 370, which overlaps with the mounting base 380. The liner 30C is connected to the cavity body 100 by overlapping the mounting base 380 with the top flange 370, which makes disassembly and assembly more convenient and ensures the ease of cleaning and replacement of the liner 30C, thereby ensuring the ease of maintenance of the semiconductor process cavity.

[0065] In embodiments of the present invention, such as Figure 2As shown, the outer diameter of the first blocking ring 320 is larger than the outer diameter of the second blocking ring 330. The outer wall of the first shielding ring 320 and the cavity sidewall 120 of the cavity 110 are provided for radial position adjustment of the first shielding ring 320 during adjustment steps. In the first deposition cycle, the inner wall of the first shielding ring 320 extends the second shielding ring 330 radially inward, while the outer wall of the first shielding ring 320 extends the second shielding ring 330 radially outward. Thus, the first shielding ring 320 can block the upper and lower cavities with a large area. At the same time, the second shielding ring 330 provides secondary shielding above the first shielding ring 320. In the second deposition cycle, the first shielding ring 320 moves radially closer to the cavity sidewall 120. The second shielding ring 330 and the first shielding ring 320 are arranged alternately with a large overlap area, thereby ensuring the comprehensive isolation of the upper and lower cavities by the shielding component 300 throughout the two deposition cycles, effectively reducing the deposition contamination caused by sediment entering the lower cavity and affecting the bearing component 200 and the cavity wall.

[0066] In embodiments of the present invention, such as Figure 2 As shown, the carrier component 200 includes a base 210 and a deposition ring 220 disposed on the top of the base 210. The deposition ring 220 includes a receiving boss 221 located in the annular shape and a shielding edge 222 surrounding the bottom end of the receiving boss 221. The outer diameter of the shielding edge 222 is larger than the diameter of the wafer 10. The receiving boss 221 is arranged within the ring of the shielding edge 222 and protrudes upward relative to the shielding edge 222. In the first deposition cycle, the receiving boss 221 carries the wafer 10. The shielding edge 222 and the first shielding ring 320 have a radially overlapping area. The shielding edge 222 can provide secondary shielding for the gap between the first shielding ring 320 and the wafer 10, thereby increasing the difficulty for the deposits in the upper cavity to enter the lower cavity through the gap between the first shielding ring 320 and the wafer 10. This further improves the isolation between the upper and lower cavities, reduces the deposition contamination caused by the deposits in the upper cavity entering the lower cavity and affecting the cavity wall and the outer wall of the carrier component 200, and correspondingly further improves the maintenance convenience and production capacity of the semiconductor process chamber.

[0067] In embodiments of the present invention, such as Figure 2 As shown, the outer diameter of the shielding edge 222 is larger than the outer diameter of the second shielding ring 330. In both the first and second deposition cycles, the shielding edge 222 and both the first and second shielding rings 320 and 330 have a large radial overlap, thus ensuring the isolation between the upper and lower cavities. This, in turn, ensures the cleanliness of the lower cavity throughout the deposition process, thereby improving the ease of maintenance and productivity of the semiconductor process chamber.

[0068] For example, the diameter of wafer 10 can be 300 mm. The radial dimension of the edge invalid region 12 of wafer 10 is determined to be 2 mm based on the size of the blank area at the edge of wafer 10 and the axial distance between the first shielding ring 320, the second shielding ring 330 and wafer 10. The first shielding ring 320 is located below the second shielding ring 330, and the inner diameter of the first shielding ring 320 is 299 mm, and the inner diameter of the second shielding ring 330 is 302 mm. The radial thickness of the shielding film layer accumulated on the inner walls of the first shielding ring 320 and the second shielding ring 330 in one deposition cycle is approximately 1.5 mm.

[0069] First, the first deposition step is performed, such as... Figure 3 As shown, the first shielding ring 320 effectively shields the wafer 10. Initially, the radial shielding distance of the first shielding ring 320 to the ineffective region 12 at the edge of the wafer 10 is 0.5 mm. As thin film deposition progresses, as... Figure 4 As shown, the radial thickness of the first shielding film 340 deposited on the inner wall of the first shielding ring 320 gradually increases until the radial thickness of the first shielding film 340 reaches 1.5 mm. At this point, the deposition time reaches the first preset time, the inner diameter of the first shielding structure 30A formed by the first shielding ring 320 and the first shielding film 340 shrinks to 296 mm, and the radial shielding distance of the first shielding structure 30A to the edge ineffective region 12 reaches 2 mm. The shielding range is close to the inner ring boundary of the edge ineffective region 12, and the first deposition cycle ends. During the first deposition cycle, the radial thickness of the second shielding film 350 formed on the inner wall of the second shielding ring 330 is also approximately 1.5 mm. The inner diameter of the second shielding structure 30B formed by the second shielding ring 330 and the second shielding film 350 shrinks to 299 mm.

[0070] Then, adjustment steps are performed, such as... Figure 5 As shown, the driving structure 310 drives each shielding segment 321 of the first shielding ring 320 to move radially outward by a distance greater than 1.5mm, so that each shielding segment 321 is located radially outside the ring area of ​​the second shielding structure 30B, so that the second shielding structure 30B effectively shields the wafer 10.

[0071] Continue with the second deposition step, such as Figure 5As shown, the second shielding structure 30B effectively shields the wafer 10. The radial shielding distance of the second shielding structure 30B to the edge invalid region 12 of the wafer 10 is 0.5 mm. As the thin film deposition proceeds, the radial thickness of the second shielding film layer 350 deposited on the inner wall of the second shielding ring 330 continues to increase until the radial thickness of the second shielding film layer 350 increases by 1.5 mm relative to the first deposition cycle. At this point, the deposition time reaches the second preset time, the inner diameter of the second shielding structure 30B shrinks to 296 mm, and the radial shielding distance of the second shielding structure 30B to the edge invalid region 12 reaches 2 mm. The shielding range is close to the inner ring boundary of the edge invalid region 12, and the second deposition cycle ends.

[0072] Subsequently, the semiconductor process chamber is shut down and opened, the shielding component 300 is disassembled, removed, cleaned, and replaced. This ensures that the shielding component 300 effectively shields the wafer 10, prevents the deposition of thin film on the back side of the wafer 10, and guarantees the uniformity of the deposition film on the front side of the wafer 10. It allows for two consecutive deposition cycles before the chamber needs to be shut down and the shielding component 300 needs to be disassembled, cleaned, and replaced. This doubles the deposition process time compared to related technologies, thereby reducing the frequency of opening, cleaning, and maintenance of the semiconductor process chamber, and improving the ease of maintenance and production capacity of the process chamber.

[0073] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A thin film deposition process, characterized in that, The semiconductor process chamber includes: a chamber body (100) with an internal cavity (110); A carrier component (200) is disposed within the cavity (110), and the carrier component (200) is configured to carry a wafer (10). The shielding assembly (300) includes a drive structure (310) disposed in the cavity body (100) and a first shielding ring (320) and a second shielding ring (330) disposed in the cavity (110). The first shielding ring (320) includes a plurality of arc-shaped shielding segments (321) along its circumference. The drive structure (310) is connected to each of the shielding segments (321) and is configured to drive the shielding segments (321) to move radially away from the axis of the first shielding ring (320). The first shielding ring (320), the second shielding ring (330) and the wafer (10) are coaxially arranged. The second shielding ring (330) is configured such that its inner diameter is larger than that of the first shielding ring (320), and it is capable of performing two consecutive deposition cycles. In the first deposition cycle, the first shielding structure (30A) formed by the film deposited on the inner wall of the first shielding ring (320) shields the edge invalid region (12) of the wafer (10). In the second deposition cycle, the second shielding structure (30B) formed by the film deposited on the inner wall of the second shielding ring (330) shields the edge invalid region (12) of the wafer (10). The thin film deposition process includes: First deposition step: Thin film deposition is performed on the wafer (10) supported on the support base (210) for a first preset time, wherein the first shielding ring (320) and the film deposited on its inner wall form a first shielding structure (30A), and the second shielding ring (330) and the film deposited on its inner wall form a second shielding structure (30B). Adjustment step: Adjust the blocking section (321) of the first blocking structure (30A) to move radially away from its axis until it avoids the area within the ring formed by the second blocking structure (30B); Second deposition step: Perform thin film deposition on the wafer (10) supported on the support substrate (210) for a second preset time.

2. The thin film deposition process according to claim 1, characterized in that, The difference between the diameter of the wafer (10) and the inner diameter of the first shielding ring (320) is 0~1mm; The second shielding ring (330) is located above the first shielding ring (320). The difference between the inner diameter of the second shielding ring (330) and the diameter of the wafer (10) is 2d1. The thickness of the film deposited on the inner wall of the second shielding ring (330) in the first deposition cycle is d2. The difference between d2 and d1 is 0~0.5mm. Alternatively, the second shielding ring (330) is located below the first shielding ring (320), and the inner diameter of the second shielding ring (330) is smaller than the diameter of the wafer (10).

3. The thin film deposition process according to claim 1, characterized in that, The second shielding ring (330) is located above the first shielding ring (320), and the outer edge of the second shielding ring (330) is surrounded by an upwardly extending side panel (360), the top of which is connected to the chamber body (100).

4. The thin film deposition process according to claim 3, characterized in that, The upper region of the cavity sidewall (120) of the cavity (110) is surrounded by an overlapping seat (380), and the top edge (370) is provided around the top edge of the side panel (360), which overlaps the overlapping seat (380).

5. The thin film deposition process according to any one of claims 1-4, characterized in that, The outer diameter of the first shielding ring (320) is larger than the outer diameter of the second shielding ring (330).

6. The thin film deposition process according to any one of claims 1-4, characterized in that, The carrier component (200) includes a base (210) and a deposition ring (220) disposed on the top of the base (210). The deposition ring (220) includes a receiving boss (221) located in the ring and a shielding edge (222) surrounding the bottom ring of the receiving boss (221). The outer diameter of the shielding edge (222) is larger than the diameter of the wafer (10).

7. The thin film deposition process according to claim 6, characterized in that, The outer diameter of the shielding edge (222) is greater than the outer diameter of the second shielding ring (330).

8. The thin film deposition process according to any one of claims 1-4, characterized in that, In the connecting ends of two adjacent shielding sections (321), one of them has an upper connecting groove (321a) at the top and a lower connecting step (321b) at the bottom, while the other has an upper connecting step (321c) at the top and a lower connecting groove (321d) at the bottom. The upper connecting step (321c) is inserted into the upper connecting groove (321a), and the lower connecting step (321b) is inserted into the lower connecting groove (321d).

9. The thin film deposition process according to any one of claims 1-4, characterized in that, The drive structure (310) includes a plurality of drive members (311), each of which is connected to one of the shielding segments (321) and is configured to drive the corresponding shielding segment (321) to move radially away from the axis of the first shielding ring (320).

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