An exposure method, system, and semiconductor device

Abstract

This application provides an exposure method, system, and semiconductor device, relating to the field of semiconductor technology. Addressing the difference in crystal plane height between the edge and center regions of a wafer, this application, when performing a second exposure process to eliminate bridging defects, divides the wafer into multiple exposure blocks and determines suitable exposure parameters for each exposure block based on the first exposure process prior to the second exposure process. This allows for the corresponding second exposure process to be performed on exposure blocks with different crystal plane heights, avoiding the situation where the overall exposure parameters are difficult to adapt to regions with different crystal plane heights (especially the lower-height edge regions) when performing the second exposure process on the entire wafer. Furthermore, in determining the exposure parameters, this application uses simulation algorithms to determine the impact of different exposure parameters at different crystal plane heights on critical dimension correction when the first exposure process parameters are fixed, thereby determining suitable exposure parameters for each crystal plane height and improving the accuracy of critical dimensions in semiconductor devices.

Description

Technical Field

[0001] This application relates to semiconductor technology, specifically to an exposure method, system, and semiconductor device. Background Technology

[0002] The exposure process of photoresist is a particularly important process in semiconductor fabrication. Specifically, when forming a specific semiconductor structure on a wafer, photoresist can be coated on the wafer, and then the photoresist can be modified locally through an exposure process to achieve patterning of the photoresist. Then, the specific semiconductor structure can be fabricated based on the patterned photoresist layer.

[0003] As semiconductor device structures become increasingly complex, some structures (such as the pixel layer of an image sensor) often require a thicker layer of photoresist for fabrication. However, in exposure processes using thicker photoresist, a single exposure often only shapes the critical bottom dimensions, while bridging defects form in the upper part of the photoresist. Therefore, optimizing the exposure process to eliminate bridging defects is a crucial technical problem that needs to be solved by those skilled in the art. Summary of the Invention

[0004] In view of this, embodiments of this application provide an exposure method, system, and semiconductor device, which employs a double exposure process for thicker photoresist and eliminates bridging defects formed within the photoresist through a subsequent second exposure process, thereby improving the accuracy of semiconductor structure formation.

[0005] In a first aspect, this application provides an exposure method applied to a photoresist exposure system. The exposure method includes: in response to a target wafer coated with photoresist being placed on a workpiece stage, determining the crystal plane height of each exposure block of the target wafer; determining first target exposure parameters for a first exposure process, wherein the exposure depth range based on the focus position in the first target exposure parameters covers the interface between the photoresist and the target wafer; determining a first correlation between different crystal plane heights and critical dimension deviations in the target wafer after performing the first exposure process; performing a second exposure simulation for the target exposure blocks based on the target crystal plane height after performing the first exposure process, determining a second correlation between the second exposure parameters and critical dimension compensation at the target crystal plane height, wherein the second exposure parameters include at least the focus position; determining second target exposure parameters for eliminating the target crystal plane height based on the first and second correlations, thereby determining the second target exposure parameters for each exposure block; performing the first exposure process based on the first target exposure parameters, and then sequentially performing the second exposure process on each exposure block based on the second target exposure parameters for each exposure block.

[0006] Secondly, this application provides a photoresist exposure system, comprising: an exposure device for releasing an exposure beam; a workpiece stage for carrying a wafer; and a controller communicatively connected to the exposure device and the workpiece stage for controlling the exposure device and the workpiece stage based on the exposure method described in the first aspect.

[0007] Thirdly, this application provides a semiconductor device fabricated based on the exposure method described in the first aspect.

[0008] The exposure method, system, and semiconductor device provided in this application address the difference in crystal plane height between the edge and center regions of a wafer. When performing a second exposure process to eliminate bridging defects, this application divides the wafer into multiple exposure blocks and determines suitable exposure parameters for each exposure block based on the first exposure process prior to the second exposure process. This allows for the corresponding second exposure process to be performed on exposure blocks with different crystal plane heights, avoiding the situation where the overall exposure parameters are difficult to adapt to regions with different crystal plane heights (especially the lower-height edge regions) when performing the second exposure process on the entire wafer. Furthermore, when determining the exposure parameters, this application uses simulation algorithms to determine the impact of different exposure parameters at different crystal plane heights on critical dimension correction when the first exposure process parameters are fixed, thereby determining suitable exposure parameters for each crystal plane height and improving the accuracy of critical dimensions in the semiconductor device. Attached Figure Description

[0009] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0010] Figure 1 This is a schematic diagram of the structure of a photoresist exposure system provided in some embodiments of this application.

[0011] Figure 2 This is a schematic diagram of the crystal plane height distribution of a wafer provided in some embodiments of this application.

[0012] Figure 3 This is an exemplary flowchart of an exposure method provided in some embodiments of this application.

[0013] Figure 4 This is a schematic diagram of fitting a first correlation relationship provided by some embodiments of this application.

[0014] Figure 5 This is a schematic diagram of fitting a second correlation relationship provided in some embodiments of this application.

[0015] Figure 6 This is an exemplary flowchart of the second exposure process execution procedure provided in some embodiments of this application.

[0016] Figure 7 This is an exemplary flowchart of a second exposure parameter determination process provided in some embodiments of this application.

[0017] Figure 8 This is an exemplary flowchart of a second exposure parameter determination process provided in some embodiments of this application. Detailed Implementation

[0018] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0019] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the shape, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0020] In this invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first" and "second" are used only for descriptive and distinguishing purposes and should not be construed as indicating or implying relative importance.

[0021] Application Overview:

[0022] To further illustrate the photoresist exposure process, this application also provides a schematic diagram of a photoresist exposure system. Figure 1 ).

[0023] like Figure 1 As shown, the wafer photoresist exposure system 100 may include an exposure device 110 and a workpiece stage 120. The exposure device 110 is used to release the exposure beam and generally includes an optical system 111, a mask system 112, and auxiliary systems (not shown in the figure).

[0024] Optical system 111 can be used to generate an exposure beam, and may include a light source generating device (such as a laser) for generating the exposure beam and an optical projection device (generally a combination of optical components) for spatially modulating the exposure beam. Mask system 112 is disposed between optical system 111 and stage along the propagation direction of the exposure beam, and is used to load and control mask 220 for the exposure process. Mask 220 can selectively transmit the exposure beam, allowing the pattern on mask 220 to be transferred to the photoresist layer on wafer 210. Auxiliary systems may be other related devices that assist in the execution of the exposure process. For example, an alignment system may be included for aligning mask 220 with existing patterns on wafer 210.

[0025] The stage 120 can be used to hold the wafer 210 to be exposed. The stage 120 often has spatial movement capability so that the exposure beam is focused on the photoresist layer on the wafer 210 to achieve exposure of the photoresist layer. That is, when the wafer is placed on the stage 120, the exposure device 110 can load the corresponding mask layer 220 and align it. After alignment, an exposure beam can be generated to perform the corresponding exposure process on the wafer 210 on the stage 120.

[0026] Based on the modulation of the aforementioned optical system 111, the exposure beam has a certain depth of focus (DOF) range depending on its focal position. This depth of focus range refers to the defocus range that can maintain image sharpness and quality. It generally presents as a symmetrical range distributed along the longitudinal direction (i.e., the photoresist stacking direction) with the focal position as the center of symmetry. For example, an exposure depth of focus range of 0.4 μm can be understood as the image on the photoresist formed by the exposure process continuously maintaining sharpness (i.e., meeting the requirements for pattern resolution and morphology) within a range of ±0.2 μm from the focal position.

[0027] During the exposure process, to shape the critical dimensions of the substrate, the exposure process prioritizes focusing on the area near the interface between the photoresist and the substrate, ensuring that the exposure focus covers this interface. By precisely controlling the exposure dose, sufficient photochemical reaction is ensured on the photoresist substrate, resulting in a clear and dimensionally accurate substrate pattern after development. This guarantees the stability of the semiconductor structure formed in subsequent fabrication processes.

[0028] However, in the fabrication of some semiconductor devices, thicker photoresists are often required to create microstructures with high aspect ratios (for example, the fabrication of shallow trench isolation structures of 2500 Å in image sensors requires thicker photoresists). With thicker photoresists, prioritizing the shaping of the bottom critical dimension (CD) may result in the upper portion of the photoresist being outside the aforementioned depth of focus, leading to defocus defects. This can result in insufficient exposure of this portion of the photoresist, creating bridge defects.

[0029] To eliminate the aforementioned issues, compensatory exposure can be performed after the bottom critical dimensions have been shaped, based on the defects that have formed. This is achieved by supplementing the exposure of the upper portion of the photoresist, which is prone to bridging defects, to eliminate these defects. Therefore, to distinguish between the two types of exposure, the exposure process used to shape the bottom critical dimensions can be referred to as the first exposure process, and the exposure process used to eliminate bridging defects can be referred to as the second exposure process.

[0030] This application further discovers that before the exposure process, the wafer often exhibits significant differences in crystal plane height due to other processes. In particular, processes such as edge washing often result in a significant difference between the crystal plane height at the wafer edge and that at the wafer center.

[0031] To further illustrate this point, this application provides a schematic diagram of the crystal plane height distribution of a CMOS image sensor (CIS) wafer as an example. Figure 2 ).

[0032] exist Figure 2 In the height distribution diagram shown, a circular border represents a wafer, and the rectangular array on it reflects the various partitions. Wafer surface height can be represented by grayscale, where black indicates a higher crystal plane height, and white indicates a lower crystal plane height. Based on... Figure 2 It can be observed that the crystal plane height is higher in the central part of the wafer, while the crystal plane height is lower in the edge region of the wafer.

[0033] Specifically, in the fabrication process of CMOS image sensors (CIS), the height difference between the crystal planes on the wafer surface can reach 0.3 μm. This is generally not something that can be optimized through process optimization.

[0034] Based on the aforementioned differences in crystal plane height, the first exposure process can be configured according to the crystal plane height to comprehensively cover the interface between the photoresist and the wafer. Due to these differences in crystal plane height, the varying depth of focus of the first exposure process relative to the photoresist often leads to different critical dimension deviations at different crystal plane heights (e.g., different critical dimensions at the photoresist surface furthest from the wafer). Even with compensation using a second lithography process, the globally executed second lithography process cannot adapt to the different critical dimension deviations caused by varying crystal plane heights. Consequently, the photoresist compensated by the second lithography process (especially in areas with lower crystal plane heights) may still exhibit defocus defects, potentially leading to the continued existence of bridging defects.

[0035] To address the aforementioned technical problems, this application adjusts the execution method of the second exposure process and improves the parameter determination logic of the second parameter exposure process. Addressing the difference in crystal plane height between the wafer edge and center regions, this application divides the wafer into multiple exposure blocks when performing the second exposure process to eliminate bridging defects. Based on the first exposure process prior to the second exposure process, suitable exposure parameters are determined for each exposure block. This allows for the corresponding second exposure process to be performed on exposure blocks with different crystal plane heights, avoiding the situation where the overall exposure parameters are difficult to adapt to regions with different crystal plane heights (especially the lower-height edge regions) when performing the second exposure process on the entire wafer. Furthermore, in determining the exposure parameters, this application uses simulation algorithms to determine the impact of different exposure parameters at different crystal plane heights on critical dimension correction when the first exposure process parameters are fixed. This allows for the determination of suitable exposure parameters at each crystal plane height, improving the accuracy of critical dimensions in semiconductor devices.

[0036] The following is combined Figures 3-8 The exposure method provided in this application is described in detail.

[0037] Exemplary exposure method:

[0038] To further illustrate the exposure method provided in this application, an exemplary flowchart of the exposure method is also provided ( Figure 3 ).in, Figure 3 The exposure method P300 shown can be executed by the controller in the aforementioned exposure system 100. The controller of the exposure system 100 can be communicatively connected to the exposure apparatus and the workpiece stage, and control the exposure apparatus and the workpiece stage based on the exposure method P300 provided in this application.

[0039] like Figure 3 As shown, P300 may include the following steps:

[0040] S310, in response to the target wafer coated with photoresist being placed on the workpiece stage, determine the crystal plane height of each exposure block of the target wafer.

[0041] S320. Determine the first target exposure parameters for the first exposure process.

[0042] S330. Determine the first correlation between different crystal plane heights and critical dimension deviations in the target wafer after performing the first exposure process.

[0043] S340. Perform a second exposure simulation on the target exposure block based on the target crystal plane height after the first exposure process, and determine the second correlation between the second exposure parameters and the critical dimension compensation under the target crystal plane height.

[0044] S350. Based on the first correlation and the second correlation, determine the second target exposure parameters for eliminating the critical size deviation of the target crystal plane height, so as to determine the second target exposure parameters for each exposure block.

[0045] S360. Execute the first exposure process based on the first target exposure parameters, and then execute the second exposure process on each exposure block sequentially based on the second target exposure parameters of each exposure block.

[0046] In the aforementioned S310, the target wafer can refer to the wafer currently undergoing the exposure process. That is, after the wafer is coated with photoresist, it can be placed on the worktable for subsequent exposure processes, thereby realizing the pattern transfer from the photomask to the photoresist.

[0047] The subsequent steps of this application rely on the mobility of the worktable, optimizing the execution process of the second exposure process by progressively exposing different areas of the target wafer in a partitioned manner. The portion of the wafer exposed in a single pass during the second exposure process can be referred to as an exposure block. That is, an exposure block can be a virtual region defined on the wafer, reflecting an exposure area during the partitioned exposure process. The exposure blocks can be planned based on preset rules. For example, an exposure block can be presented as... Figure 2 The multiple rectangular regions shown.

[0048] Crystal plane height refers to the height at the wafer surface (i.e., the interface with the photoresist). It can be characterized as a relative height. For example, the planar height of the wafer surface can be determined, and the actual height at each location can be characterized as a value relative to the average height, with the sign of the value indicating whether it is high or low relative to the average height. Alternatively, other values ​​(such as minimum or maximum values) can be selected as the height reference.

[0049] In practice, the aforementioned S310 can be determined using the relevant detection equipment of the exposure system. Specifically, the exposure system often includes sensors that measure the vertical height (Z-direction) and tilt angle at various points on the wafer surface after it is placed on the stage, thereby ensuring that the exposed area remains within the depth of focus range of the projection lens. The test results can be visualized as follows: Figure 2 The image shown illustrates that, in actual execution, the aforementioned S310 can determine the crystal plane height of each exposure block by scanning the target wafer through sensors in the exposure apparatus after the target wafer is placed on the worktable.

[0050] As described above in S320, the first exposure process is used to shape the bottom of the photoresist. Therefore, the exposure depth range based on the focus position in the first target exposure parameters includes the interface between the photoresist and the target interface, in order to shape the critical dimensions at the interface.

[0051] Since this application does not make any additional adjustments to the first exposure process under normal conditions, its corresponding first target exposure parameters can be determined based on traditional algorithms (such as Focus-Energy Matrix (FEM) analysis). FEM is a key experimental method for determining the lithography process window. By systematically changing the focal length and exposure energy parameters, its impact on the pattern linewidth (critical dimension) is evaluated, thereby optimizing the exposure conditions. Considering that the first exposure process is a relatively mature process, its FEM analysis can be performed based on historical data to determine optimal exposure parameters as the first target exposure parameters. The specific determination process can be found in the relevant description of FEM.

[0052] Furthermore, considering that in actual device manufacturing processes, semiconductor devices using the same processes are often produced in batches, meaning wafers in the same batch often have similar specifications, with only slight differences in crystal plane height and distribution across individual wafers, the aforementioned first target exposure parameters can be determined based on the currently matched wafer data. Specifically, when S320 is executed, the wafer topography data of the batch containing the target wafer can be determined first. Then, based on the wafer topography data, the first target exposure parameters of the first exposure process are determined through focus-energy matrix data analysis.

[0053] In some embodiments, considering that globally executing the first exposure process often requires the crystal plane height range of the target wafer to be less than the exposure depth range, the first target exposure parameters for the first exposure process, which simultaneously processes each exposure block, can be determined based on wafer data through focus-energy matrix data analysis. However, when the crystal plane height range is greater than or equal to the exposure depth range, the first exposure process can be executed in partitions, ensuring that the crystal plane height range within each partition is less than the exposure depth range. That is, the crystal plane height range of the target wafer can be determined first. Then, in response to the crystal plane height range being greater than or equal to the exposure depth range, multiple first exposure regions are defined based on the crystal plane height of the target wafer, and the first target exposure parameters for each first exposure region are determined based on wafer data through focus-energy matrix data analysis. The first exposure region includes multiple exposure blocks with a crystal plane height range less than the exposure depth range.

[0054] Considering that historical data also exists for the second exposure process, its exposure parameters can also be determined by referring to the aforementioned process to determine a candidate value. However, considering that the relationship between the internal parameters of the second exposure process and CD will be determined based on the simulation process to determine the appropriate process parameters, in S320, only the process parameters of the first exposure process can be determined.

[0055] The aforementioned S330, the first correlation, can refer to the relationship between different crystal plane heights and critical dimension deviations after performing the first exposure process. Considering that the first exposure process is used to shape the bottom critical dimension, the area where critical dimension deviations exist is often in the upper-middle section of the photoresist. Therefore, when characterizing the first correlation, the critical dimension deviations at one or more specific points can be selected for description, or the critical dimension deviations at various locations can be used for description.

[0056] Specifically, considering that the critical dimension difference is often greatest on surfaces far from the bottom when forming the bottom critical dimension, the aforementioned critical position deviation can be considered as the critical dimension deviation of the photoresist surface. For example, after performing the first exposure process on an exposure block with a crystal plane height of 200nm, it can be simulated that the critical dimension of the bottom edge can be 163nm, the critical dimension of the middle region can be 232nm, and the critical dimension of the top region (i.e., the photoresist surface) can be 272nm, with the remaining bottom critical dimensions showing the greatest deviation.

[0057] In some embodiments, considering that the aforementioned S320 can be determined based on historical data, the aforementioned S330 can also be determined based on historical process data. That is, the first correlation between the crystal plane height and the critical dimension deviation after the photoresist performs the first exposure process can be determined based on historical process data. In some embodiments, the first correlation can also be further fitted to the crystal plane height and the critical dimension deviation, thereby characterizing it as a fitting relationship (such as a linear relationship) between the critical dimension deviation and the crystal plane height.

[0058] In some embodiments, the aforementioned critical size deviation can be characterized in a way that reflects the influence of the crystal plane height on the critical size. It can be characterized as the difference between the critical size and the bottom critical size, or it can be directly characterized by the critical size value.

[0059] In some embodiments, besides the method of determining the first correlation based on historical process data, considering the need to determine the second correlation in a simulation environment later, the first correlation can also be determined in a simulation environment. That is, the target wafer is loaded into the simulation environment and a simulation is performed based on the first exposure process to determine the critical dimensional deviations after the first exposure process at different crystal plane heights, thereby forming the first correlation.

[0060] In practice, the two methods can be used independently or in combination. For example, historical process data can be used first to determine the primary correlation, while for crystal plane heights not covered by historical process data, the primary correlation can be determined through simulation / fitting functions.

[0061] In some embodiments, the locations corresponding to the aforementioned critical size deviations are primarily used for performing a second exposure process. If a single second exposure process cannot compensate for the critical size deviations at each location, multiple compensatory exposures can be performed. That is, the second exposure process may include at least one compensatory exposure process. For details on the configuration process for at least one compensatory exposure process, please refer to [link to relevant documentation]. Figure 7 , 8 And its related descriptions.

[0062] In the aforementioned S340, the second correlation can reflect the correspondence between different second exposure parameters and critical size compensation at a specific crystal plane height.

[0063] The critical dimension compensation in the second correlation corresponds to the critical dimension deviation in the aforementioned first correlation, both reflecting the critical dimension situation at the same location. To correspond with the critical dimension deviation in the first correlation, when the critical dimension deviation in the first correlation is represented as a critical dimension value, the critical dimension compensation in the second correlation can be represented as the maximum critical dimension that can be corrected for the bottom critical dimension. When the critical dimension deviation in the first correlation is represented as the deviation of the critical dimension value relative to the bottom critical dimension, the critical dimension compensation in the second correlation can be represented as the deviation of the maximum correctable critical dimension relative to the bottom critical dimension.

[0064] In the actual execution of the aforementioned S340, individual simulations can be performed based on the height of each crystal plane contained in the target wafer, with each simulation focusing on only one crystal plane height. During the simulation, the first exposure process is executed based on the aforementioned first target exposure parameters to determine the correspondence between different exposure parameters of the second exposure process and critical dimension compensation (i.e., the second correlation). Similar to the aforementioned first correlation, the second correlation can also be used to fit the exposure parameters and critical dimension compensation to determine the fitting relationship between the two.

[0065] In the aforementioned S350, the second target exposure parameter can refer to a second exposure process execution parameter that can eliminate the critical size deviation formed after performing the first exposure process. Specifically, it can be determined based on the combined first and second correlation relationships. That is, for a crystal plane height, its corresponding critical size deviation can be determined from the first correlation relationship, and then the exposure parameter that can correct the critical size deviation (the critical size deviation is generally the same as the critical size compensation) can be determined based on the second correlation relationship of the crystal plane height, and used as the aforementioned second target exposure parameter. Thus, based on this process, the second target exposure parameter corresponding to each crystal plane height can be determined.

[0066] In some embodiments, considering that the aforementioned first correlation relationship and the second correlation relationship can be linearly fitted, the aforementioned S350 can also directly combine the two fitting relationships to directly parse the second target exposure parameters at each crystal plane height.

[0067] For example, assuming the exposure parameters only involve the focus position, the fitting relationship between the crystal plane height Z and the critical size deviation X can be Z = AX + B. At a specific crystal plane height z', the fitting relationship between the second exposure parameter P (e.g., exposure focal length) and the critical size compensation X' can be P = CX' + D. When the critical size deviation X and the critical size compensation X' adopt interchangeable correspondences, the two fitting relationships can be combined to obtain the second target exposure parameter P' = (C / A) * (z' - B) + D at a specific crystal plane height z'. Here, A, B, C, and D are constants determined based on testing and fitting.

[0068] To further illustrate this process, this application also provides a schematic diagram of fitting the first correlation relationship ( Figure 4 ) and a schematic diagram of the second correlation fitting at a specific crystal plane height (200nm) ( Figure 5 ).

[0069] exist Figure 4 In this model, the horizontal axis represents the critical dimension value of the wafer (typically in nm), and the vertical axis represents the crystal plane height (typically in nm). Based on different crystal plane heights, corresponding critical dimension values ​​can be collected as critical dimension deviations. Based on the collected data, a first correlation can be fitted. For example... Figure 4 As shown, the data generally exhibits linear regression, and the first correlation fitted based on this data is: Z = -4.0422X + 1337.7.

[0070] and Figure 4 resemblance, Figure 5 The horizontal axis can be the critical dimension value of the wafer (usually in nm), and the vertical axis can be the focus position of the second exposure process (usually in μm). Figure 5The data shown can be simulation data at a crystal plane height of 200nm, and it also exhibits a linear relationship. The second correlation fitted based on this data is: P=-0.0025X-0.7741.

[0071] Combining the two equations above, we can obtain the focus position of the second exposure process at a crystal plane height of 200nm as -1.47774. That is, using the aforementioned focus position as the second target exposure parameter can eliminate the critical dimensional deviation at a crystal plane height of 200nm.

[0072] In summary, when the second exposure parameter is primarily characterized by the focus position, during the execution of S340, the target wafer after the first exposure process can be loaded into the simulation environment first. Then, for the exposure blocks of the target crystal plane height, different exposure focus positions are used to perform the second exposure simulation, determining the critical dimension compensation for different exposure focus positions to construct the second correlation relationship for the target crystal plane height. During the execution of S350, the target critical dimension deviation of the target crystal plane height can be determined based on the first correlation relationship. The target focus position corresponding to the target critical dimension compensation matching the target critical dimension deviation in the second correlation relationship is determined as the second target exposure parameter.

[0073] Therefore, based on the aforementioned determined second target exposure parameters and first target exposure parameters, the corresponding exposure process can be executed to perform the aforementioned S360.

[0074] When performing the aforementioned S360, the first exposure process generally performs global processing on the target wafer. That is, when performing the first exposure process, the target wafer can be placed at a specific position in the exposure system according to the requirements of the first target exposure parameters, and the exposure device can be controlled to expose the wafer at the focus position and focus energy specified by the first target exposure parameters in order to realize the first exposure process.

[0075] Considering that this application configures different second target exposure parameters for each exposure block with different crystal plane heights, when performing the second exposure process, the exposure blocks can be placed one by one within the working range, and the corresponding second target exposure parameters can be called based on the crystal plane height of the exposure blocks within the working range. The exposure system can then be configured based on the second target exposure parameters to realize the second exposure process for the exposure block.

[0076] In some embodiments, the present application can control the exposure process through a stage, that is, by controlling the position of the stage in the longitudinal direction (in the same direction as the crystal plane height), the focus position can be adjusted, thereby executing the aforementioned second exposure process.

[0077] Therefore, based on the aforementioned exposure method, and considering the difference in crystal plane height between the wafer edge and center regions, this application divides the wafer into multiple exposure blocks when performing a second exposure process to eliminate bridging defects. Based on the first exposure process prior to the second exposure process, suitable exposure parameters are determined for each exposure block. This allows for the corresponding second exposure process to be performed on exposure blocks with different crystal plane heights, avoiding the situation where the overall exposure parameters are difficult to adapt to regions with different crystal plane heights (especially the lower-height edge regions) when performing the second exposure process on the entire wafer. Furthermore, when determining the exposure parameters, this application uses simulation algorithms to determine the impact of different exposure parameters at different crystal plane heights on critical dimension correction when the first exposure process parameters are fixed. This allows for the determination of suitable exposure parameters at each crystal plane height, improving the accuracy of critical dimensions in semiconductor devices.

[0078] An exemplary process for performing the second exposure process:

[0079] As described above, in the second exposure process of this application, it is often necessary to load the exposure block into the working range of the exposure equipment by moving the worktable planarly so that the exposure equipment can expose the area. That is, for the exposure area already loaded into the working range (denoted as the target exposure area), when executing the second exposure process, in response to the worktable loading the target exposure block into the working range, the longitudinal movement of the worktable can be controlled, thereby focusing the exposure beam of the exposure device onto the target focusing position in the photoresist. Then, the exposure device is controlled to execute the second exposure process.

[0080] In this process, considering that the crystal plane height distribution is often discrete, loading each exposure block into the working range one by one in sequence may cause the stage to move frequently. Therefore, this application can plan each exposure block for performing the second exposure process, and load multiple exposure blocks with the same focus position continuously in a group to reduce the longitudinal movement of the stage.

[0081] To further illustrate this process, some embodiments of this application also provide an exemplary flowchart of the second exposure process execution ( Figure 6 ).

[0082] like Figure 6 As shown, the second exposure process P600 may include the following steps:

[0083] S610: Delineate multiple second exposure areas based on the target focus position of each exposure block.

[0084] S620: For a target second exposure area in multiple second exposure areas, control the workpiece stage to load each exposure block of the target second exposure area into the working range in sequence.

[0085] S630, Execute the second exposure process based on the second target exposure parameters of the exposure blocks within the work area.

[0086] The delineation of the aforementioned second exposure region is similar to that of the aforementioned first exposure region, both being determined based on crystal plane height. Specifically, the second exposure region is the area constructed from the exposure blocks with the same target focusing position. It can also be understood as a collection of exposure blocks.

[0087] As described above, the focus position in the second target focusing parameters generally corresponds to the crystal plane height. The same crystal plane height has the same focus position, so the aforementioned second exposure area can be defined based on the crystal plane height of each exposure area.

[0088] In the aforementioned S620, a second exposure area can be understood as a continuous second exposure process, in which the exposure parameters are fixed. In actual execution, the aforementioned S620 can form a planar movement path based on the distribution of each exposure block within the second exposure area, thereby loading each exposure area within the second exposure area into the working range sequentially based on this movement path.

[0089] As another implementation, when loading exposure blocks, based on a block traversal control strategy and the enable control of the exposure device, the exposure device will only perform operations when exposure blocks within a second exposure region are loaded into the working range. In this case, although exposure blocks outside the second exposure region will also be loaded into the working range, the exposure device will not operate when they are loaded into the working range. Thus, the aforementioned process can also equivalently achieve the sequential loading of each exposure block into the working range. Furthermore, considering that crystal plane heights are often radially distributed, exposure blocks can be loaded in a circular fashion when traversing each exposure region.

[0090] When S630 is executed, maintaining the same focus position (i.e., stage height) for each second exposure area is sufficient to achieve exposure of each exposure block within that second exposure area. See the foregoing for details.

[0091] Therefore, based on the aforementioned second exposure process execution flow, by continuously loading exposure blocks with the same crystal plane height, the longitudinal height (focus position) of the stage can be maintained, reducing its variation and thus reducing the fluctuations caused by its variation, thereby improving process stability.

[0092] Example of multiple rounds of compensated exposure:

[0093] As mentioned above, the actual function of the second exposure process is to perform compensatory exposure in the out-of-focus area of ​​the first exposure process. The number of exposures in the second exposure process during its actual execution is not limited. That is, if the current compensatory exposure cannot eliminate the bridging defects caused by out-of-focus areas, an additional exposure can be added until the exposure is complete.

[0094] For the aforementioned second exposure process that is executed multiple times, when determining its exposure parameters, an overall plan can be made, or the next compensation exposure process can be determined based on the "executed" exposure process, until the compensation exposure of the entire photoresist is completed.

[0095] To address the aforementioned issues, this application provides two methods for determining the second target exposure parameters based on a multi-round compensating exposure process. Figure 7 , Figure 8 The following will explain in turn.

[0096] like Figure 7 As shown, process P700 may include the following steps:

[0097] S:710. Based on the first target exposure parameters and the exposure depth range, determine at least one compensation exposure process and its corresponding compensation position in the second exposure process.

[0098] S720. For at least one compensation exposure process, determine the first correlation between the critical dimension deviation of different crystal plane heights of the target wafer and the target compensation position after executing the first exposure process and the historical compensation exposure processes, wherein the target compensation position corresponds to the target compensation exposure process, and the historical compensation exposure processes are each compensation exposure process whose compensation position is below the target compensation position.

[0099] S730. Perform target compensation exposure process simulation on the target exposure block based on the target crystal plane height after performing the first exposure process and the historical compensation exposure process, and determine the second correlation between the second exposure parameter and the critical dimension compensation at the target compensation position under the target crystal plane height.

[0100] S740. Based on the first correlation and the second correlation, determine the second target exposure parameters of the target compensation exposure process corresponding to the key size deviation of the target compensation position used to eliminate the target crystal plane height, so as to determine the second target exposure parameters of the target compensation exposure process of each exposure block, and then determine the second target exposure parameters of each compensation exposure process in the second exposure process.

[0101] In the aforementioned S710, the second exposure process can consist of at least one compensation exposure process to eliminate the defocusing defect of the first target exposure process. Therefore, when determining the specific number and location of the compensation exposure processes to be used, all compensation exposure processes can be determined directly, or an iterative algorithm can be used to calculate based on the required compensation exposure processes. For details on the iterative calculation method, please refer to [link to relevant documentation]. Figure 8 The relevant descriptions are explained here, taking all compensation exposure processes as an example.

[0102] When performing the aforementioned S710, the approximate exposure range of each exposure process in the photoresist can be planned based on the exposure depth range of each exposure process, thereby ensuring that the overall depth of the photoresist has good critical dimensions. Generally, the planning can be based on the depth of the area to be compensated in the photoresist during the first exposure process and the depth range that a single compensation exposure process can compensate for, thereby determining the number of compensation exposure processes and the range that each compensation exposure process needs to compensate for.

[0103] The aforementioned S720-S740 can be described as a process for determining the second target exposure parameter of the target compensation exposure process in at least one compensation exposure process. The target compensation exposure process can be the compensation exposure process currently performing exposure parameter calculations. Considering that the exposure process in this application is executed from bottom to top, the target exposure process can also be selected from bottom to top. That is, the target exposure process can be the compensation exposure process that has not yet performed parameter calculations and is closest to the focus position of the first exposure process.

[0104] In the specific calculation process, the compensated exposure process with calculated parameters (referred to as the historical compensated exposure process) can be processed in a similar way to the first exposure process. That is, in the simulation environment, the critical dimension compensation after executing both the first exposure process and the historical compensated exposure process can be simulated to determine the specific exposure parameters of the target compensated exposure process. The specific execution process involves treating the historical compensated exposure process as part of the first exposure process, and using the parameter determination method for the aforementioned second exposure process to determine the process parameters of the target compensated exposure process. For details, please refer to the preceding content; further elaboration will not be repeated here.

[0105] Considering that the actual compensation position of each compensation exposure process may be adjusted based on the parameters of historical compensation exposure processes, the aforementioned process can be changed to an iterative process. That is, in response to the existence of out-of-focus defects, a compensation exposure process can be applied, and the process parameters of the compensation exposure process can be determined. Then, it is determined whether the out-of-focus defect still exists after executing the compensation exposure process. If yes, the aforementioned steps are repeated. If no, the loop ends.

[0106] The foregoing Figure 8 The process has been explained. For example... Figure 8As shown, process P800 may include the following steps:

[0107] S810. For the target exposure block with the target crystal plane height, determine the key dimensions of the target exposure block after performing the first exposure process and the historical compensation exposure process.

[0108] S820 determines whether to perform target compensation exposure process based on the key size of the target exposure block.

[0109] S830, if so, then the target compensation position corresponding to the target compensation exposure process is determined based on the thickness of the photoresist, the key dimensions of the target exposure block, and the exposure depth range.

[0110] S840. Determine the second target compensation parameter for the target compensation process, and use the target compensation process as a historical compensation exposure process.

[0111] S850, if not, then the critical dimensions are deemed to meet the requirements.

[0112] In the aforementioned P800, S820 can be a step to determine whether to perform a compensation exposure process. S830 and S840 can reflect the subsequent situation after performing the compensation exposure process. S850 can be the subsequent situation where the requirements have been met and no further exposure is needed. Among them, after executing S840, the process can return to the previously iterated S810 until S850.

[0113] In the aforementioned S810, the historical compensation exposure method can be similarly processed to the execution method of the first exposure process, thereby determining the critical dimensions of the target exposure block after executing the first exposure process and the historical compensation exposure process. These critical dimensions may include the critical dimensions of each depth of the photoresist.

[0114] The aforementioned S820 can be executed based on whether the aforementioned critical dimension requirements are met. The critical dimension requirements can be determined directly or indirectly during semiconductor design. For example, if the area where the photoresist is exposed can be used for a trench, the critical dimension requirements for the exposure of the photoresist above it can be determined based on the general fabrication requirements of the trench.

[0115] For subsequent steps S830 and S840, please refer to the relevant description of P700 above. After S840 is completed, the target compensation exposure can be used as the determined historical compensation exposure to re-execute the aforementioned S810 until the critical size requirement is met (i.e., jump to S850 in the judgment of S820).

[0116] Unexpected technical effects:

[0117] In summary, the semiconductor device and manufacturing method provided in this application have the following unexpected effects:

[0118] ① In response to the difference in crystal plane height between the edge region and the center region of the wafer, this application divides the wafer into multiple exposure blocks when performing the second exposure process to eliminate bridging defects, and determines the appropriate exposure parameters for each exposure block based on the first exposure process before performing the second exposure process. This allows the second exposure process to be performed on exposure blocks with different crystal plane heights, thereby avoiding the situation where the overall exposure parameters are difficult to adapt to regions with different crystal plane heights (especially the edge region with lower height) when performing the second exposure process on the entire wafer.

[0119] ② When determining the exposure parameters, this application uses simulation algorithms to determine the influence of different exposure parameters on the critical dimension correction at the crystal plane height when the first exposure process parameters are fixed, thereby determining the appropriate exposure parameters at each crystal plane height and improving the accuracy of the critical dimensions of semiconductor devices.

[0120] ③ Considering that the crystal plane height distribution is often discrete, loading each exposure block into the working range one by one in sequence may cause the stage to move frequently. Therefore, this application can plan each exposure block for performing the second exposure process, and load multiple exposure blocks with the same focus position in a group to reduce the longitudinal movement of the stage and improve the execution efficiency of the second exposure process.

[0121] ④ Considering that globally executing the first exposure process often requires the crystal plane height range of the target wafer to be less than the exposure depth range, only then can the first target exposure parameters for the first exposure process, which simultaneously processes each exposure block, be determined based on wafer data and focus-energy matrix data analysis. When the crystal plane height range is greater than or equal to the exposure depth range, the first exposure process can be executed in sections, ensuring that the crystal plane height range within each section is less than the exposure depth range. That is, the crystal plane height range of the target wafer can be determined first. Then, in response to the crystal plane height range being greater than or equal to the exposure depth range, multiple first exposure regions are defined based on the crystal plane height of the target wafer, and the first target exposure parameters for each first exposure region are determined based on wafer data and focus-energy matrix data analysis. The first exposure region includes multiple exposure blocks with a crystal plane height range less than the exposure depth range. This overcomes the inability to expose due to wafer edge anomalies, thereby improving semiconductor yield.

[0122] ⑤ Considering that the actual function of the second exposure process is to perform compensatory exposure in the out-of-focus area of ​​the first exposure process, the number of exposures in the actual execution of the second exposure process can be unlimited. That is, if the current compensatory exposure cannot eliminate the bridging defects caused by out-of-focus exposure, an additional exposure can be added until the exposure is completed. This further increases the photoresist thickness that this application can accommodate.

[0123] The embodiments of the present invention disclosed above are merely illustrative of the invention. The embodiments do not exhaustively describe all details, nor do they limit the invention to the specific implementations described. Clearly, many modifications and variations can be made based on the content of this specification. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the invention, thereby enabling those skilled in the art to better understand and utilize the invention. The invention is limited only by the claims and their full scope and equivalents.

Claims

1. An exposure method characterized by, The application is applied to a photoresist exposure system, and the exposure method comprises the following steps: In response to a target wafer coated with photoresist being placed on a workpiece table, the crystal surface height of each exposure block of the target wafer is determined; A first target exposure parameter of a first exposure process is determined, wherein in response to the range of the crystal surface height of the target wafer being smaller than the range of the exposure focal depth, the first target exposure parameter is determined when the exposure focal depth range of the focusing position in the first exposure process covers the interface between the photoresist and the target wafer at different crystal surface heights, so as to shape the critical dimension at the interface; A first correlation is determined, wherein the first correlation at least reflects the relationship between the critical dimension deviation of a specific position caused by the different focusing depths of the photoresist of the first exposure process relative to different crystal surface heights and the crystal surface height; Second exposure simulation is performed on the target exposure block based on the target crystal surface height after the first exposure process is performed, and a second correlation is determined, wherein the second correlation reflects the relationship between the critical dimension compensation of the specific position by the second exposure process and the second exposure parameter, and the second exposure parameter at least includes the focusing position; Based on the first correlation and the second correlation, the second target exposure parameter for eliminating the critical dimension deviation of the specific position at the target crystal surface height is determined, so as to determine the second target exposure parameter of each exposure block; The first exposure process is performed based on the first target exposure parameter, and the second exposure process is sequentially performed on each exposure block based on the second target exposure parameter of each exposure block.

2. The exposure method according to claim 1, wherein The second exposure simulation on the exposure block of the target crystal surface height in the photoresist after the first exposure process is performed, and the second correlation is determined, comprising: loading the target wafer after the first exposure process in a simulation environment; performing second exposure simulation on the exposure block of the target crystal surface height by using different exposure focusing positions to determine the critical dimension compensation of different exposure focusing positions, so as to construct the second correlation of the target crystal surface height; based on the first correlation and the second correlation, the second target exposure parameter of the second exposure process for eliminating the critical dimension deviation of the photoresist at the target crystal surface height is determined, comprising: determining the target critical dimension deviation of the target crystal surface height based on the first correlation; determining the target focusing position corresponding to the target critical dimension compensation in the second correlation as the second target exposure parameter.

3. The exposure method according to claim 2, wherein The second exposure process is sequentially performed on each exposure block based on the second target exposure parameter of each exposure block, comprising: in response to the workpiece table loading the target exposure block into the working range, controlling the workpiece table to move longitudinally, so that the exposure beam of the exposure device is focused on the target focusing position in the photoresist; controlling the exposure device to perform the second exposure process.

4. The exposure method according to claim 2, wherein The second exposure process is sequentially performed on each exposure block based on the second target exposure parameter of each exposure block, comprising: drawing a plurality of second exposure areas based on the target focus positions of the exposure blocks, wherein the second exposure areas include a plurality of exposure blocks with the same target focus position; controlling the workpiece table to sequentially load each exposure block of a target second exposure area in the plurality of second exposure areas into a working range; performing the second exposure process based on the second target exposure parameters of the exposure blocks in the working range.

5. The exposure method according to any one of claims 1, wherein The first target exposure parameters of the first exposure process of the photoresist based on the target wafer include: determining wafer data of a wafer batch in which the target wafer is located; determining the first target exposure parameters of the first exposure process based on the wafer data through focus-energy matrix data analysis.

6. The exposure method according to claim 5, wherein The first target exposure parameters of the first exposure process based on the wafer data through focus-energy matrix data analysis include: determining a crystal face height range of the target wafer; in response to the crystal face height range being less than an exposure focal depth range, determining the first target exposure parameters of the first exposure process based on the wafer data through focus-energy matrix data analysis; in response to the crystal face height range being greater than or equal to the exposure focal depth range, drawing a plurality of first exposure areas based on the crystal face height of the target wafer, and determining the first target exposure parameters of each first exposure area based on the wafer data through focus-energy matrix data analysis, wherein the first exposure areas include a plurality of exposure blocks with a crystal face height range less than the exposure focal depth range.

7. The exposure method according to any one of claims 1, wherein The exposure method further includes: determining at least one compensation exposure process and a corresponding compensation position in the second exposure process based on the first target exposure parameters and an exposure focal depth range; The determination of the first correlation between different crystal face heights of the target wafer and critical dimension deviations after the first exposure process includes: for a target compensation exposure process in the at least one compensation exposure process, determining a first correlation between different crystal face heights of the target wafer and critical dimension deviations at a target compensation position after the first exposure process and historical compensation exposure processes, wherein the target compensation position corresponds to the target compensation exposure process, and the historical compensation exposure processes are each compensation exposure process with a compensation position below the target compensation position; The second exposure simulation for the target exposure block based on the target crystal face height after the first exposure process includes: performing target compensation exposure process simulation for the target exposure block based on the target crystal face height after the first exposure process and the historical compensation exposure processes to determine a second correlation between the second exposure parameters at the target crystal face height and the critical dimension compensation at the target compensation position.

8. The exposure method according to claim 7, wherein The determination of the at least one compensation exposure process and the compensation position corresponding to the compensation exposure process in the second exposure process based on the first target exposure parameters and the exposure focal depth range includes: For a target exposure block of a target crystal face height, determining a critical dimension condition of the target exposure block after performing a first exposure process and a history compensation exposure process; determining whether to perform the target compensation exposure process based on the critical dimension condition of the target exposure block; if yes, determining a target compensation position corresponding to the target compensation exposure process based on the thickness of the photoresist, the critical dimension condition of the target exposure block and the exposure depth of focus range.

9. A photoresist exposure system, characterized by, The photoresist exposure system comprises: an exposure device for releasing an exposure beam; a workpiece table for carrying a wafer; and a controller in communication connection with the exposure device and the workpiece table, for controlling the exposure device and the workpiece table based on the exposure method of any one of claims 1-8.

10. A semiconductor device, characterized by comprising: The semiconductor device is prepared based on the exposure method of any one of claims 1-8.

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