Method of performing atomic memory operations and multicore processor

Abstract

The present disclosure provides an execution method of an atomic memory operation and a multi-core processor. The method comprises: a first node interacts with a master node to execute the atomic memory operation, wherein the first data is generated after the execution of the atomic memory operation; the first node sends a unique permission read request to the master node; the first node receives the first data returned by the master node in response to the unique permission read request; and the first node stores the first data in the cache of the first node.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the field of computer technology, and in particular, to an execution method of atomic memory operation and a multi-core processor. BACKGROUND

[0002] In a multi-core processor, multiple threads or processes may access shared resources simultaneously. Without constraints, data race or data inconsistency problems may occur. Lock mechanism avoids such problems by ensuring that only one thread or process can access a specific resource at any time.

[0003] The Reduced Instruction Set Computer-five (RISC-V) architecture can implement common locks such as spin locks through Load-Reserved (LR) / Store-Conditional (SC) or Atomic Memory Operation (AMO) methods. For the implementation of LR / SC, first, an exclusive identifier is obtained through LR, and when executing SC operations of the same cacheline, if the exclusive identifier is not cleared, the execution is successful, and if the exclusive identifier is cleared, the exclusive fails, and LR / SC needs to be re-executed. However, in a large multi-core system, lock contention between multiple cores can cause strong competition, and the LR / SC method can cause cache thrashing, resulting in a decrease in the success rate of lock contention.

[0004] The AMO method can ensure that the access to shared data is atomic, reduce lock contention, and improve the concurrent performance of the program. The execution efficiency of the AMO instruction is closely related to the lock contention efficiency, and low lock contention efficiency can reduce system performance and waste system resources. SUMMARY

[0005] The present disclosure provides an execution method of AMO and a multi-core processor, which improves the lock contention efficiency of the core by reducing data transmission between the Request Node (RN) and the Home Node (HN).

[0006] The present disclosure provides an execution method of atomic memory operation, comprising: a first node interacting with a home node to execute the atomic memory operation, wherein the first data is generated after executing the atomic memory operation; the first node sends a unique permission read request to the home node; the first node receives the first data returned by the home node in response to the unique permission read request; and the first node stores the first data in the cache of the first node.

[0007] The present disclosure also provides a multi-core processor, comprising a plurality of cores, at least one of the plurality of cores being configured to perform the execution method of the atomic memory operation according to the present disclosure.

[0008] According to various embodiments of the present disclosure, the requesting node sends a unique permission read request to the master node immediately after the master node performs the AMO, which can reduce the interaction between the requesting node and the master node, reduce the propagation delay of data, and improve the lock acquisition efficiency. BRIEF DESCRIPTION OF DRAWINGS

[0009] In the drawings of the embodiments of the present disclosure:

[0010] Figure 1 The overall block diagram of the remote execution of the AMO instruction is shown;

[0011] Figure 2 The interaction process between the RN and the HN when the RN executes the AMO is shown;

[0012] Figure 3 The flowchart of the execution method of the AMO according to the embodiments of the present disclosure is shown;

[0013] Figure 4 The detailed flowchart of step S100 in the execution method of the AMO according to the embodiments of the present disclosure is shown;

[0014] Figure 5 The flowchart of the steps performed by the master node in response to the unique permission read request in the execution method of the AMO according to the embodiments of the present disclosure is shown;

[0015] Figure 6 The processing flow of the ReadUnique request is shown;

[0016] Figure 7 The interaction process between the RN and the HN in the execution method of the AMO according to the embodiments of the present disclosure is shown. DETAILED DESCRIPTION

[0017] In order for those skilled in the art to better understand the technical solutions of the present disclosure, the embodiments of the present disclosure will be described in detail below with reference to the drawings.

[0018] The present disclosure will be described more fully hereinafter with reference to the accompanying drawings, but the embodiments shown can be embodied in different forms and the present disclosure should not be construed as being limited to the embodiments set forth below. Rather, these embodiments are provided so that the present disclosure is thorough and complete, and will fully convey the scope of the present disclosure to those skilled in the art.

[0019] The accompanying drawings are used to provide a further understanding of embodiments of the present disclosure and constitute a part of the specification, and together with the detailed embodiments, serve to explain the present disclosure, and do not constitute a limitation of the present disclosure. The above and other features and advantages will become more apparent from the detailed embodiments described below taken in conjunction with the accompanying drawings.

[0020] The present disclosure can be described with reference to plan views and / or cross-sectional views by idealized figures of the present disclosure. Thus, the example illustrations can be modified according to manufacturing techniques and / or tolerances.

[0021] The embodiments of the present disclosure and each feature in the embodiments can be combined with each other if there is no conflict.

[0022] The terms used in the present disclosure are merely used to describe particular embodiments, and are not intended to limit the present disclosure. As used in the present disclosure, the term "and / or" includes any and all combinations of one or more of the associated listed items. As used in the present disclosure, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. As used in the present disclosure, the term "comprises" or "comprising," or "includes" or "including" means the presence of stated features, integers, steps, operations, elements, and / or components, but does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0023] Unless otherwise defined, all terms used in the present disclosure, including technical terms and scientific terms, have the same meaning as those generally understood by a person of ordinary skill in the art. It will also be understood that terms such as those defined in a generally used dictionary should be interpreted as having a meaning that is consistent with its meaning in the context of the relevant art and the present disclosure, and should not be interpreted in an idealized or overly formal sense unless expressly so defined in the present disclosure.

[0024] The present disclosure is not limited to the embodiments shown in the drawings, but includes modifications of configurations formed based on manufacturing processes. Therefore, the regions exemplified in the drawings have a schematic property, and the shape of the regions shown in the drawings exemplifies a specific shape of the region, but is not intended to be restrictive.

[0025] An AMO instruction performs an atomic operation on an operand in memory and sets a target register to the memory value before the operation. "Atomic" means that the process between memory read and write is not interrupted, and the memory value is not modified by other cores (or processors).

[0026] The atomic operation of the AMO instruction can be performed in Near or Far. Figure 1 A general block diagram of Far execution of the AMO instruction is shown.

[0027] As Figure 1As shown, the multi-core processor system can include a plurality of cores Core0 to CoreN, each having a local cache (Cache) and a request node RN. The home node HN is the control center of the coherence interface protocol, usually a shared cache (e.g., L3 cache) in the system, for receiving protocol transactions from RNs, completing corresponding coherence operations and returning responses to RNs. The slave node (SN) is the node where data is finally stored, usually the system main memory (e.g., DRAM). The slave node SN can handle memory access requests from the home node HN. Cacheable AMO instructions first determine whether there is a hit in the cache within the core, if the hit state is unique (U) state, i.e., there is no cache copy in other cores, the atomic operation is directly executed in the core (i.e., in the near end), if the hit state is shared (S) state, i.e., there is a cache copy in other cores, a request is sent to other cores to invalidate the copy in other cores, so as to finally obtain unique permission, and then the atomic operation is executed in the near end, and the latest data is written into the cache; if there is a miss in the core, a remote AMO is triggered, and the execution of the remote AMO needs a corresponding bus to support the atomic operation. The process of the remote AMO is as shown in Figure 2

[0028] Figure 2 The interaction process between RN and HN when executing AMO in the remote end is shown.

[0029] As shown in Figure 2 ​As shown, taking the AMO Load transaction as an example, the RN sends an AMO Load transaction to the HN through a Transmit Request (Txreq) channel; when the HN has resources to receive data, it returns a Data Buffer ID Response (DbidResp) to the RN through a Receive Response (Rxrsp) channel, indicating that the HN has resources to receive write data information; after the RN receives the DbidResp, it sends the operation number of write data (Write Data, WrData) to the HN through a Transmit Data (Txdat) channel; when the request is visible to other cores, the HN sends a Completion with Data (CompData) response to the RN through a Receive Data (Rxdat) channel to return initial data (Initial Data) for instruction submission; according to the data carried by the WrData and the initial data, the atomic operation specified in the AMO Load transaction is executed, and the new data obtained is retained in the system cache or main memory (i.e., the master node HN or the slave node SN). The processing flow of other AMO types (for example, AMOCompare, AMOSwap) is similar to that shown above, and will not be described again. Figure 2 The process shown above is similar and will not be described again.

[0030] As can be seen from the above process, the new data obtained is not stored in the cache in the RN core, and when the AMO instruction of the same cacheline is accessed again, it is still a miss in the core, thereby triggering a remote AMO again and repeating the above steps. Continuous interaction between the RN and the HN will cause a delay in data transmission and affect performance.

[0031] The present disclosure proposes an AMO execution method, aiming to optimize the processing flow of the remote operation of cacheable AMO instructions, reduce the interaction between the RN and the HN, and improve the lock performance.

[0032] Figure 3 A flowchart of an AMO execution method according to an embodiment of the present disclosure is shown.

[0033] As Figure 3 As shown, the atomic memory operation execution method according to an embodiment of the present disclosure includes the following steps S100-S400.

[0034] In step S100, the first node interacts with the master node to execute an atomic memory operation, wherein the first data is generated after the atomic memory operation is executed.

[0035] Figure 4 A detailed flow chart of step S100 in the execution method of AMO is shown according to an embodiment of the present disclosure.

[0036] As shown in Figure 4 According to an embodiment of the present disclosure, the first node interacts with the master node to perform the atomic memory operation (i.e., step S100) can include the following steps S110-S140.

[0037] In step S110, the first node sends a request to the master node to perform the atomic memory operation.

[0038] In step S120, the first node receives a first response from the master node, wherein the first response indicates that the master node has resources to receive data information.

[0039] In step S130, the first node sends the data to be operated to the master node.

[0040] In step S140, the first node receives the original data from the master node, wherein the first data is obtained after the atomic memory operation is performed on the data to be operated and the original data at the master node.

[0041] According to an embodiment of the present disclosure, the first data obtained after the atomic memory operation is stored in the system cache or the main memory.

[0042] According to an embodiment of the present disclosure, the first node interacts with the master node to perform the atomic memory operation in response to a cache miss.

[0043] According to an embodiment of the present disclosure, the atomic memory operation can include one of the following: AMO Load, AMO Compare, AMO Swap.

[0044] Table I shows the instruction format, opcode, format type and name of the RISC-V 32-bit Atomic (RV32A) extension instruction set.

[0045] Table I

[0046]

[0047] Table II shows the instruction format, opcode, format type of the AMO Compare-and-Swap (CAS) instruction set.

[0048] Table II

[0049]

[0050] In addition, in the Zabha extension of RISC-V, byte (8-bit) and half-word (16-bit) atomic operations are extended to AMO, such as AMOADD.B, AMOADD.H.

[0051] AMOCompare is the transaction name sent by the core to the bus, which is derived from the AMOCAS instruction. AMOLoad is a type of transaction name sent by the core to the bus, which is derived from the AMOADD, AMOAND, AMOOR, AMOXOR, AMOMAX[U], AMOMIN[U] instruction. AMOSwap is the transaction name sent by the core to the bus, which is derived from the AMOSWAP instruction.

[0052] The process in which the first node interacts with the master node to perform the atomic memory operation (i.e., step S100) is consistent with the process described with reference to Figure 1 and Figure 2 The interaction process between the RN and the HN is consistent with the description above, and will not be repeated here.

[0053] At step S200, the first node sends a unique permission read request to the master node.

[0054] By sending a unique permission read request to the master node, the first node (i.e., the requesting node RN) can obtain the first data (i.e., new data) obtained after performing the AMO at the master node in an exclusive manner.

[0055] According to embodiments of the present disclosure, after the first node receives the original data from the master node (i.e., step S140), the original data can be stored in a general target register for submission of instructions, and the original data is not stored in the cache of the first node.

[0056] After the first node requests to perform the AMO at the master node and obtains the original data returned by the master node, the first node immediately sends a unique permission read request to the master node.

[0057] Figure 5 A flowchart showing the steps performed by the master node in response to the unique permission read request in the execution method of the AMO according to embodiments of the present disclosure is shown.

[0058] As Figure 5 According to embodiments of the present disclosure, in response to receiving the unique permission read request sent by the first node, the master node performs the following steps S210 to S220.

[0059] At step S210, the copy of the first data of the other nodes except the first node is invalidated.

[0060] At step S220, the first data is returned to the first node.

[0061] According to an embodiment of the present disclosure, the unique permission read request comprises a ReadUnique request.

[0062] Through the ReadUnique request, the first node (i.e., the requesting node RN) can obtain a unique (Unique, U) state of a cacheline of one snoopable region, including a Unique Clean (UC) state or a Unique Dirty (UD) state. After obtaining the U state, the first node (i.e., the requesting node RN) can rewrite the cacheline.

[0063] Returning to Figure 4 At step S300, the first node receives the first data returned by the home node in response to the unique permission read request.

[0064] At step S400, the first node stores the first data in the cache of the first node.

[0065] Figure 6 A processing flow of the ReadUnique request is shown.

[0066] As shown in Figure 6 , the requesting node RN sends a ReadUnique request to the home node HN to exclusively obtain the first data (step S200); in response to receiving the ReadUnique request, the HN invalidates the copies of the first data of other nodes except the RN (step S210), and returns the first data to the RN (step S220); the RN obtains the new data (i.e., the first data) and the unique permission (step S300), and writes back the new data (i.e., the first data) to the cache of the RN (step S400).

[0067] The execution method of the AMO according to the embodiment of the present disclosure can further comprise: in response to receiving the first data, the first node sends a second response to the home node.

[0068] After receiving the first data returned by the home node, the first node can send a second response, such as a Completion acknowledgment (CompAck) response, to the home node for in-order notification.

[0069] In-order is a mechanism used to avoid conflicts when other cores access the system cache (or main memory). Memory order is a key to multi-threaded programming and atomic operations, especially when concurrent data access is involved. Memory order defines the visibility and order of memory operations in a multi-threaded environment, ensuring that different threads operate on shared data as expected, avoiding data inconsistency problems caused by compiler or hardware optimization.

[0070] Figure 7 RN and HN interaction processes of the execution method of the AMO according to an embodiment of the present disclosure are shown.

[0071] As shown in Figure 7 , taking an AMOLoad transaction as an example, the RN sends an AMOLoad transaction to the HN through a Txreq channel; when the HN has resources to receive data, it returns a DbidResp to the RN through a Rxrsp channel, indicating that the HN has resources to receive write data information; after the RN receives the DbidResp, it sends the operation number WrData to the HN through a Txdat channel; when the request is visible to other cores, the HN sends a CompData response to the RN through a Rxdat channel to return the InitialData for the submission of the instruction; according to the data carried by the WrData and the InitialData, the atomic operation specified in the AMOLoad transaction is executed, and the obtained NewData is retained in the system cache or the main memory (i.e., the master node HN or the slave node SN). The above processing process is similar to the process shown in Figure 2 , and different from the process shown in Figure 2 , in that, after the RN receives the CompData, it immediately sends a ReadUnique transaction to the HN through the Txreq channel, and the HN returns a CompData response to the RN through the Rxdat channel after ensuring that there is no cache copy in other cores, to return the NewData, and the RN stores the NewData in the cache in the core and saves the unique permission in the core after receiving the CompData response, and returns a CompAck response to the HN for the in-order notification. When there is again an AMO operation at the same address, the RN hits in the core and the state is U, so that the normal execution in the near end can be performed. In this way, it is not necessary to send the AMO transaction to the HN again, and the data transmission delay is reduced.

[0072] According to the execution method of the AMO, after the first node requests to execute the AMO at the master node (i.e., the far end) and obtains the InitialData returned by the master node, it immediately sends a unique permission read request to the master node to obtain the NewData generated after the execution of the AMO, and writes the NewData back to the cache of the first node, thereby avoiding the triggering of the far end AMO again when the AMO instruction of the same cacheline is accessed again, optimizing the processing flow of the far end operation of the cacheable AMO instruction, reducing the interaction between the RN and the HN, accelerating the execution of the AMO instruction, and improving the lock performance.

[0073] The execution method of the AMO according to the embodiment of the present disclosure can be applied to all on-chip systems (SOCs) that support the far end AMO operation.

[0074] Embodiments of the present disclosure also provide a multi-core processor including a plurality of cores, at least one core of the plurality of cores being configured as a first node to perform the execution method of AMO according to embodiments of the present disclosure. That is, at least a part of the plurality of cores or all of the plurality of cores can be configured as the first node to perform the execution method of AMO according to embodiments of the present disclosure.

[0075] Those skilled in the art can understand that all or some of the functional modules / units in the above disclosed steps, systems, and devices can be implemented as software, firmware, hardware, and appropriate combinations thereof.

[0076] In hardware implementation, the division between the functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components, for example, one physical component can have multiple functions, or one function or step can be performed by several physical components in cooperation.

[0077] Some or all of the physical components can be implemented as software executed by a processor, such as a central processing unit (CPU), a digital signal processor, or a microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit. Such software can be distributed on computer readable media, which can include computer storage media (or non-transitory media) and communication media (or transitory media). As is known to those skilled in the art, the term computer storage media includes both volatile and non-volatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data. Computer storage media includes, but is not limited to, random access memory (RAM, more specifically SDRAM, DDR, etc.), read only memory (ROM), electrically erasable programmable read only memory (EEPROM), FLASH memory or other solid state memory; compact disc read-only memory (CD-ROM), digital versatile discs (DVDs), or other optical disk storage; magnetic cassettes, magnetic tapes, magnetic disk storage or other magnetic storage devices; any other medium that can be used to store the desired information and that can be accessed by a computer. Further, as is known to those skilled in the art, communication media typically embodies computer readable instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism and includes any information delivery media. In this document, the term "modulated data signal" means a signal that has one or more of its characteristics changed or set in a manner so as to encode information in the signal. By way of example, and not limitation, communication media includes wired media such as a wired network or direct-wired connection, and wireless media such as wireless media networks, cellular telephone networks, code division multiple access (CDMA) networks, and other terrestrial and satellite radio frequency communication networks.

[0078] The present disclosure has disclosed example embodiments, and while specific terminology has been employed, it is merely in the service of a general descriptive purpose and should not be construed as limiting. In some instances, it will be apparent to those skilled in the art that features, characteristics, and / or elements described in connection with a particular embodiment can be used in conjunction with other embodiments unless otherwise explicitly stated. As such, those skilled in the art will appreciate that various changes can be made in form and detail without departing from the scope of the disclosure as set forth in the appended claims.

Claims

1. A method of performing an atomic memory operation, the method comprising: The method comprises: The first node interacts with the home node to perform the atomic memory operation, wherein the first data is generated after the atomic memory operation is performed; The first node sends a unique permission read request to the home node; The first node receives the first data returned by the home node in response to the unique permission read request; The first node stores the first data in the cache of the first node, Wherein, the unique permission read request comprises a ReadUnique request.

2. The method of claim 1, wherein, The first node performs the atomic memory operation at the home node comprises: The first node sends a request to the home node to perform the atomic memory operation; The first node receives a first response from the home node, wherein the first response indicates that the home node has resource information to receive data; The first node sends data to be operated to the home node; The first node receives original data from the home node, Wherein, the first data is obtained after the atomic memory operation is performed at the home node according to the data to be operated and the original data.

3. The method of claim 2, wherein, After the first node receives the original data from the home node, the original data is not stored in the cache of the first node.

4. The method of claim 1, wherein, The first data obtained after the atomic memory operation is performed is stored in the system cache or the main memory.

5. The method of claim 1, wherein, In response to receiving the unique permission read request sent by the first node, the home node: Invalidates the copy of the first data of other nodes except the first node; Returns the first data to the first node.

6. The method of claim 1, wherein, The method further comprises: In response to receiving the first data, the first node sends a second response to the home node.

7. The method of claim 1, wherein, In response to a cache miss, the first node interacts with the home node to perform the atomic memory operation.

8. The method of claim 1, wherein, The atomic memory operation comprises one of: AMOLoad, AMOCompare, AMOSwap.

9. A multi-core processor comprising a plurality of cores, characterized in that, At least one core of the plurality of cores is configured as a first node to perform the method according to any one of claims 1 to 8.

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