A graph-based traversal method and apparatus for power electronic converter topologies

Abstract

The application discloses a kind of based on graph theory's power electronic converter topological traversal method and device, it is related to power electronic converter topological technical field.The method includes: setting circuit element quantity and node quantity, each circuit element is represented as edge and numbered;All numbers are counted, 0 element is supplemented, and unordered array is obtained;All elements of unordered array are arranged in ascending order or descending order, and a plurality of ordered arrays are obtained;For each ordered array, its elements are sequentially filled into the upper triangular region of matrix, and the lower triangular region is filled based on the elements of the upper triangular region;Diagonal elements are set to 0;For each matrix, confirm the corresponding graph connection, and convert the graph connection into circuit element connection according to the number, to obtain the power electronic converter topology.The method can determine all potential power electronic converter topologies based on the number of circuit elements and nodes;Further, it can provide topological data support for determining the optimal performance of power electronic converter topology for each specific application scenario.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of power electronic converter topology, and particularly relates to a power electronic converter topology traversal method and device based on graph theory. BACKGROUND

[0002] With the rapid development of new energy power generation, new energy vehicles, energy storage and other technical fields, power electronic converters capable of efficiently and flexibly converting and controlling electric energy have been widely used.

[0003] Traditional power electronic converter topologies are difficult to meet the high-quality electric energy conversion requirements in multiple application scenarios. Therefore, how to determine the power electronic converter topology with optimal performance in a specific application scenario has become an urgent technical requirement. Further, the traditional power electronic converter derivation method usually relies on the experience and inspiration of designers, and is greatly affected by chance factors, making it difficult to quickly and accurately determine all potential power electronic converter topologies. SUMMARY

[0004] To solve the above technical problems in the prior art, the present application aims to provide a power electronic converter topology traversal method that can obtain all potential power electronic converter topologies in a specific application scenario.

[0005] Specifically, in a first aspect, the present application provides a power electronic converter topology traversal method based on graph theory, comprising the following steps:

[0006] Step S1: Set the number of circuit elements m and the number of nodes n in the power electronic converter topology to be generated, represent each circuit element as an edge, and number them;

[0007] Step S2: Count all numbers, and supplement (n 2 -n-2m) / 2 0 elements to represent non-connected edges, to obtain an unordered array of (n 2 -n) / 2 dimensions;

[0008] Step S3: Sort all elements of the unordered array in ascending order or descending order to obtain multiple ordered arrays of (n 2 -n) / 2 dimensions;

[0009] Step S4: For an ordered array, fill its elements into the upper triangular region of an n-order matrix one by one, and fill the elements of the lower triangular region based on the elements of the upper triangular region; fill the diagonal elements as 0;

[0010] Determine the corresponding graph connection according to the value and position of each element, and convert the graph connection to a circuit element connection according to the number, to obtain a power electronic converter topology;

[0011] Wherein, the element of the i-th row and the j-th column of the n-order matrix corresponds to the edge between the i-th node and the j-th node in the graph connection, i=1, 2, …, n, j=1, 2, …, n;

[0012] Step S5: traversing each ordered array according to step S4.

[0013] In a second aspect, the present application provides a graph theory-based power electronic converter topology traversal device, comprising:

[0014] A first generating module is configured to determine the number of circuit elements m and the number of nodes n in the power electronic converter topology to be generated;

[0015] A second generating module is configured to represent each circuit element as an edge and number them;

[0016] A third generating module is configured to count all the numbers, and supplement (n 2 -n-2m) / 2 0 elements to represent non-connected edges, to obtain an unordered array of (n 2 -n) / 2 dimensions;

[0017] A fourth generating module is configured to arrange all the elements of the unordered array in ascending order or descending order, to obtain a plurality of ordered arrays of (n 2 -n) / 2 dimensions;

[0018] A fifth generating module is configured to fill the elements of the ordered array into the upper triangular region of the n-order matrix in the order from left to right and from top to bottom;

[0019] Further configured to fill the elements of the n-order matrix,

[0020] When the element of the j-th row and the i-th column corresponds to a circuit element allowing bidirectional current, the same element is filled into the i-th row and the j-th column; when the element of the j-th row and the i-th column corresponds to a circuit element allowing unidirectional current, 0 is filled into the i-th row and the j-th column; wherein, i>j;

[0021] Further configured to fill the diagonal elements as 0;

[0022] A sixth generating module is configured to convert the n-order matrix into a corresponding graph connection according to the values and positions of the elements;

[0023] A seventh generating module is configured to convert the graph connection into a circuit element connection, to obtain the power electronic converter topology.

[0024] Compared with the prior art, the technical solution provided by the present application can determine all potential power electronic converter topologies based on the number of circuit elements and the number of nodes; further, it can provide topology data support for determining the power electronic converter topology with the optimal performance for each specific application scenario. BRIEF DESCRIPTION OF DRAWINGS

[0025] Figure 1 A flow chart of a graph theory based power electronic converter topology traversal method in an embodiment of the present application.

[0026] Figure 2 A schematic diagram of a correspondence between actual circuit elements and numbered edges in an embodiment of the present application.

[0027] Figure 3 A schematic diagram of a correspondence between an n-order matrix and an n-node graph in an embodiment of the present application.

[0028] Figure 4 A schematic diagram of a correspondence between an n-node graph and a power electronic converter in an embodiment of the present application.

[0029] Figure 5 A schematic diagram of a structure of a power electronic converter topology traversal device in an embodiment of the present application. DETAILED DESCRIPTION

[0030] In the following, the technical solutions provided by the present application will be further described in detail with reference to the embodiments and the accompanying drawings.

[0031] Embodiment 1

[0032] The flow of the graph theory based power electronic converter topology traversal method provided by the present embodiment is shown in FIG. 1 and includes the following steps: Figure 1

[0033] Step S1, set the number of circuit elements and the number of connection nodes of the circuit elements of the power electronic converter topology to be generated.

[0034] Specifically, the approximate number range of the inductors, capacitors, power devices and other circuit elements to be used is determined respectively, and the number range of the circuit element connection nodes is determined, and within the above-mentioned device and node number range, all devices and nodes satisfying the requirements are analyzed respectively.

[0035] Step S2, convert all circuit elements into abstract numbered edges.

[0036] Specifically, for a specific number of circuit elements including inductors, capacitors, power devices and the like, mathematical modeling is performed, and the circuit elements are converted into abstract numbered edges in a manner that different circuit elements correspond to different numbers and the same circuit elements correspond to the same number.

[0037] Step S3, count the numbers of all edges, and supplement 0 elements according to the number of nodes to obtain an unordered array.

[0038] ​Specifically, the numbers of all edges are composed into a multi-dimensional unordered array, and based on this, a proper number of 0 elements are added to facilitate the representation of non-connected edges. If there are n nodes and m edges in total, n(n-1) / 2-m 0 elements are added to obtain an n(n-1) / 2-dimensional unordered array.

[0039] Step S4, the unordered array is sorted, and all ordered arrays that can be formed are output in ascending or descending order.

[0040] Specifically, all elements contained in the n(n-1) / 2-dimensional unordered array are sorted using a sorting algorithm, and all n(n-1) / 2-dimensional ordered arrays that can be formed by the n(n-1) / 2-dimensional unordered array are output in ascending or descending order.

[0041] Step S5, the elements of an ordered array are filled into the upper triangular region of the matrix, the elements of the lower triangular region of the matrix are determined according to the original circuit element type, and the diagonal elements are set to 0.

[0042] Specifically, for a specific n(n-1) / 2-dimensional ordered array, it is filled into the upper triangular region of an n-order matrix excluding the diagonal line according to certain principles, and the size of the lower triangular region of the n-order matrix excluding the diagonal line is determined according to the original circuit element type corresponding to different numbers, and the diagonal elements are set to 0.

[0043] Step S6, repeat the above process until all ordered arrays are filled into the matrix.

[0044] Specifically, the above process of obtaining an n-order matrix is repeated.

[0045] Step S7, based on the above matrix, the corresponding graph connection mode is obtained.

[0046] Specifically, consider that each n-order matrix corresponds to a graph connection mode composed of n nodes. Among them, the element in the ith row and jth column of the n-order matrix corresponds to the connection between the ith node and the jth node in the graph connection. Further, corresponding to the power electronic converter topology, the value of the element represents the number of circuit elements. If it is 0, it means that the ith node and the jth node are not directly connected through a single circuit element.

[0047] Step S8, convert the graph connection into circuit element connection according to the numbering principle to obtain a potential power electronic converter topology.

[0048] Specifically, by traversing the multi-dimensional ordered array, the traversal of all graph connection modes is indirectly realized and converted into the connection topology of circuit elements, i.e. the potential power electronic converter topology, thereby realizing the traversal of all possible power electronic converters composed of n circuit elements.

[0049] The correspondence between the actual circuit elements of the embodiment and the numbered edges is shown as Figure 2 .

[0050] Specifically, the input / output voltage port, the inductive element, the capacitive element, and the power device correspond to different numbers respectively. The input voltage port V i and the output voltage port V o are numbered 1, the inductive element L is numbered 2, the IGBT (Insulated Gate Bipolar Transistor) and the MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) are numbered 3, and the capacitive element C is numbered 4.

[0051] Specifically, the elements of an ordered array are sequentially filled into the upper triangular region of the matrix in the order of "from left to right, from top to bottom", and the lower triangular region of the matrix is determined according to the original circuit element type corresponding to the array element. If the original circuit element allows the bidirectional flow of circuit current, the element in the i-th row and the j-th column of the lower triangular region of the matrix is consistent with the element in the j-th row and the i-th column of the upper triangular region of the matrix; if the original circuit element only allows the unidirectional flow of circuit current, the element in the i-th row and the j-th column of the lower triangular region corresponding to the element in the j-th row and the i-th column of the upper triangular region of the matrix is directly set to 0. In addition, the diagonal elements of the matrix are directly set to 0.

[0052] For example, the process of converting the 6-dimensional ordered array {0, 1, 1, 2, 3, 3} and the ordered array {0, 2, 1, 3, 1, 3} into a 4-order matrix is as follows,

[0053] ;

[0054] .

[0055] The correspondence between the n-order matrix of the embodiment and the n-node graph is shown as Figure 3 .

[0056] Specifically, a specific n-order matrix corresponds to a uniquely determined graph connection mode with n numbered nodes, and a specific graph connection mode with n numbered nodes corresponds to a uniquely determined n-order matrix, and the two constitute a bijection.

[0057] The n-node graph of the embodiment corresponds to the corresponding mode of the power electronic converter as shown in Figure 4

[0058] Specifically, one specific graph connection mode with n numbered nodes corresponds to one uniquely determined power electronic converter topology with numbered nodes, and one specific power electronic converter topology with numbered nodes corresponds to one uniquely determined graph connection mode with n numbered nodes, both of which constitute a bijection.

[0059] The following verifies a graph theory-based power electronic converter topology traversal method of the embodiment of the application with one specific embodiment, specifically including:

[0060] Step (1): Set the number of circuit elements of the power electronic converter topology to be generated, including 2 input / output ports, 1 inductor, and 2 IGBTs, and set the number of connection nodes to be 4.

[0061] Step (2): Abstract the physical model of the circuit element into an edge with a number, the 2 input / output ports are represented by 2 edges numbered 1, the 1 inductor is represented by 1 edge numbered 2, and the 2 IGBTs are represented by 2 edges numbered 3.

[0062] Step (3): Count the numbers of all edges to form an unordered array {1, 1, 2, 3, 3}, and add 1 0 element to the unordered array according to the number of nodes to obtain a new unordered array {0, 1, 1, 2, 3, 3}.

[0063] Step (4): Sort the new unordered array {0, 1, 1, 2, 3, 3} and output all ordered arrays that can be formed in ascending order, including {0, 1, 1, 2, 3, 3}, {0, 1, 1, 3, 2, 3}, {0, 1, 1, 3, 3, 2}, …, {3, 3, 2, 1, 0, 1}, {3, 3, 2, 1, 1, 0}.

[0064] Step (5): Fill the elements of the ordered array {0, 1, 1, 2, 3, 3} into the upper triangular region of the matrix in the order of “from left to right, from top to bottom”, since the input / output port, the inductor, and the IGBT all allow bidirectional current flow, the matrix is a symmetric matrix, and the diagonal elements are set to 0, obtaining the matrix:

[0065] ;

[0066] ​Step (6): Repeat step (5) to complete the conversion of the ordered array {0, 1, 1, 3, 2, 3}, {0, 1, 1, 3, 3, 2}, …, {3, 3, 2, 1, 0, 1}, {3, 3, 2, 1, 1, 0} to the matrix.

[0067] Step (7): Based on the matrix in steps (5) and (6), the corresponding graph connection mode is obtained, and the element in the ith row and jth column of the matrix represents the number of the one-way edge connected from node i to node j in the graph connection, for the matrix in step (5), the element in the 1st row and 2nd column is 0, indicating that there is no direct connection edge from node ① to node ②, the element in the 1st row and 3rd column is 1, indicating that there is a connection edge numbered 1 from node ① to node ③, and the remaining elements of the matrix are the same, and the connection mode between all nodes can be obtained on this basis.

[0068] Step (8): According to the numbering principle in step (2), the connection mode of the circuit elements between different nodes can be obtained, and the connection edges numbered 1, 2 and 3 correspond to input / output ports, inductors and IGBTs respectively.

[0069] After the above steps are completed, the traversal of all potential power electronic converter topologies can be realized.

[0070] Based on the embodiment and the drawings, it can be seen that the technical scheme provided by the present application has the function of realizing the traversal of potential power electronic converter topologies, thereby providing a large number of options for designers, and enabling the converter topologies to be flexibly selected according to specific requirements in different application scenarios.

[0071] To realize embodiment 1, the present application further provides a power electronic converter topology traversal device based on graph theory, as shown in Figure 5 The device comprises a first generation module M1, a second generation module M2, a third generation module M3, a fourth generation module M4, a fifth generation module M5, a sixth generation module M6 and a seventh generation module M7.

[0072] The first generation module M1 is used to determine the number of circuit elements and the number of connection nodes of the power electronic converter topology to be generated.

[0073] The second generation module M2 is used to realize the conversion of the circuit elements from actual devices to abstract graphs according to the number of circuit elements in M1, and to number them.

[0074] The third generation module M3 is used to count all the numbers in M2, and supplement 0 elements according to the number of nodes in M1, to form an unordered array with all the elements.

[0075] A fourth generation module M4 is configured to sort the unordered arrays in M3 and output all ordered arrays that can be formed by the unordered arrays in ascending / descending order;

[0076] A fifth generation module M5 is configured to fill an ordered array in M4 into the upper triangular region of a matrix, determine the lower triangular region and diagonal elements of the matrix, and repeat the above process until all ordered arrays in M4 are filled;

[0077] A sixth generation module M6 is configured to convert the matrix in M5 into a corresponding graph connection mode;

[0078] A seventh generation module M7 is configured to convert the graph connection mode in M6 into a circuit element connection according to the numbering mode in M2 to obtain all possible power electronic converter topologies.

[0079] As can be seen from the above, compared with the prior art, the technical solution provided by the application can determine all potential power electronic converter topologies based on the number of circuit elements and the number of nodes; further, the technical solution can provide topology data support for determining the power electronic converter topology with optimal performance for each specific application scenario.

Claims

1. A graph theory-based topology traversal method for power electronic converters, characterized in that, Includes the following steps: Step S1: Define the number of circuit elements m and the number of nodes n in the proposed power electronic converter topology, represent each circuit element as an edge, and number it; Step S2: Count all numbers and supplement (n) 2 -n-2m) / 2 zero elements represent non-connected edges, resulting in a (n 2 -n) / 2-dimensional unordered array; Step S3: Sort all elements of the unsorted array in ascending or descending order to obtain multiple (n) 2 -n) / 2 dimensional ordered array; Step S4: For an ordered array, fill its elements into the upper triangular region of an n-order matrix in sequence, and fill the lower triangular region with the elements based on the elements of the upper triangular region. Fill the diagonal elements with 0; The corresponding graphical connections are determined based on the values ​​and positions of each element, and the graphical connections are converted into circuit element connections according to the numbers to obtain a power electronic converter topology; In this context, the element in the i-th row and j-th column of the n-order matrix corresponds to the edge connecting the i-th node and the j-th node in the graph connection, i = 1, 2, ..., n, j = 1, 2, ..., n; Step S5: Traverse each sorted array according to step S4.

2. The graph theory-based topology traversal method for power electronic converters as described in claim 1, characterized in that, The step of sequentially filling its elements into the upper triangular region of an n-order matrix specifically includes: Fill the upper triangular region of the n-order matrix with the elements of the sorted array in order from left to right and from top to bottom; The process of filling the lower triangular region with elements based on the upper triangular region specifically includes: In an n-order matrix, if the circuit element corresponding to the element in the j-th row and i-th column is allowed to have bidirectional current, then fill in the same element in the i-th row and j-th column; otherwise, fill in 0; where i > j.

3. A graph-theory-based topology traversal device for power electronic converters, characterized in that, include: The first generation module is used to determine the number of circuit elements m and the number of nodes n in the proposed power electronic converter topology; The second generation module is used to represent each circuit element as an edge and number it; The third generation module is used to count all numbers and supplement (n) 2 -n-2m) / 2 zero elements represent non-connected edges, resulting in a (n 2 -n) / 2-dimensional unordered array; The fourth generation module is used to sort all elements of an unordered array in ascending or descending order, resulting in multiple (n) 2 -n) / 2 dimensional ordered array; The fifth generation module is used to fill the elements of the ordered array into the upper triangular region of the n-order matrix in order from left to right and from top to bottom. It is also used in an n-order matrix to fill the same element in the i-th row and j-th column when the circuit element corresponding to the element in the j-th row and i-th column is allowed to have bidirectional current. When the circuit element corresponding to the element in row j and column i is only allowed to have unidirectional current, fill in 0 in row i and column j; where i > j; It is also used to fill diagonal elements with 0; The sixth generation module is used to convert an n-order matrix into a corresponding graphical connection based on the value and position of each element; The seventh generation module is used to convert graphical connections into circuit element connections to obtain the power electronic converter topology.

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