Compound semiconductor back hole device, method for manufacturing the same, and transistor

Abstract

The application discloses a compound semiconductor back hole device and a preparation method and a transistor thereof, and belongs to the technical field of semiconductor devices. The device comprises a compound semiconductor substrate, a back hole, one of palladium, a palladium alloy, platinum or a platinum alloy formed by chemical plating as a metal seed layer, and an AgX alloy layer (X is Au, Pd or Pt, and the content is 0-50%) formed by electroplating. The preparation method comprises the steps of etching the back hole, preparing the seed layer by chemical plating, and electroplating the AgX alloy layer. The seed layer of palladium, a palladium alloy, platinum or a platinum alloy effectively blocks the diffusion of silver, solves the problems of high cost of traditional pure gold and poor reliability of copper or silver, realizes the cost reduction while ensuring and improving the long-term reliability of the device, and is especially suitable for compound semiconductor radio frequency devices.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor devices, and relates to a compound semiconductor back hole device and a preparation method and a transistor thereof. BACKGROUND

[0002] Compound semiconductor devices, such as heterojunction bipolar transistors (HBT) and high electron mobility transistors (HEMT), have irreplaceable roles in power amplifiers, micron wave and millimeter wave electronic components in the fields of national defense, aerospace, oil exploration, broadband communication, automobile manufacturing and smart grid, etc. due to their excellent high-frequency characteristics. Such devices usually need to be prepared with back holes and metalized through the back holes to achieve good grounding and heat dissipation.

[0003] At present, in the compound semiconductor back hole metallization process in the industry, gold is used as the back hole metal by the vast majority of people. For example, patent documents CN113808948A, CN110767604B, etc. all disclose the use of gold. This is mainly because gold has excellent physical and chemical properties: low diffusion coefficient, not easy to react or mutually diffuse with other materials; high thermal conductivity, conducive to heat dissipation; good oxidation resistance, can maintain stable electrical properties for a long time.

[0004] However, with the continuous and substantial rise in global gold prices, the use of pure gold as a back hole metal has brought huge cost pressure to semiconductor suppliers. In order to reduce costs, the industry has explored the use of copper as a substitute for gold. Copper has good electrical conductivity and thermal conductivity, and its price is much lower than that of gold. However, the diffusion coefficient of copper atoms in compound semiconductors is extremely high, and even if a trace amount of copper diffuses to the active area of the device such as the source electrode, it will cause serious degradation or even failure of the device performance. In addition, the device failure problem caused by copper oxidation is also a potential risk. Therefore, due to the inability to solve the reliability problems caused by copper diffusion and oxidation, this scheme has not been applied in mass production.

[0005] On the other hand, considering that silver sintering process is usually used when packaging radio frequency devices to connect them to copper lines of the circuit board, theoretically, using silver or silver alloy as back hole metal has advantages in bonding compatibility. However, silver itself also has the problem of high diffusion coefficient, especially in high temperature environments, silver atoms in the seed layer prepared by traditional physical vapor deposition, such as TiAu or TiWAu, are easy to oxidize, causing voids or cracks at the plating layer interface, which seriously affects the reliability of the device, such as the problem mentioned in patent document CN119852281A.

[0006] In summary, existing technologies suffer from the following drawbacks: 1) using pure gold is costly; 2) using copper presents serious diffusion reliability issues, hindering mass production; 3) simply replacing gold with silver leads to interface reliability problems due to silver diffusion in traditional seed layer processes. Therefore, there is an urgent need in the field for a new compound semiconductor back-hole metallization technology that can simultaneously resolve the conflict between cost and reliability. Summary of the Invention

[0007] The primary objective of this invention is to overcome the shortcomings of existing technologies and provide a novel compound semiconductor back-hole device, aiming to solve the problems of excessive cost due to the use of pure gold as the back-hole metal and the diffusion reliability issues that exist when using copper or silver. Another objective of this invention is to provide a method for fabricating the aforementioned back-hole device, which employs a specific seed layer technology combined with AgX alloy plating to ensure that costs are significantly reduced without sacrificing, and may even improve, the long-term reliability of the device. To achieve the above objectives, this invention adopts the following technical solution.

[0008] In a first aspect, the present invention provides a compound semiconductor back-hole device, comprising:

[0009] A compound semiconductor substrate having a front side and a back side, wherein a surface metal layer is formed on the front side; the surface metal layer is typically gold, but other suitable metals or alloys may also be selected.

[0010] A back hole is formed on the back side of the substrate and exposes the surface metal layer;

[0011] A metal seed layer is formed in the back hole and on the back side of the substrate, wherein the material of the metal seed layer is one of palladium, palladium alloy, platinum or platinum alloy;

[0012] An AgX alloy layer is formed on the metal seed layer, wherein X is at least one of Au, Pd, and Pt, and the weight content of X in the AgX alloy layer is 0% to 50%.

[0013] The compound semiconductor back-hole device provided by this invention creates a unique structure of "palladium, palladium alloy, platinum or platinum alloy as seed layer + AgX alloy layer". The AgX alloy layer replaces pure gold to reduce costs, while the palladium / platinum or their alloys are used as seed layer to block silver diffusion and avoid device reliability issues. At the same time, compared with titanium or titanium-tungsten alloys, it does not have the problem of interface failure at high temperature, thus ensuring the balance between low cost and high reliability at the material level.

[0014] Preferably, the material of the compound semiconductor substrate is gallium arsenide or gallium nitride.

[0015] Preferably, the thickness of the metal seed layer is 20~500 nm. This thickness range ensures that the seed layer has good continuity, conductivity, and diffusion blocking effect, while avoiding excessive thickness that would increase costs or generate internal stress.

[0016] Preferably, the thickness of the AgX alloy layer is 1~5μm. This thickness range ensures that the back hole metal has good electrical conductivity, thermal conductivity, and mechanical strength, meeting the requirements for device grounding and heat dissipation, while controlling process time and material costs.

[0017] Secondly, the present invention provides a method for fabricating a compound semiconductor back-hole device, comprising the following steps:

[0018] A compound semiconductor substrate is provided having a front side and a back side, wherein a surface metal layer, typically gold, is formed on the front side.

[0019] Etching is performed from the back side of the substrate to form a back hole that exposes the surface metal layer;

[0020] A metal seed layer is formed in the back hole and on the back side of the substrate by a chemical plating process. The material of the metal seed layer is one of palladium, palladium alloy, platinum or platinum alloy.

[0021] An AgX alloy layer is formed on the metal seed layer by an electroplating process, wherein X is at least one of Au, Pd, and Pt, and the weight content of X in the AgX alloy layer is 0% to 50%.

[0022] The preparation method provided by this invention effectively suppresses the diffusion of silver atoms in the subsequent AgX alloy layer at high temperatures by using one of electroless palladium plating, palladium alloy, platinum, or platinum alloy as a seed layer, thereby improving the reliability of the device. Simultaneously, by forming the AgX alloy layer through electroplating, replacing pure gold as the main metal, the manufacturing cost is significantly reduced.

[0023] The preparation method provided by the present invention has no special requirements for chemical plating and electroplating processes. A metal seed layer of the target thickness can be obtained by using conventional chemical plating processes in the art, and an AgX alloy layer of the target thickness and composition can be obtained by using conventional electroplating processes in the art.

[0024] Thirdly, the present invention provides a heterojunction bipolar transistor or a high electron mobility transistor, comprising the compound semiconductor back-hole device provided by the present invention.

[0025] Compared with the prior art, the present invention has the following significant beneficial technical effects:

[0026] (1) Significantly reduced cost: This invention uses AgX alloy (with silver as the main component) to replace pure gold as the main body of the back hole metal. The market price of silver is much lower than that of gold. By controlling the content of X elements (Au, Pd, Pt) in the alloy to 0-50%, the raw material cost of the back hole metal can be significantly reduced, effectively alleviating the cost pressure on semiconductor suppliers caused by rising gold prices.

[0027] (2) Significantly improved reliability: This invention creatively employs a process of electroless plating of palladium, palladium alloy, platinum, or platinum alloy to prepare the seed layer. Palladium, palladium alloy, platinum, or platinum alloy are known excellent diffusion barrier layer materials. The palladium, palladium alloy, platinum, or platinum alloy seed layer formed by electroless plating is dense, continuous, and has good adhesion to the compound semiconductor substrate. It can effectively block the diffusion of silver atoms in the subsequent AgX alloy layer to the active region (such as the source electrode) of the device under high-temperature processing or long-term operating conditions, fundamentally solving the device reliability problem caused by silver or copper diffusion.

[0028] (3) Compared with titanium or titanium-tungsten as an adhesive layer, silver and palladium, palladium alloys, platinum or platinum alloys are all precious metals with good compatibility between metals. Therefore, long-term placement at high temperature will not cause problems such as interface voids or poor bonding due to oxidation.

[0029] (4) Good process synergy: This invention combines a specific seed layer technology (electrochemical palladium plating, palladium alloy plating, platinum plating, or platinum alloy plating) with a specific main metal layer (electroplating AgX alloy plating) to form a complete and optimized technical solution. The electrochemical plating process has good step coverage, which can ensure the formation of a uniform seed layer in the back hole with a large depth-to-width ratio. The electroplating AgX alloy plating process is mature and controllable, and the alloy ratio can be precisely controlled by adjusting the composition of the electroplating solution. The combination of the two results in a smooth process flow and easy integration into existing semiconductor production lines.

[0030] (5) Broad application prospects: This invention is particularly suitable for high-performance compound semiconductor radio frequency devices, such as HEMTs and HBTs based on GaAs or GaN. These devices are extremely sensitive to cost and reliability. The solution provided by this invention precisely meets this market demand, and has extremely high industrialization value and broad application prospects. Attached Figure Description

[0031] Figure 1 This is a schematic diagram of a compound semiconductor and a front-side metal.

[0032] Figure 2 This is a schematic diagram of back-hole etching in a compound semiconductor.

[0033] Figure 3 This is a schematic diagram of the preparation of a seed layer using chemical plating of compound semiconductors.

[0034] Figure 4 This is a schematic diagram of AgX alloy electroplating in compound semiconductors.

[0035] Figure 5 These are SEM images of a compound semiconductor back-hole device prepared using the process described in Example 1 of this invention.

[0036] Figure reference numerals: 101-Surface metal layer; 102-Compound semiconductor substrate; 103-Metal seed layer; 104-AgX alloy layer. Detailed Implementation

[0037] The technical solution of the present invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the protection scope of the present invention.

[0038] First, combined Figures 1 to 4 The structure of the compound semiconductor back-hole device described in this invention will be explained.

[0039] See Figure 4 The compound semiconductor back-hole device provided by the present invention includes:

[0040] A compound semiconductor substrate 102 has a front side and a back side, wherein a surface metal layer 101 is formed on the front side;

[0041] A back hole is formed on the back side of the compound semiconductor substrate 102 and exposes the surface metal layer 101;

[0042] A metal seed layer 103 is formed in the back hole and on the back side of the compound semiconductor substrate 102. The material of the metal seed layer 103 is one of palladium, palladium alloy, platinum or platinum alloy.

[0043] An AgX alloy layer 104 is formed on the metal seed layer 103, wherein X is at least one of Au, Pd, and Pt, and the weight content of X in the AgX alloy layer 104 is 0% to 50%.

[0044] This structure is the core of the invention. Through a unique combination of "palladium, palladium alloy, platinum or platinum alloy as a seed layer + AgX alloy layer", it ensures a balance between low cost and high reliability at the material level.

[0045] The present invention will be further illustrated below through specific examples of preparation methods.

[0046] Example 1

[0047] Fabricate GaAs devices with AgAu alloy back holes.

[0048] Substrate provided: See Figure 1 A compound semiconductor substrate 102 is provided, which is made of GaAs, and an active region structure and a surface metal layer 101 have been formed on its front side by conventional semiconductor processes.

[0049] Back hole etching: See Figure 2 A back hole pattern is defined on the back side of the compound semiconductor substrate 102 by photolithography, and then a deep reactive ion etching process is used to etch downwards until the surface metal layer 101 on the front side is fully exposed to form a back hole.

[0050] See chemically plated metal seed layer: Figure 3 The etched wafer was immersed in an electroless palladium plating solution. The solution consisted of 4 g / L palladium chloride, 15 ml / L ammonia (28% concentration), 30 mg / L sodium thiosulfate, and 15 g / L sodium hypophosphite. The pH was adjusted to 9 with ammonia, and the solution temperature was controlled at 45°C. Under these conditions, the deposition rate of electroless palladium plating was approximately 2 μm / h. By controlling the immersion time, a dense and continuous metal seed layer 103, approximately 100 nm thick, was formed on the inner wall of the back hole and the entire back side of the substrate. The material was palladium.

[0051] Electroplated AgAu alloy: See Figure 4 A wafer with a metal seed layer 103 is placed in a horizontal electroplating apparatus and immersed in a silver-gold alloy electroplating solution for electroplating. The electroplating solution consists of: potassium silver cyanide with a silver ion concentration of 8 g / L, potassium gold cyanide with a gold ion concentration of 8 g / L, 5,5-dimethylhydantoin as a complexing agent, and potassium pyrophosphate as a conductive salt. The pH is adjusted to 9 with potassium hydroxide, the solution temperature is controlled at 30°C, and a current density of 0.5 ASD is applied. After electroplating for a certain period of time, an AgX alloy layer 104 with a thickness of approximately 4 μm is formed, where X represents Au. By adjusting the ratio of potassium silver cyanide and potassium gold cyanide in the plating solution, the final alloy layer is controlled to have a silver weight content of 90% and a gold weight content of 10%.

[0052] Subsequent processes: After electroplating, standard processes such as photoresist removal, cleaning, and annealing can be performed as needed.

[0053] Figure 5 The SEM image of the back-hole device fabricated in this embodiment is shown. It can be clearly seen from the image that the palladium seed layer is well bonded to the GaAs substrate without delamination; the AgAu alloy layer completely fills the back hole, providing uniform coverage without voids or cracks, and the interface is clear and dense.

[0054] Example 2

[0055] Fabrication of GaN devices with AgPd alloy back holes.

[0056] Providing a substrate and etching the back hole: The steps are similar to those in Example 1, but the compound semiconductor substrate 102 is made of GaN.

[0057] Electroless plating of the metal seed layer: The wafer is immersed in an electroless plating solution. The solution composition is: 4 g / L disodium hexahydroxyplatinate, 5 g / L sodium hydroxide, 10 g / L ethylenediamine, and 1 g / L hydrazine monohydrate. The pH is adjusted to 9 with sodium hydroxide, and the solution temperature is controlled at 30°C. The deposition rate is approximately 4 μm / h. By controlling the immersion time, a metal seed layer 103 with a thickness of approximately 20 nm is formed, and the material is platinum.

[0058] Electroplating of AgPd alloy: The wafer is placed in a silver-palladium alloy electroplating solution for electroplating. The electroplating solution composition is as follows: silver nitrate providing 4 g / L silver ions, tetraamminepalladium nitrate providing 6 g / L palladium ions, disodium ethylenediaminetetraacetate providing 10 g / L, potassium nitrate providing 60 g / L, pH adjusted to 9 with ammonia, temperature 30℃, and current density 0.5 ASD. After electroplating, an AgX alloy layer 104 with a thickness of approximately 1 μm is formed, where X is Pd, and the weight content of silver is 70% and palladium is 30%.

[0059] The subsequent processes are the same as in Example 1.

[0060] Example 3

[0061] Fabricate GaAs devices with AgPt alloy back holes.

[0062] Substrate and back hole etching: The steps are the same as in Example 1.

[0063] Chemically plated metal seed layer: The steps are the same as in Example 1, forming a metal seed layer 103 with a thickness of about 500 nm, the material of which is palladium.

[0064] Electroplating of AgPt alloy: The wafer is placed in a silver-platinum alloy electroplating solution for electroplating. The electroplating solution composition is as follows: silver nitrate providing 4 g / L silver ions, tetraammineplatinum nitrate providing 4 g / L platinum ions, disodium ethylenediaminetetraacetate (EDTA) at 30 g / L, potassium nitrate at 60 g / L, pH adjusted to 10 with ammonia, temperature 50°C, and current density 0.5 ASD. After electroplating, an AgX alloy layer 104 with a thickness of approximately 5 μm is formed, where X is Pt, and the weight content of silver is 50% and platinum is 50%.

[0065] The subsequent processes are the same as in Example 1.

[0066] Comparative Example

[0067] Traditional TiAu seed layer + electroplated pure silver.

[0068] In contrast, a Ti / Au composite seed layer was prepared using conventional PVD sputtering, followed by electroplating of a pure silver layer. The prepared devices were then subjected to high-temperature storage tests together with the device from Example 1 of this invention. The results showed that after 1000 hours of storage at 150°C, the comparative device exhibited significant cracking and voids at the back-hole metal interface; while the device from Example 1 of this invention maintained an intact interface under the same conditions, demonstrating extremely high reliability.

[0069] Although embodiments of the present invention have been shown and described above, it is understood that these embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions, and alterations to the above embodiments within the scope of the present invention without departing from its principles and spirit. The scope of protection of the present invention is defined by the claims and their equivalents.

Claims

1. A compound semiconductor back hole device characterized by comprising: The compound semiconductor substrate has a front surface and a back surface, and the front surface is formed with a surface metal layer. A back hole is formed in the back surface of the substrate and exposes the surface metal layer. A metal seed layer is formed in the back hole and on the back surface of the substrate by a chemical plating process, and the material of the metal seed layer is one of palladium, palladium alloy, platinum or platinum alloy. An AgX alloy layer is formed on the metal seed layer, wherein X is at least one of Au, Pd and Pt, and the weight content of X in the AgX alloy layer is 50% or less. The material of the compound semiconductor substrate is gallium arsenide or gallium nitride.

2. The compound semiconductor back hole device according to claim 1, wherein The thickness of the metal seed layer is 20-500 nm.

3. The compound semiconductor back hole device according to claim 1, characterized by The thickness of the AgX alloy layer is 1-5 μm.

4. The compound semiconductor back hole device according to claim 1, characterized by The compound semiconductor substrate has a front surface and a back surface, and the front surface is formed with a surface metal layer.

5. A method for manufacturing a compound semiconductor back hole device, characterized by A back hole is formed in the back surface of the substrate and exposes the surface metal layer. A metal seed layer is formed in the back hole and on the back surface of the substrate by a chemical plating process, and the material of the metal seed layer is one of palladium, palladium alloy, platinum or platinum alloy. An AgX alloy layer is formed on the metal seed layer, wherein X is at least one of Au, Pd and Pt, and the weight content of X in the AgX alloy layer is 50% or less. The compound semiconductor substrate has a front surface and a back surface, and the front surface is formed with a surface metal layer. A back hole is formed in the back surface of the substrate and exposes the surface metal layer.

6. A heterojunction bipolar transistor or high electron mobility transistor, characterized in that, A metal seed layer is formed in the back hole and on the back surface of the substrate by a chemical plating process, and the material of the metal seed layer is one of palladium, palladium alloy, platinum or platinum alloy. An AgX alloy layer is formed on the metal seed layer, wherein X is at least one of Au, Pd and Pt, and the weight content of X in the AgX alloy layer is 50% or less. The compound semiconductor substrate has a front surface and a back surface, and the front surface is formed with a surface metal layer. A back hole is formed in the back surface of the substrate and exposes the surface metal layer. A metal seed layer is formed in the back hole and on the back surface of the substrate by a chemical plating process, and the material of the metal seed layer is one of palladium, palladium alloy, platinum or platinum alloy. An AgX alloy layer is formed on the metal seed layer, wherein X is at least one of Au, Pd and Pt, and the weight content of X in the AgX alloy layer is 50% or less. The compound semiconductor substrate has a front surface and a back surface, and the front surface is formed with a surface metal layer. A back hole is formed in the back surface of the substrate and exposes the surface metal layer. A metal seed layer is formed in the back hole and on the back surface of the substrate by a chemical plating process, and the material of the metal seed layer is one of palladium, palladium alloy, platinum or platinum alloy. An AgX alloy layer is formed on the metal seed layer, wherein X is at least one of Au, Pd and Pt, and the weight content of X in the AgX alloy layer is 50% or less. The compound semiconductor substrate has a front surface and a back surface, and the front surface is formed with a surface metal layer. A back hole is formed in the back surface of the substrate and exposes the surface metal layer. A metal seed layer is formed in the back hole and on the back surface of the substrate by a chemical plating process, and the material of the metal seed layer is one of palladium

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