Drive signal calibration circuit for h-bridge circuits, digital to analog converter and transmitter

Abstract

Embodiments of the present disclosure provide a driving signal calibration circuit of an H-bridge circuit, a digital-to-analog converter and a transmitter. The driving signal calibration circuit comprises a virtual H-bridge circuit, at least two pairs of switching elements and at least two pairs of driving units arranged correspondingly; a phase detection unit configured to detect the phase sequence relationship between a pair of driving signals and output a phase relationship detection signal; a logic judgment unit configured to count the phase relationship detection signal every predetermined time period and generate an adjustment signal according to the counting result; and a level adjustment unit configured to adjust the supply voltage according to the adjustment signal to adjust the phase relationship between a pair of driving signals, wherein the supply voltage of the driving unit of the calibrated H-bridge circuit is the same as the supply voltage of a pair of driving units. The technical solution of the present disclosure can effectively improve the signal accuracy and output linearity in high-speed and high-swing H-bridge circuits and H-bridge digital-to-analog converters, and improve the signal integrity.

Description

Technical Field

[0001] This invention relates to electronic circuits, and more particularly to a drive signal calibration circuit for an H-bridge circuit, and a digital-to-analog converter and a SerDes transmitter using the circuit. Background Technology

[0002] In the structure of an H-bridge circuit, the switching devices of the upper and lower bridge arms are typically controlled by two complementary drive signals. To avoid shoot-through between the upper and lower arms and to ensure the symmetry of the output waveform, the phase, amplitude, and threshold of the two drive signals need to be precisely matched.

[0003] However, in actual circuits, due to circuit layout, manufacturing process, temperature changes, etc., the driving delay is inconsistent or the power supply voltage fluctuates. The driving signals of the upper and lower arms often have phase deviation or edge misalignment, which leads to output waveform distortion, reduced efficiency, affects signal integrity, and may even cause overcurrent or device breakdown risks.

[0004] To achieve high signal-to-noise ratio and excellent linearity, high-speed, high-precision digital-to-analog converters (DACs) commonly employ a differential output structure with an H-bridge circuit. This timing mismatch severely limits the performance of high-speed DACs.

[0005] Existing technologies propose an open-loop delay matching compensation method, which artificially adds delay units to the drive path to compensate for the asymmetric delay introduced by the level converter, thereby realigning the PMOS and NMOS control signals. While this method can improve timing mismatches to some extent, it still has significant drawbacks: firstly, fixed delay units can affect signal integrity in high-speed applications; secondly, this compensation is an open-loop matching method, limited by layout routing positions and the Monte Carlo effect, making it difficult to achieve stable and accurate results. To address this, some research has proposed using variable delay units for dynamic adjustment. However, variable delay units often introduce bandwidth limitations, increase power consumption, or add noise, ultimately affecting signal path integrity and the output performance of the digital-to-analog converter.

[0006] Therefore, how to effectively align the drive signals of the H-bridge and maintain excellent signal integrity under high-speed data transmission (especially above 10GHz) has become a technical problem that urgently needs to be solved in this field. Summary of the Invention

[0007] Based on the deficiencies of the prior art, this disclosure aims to provide a circuit capable of self-calibrating H-bridge drive signals and a digital-to-analog converter using the circuit.

[0008] A first aspect of this disclosure provides a drive signal calibration circuit for an H-bridge circuit, including a virtual H-bridge circuit comprising at least two pairs of switching elements and at least two pairs of corresponding drive units. The virtual H-bridge circuit is used to receive a virtual clock signal and an inverted signal of the virtual clock signal. A phase detection unit is configured to receive a pair of drive signals sent by a pair of drive units from the at least two pairs of drive units, detect the phase sequence relationship between the pair of drive signals, and output a phase relationship detection signal. A logic judgment unit is configured to perform statistics on the phase relationship detection signal at each predetermined time period and generate an adjustment signal based on the statistical results. A level adjustment unit is configured to adjust the supply voltage of the pair of drive units according to the adjustment signal to adjust the phase relationship between the pair of drive signals, thereby adjusting the phase relationship of the drive signal of the H-bridge circuit being calibrated, wherein the supply voltage of the drive unit of the H-bridge circuit being calibrated is the same as the supply voltage of the pair of drive units.

[0009] The embodiments of this disclosure construct a replica path that accurately reflects the dynamic characteristics of the original H-bridge circuit. The supply voltage of the driving unit in this replica path can be the same as the supply voltage of the driving unit in the H-bridge circuit being calibrated. This virtual H-bridge circuit is driven by a virtual clock signal to generate multiple driving signals corresponding to the real H-bridge circuit, providing a stable and controllable test signal source for phase detection. The phase detection unit detects the phase sequence relationship between the upper and lower bridge arm driving signals of each bridge arm in the multiple driving signals and outputs the detection result to the logic judgment unit. The logic judgment unit generates a corresponding level adjustment signal based on the statistical results of the phase relationship.

[0010] The level adjustment unit can dynamically adjust the upper and / or lower limits of the power supply voltage of the drive unit according to the level adjustment signal, thereby achieving automatic phase alignment of the drive signal by changing the delay characteristics of the drive stage. This embodiment can achieve automatic calibration of the drive signal without introducing an additional delay unit in the signal path, thus avoiding the problems of limited signal bandwidth, increased noise, and increased power consumption caused by existing delay compensation schemes. This scheme can effectively improve signal symmetry and output linearity, improve signal integrity, reduce common-mode noise and dynamic distortion, and significantly improve the overall high-speed performance and robustness of the system in high-speed, large-swing H-bridge digital-to-analog converter circuits.

[0011] Optionally, in the drive signal calibration circuit of the H-bridge circuit according to the first aspect of the present disclosure, the virtual H-bridge circuit further includes a level converter connected to one of the drive units in each pair of drive units. The level converter is used to convert the level it receives into a level adapted to the switching element driven by the one drive unit, and output the converted level to the one drive unit.

[0012] Optionally, each pair of switching elements in the virtual H-bridge circuit includes a P-type transistor and an N-type transistor, with each pair of P-type and N-type transistors forming a bridge arm structure, and each drive unit includes a buffer or amplifier. Optionally, the virtual H-bridge circuit may include more than one level of buffers for progressively driving signals and improving signal edge characteristics. The buffer connected to the switching elements of the differential output circuit may be the last level buffer. The H-bridge circuit may consist of two bridge arms, each including a pair of P-type and N-type transistors. The midpoint of the two bridge arms is connected to a load element to form a differential output node.

[0013] The level converter can convert the signal level output from the pre-stage buffer into a level that matches the driving requirements of the upper bridge arm P-type transistor. Optionally, the level converter can convert the logic level into a high-level signal that matches the corresponding switching element, making the drive signal calibration circuit of the H-bridge circuit particularly suitable for high-swing scenarios.

[0014] Optionally, in the drive signal calibration circuit of the H-bridge circuit according to the first aspect of the present disclosure, the phase detection unit includes an AC coupling buffer module configured to AC couple the at least one pair of drive signals to remove the DC component and establish a DC bias point; and a phase comparison module configured to receive the output of the AC coupling buffer module and compare the phase sequence relationship between the pair of drive signals.

[0015] Optionally, in the drive signal calibration circuit of the H-bridge circuit according to the first aspect of the present disclosure, the AC coupling buffer module includes a coupling capacitor configured to remove the DC component in the drive signal; a multi-stage inverter including a plurality of inverters connected in series; and a feedback resistor configured to have one end connected to the output terminal of the coupling capacitor and its two ends connected in parallel with at least one inverter in the multi-stage inverter.

[0016] Optionally, the multi-stage inverter can be connected in series with a coupling capacitor, and the feedback resistor can generate a bias voltage at the node where it is connected to the coupling capacitor, thereby establishing a DC bias point. The phase comparator module can compare the phase order of the drive signals of the P-type transistor and the N-type transistor on a bridge arm.

[0017] Optionally, in the drive signal calibration circuit of the H-bridge circuit according to the first aspect of the present disclosure, the phase comparison module includes a D flip-flop, the clock terminal and data terminal of the D flip-flop respectively receive the pair of drive signals, and the signal output by the output terminal of the D flip-flop represents the phase sequence relationship of the pair of drive signals.

[0018] Optionally, in the drive signal calibration circuit of the H-bridge circuit according to the first aspect of the present disclosure, the phase detection unit further includes a phase difference detection module, which includes logic gates and RC filters to convert the phase difference of the pair of drive signals into a voltage signal.

[0019] Optionally, in the drive signal calibration circuit of the H-bridge circuit according to the first aspect of the present disclosure, the logic judgment unit is configured to receive a phase relationship detection signal, the two drive signals include a first drive signal and a second drive signal, and to count the number of detection signals indicating that the first drive signal leads and the second drive signal leads respectively within the predetermined time period, and to generate an adjustment signal based on the statistical results.

[0020] Optionally, the phase comparison module can use two D flip-flops to output detection signals indicating that the first drive signal leads and the second drive signal leads, respectively.

[0021] Optionally, the adjustment signal can indicate whether the power supply voltage of the drive unit needs to be adjusted and the direction of the adjustment. Statistically analyzing the phase relationship within a predetermined time window before deciding whether and how to adjust the power supply voltage can avoid frequent small-amplitude repetitive adjustments, significantly improving closed-loop stability. When the phases are almost coincident, the output of the phase comparison module may be uncertain or random; statistical majority decision can effectively suppress disturbances and make the decision more robust.

[0022] Optionally, in the drive signal calibration circuit of the H-bridge circuit according to the first aspect of the present disclosure, when the difference between the number of detection signals in which the first drive signal leads and the number of detection signals in which the second drive signal leads exceeds a predetermined threshold within the predetermined time period, the supply voltage of the first drive unit is adjusted in fixed steps. For example, the low potential voltage of the buffer for directly driving the P-type transistor and / or the high potential voltage of the buffer for directly driving the N-type transistor can be adjusted in fixed steps.

[0023] Optionally, in the drive signal calibration circuit of the H-bridge circuit according to the first aspect of the present disclosure, the circuit structure of the virtual H-bridge circuit is the same as the circuit structure of the H-bridge circuit being calibrated. Alternatively, the circuit structure of the virtual H-bridge circuit can be configured such that the phase difference of the drive signal of the drive unit is consistent with the phase difference of the drive signal of the drive unit of the H-bridge circuit being calibrated.

[0024] A second aspect of the present disclosure provides a digital-to-analog converter (DAC) including a drive signal calibration circuit for an H-bridge circuit as described in any of the preceding claims and a plurality of DAC units, each DAC unit having an H-bridge circuit with the same circuit structure. Optionally, the circuit structure of the virtual H-bridge circuit is the same as the circuit structure of the H-bridge circuit of the DAC unit in the DAC.

[0025] A third aspect of the present disclosure provides a SerDes transmitter, including a feedforward equalizer, a multiplexer, a digital-to-analog converter (DAC) as described above, and a clock generation circuit. The feedforward equalizer, the multiplexer, and the DAC are connected in sequence, and the clock generation circuit provides corresponding clock signals to the feedforward equalizer, the multiplexer, and the DAC.

[0026] Implementing any apparatus or method of this disclosure does not necessarily require achieving all of the advantages described above simultaneously. Other features and advantages of this disclosure will be set forth in the following description and will be apparent in part from the description and embodiments, or may be learned by practicing this disclosure. The objects and advantages of embodiments of this disclosure may be realized and obtained by means of the structures pointed out in the description, claims, and drawings. Attached Figure Description

[0027] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly introduced below. Obviously, the drawings described below only relate to some embodiments of this disclosure, and are not intended to limit this disclosure.

[0028] Figure 1 This is a schematic diagram of a drive signal calibration circuit for an H-bridge circuit according to an embodiment of the present disclosure;

[0029] Figure 2 This is a schematic diagram of the phase detection unit of the drive signal calibration circuit of an H-bridge circuit according to an embodiment of the present disclosure;

[0030] Figure 3 This is a schematic diagram of the structure of an H-bridge circuit of a plurality of digital-to-analog converter units according to an embodiment of the present disclosure;

[0031] Figure 4 This is a schematic diagram of the drive signal calibration circuit of the H-bridge circuit of a digital-to-analog converter according to an embodiment of the present disclosure;

[0032] Figure 5 This is a schematic diagram of a SerDes transmitter according to an embodiment of the present disclosure, which can be used... Figure 3 and Figure 4 The digital-to-analog converter shown;

[0033] Figure 6 This is a schematic diagram of an H-bridge circuit based on existing technology. Detailed Implementation

[0034] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. Various different embodiments can be combined with each other to constitute other embodiments not shown in the following description. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0035] Unless otherwise defined, the technical or scientific terms used herein should have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure and the claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an” or “a” and similar terms do not necessarily indicate a quantity limitation. The terms “comprising” or “including” and similar terms mean that the element or object preceding the word covers the element or object listed following the word and its equivalents, without excluding other elements or objects. The terms “connected” or “linked” and similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper,” “lower,” “left,” “right,” etc., are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described object changes.

[0036] Figure 6 A schematic diagram of an existing H-bridge circuit is shown. This H-bridge circuit typically includes four power switching devices, for example, two pairs of complementary P-type and N-type transistors, forming the upper and lower bridge arms, respectively. By controlling the on and off states of the switching devices in each bridge arm, the direction and amplitude of the current flowing through the load can be modulated, thereby forming a bidirectional differential signal across the load. The input signals VIP and VIN of the H-bridge circuit are output to the switching devices via buffers as drive signals. Ideally, the two complementary drive signals (e.g., Figure 6 The signals A' and B', and Ab' and Bb' shown should be strictly synchronized in the time domain to ensure the symmetry of the output waveform and the correct switching of the bridge arm conduction state.

[0037] However, as described in the background section, differences in hardware layout and process parameters can lead to timing mismatches between A' and B', and between Ab' and Bb'. This can not only cause common-mode noise and waveform distortion, but may also cause the upper and lower transistors to conduct simultaneously for a brief period, generating shoot-through current, which in turn significantly reduces the dynamic performance and signal integrity of the system.

[0038] Figure 1 A schematic diagram of the drive signal calibration circuit of an H-bridge circuit according to an embodiment of the present disclosure is shown. Figure 1 As shown, the drive signal calibration circuit of the H-bridge circuit includes a first virtual H-bridge circuit 10, a first phase detection unit 20, a first logic judgment unit 30, and a first level adjustment unit 40. The first virtual H-bridge circuit 10 may have the same topology as the original H-bridge circuit being calibrated. For example, the original H-bridge circuit being calibrated is as follows: Figure 6 The circuit shown is an example. The original H-bridge circuit refers to the main circuit used for the actual output differential signal, whose drive signals require phase alignment and / or adjustment. The first virtual H-bridge circuit 10 is only used to generate a signal for phase detection, used for the alignment and / or adjustment of the drive signals, and does not participate in the output signal. Optionally, the first virtual H-bridge circuit 10 may also have a topology that is not exactly the same as the original H-bridge circuit being calibrated. The first virtual H-bridge circuit can be configured as an equivalent circuit to the original H-bridge circuit, or the phase relationship between the drive signals in the first virtual H-bridge circuit can be consistent with the phase relationship of the drive signals in the original H-bridge circuit being calibrated.

[0039] In this embodiment, the first virtual H-bridge circuit 10 receives complementary virtual clock signals at its input. The first buffer BUF1 and the fourth buffer BUF4 respectively receive the first virtual clock signals, which are inversely related, and are used to drive the upper and lower arms of the first virtual H-bridge circuit 10. The frequency of this first virtual clock signal does not need to be the same as the system clock; a clock signal with a lower frequency than the system clock can be used, resulting in lower power consumption, simpler circuit construction, and lower cost.

[0040] Because the first virtual H-bridge circuit topology has the aforementioned relationship with the original H-bridge circuit, the driving signal used to drive the first virtual H-bridge circuit can accurately reflect the phase relationship and delay characteristics between the driving signals of the original H-bridge circuit, providing a realistic input excitation environment for phase detection and delay adjustment. By using a virtual H-bridge circuit for phase detection, instead of directly acquiring signals from the original H-bridge circuit, the influence on the main circuit output characteristics and load conditions can be effectively avoided, thereby achieving phase detection and accurate calibration of the driving signal.

[0041] The first virtual H-bridge circuit 10 includes a first signal driving circuit and a first differential output circuit. The first signal driving circuit receives a first virtual clock signal and its inverted signal as input signals, and generates two sets of driving signals A and B, and Ab and Bb, respectively. The first signal driving circuit may include one or more stages of buffers. Optionally, the input signals may pass through at least two stages of buffers to output driving signals A, B, Ab, and Bb, which are then input to the first differential output circuit. Figure 1 In this embodiment, the first signal driving circuit includes first to sixth buffers BUF1-BUF6. The buffers not only provide level driving capability but can also shape and / or amplify signals. The buffers can be used to enhance driving capability while simultaneously achieving signal isolation to prevent mutual interference between preceding logic and the driving signal. The buffers can be implemented using one or more inverters, or other equivalent level driving circuits, such as amplifiers or gated output stages.

[0042] The first differential output circuit may include complementary P-type and N-type transistor structures to achieve differential signal output. Specifically, for example, a first P-type transistor P1 and a first N-type transistor N1 form a first bridge arm, and a second P-type transistor P2 and a second N-type transistor N2 form a second bridge arm. The source of P1 is connected to the power supply voltage VDD1, its drain is connected to the drain of N1, and the source of N1 is grounded. Similarly, the source of P2 is connected to the power supply voltage VDD1, its drain is connected to the drain of N2, and the source of N2 is grounded. A first load element R1 is connected between the midpoints of the two bridge arms. That is, one end of the first load element R1 is connected to the connection node of P1 and N1, and the other end is connected to the connection node of P2 and N2. R1 in Figure 1 In this embodiment, a resistive element is used, but it can also be configured as an inductive load or an active load, depending on the application. P-type and N-type transistors can be PMOS and NMOS, or other suitable transistors.

[0043] The first signal driving circuit provides drive signals for the switching elements of the first differential output circuit. On one side of the first virtual H-bridge circuit, the input of the first buffer BUF1 receives the first virtual clock, and its output is connected to the inputs of the second buffer BUF2 and the third buffer BUF3, respectively. The outputs of the second buffer BUF2 and the third buffer BUF3 are connected to the gates of P1 and N1 in the first differential output circuit, respectively, and output drive signals A and B.

[0044] Specifically, the high-potential terminal of BUF2 is connected to a fixed power supply voltage VDD1, and the low-potential terminal voltage is VCC1; the high-potential terminal of BUF3 is VCC2, and its low-potential terminal is grounded. The output signal of BUF2 is connected to the gate of P1. When the output signal of BUF2 is high, P1 is off; when the output signal of BUF2 is low, P1 is on. The output signal of BUF3 is connected to the gate of N1. When the output signal of BUF3 is high, N1 is on; when the output signal of BUF3 is low, N1 is off. Thus, the drive signals A and B change complementaryly, causing the two arms of the first differential output circuit to conduct alternately, achieving complementary differential drive.

[0045] Similarly, on the other side of the first virtual H-bridge circuit, the input of the fourth buffer BUF4 receives the inverted signal of the first virtual clock, and its output is connected to the inputs of the fifth buffer BUF5 and the sixth buffer BUF6, respectively. The outputs of BUF5 and BUF6 are connected to the gates of P2 and N2 in the first differential output circuit, respectively, and output drive signals Ab and Bb, respectively.

[0046] Specifically, the high-potential terminal of BUF5 is connected to a fixed power supply voltage VDD1, and the low-potential terminal voltage is VCC1; the high-potential terminal of BUF6 is VCC2, and its low-potential terminal is grounded. The output signal of BUF5 is connected to the gate of P2. When the output signal of BUF5 is high, P2 is off; when the output signal of BUF5 is low, P2 is on. The output signal of BUF6 is connected to the gate of N2. When the output signal of BUF6 is high, N2 is on; when the output signal of BUF6 is low, N2 is off. Thus, the drive signals Ab and Bb change complementaryly, causing the two arms of the first differential output circuit to conduct alternately, achieving complementary differential drive.

[0047] exist Figure 1 In the illustrated embodiment, the drive units driving the two switching elements on each bridge arm have the same supply voltage; that is, the drive units driving P1 and P2 have the same supply voltage; the drive units driving N1 and N2 have the same supply voltage. The aforementioned supply voltage of the first virtual H-bridge circuit is the same as the supply voltage of the drive circuit of the original H-bridge circuit being calibrated.

[0048] By controlling the conduction states of the four switching transistors, a variable-direction current can be generated across the first load element. When P1 and N2 are on, and P2 and N1 are off, the current flows from the power source through P1 to the first load element, then through N2 to ground, creating a positive voltage across the first load element. When P2 and N1 are on, and P1 and N2 are off, the current path changes to flow from the power source through the first load element, then through N1 to ground, creating a reverse voltage across the first load element.

[0049] Misalignment of drive signals between P1 and N1, and between P2 and N2, may occur due to hardware circuit layout, transmission paths, etc. When the rising or falling edges of the two drive signals cannot be perfectly aligned, the upper and lower bridge arm devices may conduct simultaneously at the moment of switching, resulting in shoot-through current, reduced signal integrity, increased power consumption, waveform distortion, and increased jitter during high-speed signal transmission.

[0050] The on-time of P-type and N-type transistors (such as PMOS and NMOS) is related to the voltage between the source and gate. For Figure 1 In the circuit shown, when the phase of drive signal A leads that of drive signal B, the delay of drive signal A can be increased and / or the delay of drive signal B can be decreased by increasing VCC1 and / or increasing VCC2; similarly, when the phase of drive signal A lags that of drive signal B, the delay of drive signal A can be decreased and / or the delay of drive signal B can be increased by decreasing VCC1 and / or decreasing VCC2.

[0051] The first phase detection unit 20 of the H-bridge drive signal calibration circuit 1 receives a set of drive signals from one bridge arm, such as drive signals A and B, to determine the phase relationship between the drive signals, and optionally, to determine the phase difference between the drive signals. The first logic judgment unit 30 determines whether to adjust VCC1 and / or VCC2 and the direction of adjustment. The first level adjustment unit 40 adjusts VCC1 and / or VCC2 according to the output of the first logic judgment unit 30, thereby changing the voltage amplitude of the drive signals and adjusting the conduction timing of the corresponding transistors.

[0052] for Figure 1 In the illustrated embodiment, VCC1 and VCC2 are the lower limit voltage of the upper bridge arm drive signal and the upper limit voltage of the lower bridge arm drive signal, respectively. By adjusting the upper and lower limit voltages of the drive signals, the turn-on speed of the transistors can be changed, thereby achieving timing alignment of the two drive signals. The method of adjusting the drive signal voltage is not limited to this; the purpose is to change the voltage amplitude input to the transistors by adjusting the drive voltage, thereby achieving calibration of the H-bridge drive signals.

[0053] Figure 2 A schematic diagram of the structure of a first phase detection unit according to an embodiment of this application is shown. A first virtual H-bridge circuit 10 outputs a set of drive signals from one bridge arm to the input terminal of the first phase detection unit 20. For example, the set of drive signals are drive signals A and B, which are used to drive P1 and N1 respectively. Optionally, drive signals Ab and Bb can also be used as inputs to the first phase detection unit 20. The first phase detection unit 20 may include an AC coupling buffer module 21 and a phase comparison module 22. Optionally, the first phase detection unit 20 may further include a phase difference detection module 23.

[0054] The AC coupling buffer module 21 is used to AC couple the input signal to remove the DC component and establish a DC bias point, so that the output signal has a stable waveform and amplitude while maintaining its phase characteristics. The AC coupling buffer module 21 includes an AC coupling module, a DC bias establishment module, and a buffer module, and its processing method and circuit structure for the two drive signals A and B are the same.

[0055] An AC coupling module is used to AC couple a signal, removing the DC component from the signal and thereby extracting the AC component from the drive signal. In a preferred embodiment, as shown in the figures, the AC coupling module includes at least one coupling capacitor, such as capacitors C1 and C2. The first and second coupling capacitors C1 and C2 receive drive signals A and B, respectively, allowing only the AC component of the signal to pass through.

[0056] A DC bias establishment module is connected to the output of the AC coupling module and is used to establish a stable DC bias potential at the output node of the AC coupling module through a feedback mechanism. In a preferred embodiment, the DC bias establishment module includes feedback paths formed by a third resistor R3 and a fourth resistor R4, which stabilize the DC potential at the output of the AC coupling module at a predetermined level through the feedback mechanism. Specifically, R3 is connected in parallel between the input and output of the first inverter INV211, and R4 is connected in parallel between the input and output of the third inverter INV213, forming DC feedback bias paths respectively.

[0057] The buffer module can be used to shape and output signals from the AC-coupled module. In a preferred embodiment, the buffer module includes at least two stages of inverters. First and second inverters INV211 and INV212, and third and fourth inverters INV213 and INV214, each constitute two stages of inverters. These inverters can shape the rising and falling edges of the signal and provide sufficient current drive capability. The output signal of INV212 is at the same frequency as drive signal A, and the output signal of INV214 is at the same frequency as drive signal B, and both output signals are in phase with drive signals A and B, respectively.

[0058] The AC coupling module, DC bias establishment module, and buffer module can optionally be implemented using other circuits. For example, the AC coupling module can be implemented using a capacitor array, and the DC bias establishment module can be implemented using multiple resistors, active bias circuits, etc. The buffer module can include more stages of inverters as needed, or it can be implemented using other amplifiers or follower structures. The preferred embodiments shown in this disclosure have simple circuits, small footprint, and lower power consumption.

[0059] After being processed by AC coupling buffer module 21, drive signals A and B output signals are input to phase comparison module 22. Optionally, the output signal of AC coupling buffer module 21 can be further output to phase difference detection module 23. Phase comparison module 22 compares the phase order of the two signals and outputs a phase relationship detection signal. The phase relationship detection signal can be represented by high and low levels. For example, phase comparison module 22 outputs a high level (or signal "1") to indicate that signal A is leading, and outputs a low level (or signal "0") to indicate that signal B is leading. Alternatively, two signals can be output to represent the leading states of A and B respectively, for example... Figure 2 The phase comparison module 22 is shown.

[0060] Figure 2 A specific example of phase comparison module 22 is shown. Phase comparison module 22 can be implemented using D flip-flops. Two signals are input to the clock input (CLK) and data input (D) of the first and second D flip-flops D1 and D2, respectively. The phase order between the signals is determined by judging the level of the output Q. Phase comparison module 22 uses two D flip-flops to output two cases: A leading and B leading. After being processed by AC coupling buffer module 21, drive signals A and B are input to the data input and clock input of D1, respectively. A stable high level output of Q indicates that the phase of A leads the phase of B. Similarly, when they are input to the clock input and data input of D2, a stable high level output of Q indicates that the phase of B leads the phase of A. Alternatively, a single D flip-flop can be used to determine the phase order, with the high or low level output of Q indicating the phase relationship between the two signals. Using two flip-flops allows for a more balanced circuit layout and higher stability and reliability of the output signal.

[0061] The phase difference detection module 23 converts the phase difference between the two driving signals into a voltage signal for output as the phase difference detection signal. The phase difference detection module 23 may include a logic gate circuit and an RC filter circuit. Specifically, the logic gate circuit uses a NAND gate, whose inputs receive the two signals to be detected from the AC coupling module. When a phase difference exists between the two signals, the output of the NAND gate generates a pulse waveform, the pulse width of which is proportional to the phase difference between the two signals. The RC filter circuit is connected in series with the output of the NAND gate to convert the pulse signal into an analog voltage signal proportional to the phase difference. The RC filter circuit may consist of a fifth resistor R5 and a third capacitor C3, where the output of the NAND gate is connected to one end of C3 via R5, and the other end of C3 is grounded. The connection node between R5 and C3 forms a filter output node, the voltage of which is an integrated and smoothed analog signal, the level of which is proportional to the phase difference between the input signals. Therefore, the phase difference detection module 23 can convert the phase difference in the time domain into an analog voltage signal, realize the quantitative detection of the phase difference, and provide quantitative information for the adjustment of VCC1 and VCC2.

[0062] The phase comparison module 22 of the first phase detection unit 20 outputs a phase relationship detection signal to the first logic judgment unit 30. The first logic judgment unit 30 determines the phase relationship between driving signals A and B based on the detection signal from the phase comparison module 22. The first logic judgment unit 30 counts the number of detected signals in each predetermined period. If the number of signals indicating A leading is approximately equal to the number of signals indicating B leading within the predetermined time period, the driving signals are determined to be aligned, and the first logic judgment unit outputs a corresponding adjustment signal, indicating that VCC1 and VCC2 are not adjusted. If the number of signals indicating A leading is greater than the number of signals indicating B leading within the predetermined time period, and the difference is greater than a threshold, A is determined to lead B, and vice versa. Based on the judgment result, the first logic judgment unit 30 outputs an adjustment signal to adjust VCC1 and / or VCC2. Optionally, VCC1 and / or VCC2 can be adjusted using a fixed step size. For example, when it is determined that A is ahead of B, VCC1 and / or VCC2 can be increased step by step with a fixed step size. When it is determined that B is ahead of A, VCC1 and / or VCC2 can be decreased step by step with a fixed step size.

[0063] The first level adjustment unit 40 is used to dynamically adjust the upper and / or lower limits (VCC1, VCC2) of the buffer's supply voltage according to the adjustment signal output by the first logic judgment unit 30, thereby changing the output level range of the corresponding drive signal to achieve phase alignment between drive signals A and B. The first level adjustment unit 40 may include a digital-to-analog converter module (represented by DAC1 and DAC2 in the figure) and a voltage control module (not shown). The adjustment signal output by the first logic judgment unit 30 can be a digital control signal, indicating whether to adjust VCC1 and / or VCC2 and the direction of adjustment. The digital-to-analog converter module converts the digital signal into a corresponding analog voltage signal and outputs it to the voltage control module, which can then adjust VCC1 and VCC2 in fixed steps. The voltage control module may include a voltage buffer stage or a variable reference voltage circuit for stabilizing or adjusting the output voltages VCC1 and VCC2. Alternatively, the first level adjustment unit 40 may not include a digital-to-analog converter module, but instead use a variable reference source where the digital signal output by the first logic judgment unit controls the switching element to select different voltage divider paths, thereby changing the output voltage.

[0064] In one implementation, the first level adjustment unit 40 can adjust the voltage value in a fixed step manner, that is, increase or decrease the voltage values ​​of VCC1 and / or VCC2 in a fixed step manner within each control cycle, thereby achieving closed-loop phase calibration. For example, when the first logic judgment unit determines that the drive signal A leads relative to the signal B, the first level adjustment unit can increase VCC1 and / or VCC2 in a fixed step manner; when it determines that the signal B leads, it can decrease VCC1 and / or VCC2 in a fixed step manner. Optionally, adjusting VCC1 and VCC2 simultaneously can make the circuit more balanced, prevent common-mode voltage drift, and maintain the integrity and dynamic symmetry of the H-bridge drive signal. By adjusting VCC1 and VCC2, the phase relationship between drive signals A and B, as well as drive signals Ab and Bb, is calibrated.

[0065] In another embodiment, the first level adjustment unit 40 can also adjust simultaneously based on the adjustment signal output by the first logic judgment unit 30 and the phase difference detection signal output by the phase difference detection module 23, resulting in a larger adjustment range and faster adjustment speed. Furthermore, the adjustment signal output by the phase difference detection module allows the first level adjustment unit 40 to adjust the phase difference of the driving signals to a predetermined value as needed, rather than making the two driving signals perfectly aligned.

[0066] Due to the driving unit of the calibrated H-bridge circuit (e.g., Figure 6The buffer shown is connected to the same power supply voltage, and the phase difference of its switching element drive signal is basically consistent with the phase difference of the first virtual H-bridge circuit. Therefore, the drive signal of the H-bridge circuit can be calibrated by adjusting VCC1 and VCC2.

[0067] Figure 3 A circuit diagram of a portion of a digital-to-analog converter according to an embodiment of the present disclosure is shown. As a key interface circuit connecting the digital and analog domains, the performance of the digital-to-analog converter directly determines the overall performance limits of modern communication, audio, and video processing systems. Figure 3 A current-steering digital-to-analog converter is shown, which includes multiple digital-to-analog conversion units, each of which uses an H-bridge circuit with the same topology.

[0068] This circuit employs a differential output structure, comprising two sets of complementary bridge arms, each consisting of a pair of P-type and N-type transistors. The differential output circuit of the H-bridge circuit is similar to... Figure 1 The differential output circuit shown has the same structure. In this structure, the phase-complementary digital input signals Data_P[X:0] and Data_N[X:0] are each buffered and output in two separate paths. One path drives the last stage buffer of the upper bridge arm after passing through a level shifter, and the other path directly drives the last stage buffer. The level shifter is used to boost the input logic level to a level suitable for driving the P-type transistor of the upper bridge arm, thereby achieving a high-swing output. The low-potential voltage of the upper bridge arm buffer is VCC11, and the high-potential voltage of the lower bridge arm buffer is VCC12. The drive voltage of the upper bridge arm varies between the power supply VDD11 and VCC11, and the drive voltage of the lower bridge arm varies between VCC12 and ground. If the drive signal is not calibrated, the voltage boosting path of the level shifter will introduce an additional delay, resulting in inconsistent delays between the upper and lower paths of the circuit, further causing the phase of the drive signal to be misaligned. Misalignment of delays between bridge arms can cause imbalance in differential outputs, leading to common-mode voltage drift and increased harmonic distortion in the output signal. This problem is particularly prominent in high-swing, high-speed digital-to-analog converter applications, affecting signal integrity and the linear performance of the digital-to-analog converter.

[0069] Figure 4 It is used for Figure 3 A schematic diagram of the drive signal calibration circuit of the H-bridge circuit of the digital-to-analog converter. The drive signal calibration circuit of the H-bridge circuit of the digital-to-analog converter includes a second virtual H-bridge circuit 100, a second phase detection unit 200, a second logic judgment unit 300, and a second level adjustment unit 400. Figure 4 circuit and Figure 1 The difference in their circuits lies in the different virtual H-bridge circuit structures. Figure 4 In the illustrated embodiment, the second virtual H-bridge circuit includes a level shifter.

[0070] The second virtual H-bridge circuit 100 can have the same... Figure 3 The digital-to-analog converter (DAC) shown has the same circuit topology as the H-bridge circuit, but the second virtual H-bridge circuit 100 is only used to generate a signal for phase detection, used for alignment and / or adjustment of the drive signal, and does not participate in the output signal. The difference between the second virtual H-bridge circuit 100 and the first virtual H-bridge circuit 10 is that it includes a level shifter, enabling it to be used in high-swing applications. Optionally, the second virtual H-bridge circuit 100 may also have a topology that is not exactly the same as the H-bridge circuit of the calibrated DAC. The second virtual H-bridge circuit can be configured to be an equivalent circuit to the H-bridge circuit of the DAC, or the phase relationship between the drive signals in the second virtual H-bridge circuit can be consistent with the phase relationship of the drive signals in the original calibrated H-bridge circuit.

[0071] In this embodiment, the second virtual H-bridge circuit 100 receives complementary virtual clock signals at its input. The seventh buffer BUF11 and the tenth buffer BUF14 receive these inverse second virtual clock signals, which drive the upper and lower arms of the second virtual H-bridge circuit 100. The frequency of this second virtual clock signal does not need to be the same as the system clock of the digital-to-analog converter; a lower frequency clock signal can be used, resulting in lower power consumption, simpler circuit construction, and lower cost.

[0072] Because the topology of the second virtual H-bridge circuit has the aforementioned relationship with the H-bridge circuit of the digital-to-analog converter (DAC), the drive signal used to drive the second virtual H-bridge circuit can accurately reflect the phase relationship and delay characteristics between the drive signals of the DAC's H-bridge circuit, providing a realistic input excitation environment for phase detection and delay adjustment. By using the virtual H-bridge circuit for phase detection, the influence on the output characteristics and load conditions of the main circuit can be effectively avoided, thereby achieving phase detection and accurate calibration of the drive signal.

[0073] The second virtual H-bridge circuit 100 includes a second signal driving circuit and a second differential output circuit. The second signal driving circuit receives a second virtual clock signal and its inverted signal as input signals, and generates two sets of driving signals A2, B2 and Ab2, Bb2, respectively. The second signal driving circuit may include multiple buffers and level shifters; the input signal can pass through at least two stages of buffers to obtain the driving signal for input to the second differential output circuit. The second signal driving circuit includes seventh to twelfth buffers BUF11-BUF16. The function of the buffers is... Figure 1 The buffer in the circuit serves the same purpose. A buffer can be implemented using one or more inverters, or other equivalent level-driving circuits, such as amplifiers or gated output stages.

[0074] The second differential output circuit has the same structure as the first differential output circuit. The second differential output circuit may include complementary P-type and N-type transistor structures to achieve differential signal output. Specifically, for example, a third P-type transistor P11 and a third N-type transistor N11 form the first bridge arm, and a fourth P-type transistor P12 and a fourth N-type transistor N12 form the second bridge arm. The source of P11 is connected to the power supply voltage VDD11, its drain is connected to the drain of N11, and the source of N11 is grounded. Similarly, the source of P12 is connected to the power supply voltage VDD11, its drain is connected to the drain of N12, and the source of N12 is grounded. The second load element R11 is connected between the midpoints of the two bridge arms; that is, one end of R11 is connected to the connection node of P11 and N11, and the other end is connected to the connection node of P12 and N12. R11 in Figure 4 In this embodiment, a resistive element is used, but it can also be configured as an inductive load or an active load, depending on the application. P-type and N-type transistors can be PMOS and NMOS, or other suitable transistors.

[0075] The second signal driving circuit provides the driving signal for the switching element. On one side of the second differential output circuit, the input of the seventh buffer BUF11 receives the second virtual clock, and its output is connected to the input of the first level converter 101 and the input of the ninth buffer BUF13, respectively. The output of the first level converter 101 is connected to the input of the eighth buffer BUF12, and the outputs of BUF12 and BUF13 are connected to the gates of P11 and N11 of the second differential output circuit, respectively, outputting driving signals A2 and B2 to them.

[0076] Specifically, the high-potential terminal of BUF12 is connected to a fixed power supply voltage VDD11, and the low-potential terminal is connected to VCC11; the high-potential terminal of BUF13 is connected to VCC12, and its low-potential terminal is grounded. The output signal of BUF12 is connected to the gate of P11. When the output signal of BUF12 is high, P11 is off; when the output signal of BUF12 is low, P11 is on. The output signal of BUF13 is connected to the gate of N11. When the output signal of BUF13 is high, N11 is on; when the output signal of BUF13 is low, N11 is off. Thus, the drive signals A2 and B2 change complementaryly, causing the upper and lower arms on the left side of the second differential output circuit to conduct alternately, achieving complementary differential drive.

[0077] The first level converter 101 is used to adjust the voltage domain, boosting a low voltage domain to a high voltage domain, for example, adjusting a voltage domain with a high potential of 1.2V to a voltage domain with a high potential of 3.3V. The first level converter 101 can be implemented using existing level converters, such as CMOS level conversion circuits, current mirror level conversion circuits, and other circuit structures.

[0078] Similarly, on the other side of the first virtual H-bridge circuit, the input of the tenth buffer BUF14 receives the inverted signal of the second virtual clock, and its output is connected to the input of the second level converter 102 and the input of the twelfth buffer BUF16, respectively. The output of the second level converter 102 is connected to the input of the eleventh buffer BUF15, and the outputs of BUF15 and BUF16 are connected to the gates of P12 and N12 in the second differential output circuit, respectively, outputting drive signals Ab2 and Bb2.

[0079] Specifically, the high-potential terminal of BUF15 is connected to a fixed power supply voltage VDD11, and the low-potential terminal voltage is VCC11; the high-potential terminal of BUF16 is VCC12, and its low-potential terminal is grounded. The output signal of BUF15 is connected to the gate of P12. When the output signal of BUF15 is high, P12 is off; when the output signal of BUF15 is low, P12 is on. The output signal of BUF6 is connected to the gate of N12. When the output signal of BUF16 is high, N12 is on; when the output signal of BUF16 is low, N12 is off. Thus, the drive signals Ab2 and Bb2 change complementaryly, causing the upper and lower bridge arms on the right side of the second differential output circuit to conduct alternately, achieving complementary differential drive.

[0080] The first and second level shifters can be voltage-boosting level shifters, whose inputs can receive signals from a virtual clock and whose outputs generate high-potential signals (e.g., 2.5–3.3V) suitable for driving the upper bridge arm P-type transistors. The aforementioned supply voltage of the second virtual H-bridge circuit is the same as the supply voltage of the drive circuit of the H-bridge circuit of the calibrated digital-to-analog converter.

[0081] By controlling the conduction states of the four switching transistors, a variable-direction current can be generated across the second load element. When P11 and N12 are on, and P12 and N11 are off, the current flows from the power source through P11 to the second load element, then to ground via N12, resulting in a positive voltage across the second load element. When P12 and N11 are on, and P11 and N12 are off, the current path changes to flow from the power source through the second load element, then to ground via N11, resulting in a reverse voltage across the second load element.

[0082] The drive signals A2 and B2 or Ab2 and Bb2 are output to the second phase detection unit 200. Figure 4In the illustrated embodiment, the second phase detection unit 200 detects the phase relationship of a set of drive signals, and optionally determines the phase difference of the drive signals; the second logic judgment unit 300 determines whether to adjust VCC11 and / or VCC12 and the direction of adjustment; the second level adjustment unit 400 adjusts VCC11 and / or VCC12 according to the output of the second logic judgment unit 300, thereby changing the voltage amplitude of the drive signal and adjusting the conduction timing of the corresponding switching element. The second phase detection unit 200, the second logic judgment unit 300, and the second level adjustment unit 400 of the drive signal calibration circuit of the H-bridge circuit are... Figure 1 and Figure 2 The first phase detection unit 20, the first logic judgment unit 30, and the first level adjustment unit 40 shown have the same structure. For the process of phase detection and drive signal adjustment, please refer to the above text. Figure 1 and Figure 2 The relevant details will not be repeated here. By adjusting VCC11 and VCC12, the phase relationship between drive signals A and B, and drive signals Ab and Bb, is calibrated. Since the drive units of the H-bridge circuit of the digital-to-analog converter are connected to the same supply voltage, the phase difference of their switching element drive signals is... Figure 3 The phase difference of the second virtual H-bridge circuit remains basically consistent. Therefore, the drive signal of the H-bridge circuit can be calibrated by adjusting VCC11 and VCC12.

[0083] For scenarios where high swing amplitude is not required, digital-to-analog converters can also be used with... Figure 6 The circuit shown is the same as the H-bridge circuit. Figure 1 The H-bridge drive signal calibration circuit can align or adjust the phase of the drive signal of the H-bridge circuit in the digital-to-analog converter.

[0084] Figure 5 A schematic diagram of a SerDes (serializer / deserializer) transmitter using the digital-to-analog converter described in an embodiment of this disclosure is shown. The SerDes transmitter mainly includes a feedforward equalizer (FFE) 51, a multiplexer (MUX) 52, a digital-to-analog converter 53, and a clock generation module 54.

[0085] The parallel digital signal is input to FFE 51, which performs pre-distortion compensation on the digital signal to suppress high-frequency attenuation and nonlinear distortion during channel transmission. The compensated signal is then sent to multiplexer 52. Multiplexer 52 may include one or more cascaded multiplexer modules to convert the parallel digital signal into a single high-speed serial digital signal. For example, the parallel digital signal can be sequentially generated into a single serial digital signal via a 64:4 multiplexer module and a 4:1 multiplexer module.

[0086] The digital-to-analog converter 53 receives a high-speed serial digital signal and converts it into an analog signal. Preferably, the digital-to-analog converter 53 can be a digital-to-analog converter as described in any of the above embodiments of this disclosure, for example... Figure 3 and Figure 4 The digital-to-analog converter (DAC) shown is equipped with a drive signal calibration circuit for an H-bridge circuit. The clock signals for the aforementioned parts of the SerDes transmitter can be provided by a clock generation circuit, which can provide different clock signals through frequency division or other methods. The DAC described in this embodiment can be effectively applied in high-speed SerDes transmission paths, improving overall signal integrity and thus enhancing the transmission quality of high-speed links.

[0087] Unlike existing technologies that achieve phase alignment by adding fixed or variable delay units to the signal path, this disclosure introduces a virtual H-bridge circuit to achieve equivalent signal replication and performs phase detection and feedback adjustment based on this virtual path. The technical solution of this disclosure detects the phase difference between the two drive signals at the output of the virtual H-bridge and outputs control signals through a phase detector and logic judgment circuit to dynamically adjust the upper and / or lower limits of the power supply voltage of the drive circuit, thereby achieving automatic phase alignment or adjustment of the drive signals of the switching devices. Because signal alignment is achieved by controlling the delay with the power supply voltage, rather than inserting additional delay elements into the signal path, no additional signal bandwidth limitations are introduced, resulting in lower noise and power consumption, and avoiding open-loop matching errors caused by process variations, layout mismatches, etc. Therefore, the technical solution of this disclosure can effectively improve signal accuracy and output linearity, enhance signal integrity, and improve the dynamic performance of the circuit in high-frequency applications in high-speed, high-swing H-bridge circuits and H-bridge digital-to-analog converters.

[0088] The embodiments of the present invention can be modified and altered in various ways without departing from the spirit and scope of the invention. Therefore, it should be understood that the scope of protection of the present invention should not be limited to the exemplary embodiments described above, but should cover the full scope defined by the claims and their equivalents.

Claims

1. A drive signal calibration circuit for an H-bridge circuit, characterized in that, include: A virtual H-bridge circuit includes at least two pairs of switching elements and at least two pairs of corresponding driving units. Each pair of switching elements in the virtual H-bridge circuit includes a P-type transistor and an N-type transistor. Each pair of P-type transistors and N-type transistors forms a bridge arm structure. The source of the P-type transistor is connected to the power supply voltage, and the source of the N-type transistor is grounded. Each driving unit includes a buffer or an amplifier. The input terminal of the virtual H-bridge circuit is used to receive a virtual clock signal and an inverted signal of the virtual clock signal. The phase detection unit is configured to receive a pair of driving signals sent by one pair of driving units from the at least two pairs of driving units, detect the phase sequence relationship between the pair of driving signals, and output a phase relationship detection signal. The logic judgment unit is configured to perform statistics on the phase relationship detection signal at each predetermined time period and generate an adjustment signal based on the statistical results. A level adjustment unit is configured to adjust the supply voltage of the pair of drive units according to the adjustment signal, thereby adjusting the phase relationship between the pair of drive signals and thus adjusting the phase relationship of the drive signals of the calibrated H-bridge circuit. The power supply voltage of the driving unit of the calibrated H-bridge circuit is the same as the power supply voltage of the pair of driving units, and the gate of each pair of P-type transistors and the gate of N-type transistors receive a pair of driving signals.

2. The drive signal calibration circuit for the H-bridge circuit according to claim 1, characterized in that, The virtual H-bridge circuit also includes a level converter connected to one of the driving units in each pair of driving units. The level converter is used to convert the level it receives into a level that is compatible with the switching element driven by the driving unit, and output the converted level to the driving unit.

3. The drive signal calibration circuit for the H-bridge circuit according to claim 1, characterized in that, The phase detection unit includes: An AC coupling buffer module is configured to AC couple the pair of drive signals, remove the DC component and establish a DC bias point; A phase comparison module is configured to receive the output of the AC coupling buffer module and compare the phase order between the pair of drive signals.

4. The drive signal calibration circuit for the H-bridge circuit according to claim 3, characterized in that, The AC coupling buffer module includes: The coupling capacitor is configured to remove the DC component from the pair of drive signals; A multi-stage inverter, comprising multiple inverters connected in series; A feedback resistor is configured such that one end is connected to the output of the coupling capacitor, and both ends of the feedback resistor are connected in parallel with at least one inverter in the multi-stage inverter.

5. The drive signal calibration circuit for the H-bridge circuit according to claim 3, characterized in that, The phase comparison module includes a D flip-flop, whose clock and data terminals respectively receive the pair of drive signals, and whose output terminal outputs a signal representing the phase sequence of the pair of drive signals.

6. The drive signal calibration circuit for the H-bridge circuit according to claim 1 or 3, characterized in that, The phase detection unit further includes a phase difference detection module, which includes logic gates and an RC filter to convert the phase difference of the pair of driving signals into a voltage signal.

7. The drive signal calibration circuit for the H-bridge circuit according to claim 1 or 3, characterized in that, The logic judgment unit is configured to receive the phase relationship detection signal, and within the predetermined time period, count the number of phase relationship detection signals indicating that the first driving signal in the pair of driving signals is leading and the number of phase relationship detection signals indicating that the second driving signal in the pair of driving signals is leading, respectively. When the difference between the number of phase relationship detection signals indicating that the first driving signal is leading and the number of phase relationship detection signals indicating that the second driving signal is leading exceeds a predetermined threshold within the predetermined time period, the power supply voltage of the pair of driving units is adjusted in fixed steps.

8. The drive signal calibration circuit for the H-bridge circuit according to claim 1, characterized in that, The circuit structure of the virtual H-bridge circuit is the same as that of the calibrated H-bridge circuit.

9. A digital-to-analog converter, characterized in that, The device includes a drive signal calibration circuit for the H-bridge circuit as described in any one of claims 1 to 8 and a plurality of digital-to-analog conversion units, each of which has an H-bridge circuit with the same circuit structure.

10. A SerDes transmitter, characterized in that, The system includes a feedforward equalizer, a multiplexer, a digital-to-analog converter as described in claim 9, and a clock generation circuit, wherein the feedforward equalizer, the multiplexer, and the digital-to-analog converter are connected in sequence, and the clock generation circuit provides corresponding clock signals to the feedforward equalizer, the multiplexer, and the digital-to-analog converter.

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