Phase detection based charge pump phase locked loop real time calibration circuit, method and apparatus

Abstract

This application provides a real-time calibration circuit, method, and apparatus for a charge pump phase-locked loop (PLL) based on phase detection. The real-time calibration circuit includes a time-to-digital converter (TDD) circuit, a thermometer code conversion circuit, and a logic state machine circuit. The TDD circuit converts two output signals from a frequency and phase detector into digital time signals based on the PLL lock indication signal output from the lock detection circuit. The thermometer code conversion circuit converts the digital time signals into binary code. The logic state machine circuit generates a calibration feedback control signal based on the binary code and transmits this signal to the current-rudder dual-channel switch charge pump in the PLL circuit to calibrate the voltage control signal output by the current-rudder dual-channel switch charge pump in real time. This real-time calibration circuit improves the consistency of the circuit under different processes, temperatures, and power supply voltages, and improves the reference spurious level of the PLL circuit.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a real-time calibration circuit, method, and apparatus for a charge pump phase-locked loop based on phase detection. Background Technology

[0002] This section is intended to provide background or context for the embodiments of this application set forth in the claims. The description herein is not an admission that it is prior art simply because it is included in this section.

[0003] In the field of integrated circuit technology, charge pump phase-locked loops (PLLs) are an important frequency synthesis and phase control circuit, widely used in various electronic systems such as communication, data processing, and radio frequency. Their core function is to achieve precise locking of the output signal and the reference signal in frequency and phase through closed-loop feedback, providing a stable clock or carrier signal for the system.

[0004] Current charge pump phase-locked loop circuits face many performance-related problems in practical applications, such as phase errors caused by non-ideal characteristics, the influence of environmental and process fluctuations, and the limitations of traditional calibration methods.

[0005] Therefore, to solve the above problems, a technology is needed that can detect phase error in real time and dynamically calibrate the charge pump based on the error, so as to improve the stability and accuracy of the charge pump phase-locked loop circuit under various environmental and process conditions. Summary of the Invention

[0006] The purpose of this invention is to provide a real-time calibration circuit, method, and apparatus for a charge pump phase-locked loop based on phase detection, so as to solve the technical problems of large circuit area and power consumption of charge pump phase-locked loops in the prior art.

[0007] One objective of this application is to provide a phase-detection-based real-time calibration circuit for a charge pump phase-locked loop (PLL), which uses digital calibration logic to improve analog mismatch. Real-time calibration can effectively improve the consistency of the PLL circuit under different processes, temperatures, and power supply voltages, improving the PLL reference spurious level with lower power consumption and area requirements. Another objective of this application is to provide a phase-detection-based real-time calibration method for a charge pump PLL. A further objective of this application is to provide a phase-detection-based charge pump PLL device.

[0008] To achieve the above objectives, this application discloses a real-time calibration circuit for a charge pump phase-locked loop based on phase detection, comprising:

[0009] A time-to-digital conversion circuit is connected to the frequency and phase detector and the lock detection circuit of the charge pump phase-locked loop circuit. It is used to convert the positive and negative output signals of the frequency and phase detector into a time-to-digital signal corresponding to the phase error based on the phase-locked loop lock indication signal output by the lock detection circuit.

[0010] A thermometer code conversion circuit, connected to the time-to-digital conversion circuit, is used to convert the time-to-digital signal into binary code;

[0011] A logic state machine circuit, coupled to the thermometer code conversion circuit, is used to generate a calibration feedback control signal based on the binary code, and transmit the calibration feedback control signal to the current-rudder type dual-channel switch charge pump of the charge pump phase-locked loop circuit, so as to calibrate the voltage control signal output by the current-rudder type dual-channel switch charge pump in real time.

[0012] Optional, further including:

[0013] The subtractor circuit is connected to the thermometer code conversion circuit and the logic state machine circuit respectively, and is used to output a phase calibration indication signal based on a preset reference phase error signal and the binary code. The logic state machine circuit outputs the calibration feedback control signal based on the phase calibration indication signal.

[0014] Optionally, it further includes a clock synchronization circuit for generating a clock synchronization signal based on a reference signal from the charge pump phase-locked loop circuit, and transmitting the clock synchronization signal to the logic state machine circuit.

[0015] Optionally, the clock synchronization circuit includes:

[0016] A buffer circuit, connected to the logic state machine circuit, is used to convert a preset first calibration clock signal into an intermediate calibration clock signal based on the enable signal of the calibration feedback control signal.

[0017] The frequency divider circuit is connected to the buffer circuit and the logic state machine circuit respectively. It is used to down-process the intermediate calibration clock signal based on the enable signal of the calibration feedback control signal to obtain a second calibration clock signal, and transmit the second calibration clock signal as the clock synchronization signal to the logic state machine circuit.

[0018] Optionally, the charge pump phase-locked loop circuit includes a current-rudder type dual-channel switching charge pump, which includes an up branch, a down branch, and a multi-channel calibration down branch, wherein the multi-channel calibration down branch is configured in parallel through a switch selection circuit;

[0019] The logic state machine circuit is used to form a calibration feedback control signal for inputting the switch selection circuit based on the binary code. The switch selection circuit is used to control the conduction or disconnection of each calibration pull-down branch based on the calibration feedback control signal.

[0020] This application also discloses a real-time calibration method for a charge pump phase-locked loop based on phase detection, including:

[0021] Based on the phase-locked loop lock indication signal output by the lock detection circuit, the positive and negative output signals of the frequency and phase detector are converted into time digital signals corresponding to the phase error.

[0022] Convert the digital time signal into binary code;

[0023] A calibration feedback control signal is generated based on the binary code and transmitted to the current-rudder type dual-channel switch charge pump of the charge pump phase-locked loop circuit to calibrate the voltage control signal output by the current-rudder type dual-channel switch charge pump in real time.

[0024] This application also discloses a charge pump phase-locked loop device based on phase detection, including the charge pump phase-locked loop real-time calibration circuit and the charge pump phase-locked loop circuit described in any one of the claims;

[0025] The charge pump phase-locked loop circuit includes a frequency and phase detector, a current-rudder type dual-channel switching charge pump, a low-pass filter, a voltage-controlled oscillator, a feedback frequency divider circuit, and a lock-in detection circuit.

[0026] The frequency and phase detector is connected to the feedback frequency divider circuit, the current-rudder dual-channel switch charge pump, and the time-to-digital converter circuit, respectively. It is used to compare the frequency difference and phase difference of the calibration feedback control signal formed by the preset reference signal and the output signal of the voltage-controlled oscillator, output charging and discharging commands to the current-rudder dual-channel switch charge pump, and output positive and negative frequency and phase detection output signals to the time-to-digital converter circuit.

[0027] The current-rudder type dual-channel switch charge pump is connected to the frequency and phase detector and the low-pass filter respectively, and is used to output charging or discharging current to the low-pass filter based on the charging and discharging command output by the frequency and phase detector.

[0028] The low-pass filter is connected to the current-rudder dual-channel switch charge pump and the voltage-controlled oscillator respectively, and is used to convert the charging or discharging current output by the current-rudder dual-channel switch charge pump into a control voltage.

[0029] The voltage-controlled oscillator is connected to the low-pass filter and the feedback frequency divider circuit respectively, and is used to convert the control voltage output by the low-pass filter into a voltage control high-frequency signal that is proportional to the control voltage.

[0030] The feedback frequency division circuit is connected to the voltage-controlled oscillator, the lock-in detection circuit, and the frequency and phase detector, respectively, and is used to perform frequency division processing on the voltage control high-frequency signal output by the voltage-controlled oscillator to generate a feedback frequency division signal that matches the frequency of the reference signal and is sent back to the frequency and phase detector and the lock-in detection circuit.

[0031] The lock detection circuit is connected to the frequency and phase detector, the feedback frequency divider circuit, and the time-to-digital converter circuit, respectively, and is used to monitor the frequency difference and phase difference between the reference signal and the feedback frequency divider signal output by the feedback frequency divider circuit in real time, determine whether the difference exceeds a predetermined threshold, and output a phase-locked loop lock indication signal to the time-to-digital converter circuit.

[0032] Optionally, the current-rudder type dual-channel switch charge pump includes an up-pull branch, a down-pull branch, and an external output node of the charge pump circuit. The down-pull branch includes multiple calibration down-pull branches, which are connected in parallel through a switch selection circuit.

[0033] The pull-up branch includes a first switch and a pull-up current source. The first end of the pull-up current source is connected to the current source, and the second end is connected to the low-pass filter through the first switch and the output node. The first switch is turned on or off based on the positive output signal of the frequency and phase detector. When turned on, it provides pull-up current to the low-pass filter.

[0034] The pull-down branch includes a second switch and a pull-down current source. The first end of the pull-down current source is connected to the output node through the second switch. The second switch is turned on or off based on the negative output signal of the frequency and phase detector. When turned on, it is used to provide pull-down current to the low-pass filter. The second end of the pull-down current source is grounded.

[0035] The multiple calibration pull-down branches are connected in parallel through a switch selection circuit. The switch selection circuit consists of multiple electronic switches, each of which corresponds to a pull-down current source and is used to receive calibration feedback control signals to control the conduction or disconnection of each calibration pull-down branch.

[0036] The charge pump circuit's output node is connected to a low-pass filter, where the currents from the pull-up and pull-down branches are combined.

[0037] Optionally, the feedback frequency division circuit includes a multi-mode frequency divider and an integral comparator modulator;

[0038] The first end of the multimode frequency divider is connected to the voltage-controlled oscillator, and the second end is connected to the lock-in detection circuit, the frequency and phase detector, and the integral comparator modulator, respectively. It is used to receive the voltage control high-frequency signal output by the voltage-controlled oscillator and perform frequency division processing to provide feedback frequency division signals for the frequency and phase detector and the lock-in detection circuit.

[0039] The integral comparator modulator is connected to the input and output terminals of the multimode frequency divider, respectively, and is used to output a modulated control signal based on the frequency division signal output by the multimode frequency divider to adjust the frequency division accuracy of the multimode frequency divider.

[0040] Optionally, the low-pass filter includes a resistor, a first capacitor, and a second capacitor;

[0041] The first end of the resistor is connected to the current-rudder type dual-channel switch charge pump and the voltage-controlled oscillator respectively, and the second end is connected to the first end of the first capacitor.

[0042] The second terminal of the first capacitor is grounded;

[0043] The first terminal of the second capacitor is connected to the current-rudder type dual-channel switch charge pump and the voltage-controlled oscillator respectively, and the second terminal is grounded.

[0044] The beneficial effects of this invention are as follows:

[0045] Compared with existing technologies, this application provides a real-time calibration circuit for a charge pump phase-locked loop (PLL) based on phase detection. The circuit includes a time-to-digital converter (TDC) circuit, a thermometer code conversion circuit, and a logic state machine circuit. The TDC circuit converts the positive and negative output signals of the frequency and phase detectors (FM / PLL) based on the PLL lock indication signal output from the lock detection circuit into a time-digital signal corresponding to the phase error. The thermometer code conversion circuit converts the time-digital signal into binary code. The logic state machine circuit generates a calibration feedback control signal based on the binary code and transmits this signal to the current-rudder dual-channel switch charge pump of the PLL circuit for real-time calibration of the voltage control signal output by the current-rudder dual-channel switch charge pump. This real-time calibration circuit improves analog mismatch using digital calibration logic. Real-time calibration effectively improves the consistency of the PLL circuit under different processes, temperatures, and power supply voltages, improving the reference spurious level of the PLL circuit with lower power consumption and area requirements. Attached Figure Description

[0046] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0047] Figure 1 A schematic diagram of a real-time calibration circuit for a charge pump phase-locked loop based on phase detection is provided in an embodiment of this application.

[0048] Figure 2 This is a schematic diagram of the structure of a charge pump phase-locked loop circuit provided in an embodiment of this application;

[0049] Figure 3 A schematic diagram of a phase detection-based charge pump phase-locked loop real-time calibration circuit and a charge pump phase-locked loop circuit is provided for embodiments of this application.

[0050] Figure 4 This is a schematic diagram of the time-to-digital conversion circuit provided in an embodiment of this application;

[0051] Figure 5 This is a schematic flowchart of a real-time calibration method for a charge pump phase-locked loop based on phase detection, provided in an embodiment of this application.

[0052] Figure label:

[0053] 100: Charge pump phase-locked loop circuit; 110: Reference signal; 120: Frequency and phase detector; 130: Current-controlled dual-channel switching charge pump; 140: Low-pass filter; 150: Voltage-controlled oscillator; 160: Feedback frequency divider circuit; 170: Lock-in detection circuit; 200: Charge pump phase-locked loop real-time calibration circuit; 210: Time-to-digital converter circuit; 220: Thermometer code conversion circuit; 230: Subtractor circuit; 240: Buffer circuit; 250: Frequency divider circuit; 260: Logic state machine circuit. Detailed Implementation

[0054] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of this application. However, those skilled in the art will understand that this application may also be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods have been omitted so as not to obscure the description of this application with unnecessary detail.

[0055] It should be understood that, when used in this application specification and the appended claims, the term "comprising" indicates the presence of the described features, integrals, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or a collection thereof.

[0056] It should also be understood that the term “and / or” as used in this application specification and the appended claims means any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0057] As used in this application specification and the appended claims, the term "if" may be interpreted, depending on the context, as "when," "once," "in response to determination," or "in response to detection." Similarly, the phrase "if determined" or "if detected [the described condition or event]" may be interpreted, depending on the context, as meaning "once determined," "in response to determination," "once detected [the described condition or event]," or "in response to detection [the described condition or event]."

[0058] Furthermore, in the description of this application and the appended claims, the terms "first," "second," "third," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0059] References to "one embodiment" or "some embodiments" as described in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.

[0060] To address at least one of the problems existing in the prior art, according to one aspect of this application, this embodiment discloses a phase-detection-based charge pump phase-locked loop real-time calibration circuit 200, such as... Figures 1-3 As shown, the circuit includes:

[0061] The time-to-digital conversion circuit 210 is connected to the frequency and phase detector 120 and the lock detection circuit 170 of the charge pump phase-locked loop circuit. It is used to convert the positive and negative output signals of the frequency and phase detector 120 into a time-to-digital signal corresponding to the phase error based on the phase-locked loop lock indication signal output by the lock detection circuit 170.

[0062] It should be noted that the digital time signal corresponding to the phase error is a digital signal expressed in 31-bit thermometer code. Compared with binary code, thermometer code has higher noise immunity and linearity, and can capture small phase errors, providing a quantitative basis for subsequent high-precision calibration.

[0063] The thermometer code conversion circuit 220 is connected to the time digital conversion circuit 210 and is used to convert the time digital signal into binary code.

[0064] Among them, the thermometer code retains the high precision of the time-to-digital conversion circuit, while the conversion to binary code facilitates the digital logic processing in the subsequent subtractor, greatly reducing the computational complexity of the subsequent digital logic and solving the problems of high computational complexity of direct thermometer code calculation and large circuit size and high latency when directly involved in calculation.

[0065] Wherein, the time-to-digital conversion circuit 210 is as follows Figure 4 As shown, the time-to-digital conversion circuit 210 is based on a differential delay chain and a data trigger sampling structure. An edge calibration module eliminates the edge asymmetry of the input differential signal. Then, a differential delay chain consisting of two inverters (32 stages in total) converts the time difference corresponding to the phase error into the signal propagation stage. Finally, a data trigger array samples and latches the output levels of each inverter using a reference clock to form a thermometer code, thereby quantizing the phase error of the differential signal output by the frequency-phase detector 120. After the charge pump phase-locked loop circuit 100 locks, the differential output signal of the frequency-phase detector 120 (containing phase error information) first passes through the edge calibration module to calibrate the rising and falling edges of the input differential signal to a preset intermediate level, eliminating the influence of edge asymmetry on quantization accuracy. The calibrated differential signal then enters the differential delay chain consisting of two inverter modules (32 stages in total). The positive and negative paths of the differential signal propagate in their respective inverter chains. Utilizing the inherent propagation delay of the inverters, the larger the time difference corresponding to the phase error, the more inverter stages the signal can propagate through. Each stage of the inverter module has a data flip-flop connected to its output. The data flip-flop uses a reference clock (or synchronous calibration clock) as its sampling clock, sampling and latching the level state of the inverter output on the rising edge of the clock. The output states of different stages of data flip-flops (1 indicating the signal has reached that stage, 0 indicating it has not) together constitute the thermometer code, completing the time-to-digital conversion.

[0066] It should be noted that the number of inverter stages in the time-to-digital conversion circuit can be flexibly adjusted according to the requirements of time resolution and quantization range, and this application does not limit it in this regard.

[0067] Specifically, the time-to-digital converter 210 has a resolution of 50 ps. The 31-bit time-to-digital converter 210 can detect a phase error range of 50 ps to 1550 ps. The output time digital signal of the time-to-digital converter 210 is a 31-bit thermometer code. Simultaneously, to optimize the number of registers and facilitate digital calculations, the thermometer code conversion circuit 220 converts the thermometer code into binary code. In a specific example, after the charge pump phase-locked loop circuit 100 locks, the output phase error signal is 250 ps. The output of the time-to-digital converter 210 is 1111100000000000000000000000000, and the thermometer code output is a 5-bit binary code 00101 containing the 250 ps phase error information.

[0068] The logic state machine circuit 260 is coupled to the thermometer code conversion circuit 220 and is used to form a calibration feedback control signal based on the binary code. The calibration feedback control signal is then transmitted to the current-rudder type dual-channel switch charge pump 130 of the charge pump phase-locked loop circuit to calibrate the voltage control signal output by the current-rudder type dual-channel switch charge pump in real time.

[0069] The logic state machine circuit 260 generates a calibration feedback control signal, a calibration circuit end indication signal, or a calibration circuit overflow indication signal based on the quantized binary code and preset calibration conditions. The logic state machine circuit 260, based on the quantized binary code, generates a targeted calibration feedback control signal through preset calibration conditions, which directly acts on the current-controlled dual-channel switching charge pump 130, adjusting its current matching degree in real time and correcting the high-frequency voltage control signal of the voltage-controlled oscillator 150 in real time. This dynamic calibration mechanism can track and correct phase errors caused by process deviations, power supply voltage fluctuations, temperature changes, etc., in real time, avoiding the limitations of traditional one-time calibration in dealing with dynamic changes, and ensuring that the charge pump phase-locked loop circuit 100 can maintain stable performance under complex operating conditions.

[0070] In particular, by calibrating the output characteristics of the current-rudder type dual-channel switch charge pump 130 in real time, the stability of the output signal of the voltage-controlled oscillator 150 can be improved, the reference spurious caused by phase error can be reduced, and the consistency of the charge pump phase-locked loop circuit 100 under different process and environmental conditions can be improved.

[0071] It should be noted that the preset calibration conditions here include calibration start conditions and calibration end conditions. The preset calibration conditions are limited according to requirements, and this application does not limit them.

[0072] In alternative implementations, such as Figure 1 As shown, it further includes:

[0073] The subtractor circuit 230 is connected to the thermometer code conversion circuit 220 and the logic state machine circuit 260 respectively, and is used to output a phase calibration indication signal based on a preset reference phase error signal and the binary code. The logic state machine circuit outputs the calibration feedback control signal based on the phase calibration indication signal.

[0074] The phase calibration indication signal output by the subtractor circuit 230 is transmitted to the logic state machine circuit 260. The latter generates a corresponding calibration feedback control signal based on the specific error direction or signal magnitude of the indication signal. This signal is then applied to the current-rudder type dual-channel switch charge pump 130 as shown in the figure. The current-rudder type dual-channel switch charge pump 130 initiates the phase error detection and calibration process of the charge pump phase-locked loop circuit 100. The phase error is compensated by adjusting the output charging and discharging current of the current-rudder type dual-channel switch charge pump 130 until the phase error of the system approaches the preset reference value. At this point, the logic state machine circuit 260 outputs a charge pump calibration circuit end indication signal, indicating that the current calibration process is complete. The charge pump phase-locked loop real-time calibration circuit 200 then stops working or enters a sleep state.

[0075] Specifically, the subtractor circuit 230, based on the full adder principle, performs binary subtraction through two's complement arithmetic. It compares the binary code (including the actual limit error) with the binary code of the reference phase error signal and outputs a phase calibration indication signal to the logic state machine circuit 260. When the binary code containing the actual phase error is greater than or equal to the reference phase error signal, it outputs a high level. The logic state machine circuit 260 then generates a calibration feedback control signal that acts on the current-rudder type dual-channel switch charge pump 130, initiating phase error detection and calibration. Otherwise, it outputs a low level, and the phase error detection and calibration process of the charge pump phase-locked loop circuit 100 is not initiated. In one specific embodiment, the reference phase error is 300 ps (binary code 00110). When the actual phase error is 450 ps (binary code 01001), the subtractor circuit 230 outputs a high level, generating a calibration feedback control signal that acts on the current-rudder type dual-channel switch charge pump 130, triggering the phase error detection and calibration process of the charge pump phase-locked loop circuit 100.

[0076] In alternative implementations, such as Figure 2 As shown, it further includes a clock synchronization circuit for generating a clock synchronization signal based on the reference signal 110 of the charge pump phase-locked loop circuit 100, and transmitting the clock synchronization signal to the logic state machine circuit 260.

[0077] The clock synchronization circuit provides a stable and synchronized clock signal to the logic state machine circuit 260, ensuring that all operations during the calibration process are performed under a unified time reference, thus avoiding calibration errors caused by timing discrepancies.

[0078] The clock synchronization circuit is based on the original reference signal (such as the external reference clock) used by the charge pump phase-locked loop circuit to achieve frequency or phase locking. It generates a clock synchronization signal through internal signal processing such as buffering, frequency division, and shaping, so that the clock of the calibration system and the core reference signal 110 of the charge pump phase-locked loop circuit 100 are from the same source, ensuring the timing consistency between the calibration action and the operation of the charge pump phase-locked loop circuit.

[0079] In addition, after the generated clock synchronization signal is transmitted to the logic state machine circuit 260, it is mainly used to control the state switching of the logic state machine and to ensure that the sampling and processing actions of the logic state machine on the phase calibration indication signal output by the subtractor circuit 230 are synchronized with the working timing of the charge pump phase-locked loop circuit 100, so as to avoid introducing additional phase disturbances due to asynchronous operation.

[0080] In alternative implementations, such as Figure 1 As shown, the clock synchronization circuit includes:

[0081] The buffer circuit 240, connected to the logic state machine circuit 260, is used to convert the preset first calibration clock signal into an intermediate calibration clock signal based on the enable signal of the calibration feedback control signal.

[0082] The buffer circuit 240 can enhance the driving capability of the first calibration clock signal, avoid signal attenuation caused by long-distance transmission or excessive load, and isolate the preceding and following circuits to prevent the load change of the frequency divider circuit 250 from interfering with the first calibration clock signal.

[0083] The frequency divider circuit 250 is connected to the buffer circuit 240 and the logic state machine circuit 260 respectively. It is used to down-frequency the intermediate calibration clock signal based on the enable signal of the calibration feedback control signal to obtain a second calibration clock signal, and transmit the second calibration clock signal as the clock synchronization signal to the logic state machine circuit 260.

[0084] The frequency divider circuit 250 matches the clock frequency with the operating speed of the logic state machine circuit 260, ensuring that the frequency of the synchronization signal is synchronized with the operating timing of the charge pump phase-locked loop circuit 100, and triggering the logic state machine circuit 260 to perform a calibration once on each rising edge of the output of the second calibration clock signal.

[0085] The logic state machine circuit 260 first determines the current calibration cycle based on the second calibration clock signal output by the frequency divider circuit 250, and performs phase error calibration based on the division between the initial cycle and the non-initialized cycle, achieving calibration by outputting a calibration feedback control signal. If the current cycle is the initial cycle, it determines whether the phase error is greater than or equal to a preset reference phase error. If the phase error is greater than the preset reference phase error, it determines whether the phase calibration indication signal meets the calibration start condition of the preset calibration conditions. If the phase calibration indication signal meets the calibration start condition of the preset calibration conditions, the calibration feedback control signal is set as the first control signal and output; if the phase calibration indication signal does not meet the calibration start condition of the preset calibration conditions, a phase detection and calibration circuit overflow indication signal is output to indicate an abnormality. If the phase error is less than the preset reference phase error, the initial value of the preset calibration feedback control signal is directly output and a calibration circuit end indication signal is output to terminate the calibration.

[0086] If the current calibration period is not the initial period, the logic state machine circuit 260 provides two implementation methods, both using the phase calibration indication signal as the judgment basis, and outputting a second or third control signal accordingly. In one implementation method, the logic state machine circuit 260 directly determines whether the phase calibration indication signal meets the calibration start condition. If the preset calibration start condition is met, the calibration feedback control signal is set as the second control signal and output; if the preset calibration start condition is not met, the calibration feedback control signal is set as the third control signal and output. In another implementation method, the logic state machine circuit 260 first determines whether the phase calibration indication signal meets the preset calibration end condition, and then determines the preset calibration start condition. If the preset calibration end condition is met, the current calibration feedback control signal is set as the second control signal and a calibration circuit end indication signal is output; if the preset calibration end condition is not met, the above-mentioned determination of whether the current charge pump phase-locked loop circuit meets the preset calibration start condition is executed. If it is met, the second control signal (decreasing adjustment) is output; if it is not met, the third control signal (increasing adjustment) is output.

[0087] When the calibration termination condition, which is preset, is met, the logic state machine circuit 260 outputs a calibration circuit termination indication signal (active high). If the termination is abnormal, the logic state machine circuit 260 synchronously outputs a calibration circuit overflow indication signal and pulls the enable signal of the calibration feedback control signal down to a low level, shutting down the charge pump phase-locked loop real-time calibration circuit 200 to reduce power consumption.

[0088] In a specific example, taking the calibration feedback control signal with a digital calibration bit n=5 as an example, the digital calibration bit is 5 bits. The logic state machine circuit 260 implements phase error calibration based on successive approximation register logic. Through phased adjustments from a large range to a small range, the digital calibration bit of the current-rudder type dual-channel switch charge pump 130 is gradually adjusted. The highest bit of the initial state of the digital calibration bit is high, and the remaining bits are low (when n=5, the initial value is 5'b10000, corresponding to decimal 16). There are a total of 2n=10 control cycles. In the initial cycle, it is determined whether the phase calibration indication signal meets the calibration start condition of the preset calibration condition. If the calibration start condition is not met, the digital calibration bit maintains the initial value of 5'b10000 and outputs, or triggers abnormal handling (such as calibration circuit overflow indication signal). If the calibration start condition is met, calibration is performed, and the digital calibration bit is reduced. (when n=5, =8), that is, adjusted from 5'b10000 to 5'b01000; in the second to n-1 cycles (cycles 2 to 4), the adjustment is made by decreasing the weight bit by bit, and the digital calibration bit is... (t is the period number, t≥1), when n=5, the digital calibration bit step size is as follows: =2, =1, meaning that when the calibration start condition of the preset calibration conditions is met, the digital calibration bit decreases by the current step size; when the calibration start condition of the preset calibration conditions is not met, the digital calibration bit increases by the current step size. In the (n+1)th to (2n-1)th cycles (cycles 6 to 9), the digital calibration bit is adjusted by ±1 for fine-tuning. When the calibration start condition of the preset calibration conditions is met, the digital calibration bit decreases by 1; when the calibration start condition of the preset calibration conditions is not met, the digital calibration bit increases by 1. Example: After the 5th cycle, the calibration bit is 5'b00101. In the 6th cycle, when the calibration start condition of the preset calibration conditions is met, it is adjusted to 5'b00100; when the calibration start condition of the preset calibration conditions is not met, it is adjusted to 5'b00110. In the 2nth cycle (cycle 10), only the step size is adjusted by decreasing by 1 or maintaining the step size. When the calibration start condition of the preset calibration conditions is met, the digital calibration bit decreases by 1; when the calibration start condition of the preset calibration conditions is not met, the digital calibration bit remains unchanged. After the first 9 cycles, the calibration bit is 5'b00111. If the calibration start condition of the preset calibration conditions is not met in the 10th cycle, it remains at 5'b00111. If the calibration start condition of the preset calibration conditions is met, it is adjusted to 5'b00110.

[0089] It should be noted that the calibration start condition of the preset calibration conditions is related to the initial value of the phase calibration indicator signal. If the initial value of the phase calibration indicator signal is high, it means that the phase error of the current-rudder type dual-channel switch charge pump output is greater than the input reference phase error during the first calibration cycle. The calibration end condition of the preset calibration conditions can be set to either all 100 digital calibration bits of the charge pump phase-locked loop circuit being 0 and the phase detection indicator signal still being high, or completing the adjustment process for 2n control cycles.

[0090] In this embodiment, the calibration feedback control signal output by the logic state machine circuit 260 includes three control signals: a first control signal, a second control signal, and a third control signal. The first control signal instructs the current-rudder dual-channel switch charge pump to increase the compensation current (or to perform a significant phase adjustment when the phase error is too large). During the initial calibration period, the first control signal is output when the phase error is greater than the preset reference phase error and the phase calibration indication signal meets the preset calibration start condition. The second control signal instructs the current-rudder dual-channel switch charge pump to decrease the compensation current (or to perform a small phase adjustment). During non-initial calibration periods, the second control signal is output when the phase calibration indication signal meets the preset calibration start condition, or in some embodiments, when the calibration end condition is met. The third control signal instructs the current-rudder dual-channel switch charge pump to maintain the current compensation current unchanged (i.e., not to perform phase adjustment). During non-initial calibration periods, the third control signal is output when the phase calibration indication signal does not meet the preset calibration start condition. In the initial period, if the phase error is already greater than the reference value and the start condition is met, the logic state machine outputs the first control signal to perform a significant adjustment for rapid convergence. If adjustment is still needed outside the initial cycle, a second control signal is output for fine-tuning; if no adjustment is needed, a third control signal is output to maintain the status quo.

[0091] In alternative implementations, such as Figure 1 and Figure 2 As shown, the charge pump phase-locked loop circuit 100 includes a current-rudder type dual-channel switch charge pump 130. The current-rudder type dual-channel switch charge pump 130 includes an up-pull branch, a down-pull branch, and an external output node of the charge pump circuit. The down-pull branch includes multiple calibration down-pull branches, which are set in parallel through a switch selection module.

[0092] The logic state machine circuit 260 is used to form a calibration feedback control signal for inputting the switch selection circuit based on the binary code. The switch selection circuit is used to control the conduction or disconnection of each calibration pull-down branch based on the calibration feedback control signal.

[0093] The charge pump circuit's output node is connected to a low-pass filter 140, where the currents from the pull-up and pull-down branches are combined.

[0094] Among them, the multi-path calibration pull-down circuit is connected in parallel to the pull-down branch through the switch selection circuit. Each calibration pull-down circuit contains an independent current source and switch. The parallel design means that the magnitude of the total pull-down current can be flexibly adjusted by controlling the conduction or disconnection of different branches.

[0095] It should be noted that the logic state machine circuit 260 generates a corresponding calibration feedback control signal based on the binary code reflecting the current phase error output by the subtractor circuit 230. This signal indicates which calibration pull-down branches need to be turned on or off. After receiving the calibration feedback control signal, the switch selection circuit controls the on / off state of the switches in each calibration pull-down branch. If the current phase error indicates insufficient pull-down current causing phase lag, more calibration pull-down branches are turned on to increase the total pull-down current. If the pull-down current is too large, causing phase lead, some calibration pull-down branches are turned off to reduce the total pull-down current.

[0096] This structure, through multi-path parallel connection and switch selection, enables fine adjustment of the pull-down current, thereby compensating for current mismatch in the current-controlled dual-path switching charge pump 130 caused by factors such as process and temperature (e.g., asymmetry between pull-up and pull-down currents). It also corrects phase errors in real time, improving the locking accuracy and stability of the charge pump phase-locked loop circuit 100. Compared to single-current-source adjustment, multiple calibration branches provide a more flexible current adjustment range and resolution. This circuit design makes the pull-down current of the current-controlled dual-path switching charge pump 130 configurable, and the logic state machine circuit 260 dynamically adjusts this configuration by outputting calibration control signals, ultimately achieving real-time calibration of the phase error of the charge pump phase-locked loop circuit 100.

[0097] Based on the same inventive concept, this application also discloses a real-time calibration method for a charge pump phase-locked loop based on phase detection, such as... Figure 5 As shown, it includes:

[0098] S100: Based on the phase-locked loop lock indication signal output by the lock detection circuit 170, the positive output signal and negative output signal of the frequency and phase detector 120 are converted into a time digital signal corresponding to the phase error.

[0099] S200: Convert the digital time signal into binary code.

[0100] S300: Based on the binary code, a calibration feedback control signal is formed, and the calibration feedback control signal is transmitted to the current-rudder type dual-channel switching charge pump of the charge pump phase-locked loop circuit 100 to calibrate the voltage control signal output by the current-rudder type dual-channel switching charge pump in real time.

[0101] Since the principle behind this system's problem-solving is similar to the methods described above, the implementation of this system can be found in the implementation of the methods, and will not be repeated here.

[0102] Based on the same inventive concept, this application also discloses a charge pump phase-locked loop device based on phase detection, including the charge pump phase-locked loop circuit 100 and the charge pump phase-locked loop real-time calibration circuit 200 as described above.

[0103] The charge pump phase-locked loop circuit includes a frequency and phase detector, a current-rudder type dual-channel switching charge pump, a low-pass filter, a voltage-controlled oscillator, a feedback frequency divider circuit, and a lock-in detection circuit.

[0104] The frequency and phase detector 120 is connected to the feedback frequency divider circuit 160, the current-rudder dual-channel switch charge pump 130, and the time-to-digital converter circuit 210, respectively. It is used to compare the frequency difference and phase difference of the calibration feedback control signal formed by the preset reference signal 110 and the output signal of the voltage-controlled oscillator 150, output charging and discharging commands to the current-rudder dual-channel switch charge pump 130, and output positive and negative frequency and phase detection output signals to the time-to-digital converter circuit 210.

[0105] It should be noted that the frequency and phase detector 120, as the core of error detection, receives the external preset reference signal 110 and the feedback frequency division signal returned by the feedback frequency division circuit 160, compares the frequency difference and phase difference between the two, and outputs charging and discharging commands to control the charging and discharging of the current rudder type dual-channel switch charge pump 130. At the same time, it transmits the positive output signal and the negative output signal of the frequency and phase detector, which reflect the phase error, to the time digital conversion circuit 210 for subsequent calibration by the charge pump phase-locked loop real-time calibration circuit 200.

[0106] The current-rudder type dual-channel switch charge pump 130 is connected to the frequency and phase detector 120 and the low-pass filter 140 respectively, and is used to output charging or discharging current to the low-pass filter 140 based on the charging and discharging command output by the frequency and phase detector 120.

[0107] It should be noted that the current-rudder type dual-channel switch charge pump 130 receives the charging and discharging commands from the frequency and phase detector 120 and outputs the charging current (pull-up current) or discharging current (pull-down current) to the low-pass filter 140; at the same time, it receives the feedback control signal from the charge pump phase-locked loop real-time calibration circuit 200 and achieves current calibration by adjusting the internal branch switches.

[0108] The low-pass filter 140 is connected to the current-rudder type dual-channel switch charge pump 130 and the voltage-controlled oscillator 150 respectively, and is used to convert the charging or discharging current output by the current-rudder type dual-channel switch charge pump 130 into a control voltage.

[0109] The low-pass filter 140 converts the charging or discharging current output by the current-rudder dual-channel switch charge pump 130 into a stable DC control voltage, which is then transmitted to the voltage-controlled oscillator 150.

[0110] The voltage-controlled oscillator 150 is connected to the low-pass filter 140 and the feedback frequency divider circuit 160 respectively, and is used to convert the control voltage output by the low-pass filter 140 into a voltage control high-frequency signal proportional to the control voltage.

[0111] The voltage-controlled oscillator 150 generates a high-frequency signal with a frequency proportional to the control voltage output by the low-pass filter 140, and transmits the voltage-controlled high-frequency signal to the feedback frequency divider circuit 160.

[0112] The feedback frequency division circuit 160 is connected to the voltage-controlled oscillator 150, the lock detection circuit 170, and the frequency and phase detector 120, respectively. It is used to perform frequency division processing on the voltage control high-frequency signal output by the voltage-controlled oscillator 150, and generate a feedback frequency division signal that matches the frequency of the reference signal 110 and is sent back to the frequency and phase detector 120 and the lock detection circuit 170.

[0113] The lock detection circuit 170 is connected to the frequency and phase detector 120, the feedback frequency divider circuit 160 and the time-to-digital converter circuit 210 respectively, and is used to monitor the frequency difference and phase difference between the reference signal 110 and the feedback frequency divider signal output by the feedback frequency divider circuit 160 in real time, determine whether the difference exceeds a predetermined threshold, and output a phase-locked loop lock indication signal to the time-to-digital converter circuit 210.

[0114] It should be noted that the lock detection circuit 170 monitors the frequency and phase difference between the reference signal 110 and the feedback frequency division signal in real time. When the difference is less than a predetermined threshold, it outputs a phase-locked loop lock indication signal, triggering the charge pump phase-locked loop real-time calibration circuit 200 to start working. At this time, the charge pump phase-locked loop circuit 100 has been basically locked, but small errors need to be calibrated.

[0115] To illustrate with a concrete example, such as Figure 1 and Figure 2As shown, the entire device's workflow forms a dual closed loop consisting of a charge pump phase-locked loop circuit 100 and a charge pump phase-locked loop real-time calibration circuit 200. The locking process of the charge pump phase-locked loop circuit 100 involves the frequency and phase detector 120 detecting the difference between the reference signal 110 and the feedback frequency divider signal, outputting a charge / discharge command to the current-controlled dual-channel switch charge pump 130. The current-controlled dual-channel switch charge pump 130 outputs the corresponding charging or discharging current to the low-pass filter 140. The low-pass filter 140 converts the charging or discharging current into a control voltage for the voltage-controlled oscillator 150. The voltage-controlled oscillator 150 adjusts the output frequency to a voltage control high-frequency signal for the feedback frequency divider circuit 160. The feedback frequency divider circuit 160 divides the frequency and sends it back until the lock detection circuit 170 detects a basic lock, outputting a phase-locked loop lock indication signal to the time-to-digital converter circuit 210. The correction process of the charge pump phase-locked loop real-time calibration circuit 200 is as follows: after the lock detection circuit 170 confirms basic lock-up, it outputs a phase-locked loop lock-up indication signal to the time-to-digital converter circuit 210. The time-to-digital converter circuit 210 quantizes the phase error into a corresponding time digital signal and transmits it to the thermometer code conversion circuit 220. The thermometer code conversion circuit 220 converts the time digital signal into binary code and transmits it to the subtractor circuit 230. The subtractor circuit 230 outputs a phase calibration indication signal to the logic state machine circuit 260 based on the preset reference phase error signal and the binary code. The logic state machine circuit 260 generates a calibration feedback control signal to the current-rudder dual-channel switch charge pump 130. The current-rudder dual-channel switch charge pump 130 adjusts the charging and discharging current to compensate for the error, thereby further improving the accuracy of the charge pump phase-locked loop circuit 100.

[0116] This design achieves basic locking functionality through a charge pump phase-locked loop circuit 100, and then eliminates non-ideal errors caused by process and environmental factors through a real-time calibration circuit of the charge pump phase-locked loop, ultimately achieving high-precision and high-stability frequency and phase control, which is suitable for scenarios with stringent signal quality requirements.

[0117] In an optional embodiment, the current-rudder type dual-channel switch charge pump 130 includes an up-pull branch, a down-pull branch, and an external output node of the charge pump circuit. The down-pull branch includes multiple calibration down-pull branches, which are connected in parallel through a switch selection circuit.

[0118] The pull-up branch includes a first switch and a pull-up current source. The first end of the pull-up current source is connected to the current source, and the second end is connected to the low-pass filter 140 through the first switch and the output node. The first switch is turned on or off based on the positive output signal of the frequency and phase discrimination. When turned on, it provides pull-up current to the low-pass filter 140.

[0119] The pull-down branch includes a second switch and a pull-down current source. The first end of the pull-down current source is connected to the output node through the second switch. The second switch is turned on or off based on the negative output signal of the frequency and phase detector. When turned on, it is used to provide pull-down current to the low-pass filter. The second end of the pull-down current source is grounded.

[0120] The multiple calibration pull-down branches are connected in parallel through a switch selection circuit. The switch selection circuit consists of multiple electronic switches, each of which corresponds to a pull-down current source and is used to receive calibration feedback control signals to control the conduction or disconnection of each calibration pull-down branch.

[0121] The charge pump circuit's output node is connected to a low-pass filter 140, where the currents from the pull-up and pull-down branches are combined.

[0122] The switch selection circuit receives the calibration feedback control signal and controls the on or off of the corresponding switches in each calibration pull-down branch to adjust the calibration current superimposed on the basic pull-down current at different levels, so that the total discharge current of the pull-down branch can be flexibly adjusted according to the phase error requirements.

[0123] To illustrate with a concrete example, suppose the frequency and phase detector 120 detects that the phase of the reference signal 110 leads the feedback divider signal (i.e., the frequency of the voltage-controlled oscillator 150 needs to be increased). At this time, the pull-up branch operates, the positive output signal of the frequency and phase detector is valid, controlling the first switch to turn on. The pull-up current source, through the turned-on first switch, provides pull-up current to the low-pass filter 140 via the current-rudder dual-channel switch charge pump 130 at its external output node, charging the filter and increasing the control voltage output of the low-pass filter, thereby increasing the output frequency of the voltage-controlled oscillator 150. When the frequency and phase detector 120 detects that the phase of the reference signal 110 lags the feedback divider signal (i.e., the frequency of the voltage-controlled oscillator 150 needs to be decreased), the pull-down branch operates, the negative output signal of the frequency and phase detector is valid, controlling the second switch to turn on. If the calibration feedback control signal indicates a need for a small pull-down current, only some electronic switches in the switch selection circuit are turned on, connecting a corresponding number of calibration pull-down branches. A small pull-down current is drawn from the low-pass filter 140 through the turned-on second switch for discharge. If the calibration feedback control signal indicates a need for a large pull-down current, more electronic switches in the switch selection circuit are turned on, connecting a larger number of calibration pull-down branches. A larger pull-down current is drawn from the low-pass filter 140, reducing the control voltage output of the low-pass filter 140 and decreasing the output frequency of the voltage-controlled oscillator 150.

[0124] In an optional implementation, the feedback frequency divider circuit 160 includes a multimode frequency divider and an integral comparator modulator.

[0125] The first end of the multimode frequency divider is connected to the voltage-controlled oscillator 150, and the second end is connected to the lock-in detection circuit 170, the frequency and phase detector 120, and the integral comparator modulator, respectively. It is used to receive the voltage control high-frequency signal output by the voltage-controlled oscillator 150 and perform frequency division processing, so as to provide feedback frequency division signals for the frequency and phase detector 120 and the lock-in detection circuit 170.

[0126] The integral comparator modulator is connected to the input and output terminals of the multimode frequency divider, respectively, and is used to output a modulated control signal based on the frequency division signal output by the multimode frequency divider to adjust the frequency division accuracy of the multimode frequency divider.

[0127] The multi-mode frequency divider features multiple division ratios, switching between different division coefficients such as N and N+1, rather than a single fixed division ratio, thus adapting to various frequency requirements. The integral comparator modulator monitors the input and output signals of the multi-mode frequency divider to generate dynamic control signals that optimize the division effect. Through dynamic adjustment, it effectively reduces quantization errors during the division process, making the feedback division signal closer to the ideal value, thereby improving the frequency synthesis accuracy and phase noise performance of the entire phase-locked loop. The feedback division circuit, through the collaboration of these two modules, achieves both the conversion of high-frequency signals to feedback division signals and ensures conversion accuracy through a dynamic adjustment mechanism, providing crucial support for the high-precision locking of the charge pump phase-locked loop device.

[0128] In an optional embodiment, the low-pass filter 140 includes a resistor, a first capacitor, and a second capacitor.

[0129] The first end of the resistor is connected to the current-rudder type dual-channel switch charge pump 130 and the voltage-controlled oscillator 150 respectively, and the second end is connected to the first end of the first capacitor.

[0130] The second terminal of the first capacitor is grounded.

[0131] The first terminal of the second capacitor is connected to the current-rudder type dual-channel switch charge pump 130 and the voltage-controlled oscillator 150 respectively, and the second terminal is grounded.

[0132] It should be noted that the low-pass filter 140 utilizes the attenuation characteristics of a resistor-capacitor circuit to filter out high-frequency components (such as glitches and noise generated by switching actions) in the output current of the current-controlled dual-channel switch charge pump 130, preventing high-frequency interference from affecting the stability of the voltage-controlled oscillator 150. Simultaneously, it converts the pulsed charging and discharging current output by the current-controlled dual-channel switch charge pump 130 into a continuous and stable DC control voltage, providing a smooth control signal for the voltage-controlled oscillator 150. This resistor-capacitor combination low-pass filter 140 achieves the dual functions of current-to-voltage conversion and high-frequency noise filtering through a simple structure, providing a stable control voltage for the voltage-controlled oscillator 150. It is a crucial element in ensuring the output signal quality of the charge pump phase-locked loop device.

[0133] The above description is merely an embodiment of this application and is not intended to limit the scope of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of the claims of this application.

Claims

1. A real-time calibration circuit for a charge pump phase-locked loop based on phase detection, characterized in that, include: A time-to-digital conversion circuit is connected to the frequency and phase detector and the lock detection circuit of the charge pump phase-locked loop circuit. It is used to convert the positive and negative output signals of the frequency and phase detector into a time-to-digital signal corresponding to the phase error based on the phase-locked loop lock indication signal output by the lock detection circuit. A thermometer code conversion circuit, connected to the time-to-digital conversion circuit, is used to convert the time-to-digital signal into binary code; A logic state machine circuit, coupled to the thermometer code conversion circuit, is used to generate a calibration feedback control signal based on the binary code, and transmit the calibration feedback control signal to the current-rudder type dual-channel switch charge pump of the charge pump phase-locked loop circuit, so as to calibrate the voltage control signal output by the current-rudder type dual-channel switch charge pump in real time. The charge pump phase-locked loop circuit includes a current-rudder type dual-channel switch charge pump, which includes an up-pull branch, a down-pull branch, and a multi-channel calibration down-pull branch. The multi-channel calibration down-pull branch is set in parallel through a switch selection circuit. The logic state machine circuit is used to form a calibration feedback control signal for inputting the switch selection circuit based on the binary code. The switch selection circuit is used to control the conduction or disconnection of each calibration pull-down branch based on the calibration feedback control signal.

2. The real-time calibration circuit for a charge pump phase-locked loop based on phase detection according to claim 1, characterized in that, Further includes: The subtractor circuit is connected to the thermometer code conversion circuit and the logic state machine circuit respectively, and is used to output a phase calibration indication signal based on a preset reference phase error signal and the binary code. The logic state machine circuit outputs the calibration feedback control signal based on the phase calibration indication signal.

3. The real-time calibration circuit for a charge pump phase-locked loop based on phase detection according to claim 1, characterized in that, It further includes a clock synchronization circuit for generating a clock synchronization signal based on a reference signal from the charge pump phase-locked loop circuit, and transmitting the clock synchronization signal to the logic state machine circuit.

4. The real-time calibration circuit for a charge pump phase-locked loop based on phase detection according to claim 3, characterized in that, The clock synchronization circuit includes: A buffer circuit, connected to the logic state machine circuit, is used to convert a preset first calibration clock signal into an intermediate calibration clock signal based on the enable signal of the calibration feedback control signal. The frequency divider circuit is connected to the buffer circuit and the logic state machine circuit respectively. It is used to down-process the intermediate calibration clock signal based on the enable signal of the calibration feedback control signal to obtain a second calibration clock signal, and transmit the second calibration clock signal as the clock synchronization signal to the logic state machine circuit.

5. A real-time calibration method for a charge pump phase-locked loop based on phase detection, characterized in that, include: The lock detection circuit based on the charge pump phase-locked loop circuit outputs a phase-locked loop lock indication signal that converts the positive and negative output signals of the frequency and phase detector of the charge pump phase-locked loop circuit into a time digital signal corresponding to the phase error. Convert the digital time signal into binary code; A calibration feedback control signal is formed based on the binary code, and the calibration feedback control signal is transmitted to the current-rudder type dual-channel switch charge pump of the charge pump phase-locked loop circuit to calibrate the voltage control signal output by the current-rudder type dual-channel switch charge pump in real time. The charge pump phase-locked loop circuit includes a current-rudder type dual-channel switch charge pump, which includes an up-pull branch, a down-pull branch, and a multi-channel calibration down-pull branch. The multi-channel calibration down-pull branch is set in parallel through a switch selection circuit. The process of forming a calibration feedback control signal based on the binary code includes: forming a calibration feedback control signal input to the switch selection circuit based on the binary code, wherein the switch selection circuit is used to control the conduction or disconnection of each calibration pull-down branch based on the calibration feedback control signal.

6. A charge pump phase-locked loop device based on phase detection, characterized in that, Includes the phase detection-based charge pump phase-locked loop real-time calibration circuit and charge pump phase-locked loop circuit as described in any one of claims 1-4; The charge pump phase-locked loop circuit includes a frequency and phase detector, a current-rudder type dual-channel switching charge pump, a low-pass filter, a voltage-controlled oscillator, a feedback frequency divider circuit, and a lock-in detection circuit. The frequency and phase detector is connected to the feedback frequency divider circuit, the current-rudder dual-channel switch charge pump, and the time-to-digital converter circuit, respectively. It is used to compare the frequency difference and phase difference of the calibration feedback control signal formed by the preset reference signal and the output signal of the voltage-controlled oscillator, output charging and discharging commands to the current-rudder dual-channel switch charge pump, and output positive and negative frequency and phase detection output signals to the time-to-digital converter circuit. The current-rudder type dual-channel switch charge pump is connected to the frequency and phase detector and the low-pass filter respectively, and is used to output charging or discharging current to the low-pass filter based on the charging and discharging command output by the frequency and phase detector. The low-pass filter is connected to the current-rudder dual-channel switch charge pump and the voltage-controlled oscillator respectively, and is used to convert the charging or discharging current output by the current-rudder dual-channel switch charge pump into a control voltage. The voltage-controlled oscillator is connected to the low-pass filter and the feedback frequency divider circuit respectively, and is used to convert the control voltage output by the low-pass filter into a voltage control high-frequency signal that is proportional to the control voltage. The feedback frequency division circuit is connected to the voltage-controlled oscillator, the lock-in detection circuit, and the frequency and phase detector, respectively, and is used to perform frequency division processing on the voltage control high-frequency signal output by the voltage-controlled oscillator to generate a feedback frequency division signal that matches the frequency of the reference signal and is sent back to the frequency and phase detector and the lock-in detection circuit. The lock detection circuit is connected to the frequency and phase detector, the feedback frequency divider circuit, and the time-to-digital converter circuit, respectively, and is used to monitor the frequency difference and phase difference between the reference signal and the feedback frequency divider signal output by the feedback frequency divider circuit in real time, determine whether the difference exceeds a predetermined threshold, and output a phase-locked loop lock indication signal to the time-to-digital converter circuit.

7. The charge pump phase-locked loop device based on phase detection according to claim 6, characterized in that, The pull-up branch includes a first switch and a pull-up current source. The first end of the pull-up current source is connected to the current source, and the second end is connected to the low-pass filter through the first switch and the output node. The first switch is turned on or off based on the positive output signal of the frequency and phase detector. When turned on, it provides pull-up current to the low-pass filter. The pull-down branch includes a second switch and a pull-down current source. The first end of the pull-down current source is connected to the output node through the second switch. The second switch is turned on or off based on the negative output signal of the frequency and phase detector. When turned on, it is used to provide pull-down current to the low-pass filter. The second end of the pull-down current source is grounded. The multiple calibration pull-down branches are connected in parallel through a switch selection circuit. The switch selection circuit consists of multiple electronic switches, each of which corresponds to a pull-down current source and is used to receive calibration feedback control signals to control the conduction or disconnection of each calibration pull-down branch. The charge pump circuit of the current-rudder type dual-channel switch charge pump is connected to a low-pass filter at its external output node, where the currents of the pull-up and pull-down branches are combined.

8. The charge pump phase-locked loop device based on phase detection according to claim 6, characterized in that, The feedback frequency division circuit includes a multi-mode frequency divider and an integral comparator modulator; The first end of the multimode frequency divider is connected to the voltage-controlled oscillator, and the second end is connected to the lock-in detection circuit, the frequency and phase detector, and the integral comparator modulator, respectively. It is used to receive the voltage control high-frequency signal output by the voltage-controlled oscillator and perform frequency division processing to provide feedback frequency division signals for the frequency and phase detector and the lock-in detection circuit. The integral comparator modulator is connected to the input and output terminals of the multimode frequency divider, respectively, and is used to output a modulated control signal based on the frequency division signal output by the multimode frequency divider to adjust the frequency division accuracy of the multimode frequency divider.

9. The charge pump phase-locked loop device based on phase detection according to claim 6, characterized in that, The low-pass filter includes a resistor, a first capacitor, and a second capacitor; The first end of the resistor is connected to the current-rudder type dual-channel switch charge pump and the voltage-controlled oscillator respectively, and the second end is connected to the first end of the first capacitor. The second terminal of the first capacitor is grounded; The first terminal of the second capacitor is connected to the current-rudder type dual-channel switch charge pump and the voltage-controlled oscillator respectively, and the second terminal is grounded.

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