Scan test circuit, method and chip

Abstract

The application relates to a scan test circuit, a method and a chip. The application comprises a receiving module for receiving a test signal; the test signal comprises a first clock control signal; a clock control module for adjusting the first clock control signal to obtain an adjusted first clock control signal; wherein the adjusted first clock control signal meets the pulse width requirement of a register in a digital chip; a test control module for testing the register of the digital chip according to the adjusted first clock control signal and outputting a test result. Based on the device, the test reliability can be improved.

Description

Technical Field

[0001] This application relates to the field of chip testing technology, and in particular to a scanning test circuit, method, and chip. Background Technology

[0002] In the mass production of ultra-large-scale digital chips, manufacturing and physical defects must be screened out. Therefore, design for testability has become an essential part of digital chip design.

[0003] In related technologies, the design for testability (DFT) based on scanning test circuits is usually used. Its core principle is to connect the internal registers of the chip into several scan chains. Under the sampling of a slow clock input from an external test interface, the data to be tested is injected into the chip, and the scan value of the internal chip is read out through the external test interface to determine the chip's quality.

[0004] In very large-scale digital chips, static registers are mostly used. However, dynamic registers are needed to reduce power consumption or save area. Static registers have a lower threshold for clock pulse width, allowing for normal sampling even at slow clock speeds, while dynamic registers have strict limitations on the rise edge pulse width. Therefore, when a chip contains both static and dynamic registers, existing DFT scan testing methods cannot simultaneously satisfy the operating characteristics of both types of registers under the same test clock, thus affecting the reliability of the test. Summary of the Invention

[0005] Therefore, it is necessary to provide a scanning test circuit that can improve test reliability in response to the above-mentioned technical problems.

[0006] In a first aspect, this application provides a scanning test circuit, comprising:

[0007] A receiving module is used to receive test signals; the test signals include a first clock control signal and a test control signal.

[0008] A clock control module is used to adjust the first clock control signal to obtain an adjusted first clock control signal; wherein the adjusted first clock control signal meets the pulse width requirements of the registers in the digital chip.

[0009] The test control module is used to test the registers of the digital chip according to the adjusted first clock control signal and the test control signal, and output the test results.

[0010] In one embodiment, the clock control module is further configured to perform widening processing on the first clock control signal, wherein the first clock control signal is obtained by compressing the clock width of a slow clock signal.

[0011] The test control module includes:

[0012] The first scan control link is used to receive the stretched clock signal and test the static register according to the stretched clock signal; the stretched clock signal is the first clock control signal after the stretched processing.

[0013] The second scan control link is used to receive the first clock control signal and test the dynamic register according to the first clock control signal.

[0014] In one embodiment, the clock control module includes:

[0015] The delay submodule is used to perform multi-level delay processing on the first clock control signal to obtain multiple delay tap signals with increasing delay durations.

[0016] The logic submodule is used to perform logical operations on the first clock control signal and each of the delay tap signals to obtain multiple extended clock signals with different pulse widths.

[0017] The selection submodule is used to select from each of the widened clock signals and transmit the selected widened clock signal to the first scan control link.

[0018] In one embodiment, the logic submodule includes a plurality of cascaded OR gates, one input of each OR gate being connected to the output of the corresponding delay unit in the delay submodule. The plurality of OR gates are used to perform a logical OR operation on the first clock control signal and a delay tap signal to obtain a plurality of extended clock signals with different pulse widths.

[0019] In one embodiment, the first input of the first OR gate is connected to the output of the corresponding delay unit, and the second input is the first clock control signal; the first input of the other OR gates is connected to the output of the corresponding delay unit, and the second input is connected to the output of the previous OR gate; the first OR gate performs a logical OR operation on the first clock control signal and the corresponding delay tap signal to obtain a first widened clock signal; the other OR gates perform a logical OR operation on the widened clock signal output by the previous OR gate and the corresponding delay tap signal to obtain other widened clock signals.

[0020] In one embodiment, each of the delay tap signals corresponds one-to-one with each of the widened clock signals; the pulse widths of each widened clock signal increase sequentially; the pulse width of the first widened clock signal is the sum of the delay duration of the corresponding delay tap signal and the pulse width of the first clock control signal; the pulse widths of the other widened clock signals are the sum of the delay duration of the corresponding delay tap signal and the pulse width of the previous widened clock signal.

[0021] In one embodiment, the clock control module is further configured to compress the first clock control signal; the first clock control signal is a slow clock signal.

[0022] The test control module includes:

[0023] The first scan control link is used to receive the slow clock signal and test the static register according to the slow clock signal;

[0024] The second scan control link is used to receive the target compressed clock signal and test the dynamic register according to the target compressed clock signal; the target compressed clock signal is the first clock control signal after compression processing.

[0025] In one embodiment, the clock control module includes:

[0026] The delay submodule is used to apply time delay and phase flip to the first clock control signal step by step to generate multiple delay tap signals;

[0027] The logic submodule is used to perform logical operations on the first clock control signal and each delay tap signal to obtain multiple target compressed clock signals with different pulse widths.

[0028] The selection submodule is used to select from multiple target compressed clock signals with different pulse widths and transmit the selected target compressed clock signal to the second scan control link.

[0029] In one embodiment, the delay submodule includes cascaded phase shifting units, each phase shifting unit including a delay unit and an inverter, the output of the delay unit being connected to the input of the inverter; the delay unit is used to perform multi-stage delay processing on the first clock control signal; the inverter is used to flip the delayed first clock control signal to obtain the delay tap signal;

[0030] The logic submodule includes multiple logic units, each logic unit including an AND gate and a pulse selector. The first input of each AND gate is connected to the output of the corresponding inverter, and the second input of each AND gate receives the first clock control signal. The first input of each pulse selector is connected to the output of the corresponding AND gate, and the second input of each pulse selector receives the first clock control signal. Each AND gate is used to perform a logical AND operation on the first clock control signal and a delay tap signal to obtain multiple initial compressed clock signals with different pulse widths. The pulse selector is used to generate multiple target compressed clock signals with different pulse widths based on the initial compressed clock signals according to the first clock control signal.

[0031] The selection submodule includes a pre-selection unit, a final selection unit, and an arbitration unit. The pre-selection unit includes multiple pre-selection sub-units. The input terminal of the pre-selection unit is the output terminal of the pulse selector. One input terminal of the final selection unit is connected to the output terminal of the corresponding pre-selection sub-unit. The pre-selection unit is used to perform hierarchical selection on each of the target compressed clock signals according to the second control signal. The final selection unit is used to select the target compressed clock signal selected by the pre-selection unit according to the final selection signal. The arbitration unit includes a NOR gate, one output terminal of which is connected to the control terminal of the final selection unit. The NOR gate is used to perform a NOR operation on the mode selection signal and the on-chip control signal to generate the final selection signal.

[0032] In one embodiment, the method further includes: when the mode selection signal is in test mode and the on-chip control signal is in non-high-speed capture mode, the final stage selection signal is a valid signal.

[0033] In one embodiment, each of the delay tap signals corresponds one-to-one with each of the target compressed clock signals; the delay duration of the delay tap signal is the same as the pulse width of the target compressed clock signal.

[0034] Secondly, this application also provides a scanning test method for scanning test circuits, the method comprising:

[0035] Receive a test signal; the test signal includes a first clock control signal;

[0036] The first clock control signal is adjusted to obtain the adjusted first clock control signal; wherein the adjusted first clock control signal meets the pulse width requirements of the register in the digital chip;

[0037] The registers of the digital chip are tested according to the adjusted first clock control signal, and the test results are output.

[0038] Thirdly, this application also provides a scanning test chip, including the scanning test circuit described in any of the above embodiments.

[0039] Fourthly, this application also provides an integrated circuit device, including the scanning test chip described in any of the above embodiments.

[0040] In the above embodiments, the first clock control signal is adjusted by the clock control module, so that the adjusted first clock control signal simultaneously meets the requirements of the static register and the pulse requirements of the dynamic register, thereby ensuring the correct transmission and retention of test data during the shifting and sampling process, avoiding test failure due to clock pulse width mismatch, and thus ensuring the reliability of the test. Attached Figure Description

[0041] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the drawings used in the description of the embodiments of this application or related technologies will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0042] Figure 1 This is a schematic diagram of the test circuit structure in one embodiment;

[0043] Figure 2 This is a schematic diagram of the striking circuit in one embodiment;

[0044] Figure 3 This is a schematic diagram of the clock and data flow of the beat circuit in one embodiment;

[0045] Figure 4 This is a schematic diagram of the scanning test circuit in one embodiment;

[0046] Figure 5 This is a schematic diagram of the test control module in one embodiment;

[0047] Figure 6 This is a schematic diagram of the clock control module in one embodiment;

[0048] Figure 7 This is a schematic diagram of the connection of a single device in one embodiment;

[0049] Figure 8 A schematic diagram of a clock control module in an exemplary embodiment;

[0050] Figure 9 for Figure 8 Corresponding clock combination diagram;

[0051] Figure 10 In one embodiment based on Figure 1 A schematic diagram of the improved scanning test circuit;

[0052] Figure 11 This is a schematic diagram of the test control module in another embodiment;

[0053] Figure 12 This is a schematic diagram of the clock control module in another embodiment;

[0054] Figure 13 This is a connection diagram of a single device in another embodiment;

[0055] Figure 14A schematic diagram of a clock control module in another exemplary embodiment;

[0056] Figure 15 for Figure 14 Corresponding clock combination diagram;

[0057] Figure 16 In another embodiment based on Figure 1 A schematic diagram of the improved scanning test circuit;

[0058] Figure 17 Here is a flowchart of a scanning test method in one embodiment;

[0059] Figure 18 This is a schematic diagram of the structure of a scanning test chip in one embodiment. Detailed Implementation

[0060] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0061] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0062] The term "embodiment" as used herein means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0063] It is understood that the terms "first," "second," "third," "fourth," etc., used in this application may be used herein to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of this application, a first register may be referred to as a second register, and similarly, a second register may be referred to as a first register. Both the first register and the second register are registers, but they are not the same register.

[0064] It is understood that the term "connection" in the following embodiments should be understood as "connection" or "communication connection" if the connected circuits, modules, units, etc. have electrical signals or data transmission between them.

[0065] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, the term “and / or” as used in this specification includes any and all combinations of the associated listed items.

[0066] For example, in combination Figure 1 , Figure 1 This is a schematic diagram of the test circuit structure in one embodiment. The signals input from the external PAD include an external slow clock input, several test inputs, and test logic control signals. The signals output from the PAD include the test result output. Inside the digital chip, the externally input slow clock controls the timing circuit (pipeline), compression and decompression logic of the DFT scan test circuit's input / output channels, and the clock circuit responsible for generating the clock for physical defect testing of the module under test, i.e., the on-chip controller (OCC).

[0067] Among them, the direction of data flow is combined Figure 2 , Figure 2 This is a schematic diagram of the stamping circuit in one embodiment. Data starts from the PAD, passes through the negative edge register (N) => positive edge register (P) => negative edge register (N), and finally reaches the test data input port of the DFT scan decompression logic. The PAD (passivation layer aperture) is a metal area on the silicon wafer inside the chip, used to connect internal fine wires to external package pins (PINs). Figure 2 The corresponding clock and data stream format are as follows: Figure 3 As shown, Figure 3 This is a schematic diagram of the clock and data flow of the timing circuit in one embodiment. Therefore, a margin of about half a clock cycle is naturally formed between the negative edge register and the positive edge register, thereby effectively ensuring the hold time requirement of the registers during timing checks.

[0068] from Figure 1 As can be seen, the slow clock input from the external PAD needs to be applied simultaneously to the DFTscan test control circuit inside the chip and the circuit under test within the chip for scanning input. However, combined with Figure 3When the rising and falling edges of the external PAD slow clock are held for the same amount of time and for a long time, only the requirements of the static register can be met. However, the dynamic register has strict constraints on the clock pulse width, and its high-level holding time cannot be too long. Otherwise, the register will not be able to sample and hold data correctly, thus affecting the reliability of the DFT scan test.

[0069] Because dynamic registers have strict constraints on clock pulse width, if the high-level clock duration is too long, data retention may fail, thus affecting the reliability of test results. Therefore, this application introduces a clock control module. The clock control module is used to adjust the first clock control signal so that the adjusted first clock control signal meets the pulse width requirements of the dynamic register in the digital chip.

[0070] Combination Figure 4 This application proposes a scanning test circuit, which includes a receiving module 1, a clock control module 2, and a test control module 3.

[0071] The first output terminal of the receiving module 1 is connected to the input terminal of the clock adjustment module 2, the second output terminal is connected to the second input terminal of the test control module 3, and the output terminal of the clock adjustment module 2 is connected to the first input terminal of the test control module 3.

[0072] The receiving module 1 is used to receive the first clock control signal and input the first clock control signal to the clock adjustment module 2. The clock adjustment module 2 is used to adjust the first clock control signal to obtain the adjusted first clock control signal and input the adjusted first clock control signal to the test control module 3.

[0073] Test control module 3 is used to test the dynamic register under test in the digital chip according to the adjusted first clock control signal and the test control signal input by receiving module 1, and obtain the test result.

[0074] The first clock control signal refers to an externally provided clock signal used to drive the DFT scan chain and related test logic. For example, the first clock control signal can be a slow clock signal input from an automated test device, used to control the shifting operation of the scan chain during testing. Test control signals refer to other signals used during DFT testing, such as scan enable signals, reset signals, and auxiliary signals used to control register operating modes and data paths during DFT testing.

[0075] Optionally, combined Figure 1The receiving module 1 can be a PAD. In other embodiments, the receiving module 1 can also be an on-chip clock interface circuit or other circuit unit for receiving an external input clock.

[0076] The test control module 3, besides the receiving module 1 and the clock control module, is a functional unit used to perform defect detection on the digital chip in conjunction with the first clock control signal and the test control signal. For example, the test control module 3 may include... Figure 1 The diagram shows the timing pipeline, compression logic, decompression logic, and clock control circuit.

[0077] For example, under the drive of the adjusted first clock control signal and the test control signal, the test control module 3 can expand and distribute the externally input test data to multiple scan chains through decompression logic; in the sampling stage, the test control module 3 uses the adjusted clock control signal to trigger the register to collect the response of the functional logic; in the output stage, the test control module 3 collects the sampling results through compression logic and outputs them to the external PAD interface for processing by the automatic test equipment.

[0078] In the above embodiments, the first clock control signal is adjusted by the clock control module, so that the adjusted first clock control signal simultaneously meets the requirements of the static register and the pulse requirements of the dynamic register, thereby ensuring the correct transmission and retention of test data during the shifting and sampling process, avoiding test failure due to clock pulse width mismatch, and thus ensuring the reliability of the test.

[0079] Since the first clock control signal adjusted by the clock control module in this application acts on the first scan control link and the second scan control link in the test control module 3 respectively, the first scan control link and the second scan control link are described here.

[0080] The first scan control link operates on the static register for scan test control; the second scan control link includes a dynamic register, which is used to perform scan test on the dynamic register under the action of the adjusted first clock control signal.

[0081] In this way, corresponding clock signals can be used to drive different scan control links, ensuring the accuracy of data sampling for different types of registers during the scan test, thereby improving the reliability of the test.

[0082] Optionally, in one embodiment, the clock control module is further configured to perform widening processing on the first clock control signal, which is obtained by compressing the clock width of the slow clock signal.

[0083] If the first clock control signal is pre-compressed, then the clock control module will widen the first clock control signal.

[0084] For example, the pulse width of the slow clock signal can be compressed in test mode using EDA (Electronic Design Automation) tools to obtain a compressed slow clock signal, i.e., the first clock control signal. This compressed slow clock signal can meet the pulse width requirements of the dynamic register. However, the compressed clock signal may cause unstable sampling of the static register in the overall scan control link. Therefore, it is necessary to widen the first clock control signal through the clock control module to take into account the timing requirements of the dynamic register and other registers, thereby improving the reliability of the test.

[0085] Correspondingly, combined Figure 5 The first clock control signal, after being widened (i.e., the widened clock signal), is input to the first scan control link, which then tests the static register 31 based on the widened first clock control signal. Simultaneously, the first clock control signal is input to the second scan control link, which then tests the dynamic register 32 based on the first clock control signal.

[0086] Furthermore, in combination Figure 6 The aforementioned clock control module 2 includes a delay submodule 21, a logic submodule 22, and a selection submodule 23.

[0087] The output of delay submodule 21 is connected to one input of logic submodule 22, and the output of logic submodule 22 is connected to one input of selection submodule 23. After receiving the first clock control signal, delay submodule 21 performs multi-level delay processing on the first clock control signal to obtain multiple delay tap signals with increasing delay durations, and inputs the delay tap signals to logic submodule 22. Logic submodule 22 performs logical operations on the first clock control signal and each delay tap signal to obtain multiple widened clock signals with different pulse widths, and inputs the widened clock signals to selection submodule 23. Selection submodule 23 selects from the widened clock signals and transmits the selected widened clock signal to the first scan control link.

[0088] The selection submodule 23 selects from various broadened clock signals based on the first control signal. The current circuit determines whether it is a test circuit based on the first control signal. If it is a test circuit, it selects from various broadened clock signals based on the first control signal and transmits the selected broadened clock signal to the first scan control link. If it is a normal circuit, it selects the first clock signal based on the first control signal and transmits it to the first scan control link.

[0089] Specifically, the delay submodule 21 performs multi-level delays on the first clock control signal to obtain multiple delay tap signals with progressively increasing delay durations. Since the delay submodule 21 performs multi-level delays on the first clock control signal, each level adds a fixed delay time to the previous delay, thus obtaining multiple progressively increasing delay tap signals. Then, the delay tap signals are input to the corresponding logic submodule 22, which performs logical processing on the first clock control signal and each level of delay tap signal. For example, the first clock control signal and the corresponding delay tap signal can be ORed. Because the delay tap signal has progressively increasing delays relative to the first clock control signal, when the two are ORed, the high-level segments of the first clock control signal and the high-level segments of the delay tap signals partially overlap and extend backward on the time axis, resulting in a waveform with a longer high-level duration in the logical OR result—that is, a broadened clock signal. Furthermore, by performing logical OR processing on the tap signals corresponding to different delay levels, the resulting widened high-level widths also differ. Therefore, widened clock signals with various pulse widths can be generated as needed. After obtaining widened clock signals with different pulse widths, these signals are input to the selection submodule 23. The selection submodule 23 selects from these widened clock signals and transmits the selected widened clock signal to the first scan control link.

[0090] Optionally, the selection submodule 23 can select from each widened clock signal based on the first control signal input from the control terminal.

[0091] In the above embodiments, the delay submodule 21, logic submodule 22, and selection submodule 23 can further generate multiple candidate clocks with different pulse widths from the pre-compressed slow clock signal, and select the target clock for output. This ensures that the strict constraints of the dynamic register on the pulse width are met, and provides matching clock drives for different links, thereby ensuring the reliability of the scan test process.

[0092] Furthermore, the aforementioned delay submodule 21 includes multiple cascaded delay units, the aforementioned logic submodule 22 includes multiple cascaded OR gates, and the aforementioned selection submodule 23 includes multiple cascaded clock selectors.

[0093] For example, in combination Figure 7 , Figure 7 This diagram illustrates the connections between a single delay unit, an OR gate, and a clock selector.

[0094] The output of the delay unit is connected to one input of the OR gate, and the output of the OR gate is connected to one input of the clock selector.

[0095] The delay submodule 21 includes multiple delay units, which are cascaded together. Each delay unit is used to delay the first clock control signal to obtain multiple sequentially increasing delay tap signals. The delay unit can be a delay line, or a delay circuit unit composed of an inverter chain, a buffer chain, or a latch array; no specific limitation is made in this embodiment.

[0096] For example, the first clock control signal can be processed in series by multiple delay units to obtain a multi-channel delay tap signal with progressively increasing delay. Since the delay units are cascaded, each stage adds a fixed delay time to the previous stage. Therefore, the output tap signal has the characteristic of progressively increasing delay, that is, the delay amount increases step by step.

[0097] The logic submodule 22 includes multiple OR gates, which are cascaded together. One input of each OR gate is connected to the output of the corresponding delay unit. Each OR gate performs a logical OR operation on the delay tap signals output from the delay units and the first clock control signal, resulting in multiple extended clock signals with different pulse widths. Because the delay tap signals are shifted sequentially after the first clock control signal, when they are logically ORed, the high level of the original clock signal and the high level of the delay tap signals are superimposed on the time axis, thus extending the duration of the high level. As the number of delay stages increases, the superposition effect is further enhanced, thus enabling the formation of extended clock signals with different degrees of pulse width.

[0098] Furthermore, the first input of the first OR gate of logic submodule 22 is connected to the output of the corresponding delay unit, and the second input is connected to the first clock control signal; the first input of the other OR gates is connected to the output of the corresponding delay unit, and the second input is connected to the output of the previous OR gate.

[0099] Specifically, the first OR gate performs a logical OR operation based on the first clock control signal and the delay tap signal output by the first delay unit to obtain the first widened clock signal. This first widened clock signal is then input to the second OR gate, which performs a logical OR operation based on the first widened clock signal and the delay tap signal output by the second delay unit to obtain the second widened clock signal. This process is repeated iteratively until the last OR gate performs a logical OR operation based on the widened clock signal output by the previous stage and the delay time tap output by the last delay unit. In this way, multiple widened clock signals with different pulse widths can be obtained.

[0100] The selection submodule 23 includes multiple clock selectors, which are cascaded together. One input of each clock selector is connected to the output of a corresponding OR gate. The clock selector is used to select based on a first clock control signal and multiple extended clock signals with different pulse widths.

[0101] Optionally, the clock selector selects from multiple extended clock signals with different pulse widths based on the first control signal. The first control signal can be a timing configuration signal input from external automated test equipment.

[0102] Furthermore, the first input of the first clock selector is connected to the output of the corresponding OR gate, and the first clock control signal serves as the input to the second input. The first input of the remaining clock selectors is connected to the output of the corresponding OR gate, and the second input is connected to the output of the previous stage clock selector.

[0103] Specifically, the first input of the first clock selector is connected to the output of the first OR gate, and the second input receives the first clock control signal. The first clock selector selects between the first clock control signal and the first broadened clock signal based on the first control signal input from the control terminal, and uses the selection result as the input of the second clock selector. The first input of the second clock selector is connected to the output of the second OR gate, and the second input receives the signal selected by the first clock selector. Similarly, the second clock selector selects between the signal selected by the first clock selector and the second broadened clock signal output by the second OR gate based on the first control signal input from the control terminal. This process is repeated iteratively until the last clock selector selects between the signal selected by the previous clock selector and the broadened clock signal output by the last OR gate based on the first control signal input from the control terminal, thus obtaining the target clock signal.

[0104] In the above embodiments, the scanning test circuit includes a delay submodule, a logic submodule, and a selection submodule. The delay submodule consists of multiple cascaded delay units, used to sequentially delay the first clock control signal to generate multiple delay tap signals. The logic submodule consists of multiple cascaded OR gates, with one input of each OR gate connected to the output of the corresponding delay unit, used to perform a logical OR operation on the first clock control signal and the corresponding delay tap signal to obtain various stretched clock signals with different pulse widths. The selection submodule consists of multiple clock selectors, with their inputs connected to the outputs of the corresponding OR gates, used to select between the first clock control signal and the stretched clock signals, outputting a target clock signal to drive the first scan control link.

[0105] For example, in one embodiment, combined with Figure 8 , Figure 8 This is a schematic diagram of a clock control module in one embodiment. Figure 8 The clock control module is used to stretch the first clock control signal.

[0106] The first clock control signal is input to delay unit 1, AND gate 1, and clock selector 1 respectively. Delay unit 1 performs delay processing on the first clock control signal to obtain delay tap signal 1. Then, delay tap 1 is input to AND gate 1. AND gate 1 performs an OR operation on delay tap signal 1 and the first clock control signal to obtain widened clock signal 1. Widened clock signal 1 is input to AND gate 2 and clock selector 1 respectively. Clock selector 1 selects from widened clock signal 1 and first clock control signal 1 according to the first control signal input and output from the control terminal to obtain selection signal 1. Delay unit 2 performs delay processing on delay tap signal 1 to obtain delay tap signal 2, and inputs delay tap signal 2 to AND gate 2. AND gate 2 performs an OR operation on the widened clock signal 1 and delay tap signal 2 to obtain widened clock signal 2, which is then input to clock selector 2. Clock selector 2 selects from the selection signal 1 output by clock selector 1 and delay tap signal 2 based on the first control signal input from the control terminal to obtain selection signal 2, which is then input to clock selector 3. The processing procedures of delay unit 3, AND gate 3, and clock selector 3 are the same as those of delay unit 2, OR gate 2, and clock selector 2, and therefore will not be repeated. Clock selector 3 outputs the final target clock signal based on the first control signal input from the control terminal.

[0107] Combination Figure 9 , Figure 9 for Figure 8The corresponding clock combination diagram is shown. Delay tap signals 1, 2, and 3 are obtained by sequentially delaying the first clock control signal using delay units 1, 2, and 3, respectively. Therefore, each delay tap signal introduces a further time delay based on the previous delay tap signal, resulting in an increasing phase difference between the delay tap signals. The widened clock signal is obtained by performing a logical OR operation between the first clock control signal and each delay tap signal. Therefore, the high-level duration of the widened clock signal gradually increases with the number of delay tap stages involved in the operation. Figure 9 The extended clock signal 1 has an additional delay time compared to the high-level width of the first clock control signal, the extended clock signal 2 has an additional delay time of two, and the extended clock signal 3 has an additional delay time of three, thus obtaining extended clock signals with different pulse widths.

[0108] Furthermore, each delay tap signal corresponds one-to-one with each widened clock signal; the pulse width of each widened clock signal increases sequentially; the pulse width of the first widened clock signal is the sum of the delay duration of the corresponding delay tap signal and the pulse width of the first clock control signal; the pulse width of other widened clock signals is the sum of the delay duration of the corresponding delay tap signal and the pulse width of the previous widened clock signal.

[0109] The first widened clock signal is obtained by performing a logical OR operation between the first clock control signal and the corresponding delay tap signal. Its pulse width is equal to the sum of the pulse width of the first clock control signal and the delay duration of the delay tap signal. The remaining widened clock signals are further performed by performing a logical OR operation between the first widened clock signal and the corresponding delay tap signal, thereby increasing the output pulse width again based on the widened result of the previous layer.

[0110] For example, in combination Figure 9 The first widened clock signal 1 is the pulse width of the first widened clock signal, which is the sum of the delay duration of the first clock control signal and the delay tap signal 1. Other widened clock signals, such as widened clock signal 2 and widened clock signal 3, have pulse widths that are the sum of the delay duration of the corresponding delay tap signal and the pulse width of the previous widened clock signal, respectively.

[0111] In yet another exemplary embodiment, combined with Figure 10 , Figure 10 For based on Figure 1 A schematic diagram of the improved scanning test circuit.

[0112] Optionally, in one embodiment, the clock control module is further configured to compress the first clock control signal. The first clock control signal is a slow clock signal.

[0113] The first clock control signal is a slow clock signal input from an external PAD. Since the high-level holding time of this slow clock signal is usually long, it cannot meet the strict constraints of the dynamic register on the clock pulse width. Therefore, the clock control module needs to compress the slow clock signal to shorten its high-level width so that it meets the pulse width requirements of the dynamic register, thereby ensuring the normal operation of the dynamic register during the DFT scan test.

[0114] Correspondingly, combined Figure 11 The slow clock signal is input to the first control scan chain, which in turn inputs the slow clock signal to the static register 32. Simultaneously, the compressed first clock control signal is input to the second scan chain, which then tests the dynamic register 31 based on the compressed first clock control signal.

[0115] In the above embodiments, by allocating the original slow clock and the compressed clock to different types of scan control links and scan control links under test within the same chip, the clock requirements of dynamic registers and static registers can be met simultaneously at a slow speed.

[0116] Furthermore, in combination Figure 12 The aforementioned clock control module includes a delay submodule 21, a logic submodule 22, a selection submodule 23, and an arbitration unit.

[0117] One output of the delay submodule 21 is connected to one input of the logic submodule 22, the output of the logic submodule 22 is connected to one input of the selection submodule 23, and the output of the arbitration unit is connected to the control terminal of the selection submodule 23.

[0118] After receiving the first clock control signal, the delay submodule 21 applies time delays and phase flips to the first clock control signal step by step to generate multiple delay tap signals, and inputs these multiple delay tap signals to the logic submodule 22. The logic submodule 22 performs logical operations on the first clock control signal and each delay tap signal to obtain multiple target compressed clock signals with different pulse widths, and inputs these target compressed clock signals to the selection submodule 23. The selection submodule 23 selects a target clock signal from the multiple target compressed clock signals with different pulse widths and the first clock control signal, and transmits the target clock signal to the second scan chain. The arbitration unit performs logical operations on the mode selection signal and the on-chip control signal to generate a final-level selection signal, and inputs this final-level selection signal to the control terminal of the selection submodule 23, so that the selection submodule 23 selects the target clock signal according to the final-level selection signal.

[0119] Optionally, the logic submodule 22 may include multiple logic units. Each logic unit performs logic operations based on a corresponding delay tap signal to obtain multiple target compressed clock signals with different pulse widths. Specifically, the first input terminal of the first logic unit is connected to the output terminal of the corresponding delay submodule 21, and its other input terminal is connected to a first clock control signal. The first input terminals of the remaining logic units are connected to the output terminals of the corresponding delay submodule 21. The first logic unit performs logic operations based on the first clock control signal and the corresponding delay tap signal, while the remaining logic units perform logic operations based on the selection result of the previous logic unit and the corresponding delay tap signal to obtain target compressed clock signals with different pulse widths.

[0120] After receiving the target compressed clock signal through the input terminal, the selection submodule 23 selects the target clock signal from multiple target compressed clock signals with different pulse widths and the first clock control signal according to the second control signal received by the control terminal, and transmits the target clock signal to the second scan control link.

[0121] In the above embodiments, the delay submodule generates multiple delay tap signals, the logic submodule performs calculations on these signals with the original clock to obtain multiple target compressed clocks with adjustable pulse widths, and the selection submodule, in conjunction with the mode determination of the arbitration unit, outputs the target clock from the candidate clocks.

[0122] In one embodiment, combined Figure 13 , Figure 13 This diagram illustrates the connections between a single delay unit, inverter, AND gate, pulse selector, preselection unit, and final selection unit.

[0123] The delay submodule 21 includes cascaded phase-shifting units, each of which includes a delay unit and an inverter. The output of each delay unit is connected to the input of the inverter. Each delay unit delays the first clock control module, and each inverter flips the delayed first clock control signal to obtain multiple delay tap signals. Multi-stage delay is used because the time offset provided by a single-stage delay is limited. By accumulating delays across multiple stages, a series of tap signals with different phase differences can be obtained within the same clock cycle, thus providing flexible selection for generating target clocks with multiple pulse widths.

[0124] The logic submodule 22 includes multiple logic units, each including an AND gate and a pulse selector. The first input of the AND gate is connected to the output of the corresponding inverter, the second input of the AND gate receives the first clock control signal, and the output of the AND gate is connected to the first input of the pulse selector. Each AND gate performs a logical AND operation on the first clock control signal and a delay tap signal to obtain multiple initial compressed clock signals with different pulse widths. These initial compressed clock signals are then input to the pulse selector. Based on the first clock control signal input to the control terminal, the pulse selector generates multiple target compressed clock signals with different pulse widths. The pulse selector uses the first clock control signal as its control input, selecting the initial compressed clock signal in its high-level range and maintaining a low level in its low-level range. Therefore, it can form an effective pulse controlled by the first clock control signal based on the initial compressed clock signal, thereby obtaining multiple target compressed clock signals with different pulse widths.

[0125] The selection submodule 23 includes a preselection unit, a final selection unit, and an arbitration unit. The input of each preselection unit is connected to the output of two logic submodules 22, that is, to the output of the pulse selector, and the output is connected to the input of the final selection unit. The preselection unit is used to perform hierarchical selection of each target compression clock signal according to the second control signal, and inputs the selected target compression signal to the final selection unit. The final selection unit selects the target clock signal from the target compression clock signal selected by the preselection unit and the first clock control signal according to the final selection signal input by the control terminal. The arbitration unit includes a NOR gate, one output of which is connected to the control terminal of the final selection unit. The NOR gate is used to perform NOR operation on the mode selection signal and the on-chip control signal to generate the final selection signal.

[0126] The arbitration unit performs logical operations based on the mode selection signal and the on-chip control signal to generate the final stage selection signal. The mode selection signal is the signal output from the externally input test mode selection register, used to indicate the current test mode of the chip, such as normal function mode and test mode; the on-chip control signal is the control signal output from the DFT clock control circuit (OCC), used to indicate whether the current clock is operating in high-speed capture mode or other scan stages.

[0127] In the above embodiment, the delay tap signal is obtained by the phase shifting unit through step-by-step delay and flipping. The logic unit, combined with AND gates and pulse selectors, generates initial compressed clocks with different pulse widths. Then, through the hierarchical and final selection of the selection submodule, the target clock signal that meets the requirements of the dynamic register is finally output. At the same time, the arbitration unit performs logical adjudication on the final selection process based on different mode signals. This allows for the flexible generation and screening of target compressed clocks with different pulse widths, ensuring the normal operation of the dynamic register under DFT testing, thereby improving the reliability of the test.

[0128] Furthermore, the arbitration unit performs a OR operation on the mode selection signal and the on-chip control signal to generate the final selection signal.

[0129] When the arbitration unit mode selection signal is in test mode and the on-chip control signal of the arbitration unit is in non-high-speed capture mode, the final stage selection signal of the arbitration unit is valid. When the final stage selection signal is valid, it indicates that the current circuit is in the test phase. At this time, the final selection unit selects the target compressed clock signal selected by the pre-selection unit based on the final stage selection signal. When the final stage selection signal is invalid, it indicates that the current circuit is functioning normally, and the final selection unit selects the first clock control signal.

[0130] For example, when the mode selection signal is high, it indicates that the chip is currently in normal function mode; when the mode selection signal is low, it indicates that the chip is in DFT test mode; when the on-chip control signal is high, it indicates high-speed capture mode; when the on-chip control signal is low, it indicates low-speed scan stage or other test stage.

[0131] When performing a OR-NOT operation between the mode selection signal and the on-chip selection signal, the final selection signal is high only when both the mode selection signal and the on-chip control signal are low, at which point the target compressed clock signal is selected; and when either the mode selection signal or the on-chip selection signal is high, the final selection signal is low, at which point the first clock control signal is selected.

[0132] For example, in one embodiment, combined with Figure 14 , Figure 14 This is a schematic diagram of a clock control module in an exemplary embodiment.

[0133] Delay unit 1 performs delay processing on the first clock control signal to obtain delay signal 1, and inputs delay signal 1 to inverter 1. Inverter 1 inverts delay signal 1 to obtain delay tap signal 1. Inverter 1 inputs delay tap signal 1 to AND gate 1. AND gate 2 performs a logical AND operation on delay tap signal 1 and the first control signal to obtain initial compressed clock signal 1. Initial compressed clock signal 1 is then input to pulse selector 1. Pulse selector 1, based on the first clock control signal, combines initial compressed clock signal 1 and the first clock control signal, and obtains target compressed clock signal 1 based on the first clock control signal input from the control terminal. Target compressed clock signal 1 is then input to preselection unit 1.

[0134] Following the above process, target compression clock signal 2 is obtained. Pulse selector 2 inputs target compression clock signal 2 to preselection unit 1. Preselection unit 1 selects from target compression clock signal 1 and target compression clock signal 2 according to the second control signal input from the control terminal, and inputs the selected target compression clock signal to the next preselection unit.

[0135] This process iterates until the last pre-selection unit inputs the selected target compression signal to the final selection unit. The last pre-selection unit is... Figure 14 The preselection unit 2 in the chip. The final selection unit selects from the target compressed signal selected by the last preselection unit and the first clock control signal based on the final selection signal to obtain the target clock signal. The final selection signal is obtained by performing a NOR operation between the mode selection signal and the on-chip control signal using a NOR gate.

[0136] Combination Figure 15 , Figure 15 for Figure 14 A schematic diagram of the corresponding clock combination. Figure 15 The diagram illustrates delayed signals 1, 2, and 3, obtained through different delay units. Each delayed signal is delayed sequentially relative to the first clock control signal, forming a hierarchical timing relationship. The delay tap signals are obtained by logically flipping the delayed signals using inverters. The initial compressed signal is a pulse signal obtained by performing a logical AND operation between the first clock control signal and each stage of the delay tap signals. Its pulse width is determined by the delay amount of the corresponding delay tap, thus allowing the generation of multiple initial compressed signals with different pulse widths.

[0137] Furthermore, each arbitration unit's delay tap signal corresponds one-to-one with each arbitration unit's target compressed clock signal; the delay duration of the arbitration unit's delay tap signal is the same as the pulse width of the arbitration unit's target compressed clock signal.

[0138] After the first clock control signal is processed by the delay unit and the inverting unit, multiple delay tap signals are obtained. Each delay tap signal is then ANDed with the first clock control signal to generate a corresponding initial compressed clock signal. Since the logical AND operation only outputs a high level when both input signals are high, the duration of the high level of the initial compressed clock signal depends on the delay of the delay tap signal relative to the first clock control signal; that is, the pulse width of the initial compressed clock signal is consistent with the delay duration of the corresponding delay tap signal.

[0139] Subsequently, the pulse selector selects from various initial compressed clock signals based on the level of the first clock control signal to output target compressed clock signals with different pulse widths. For example, when the first clock control signal is high, the pulse selector selects the corresponding initial compressed clock signal as the output, thereby outputting the target compressed clock signal; when the first clock control signal is low, the pulse selector turns off the output or maintains a low level to ensure that the output signal is synchronized with the original clock beat.

[0140] Since the pulse selector only performs the switching operation of the signal path, its selection timing is consistent with the first clock control signal. It does not re-logic or transform the waveform characteristics or pulse width of the selected initial compressed clock signal. Therefore, the pulse width of the output target compressed clock signal is completely consistent with the pulse width of the selected initial compressed clock signal.

[0141] In yet another exemplary embodiment, combined with Figure 16 , Figure 16 For based on Figure 1 A schematic diagram of the improved scanning test circuit.

[0142] Additionally, it's important to note that the appropriate clock control module can be selected to compress or widen the first clock control signal based on the distribution of dynamic registers within the chip. For example, when all circuits inside the chip, except for the test circuit and some circuits that don't require DFT scan testing, are dynamic registers, a clock control module that widens the first clock control signal is preferred. This module only requires adding a simple clock widening circuit externally at slower speeds to achieve DFT scan testing of the dynamic register chip. When the chip is large and dynamic registers exist only in a few modules, a clock control module that compresses the first clock control signal is preferred. This module can control the clock during the DFT scan test only for the specific dynamic register module under test, without affecting the clock configuration during the DFT scan test of other modules. Compressing the first clock control signal is more complex than widening it, and each dynamic register module requires its own clock control module, resulting in higher hardware overhead. In other embodiments, a clock control module that broadens the first clock control signal and a clock control module that compresses the first clock control signal can be used simultaneously in the same test circuit.

[0143] Combination Figure 17 , Figure 17 This is a flowchart of a scanning test method in one embodiment. The method is applied to a scanning test circuit and includes the following steps:

[0144] Step 1702: Receive test signals; the test signals include a first clock control signal and a test control signal.

[0145] Step 1704: Adjust the first clock control signal to obtain the adjusted first clock control signal; wherein the adjusted first clock control signal meets the pulse width requirements of the register in the digital chip.

[0146] After receiving the first clock control signal, the scanning test circuit adjusts the first clock control signal through the clock control module in the scanning test circuit to obtain the adjusted first clock control signal. For the specific adjustment process, please refer to the description in any of the above embodiments, and it will not be repeated here.

[0147] Step 1706: Test the registers of the digital chip according to the adjusted first clock control signal and test control signal, and output the test results.

[0148] For example, driven by the adjusted first clock control signal and the test control signal, the externally input test data can be expanded and distributed to multiple scan chains through decompression logic; in the sampling stage, the adjusted clock control signal is used to trigger the register to collect the response of the functional logic; in the output stage, the sampling results are collected through compression logic and output to the external PAD interface for processing by the automatic test equipment.

[0149] In the above embodiments, by adjusting the first clock control signal, the adjusted first clock control signal can simultaneously meet the requirements of the static register and the pulse requirements of the dynamic register, thereby ensuring the correct transmission and retention of test data during the shifting and sampling process, avoiding test failures caused by clock pulse width mismatch, and thus ensuring the reliability of the test.

[0150] See Figure 18 The diagram schematically illustrates the structure of a chip according to an exemplary embodiment of the present disclosure.

[0151] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program specifying the relevant hardware control circuits. The computer program can be stored in a readable storage medium, and when executed, it can include the processes of the test embodiments of the methods described above. Any references to memory or other media used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), floppy disk, flash memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM), etc. The processors involved in the embodiments provided in this application can be general-purpose processors, central processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, etc., and are not limited thereto.

[0152] In the description of this specification, the technical features of the above embodiments can be combined arbitrarily. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0153] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A scan test circuit, characterized by, The scanning test circuit includes: A receiving module is used to receive test signals; the test signals include a first clock control signal. A clock control module is used to adjust the first clock control signal to obtain an adjusted first clock control signal; wherein the adjusted first clock control signal meets the pulse width requirements of the registers in the digital chip. The test control module is used to test the registers of the digital chip according to the adjusted first clock control signal; The clock control module is further configured to widen the first clock control signal to obtain a widened clock signal when the first clock control signal is obtained by compressing the clock width of a slow clock signal; the test control module is further configured to test the static register according to the widened clock signal and test the dynamic register according to the first clock control signal. or The clock control module is further configured to compress the first clock control signal to obtain a target compressed clock signal when the first clock control signal is a slow clock signal; the test control module is further configured to test the static register according to the slow clock signal and test the dynamic register according to the target compressed clock signal.

2. The scanning test circuit according to claim 1, characterized in that, The test control module includes: The first scan control link is used to receive the stretched clock signal and test the static register according to the stretched clock signal; the stretched clock signal is the first clock control signal after the stretched processing. The second scan control link is used to receive the first clock control signal and test the dynamic register according to the first clock control signal.

3. The scan test circuit of claim 2, wherein, The clock control module includes: The delay submodule is used to perform multi-level delay processing on the first clock control signal to obtain multiple delay tap signals with increasing delay durations. The logic submodule is used to perform logical operations on the first clock control signal and each of the delay tap signals to obtain multiple extended clock signals with different pulse widths. The selection submodule is used to select from each of the widened clock signals and transmit the selected widened clock signal to the first scan control link.

4. The scanning test circuit according to claim 3, characterized in that: The logic submodule includes multiple cascaded OR gates. One input of each OR gate is connected to the output of the corresponding delay unit in the delay submodule. The multiple OR gates are used to perform a logical OR operation on the first clock control signal and a delay tap signal to obtain multiple extended clock signals with different pulse widths.

5. The scan test circuit of claim 4, wherein, The first input terminal of the first OR gate is connected to the output terminal of the corresponding delay unit, and the second input terminal is connected to the first clock control signal; the first input terminal of the other OR gates is connected to the output terminal of the corresponding delay unit, and the second input terminal is connected to the output terminal of the previous OR gate; the first OR gate performs a logical OR operation on the first clock control signal and the corresponding delay tap signal to obtain a first widened clock signal; the other OR gates perform a logical OR operation on the widened clock signal output by the previous OR gate and the corresponding delay tap signal to obtain other widened clock signals.

6. The scan test circuit of claim 5, wherein, Each of the delay tap signals corresponds one-to-one with each of the widened clock signals; the pulse widths of each widened clock signal increase sequentially; the pulse width of the first widened clock signal is the sum of the delay duration of the corresponding delay tap signal and the pulse width of the first clock control signal; the pulse widths of the other widened clock signals are the sum of the delay duration of the corresponding delay tap signal and the pulse width of the previous widened clock signal.

7. The scanning test circuit according to claim 1, characterized in that, The test control module includes: The first scan control link is used to receive the slow clock signal and test the static register according to the slow clock signal; The second scan control link is used to receive the target compressed clock signal and test the dynamic register according to the target compressed clock signal; the target compressed clock signal is the first clock control signal after compression processing.

8. The scan test circuit of claim 7, wherein, The clock control module includes: The delay submodule is used to apply time delay and phase flip to the first clock control signal step by step to generate multiple delay tap signals; The logic submodule is used to perform logical operations on the first clock control signal and each delay tap signal to obtain multiple target compressed clock signals with different pulse widths. The selection submodule is used to select from multiple target compressed clock signals with different pulse widths and transmit the selected target compressed clock signal to the second scan control link.

9. The scanning test circuit according to claim 8, characterized in that, The delay submodule includes cascaded phase shift units, each phase shift unit including a delay unit and an inverter, the output of the delay unit being connected to the input of the inverter; the delay unit is used to perform multi-stage delay processing on the first clock control signal; The inverter is used to flip the delayed first clock control signal to obtain the delayed tap signal; The logic submodule includes multiple logic units, each logic unit includes an AND gate and a pulse selector, the first input terminal of each AND gate is connected to the output terminal of the corresponding inverter, and the second input terminal of each AND gate is input to the first clock control signal; The first input terminal of each pulse selector is connected to the output terminal of the corresponding AND gate, and the second input terminal of each pulse selector receives the first clock control signal; Each of the AND gates is used to perform a logical AND operation on the first clock control signal and a delay tap signal to obtain multiple initial compressed clock signals with different pulse widths; the pulse selector is used to generate multiple target compressed clock signals with different pulse widths based on the initial compressed clock signals according to the first clock control signal. The selection submodule includes a pre-selection unit, a final selection unit, and an arbitration unit; the pre-selection unit includes multiple pre-selection sub-units; the input terminal of the pre-selection unit is the output terminal of the pulse selector; one input terminal of the final selection unit is connected to the output terminal of the corresponding pre-selection sub-unit. The pre-selection unit is used to perform hierarchical selection of each of the target compressed clock signals according to the second control signal; the final selection unit is used to select the target compressed clock signal selected by the pre-selection unit according to the final selection signal. The arbitration unit includes a NOR gate, one output of which is connected to the control terminal of the final selection unit. The NOR gate is used to perform a NOR operation on the mode selection signal and the on-chip control signal to generate the final selection signal.

10. The scan test circuit of claim 9, wherein, When the mode selection signal is in test mode and the on-chip control signal is in non-high-speed capture mode, the final stage selection signal is a valid signal.

11. The scanning test circuit according to claim 9, characterized in that, Each of the delay tap signals corresponds one-to-one with each of the target compressed clock signals; the delay duration of the delay tap signal is the same as the pulse width of the target compressed clock signal.

12. A method of scan testing, characterized by, The method for scanning test circuits includes: Receive a test signal; the test signal includes a first clock control signal; Adjusting the first clock control signal to obtain an adjusted first clock control signal includes: when the first clock control signal is obtained by compressing the clock width of a slow clock signal, widening the first clock control signal to obtain a widened clock signal; or when the first clock control signal is a slow clock signal, compressing the first clock control signal to obtain a target compressed clock signal; wherein the adjusted first clock control signal meets the pulse width requirements of the registers in the digital chip; The registers of the digital chip are tested according to the adjusted first clock control signal, and the test results are output, including: when the first clock control signal is widened to obtain a widened clock signal, the static register is tested according to the widened clock signal and the dynamic register is tested according to the first clock control signal; or when the first clock control signal is compressed to obtain a target compressed clock signal, the static register is tested according to the slow clock signal and the dynamic register is tested according to the target compressed clock signal.

13. A chip, characterized by Includes the scanning test circuit as described in any one of claims 1-11.

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