A method, system, device, medium, and product for modeling a multi-chip parallel power module electrical network

Abstract

The application discloses a kind of multi-chip parallel power module electric network modeling method, system, equipment, medium and product, it is related to multi-chip parallel power module modeling technical field, obtains the electric network structure of power module, carries out complex frequency domain conversion to electric network structure, obtains corresponding target electric network structure, based on Kirchhoff's law, using target electric network structure generates corresponding electric network matrix model, based on the chip transfer characteristic of power module, matrix operation is carried out to electric network matrix model, corresponding chip drain current model is obtained, according to electric network structure, corresponding three-dimensional structure model is generated, and according to three-dimensional structure model and chip drain current model, the electric network model corresponding to power module is determined. Overcome the technical problem that the current power module electric network modeling method cannot intuitively describe the current distribution inside the module, reduces the reliability of power module operation.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of multi-chip parallel power module modeling, and particularly relates to a multi-chip parallel power module electrical network modeling method, system, device, medium and product. BACKGROUND

[0002] With the rise and continuous development of new energy power generation, electric vehicles and other industries, the requirements for power conversion and transmission in industrial applications are becoming higher and higher, and the demand for power semiconductor devices is increasing. The current level of power modules is gradually increasing, and the current carrying capacity of a single power semiconductor chip often cannot meet the actual demand, so the multi-chip parallel method is usually used in power modules to improve the current level of the module. The electrical network structure of the multi-chip parallel power module is relatively complex, and the current path coupling phenomenon is serious. Unreasonable module layout may cause large dynamic current difference between parallel chips, which is not conducive to the safe and reliable operation of the module. Therefore, accurate modeling of the electrical network of the multi-chip parallel power module is beneficial to the reasonable layout of the power module.

[0003] At present, the existing electrical network modeling method of the power module mainly constructs the electrical network model of the power module through the SPICE software, but the method obtains a numerical solution, which cannot intuitively describe the current distribution inside the module, resulting in difficulty in effectively regulating and controlling the layout of the power module, and reducing the reliability of the power module operation. SUMMARY

[0004] The present application provides a multi-chip parallel power module electrical network modeling method, system, device, medium and product, which solves the technical problem that the existing electrical network modeling method of the power module mainly constructs the electrical network model of the power module through the SPICE software, but the method obtains a numerical solution, which cannot intuitively describe the current distribution inside the module, resulting in difficulty in effectively regulating and controlling the layout of the power module, and reducing the reliability of the power module operation.

[0005] The first aspect of the present application provides a multi-chip parallel power module electrical network modeling method, comprising:

[0006] Obtaining the electrical network structure of the power module, performing complex frequency domain conversion on the electrical network structure to obtain the corresponding target electrical network structure;

[0007] Based on Kirchhoff's law, generating a corresponding electrical network matrix model using the target electrical network structure;

[0008] Performing matrix operation on the electrical network matrix model based on the chip transfer characteristics of the power module to obtain a corresponding chip drain current model;

[0009] A three-dimensional structure model corresponding to the electrical network structure is generated, and an electrical network model corresponding to the power module is determined according to the three-dimensional structure model and the chip drain current model.

[0010] Optionally, the step of performing complex frequency domain conversion on the electrical network structure to obtain a corresponding target electrical network structure comprises:

[0011] The electrical network structure is subjected to non-target chip equivalent processing based on a pre-acquired dynamic scenario to obtain a corresponding first simplified electrical network structure;

[0012] The first simplified electrical network structure is subjected to busbar capacitance equivalent processing to obtain a corresponding second simplified electrical network structure;

[0013] The second simplified electrical network structure is subjected to complex frequency domain conversion to obtain a corresponding target electrical network structure.

[0014] Optionally, the step of generating an electrical network matrix model corresponding to the target electrical network structure based on the Kirchhoff's law comprises:

[0015] A loop voltage model corresponding to the target electrical network structure is constructed based on the Kirchhoff's law;

[0016] A node voltage model corresponding to the target electrical network structure is determined based on a pre-set node current model;

[0017] The loop voltage model and the node voltage model are coupled to obtain a corresponding electrical network matrix model.

[0018] Optionally, the step of performing matrix operation on the electrical network matrix model based on the chip transfer characteristic of the power module to obtain a corresponding chip drain current model comprises:

[0019] A transfer characteristic model is constructed based on the chip transfer characteristic of the power module;

[0020] The electrical network matrix model is subjected to matrix operation according to the transfer characteristic model to obtain a corresponding chip drain current model.

[0021] Optionally, the step of determining an electrical network model corresponding to the power module according to the three-dimensional structure model and the chip drain current model comprises:

[0022] An open circuit test is performed on the three-dimensional structure model by calling a pre-set three-dimensional tool to obtain a corresponding parasitic parameter;

[0023] The parasitic parameter and a pre-set chip parameter are input into the chip drain current model to obtain a corresponding target chip drain current model;

[0024] The drain current model of the target chip is subjected to an inverse Laplace transform to obtain the electrical network model corresponding to the power module.

[0025] Optionally, the chip drain current model is specifically as follows:

[0026] ;

[0027] ;

[0028] ;

[0029] in, This is the drain current of the chip. This is the first coefficient matrix. It is the identity matrix. This is the impedance matrix of the chip gate. This is the impedance matrix of the chip source. This is the impedance matrix of the Kelvin source of the chip. Let be the admittance matrix of the chip's input capacitor. This is the second coefficient matrix. This is a matrix representing the chip's on-threshold voltage. For loop voltage vector, This represents the transconductance matrix of the chip.

[0030] A second aspect of the present invention provides a multi-chip parallel power module electrical network modeling system, comprising:

[0031] The acquisition module is used to acquire the electrical network structure of the power module, perform complex frequency domain transformation on the electrical network structure, and obtain the corresponding target electrical network structure.

[0032] A simplification module is used to generate a corresponding electrical network matrix model based on Kirchhoff's laws and the target electrical network structure.

[0033] The computation module is used to perform matrix operations on the electrical network matrix model based on the chip transfer characteristics of the power module to obtain the corresponding chip drain current model.

[0034] A construction module is used to generate a corresponding three-dimensional structural model based on the electrical network structure, and to determine the electrical network model corresponding to the power module based on the three-dimensional structural model and the chip drain current model.

[0035] A third aspect of the present invention provides an electronic device, including a memory and a processor, wherein the memory stores a computer program, and when the computer program is executed by the processor, the processor performs the steps of the multi-chip parallel power module electrical network modeling method as described in any of the preceding claims.

[0036] The fourth aspect of the present application provides a computer readable storage medium, which stores a computer program, and the computer program is executed to implement the multi-chip parallel power module electrical network modeling method according to any one of the above.

[0037] The fifth aspect of the present application provides a computer program product, which comprises a computer program stored on a non-transitory computer readable storage medium, and the computer program comprises program instructions, wherein when the program instructions are executed by a computer, the computer executes the multi-chip parallel power module electrical network modeling method according to any one of the above.

[0038] From the above technical solutions, the present application has the following advantages:

[0039] The present application obtains the electrical network structure of the power module, performs complex frequency domain conversion on the electrical network structure, obtains the corresponding target electrical network structure, generates the corresponding electrical network matrix model based on the Kirchhoff's law and the target electrical network structure, performs matrix operation on the electrical network matrix model based on the chip transfer characteristics of the power module, obtains the corresponding chip drain current model, generates the corresponding three-dimensional structure model according to the electrical network structure, and determines the corresponding electrical network model of the power module according to the three-dimensional structure model and the chip drain current model. The technical problem that the existing electrical network modeling method of the power module mainly constructs the electrical network model of the power module through the SPICE software, cannot intuitively describe the current distribution in the module, and reduces the reliability of the power module operation is overcome. Compared with the traditional electrical network modeling method, the present application converts the complex current path in the target electrical network structure into the chip drain current model through complex frequency domain conversion on the electrical network structure, and finally determines the corresponding electrical network model of the power module according to the three-dimensional structure model and the chip drain current model, so that the user can intuitively understand the current distribution in the module through the electrical network model, and the reliability of the power module operation is improved. BRIEF DESCRIPTION OF DRAWINGS

[0040] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or prior art description will be briefly introduced as follows. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0041] Figure 1 A step flow chart of a multi-chip parallel power module electrical network modeling method provided for the first embodiment of the present application;

[0042] Figure 2 A step flow chart of a multi-chip parallel power module electrical network modeling method provided for the second embodiment of the present application is shown in the figure.

[0043] Figure 3 A three-chip parallel half-bridge type power module electrical network structure schematic diagram provided for the second embodiment of the present application is shown in the figure.

[0044] Figure 4 A second simplified electrical network structure schematic diagram of a three-chip parallel half-bridge type power module provided for the second embodiment of the present application is shown in the figure.

[0045] Figure 5 A target electrical network structure of a three-chip parallel half-bridge type power module provided for the second embodiment of the present application is shown in the figure.

[0046] Figure 6 A structure block diagram of a multi-chip parallel power module electrical network modeling system provided for the third embodiment of the present application is shown in the figure.

[0047] Figure 7 A structure block diagram of an electronic device provided for the fourth embodiment of the present application is shown in the figure. DETAILED DESCRIPTION

[0048] The embodiments of the present application provide a multi-chip parallel power module electrical network modeling method, system, device, medium and product, which are used to solve the technical problem that the existing power module electrical network modeling method mainly constructs a power module electrical network model through SPICE software, but the numerical solution obtained by the method cannot intuitively describe the current distribution in the module, which leads to difficulty in effectively regulating the arrangement of the power module and reduces the reliability of the power module operation.

[0049] In order to make the invention purpose, features and advantages of the present application more obvious and easy to understand, the technical solutions in the embodiments of the present application will be described clearly and completely in conjunction with the drawings in the embodiments of the present application. Obviously, the following described embodiments are only part of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor are within the scope of protection of the present application.

[0050] Please refer to Figure 1 , Figure 1 A step flow chart of a multi-chip parallel power module electrical network modeling method provided for the first embodiment of the present application is shown in the figure.

[0051] The multi-chip parallel power module electrical network modeling method provided by the present application comprises:

[0052] Step 101, obtaining an electrical network structure of a power module, performing complex frequency domain conversion on the electrical network structure to obtain a corresponding target electrical network structure.

[0053] The electrical network structure refers to an actual electrical structure layout of the power module (i.e., a multi-chip parallel power module), a system structure formed by key electrical components (including functional components and parasitic parameters) in the module according to a specific electrical connection relationship, for transmitting, converting, and processing electrical energy or electrical signals in the module.

[0054] The target electrical network structure refers to the target electrical network structure after complex frequency domain conversion.

[0055] In the embodiment of the application, the non-target chip equivalent processing is performed on the electrical network structure based on the pre-acquired dynamic scene to obtain a corresponding first simplified electrical network structure. The bus capacitor equivalent processing is performed on the first simplified electrical network structure to obtain a corresponding second simplified electrical network structure. The complex frequency domain conversion operation is performed on the second simplified electrical network structure to obtain a corresponding target electrical network structure.

[0056] Step 102, generating a corresponding electrical network matrix model based on the target electrical network structure according to the Kirchhoff's law.

[0057] In the embodiment of the application, the loop voltage model corresponding to the target electrical network structure is constructed based on the Kirchhoff's law. The node voltage model corresponding to the target electrical network structure is determined based on the pre-set node current model. The loop voltage model and the node voltage model are coupled to obtain a corresponding electrical network matrix model.

[0058] Step 103, performing matrix operation on the electrical network matrix model based on the chip transfer characteristic of the power module to obtain a corresponding chip drain current model.

[0059] The chip transfer characteristic refers to the fixed correlation characteristic between the drain current and the gate-source voltage of the chip in the on state, which is a core characteristic reflecting the gate control ability of the chip. For example, the SiC MOSFET chip (i.e., a metal-oxide-semiconductor field effect transistor made of silicon carbide material).

[0060] In the embodiment of the application, the transfer characteristic model is constructed based on the chip transfer characteristic of the power module. The matrix operation is performed on the electrical network matrix model according to the transfer characteristic model to obtain a corresponding chip drain current model.

[0061] Step 104, generating a corresponding three-dimensional structure model according to the electrical network structure, and determining a corresponding electrical network model of the power module according to the three-dimensional structure model and the chip drain current model.

[0062] The three-dimensional structure model refers to a digital model for reproducing the physical layout of the module, which is constructed by using drawing software such as Solidworks and AutoCAD according to the power module electrical network structure, and contains the physical size, mounting position and geometric and material properties of the connection line of the functional components, and is a physical carrier for extracting the parasitic parameters.

[0063] In the embodiment of the application, the preset three-dimensional tool is called to perform the opening test on the three-dimensional structure model, and the corresponding parasitic parameters are obtained. The parasitic parameters and the preset chip parameters are input into the chip drain current model to obtain the corresponding target chip drain current model. The target chip drain current model is subjected to Laplace inverse transformation to obtain the electrical network model corresponding to the power module.

[0064] In the embodiment of the application, the electrical network structure of the power module is obtained, the electrical network structure is subjected to complex frequency domain conversion to obtain the corresponding target electrical network structure, the target electrical network structure is used to generate the corresponding electrical network matrix model based on the Kirchhoff law, the electrical network matrix model is subjected to matrix operation based on the chip transfer characteristics of the power module to obtain the corresponding chip drain current model, the three-dimensional structure model corresponding to the electrical network structure is generated, and the electrical network model corresponding to the power module is determined according to the three-dimensional structure model and the chip drain current model. The technical problem that the existing power module electrical network modeling method mainly constructs the electrical network model of the power module through the SPICE software, and cannot intuitively describe the current distribution in the module, thereby reducing the reliability of the power module operation is overcome. Compared with the traditional electrical network modeling method, the target electrical network structure is obtained by complex frequency domain conversion of the electrical network structure in the application, and then the complex current path in the target electrical network structure is converted into the chip drain current model based on the Kirchhoff law and the chip transfer characteristics of the power module. Finally, the electrical network model corresponding to the power module is determined according to the three-dimensional structure model and the chip drain current model, so that the user can intuitively understand the current distribution in the module through the electrical network model, and the reliability of the power module operation is improved.

[0065] Please refer to Figure 2 , Figure 2 A step flow chart of a multi-chip parallel power module electrical network modeling method is provided for the second embodiment of the application.

[0066] The multi-chip parallel power module electrical network modeling method provided by the application comprises the following steps:

[0067] Step 201, obtaining the electrical network structure of the power module, and performing complex frequency domain conversion on the electrical network structure to obtain the corresponding target electrical network structure.

[0068] Further, step 201 comprises the following sub-steps:

[0069] S11. Based on the pre-acquired dynamic scene, the electrical network structure is processed to obtain the corresponding first simplified electrical network structure by performing non-target chip equivalent processing.

[0070] Dynamic scenarios refer to the specific working states that power modules exhibit during operation, such as the process of one group of chips being turned on and another group of chips being turned off (as in the turn-on process of the lower transistor chip). This serves as the basis for simplifying the electrical network structure and determines the equivalent method and simplification range of non-target chips.

[0071] Non-target chips refer to chips that are in a non-working state (such as a shutdown state) and do not participate in the current power conversion or current transmission in the pre-acquired dynamic scenario, such as the upper transistor chip in the turn-on process of the lower transistor chip. They need to be equivalently processed and the relevant circuits simplified.

[0072] In this embodiment of the invention, non-target chips in the electrical network structure are determined based on a pre-acquired dynamic scene. Each non-target chip is then equivalently processed into a voltage source with a constant output voltage, resulting in a corresponding first simplified electrical network structure. For example, see [reference needed]. Figure 3 As shown, the dynamic scenario is that the upper-side chip is turned off and the lower-side chip is turned on. The lower-side chip (such as Q) L1 Q L2 Q L3 The target chip participating in the current activation process is the upper-side chip (such as Q). H1 Q H2 Q H3 The non-target chip (the upper-side transistor chip) is not involved in the current turn-on process. Next, the non-target chip is treated as an equivalent circuit. Since the upper-side transistor chip is in the off state in this dynamic scenario and cannot carry forward current, only its reverse freewheeling function needs to be considered. Therefore, each upper-side transistor chip is equivalent to an anti-parallel diode (such as D). H The diode's conduction direction is opposite to that of the upper transistor chip, providing a current path during the freewheeling phase of the load current. Subsequently, the electrical network structure is simplified based on the equivalent processing results, omitting parasitic parameters around the non-target chip (upper transistor chip) (such as the upper transistor chip's drain parasitic inductance L). Hd1 -L Hd3 Drain parasitic resistance R Hd1 -R Hd3 Gate parasitic inductance L Hg1 -L Hg3 Gate parasitic resistance R Hg1 -R Hg3 The upper MOSFET chip and its driving circuit (such as driving voltage, corresponding driving resistor, etc.) are retained, only the target chip (lower MOSFET chip) and its associated functional components (such as DC bus capacitor, load inductor, lower MOSFET driving voltage, lower MOSFET driving resistor, lower MOSFET chip input capacitor) and parasitic parameters (lower MOSFET chip drain parasitic inductance L) are retained.Ld1 -L Ld3 , drain parasitic inductance L Ld1 -R Ld3 , source parasitic inductance L Ls1 -L Ls3 , source parasitic resistance R Ls1 -R Ls3 , gate parasitic inductance L Lg1 -L Lg3 , gate parasitic resistance R Lg1 -R Lg3 , Kelvin source parasitic inductance L Lk1 -L Lk3 , Kelvin source parasitic resistance R Lk1 -R Lk3 ).

[0073] S12, bus capacitor equivalent processing is carried out on the first simplified electric network structure, and a corresponding second simplified electric network structure is obtained.

[0074] The bus capacitor refers to a capacitor element for stabilizing the DC bus voltage and suppressing voltage fluctuation in the electric network structure of the power module, and generally has a large capacity and is one of the key components for ensuring the stability of the module power supply.

[0075] In the embodiment of the application, the bus capacitor is equivalent to a constant voltage source, and a corresponding second simplified electric network structure is obtained. For example, as shown in Figure 4 , the non-target chip equivalent processing and the bus capacitor equivalent processing are sequentially carried out on the electric network structure of the three-chip parallel half-bridge type power module, and a corresponding second simplified electric network structure is obtained.

[0076] S13, the second simplified electric network structure is subjected to complex frequency domain conversion operation, and a corresponding target electric network structure is obtained.

[0077] In the embodiment of the application, the second simplified electric network structure is subjected to complex frequency domain conversion operation based on the complex frequency domain conversion rule, and a corresponding target electric network structure is obtained. For example, as shown in Figure 5 , the second simplified electric network structure of the three-chip parallel half-bridge type power module is subjected to complex frequency domain conversion operation based on the complex frequency domain conversion rule, and a corresponding target electric network structure is obtained.

[0078] It should be noted that the complex frequency domain conversion rule is that the impedance of the resistance (R) in the time domain remains its own resistance value R in the complex frequency domain, the impedance of the inductance (L) in the time domain is converted into sL (s is a complex frequency composed of a real part damping coefficient σ and an imaginary part angular frequency ω, i.e. s=σ+jω), and the impedance of the capacitance (C) in the time domain is converted into 1 / (sC) in the complex frequency domain.

[0079] Step 202, based on Kirchhoff's law, constructing a loop voltage model corresponding to the target electric network structure.

[0080] In the embodiments of the present application, based on Kirchhoff's law, the loop voltage equations of each drive loop in each target electric network structure are written, and each loop voltage equation is combined to obtain the corresponding loop voltage model.

[0081] It should be noted that the loop voltage model is specifically:

[0082]

[0083]

[0084] wherein, is the loop voltage of the first drive loop, is the loop voltage of the qth drive loop, is the loop voltage of the nth drive loop, is the drive resistance of the first drive loop, is the drive resistance of the qth drive loop, is the drive resistance of the nth drive loop, is the pth chip gate current, is the impedance of the first lower tube chip gate, is the impedance of the qth lower tube chip gate, is the impedance of the nth lower tube chip gate, is the first chip gate current, is the qth chip gate current, is the nth chip gate current, is the input capacitance voltage of the first chip, is the input capacitance voltage of the qth chip, is the input capacitance voltage of the nth chip, is the impedance of the first lower tube chip Kelvin source, is the impedance of the qth lower tube chip Kelvin source, is the impedance of the nth lower tube chip Kelvin source, is the first chip Kelvin source current, is the qth chip Kelvin source current, is the nth chip Kelvin source current, and s is a complex frequency, is the input capacitance of the first chip, is the input capacitance of the qth chip, is the input capacitance of the nth chip, q is the first index of the chip, n is the total number of chips, and p is the second index of the chip.

[0085] Step 203, determining a node voltage model corresponding to the target electric network structure based on the preset node current model.

[0086] In the embodiment of the present application, based on the preset node current model and the target electric network structure, the node voltage model is constructed with the voltage of each chip source as a variable.

[0087] It should be noted that the node current model is specifically:

[0088]

[0089] wherein, is the first chip drain current, is the qth chip drain current, is the nth chip drain current, is the first chip gate current, is the qth chip gate current, is the nth chip gate current, is the first chip source current, is the qth chip source current, is the nth chip source current, is the first chip Kelvin source current, is the qth chip Kelvin source current, is the nth chip Kelvin source current.

[0090] It should be noted that the node voltage model is specifically:

[0091]

[0092]

[0093] wherein, is the voltage of the first chip source, is the voltage of the qth chip source, is the voltage of the pth chip source, is the voltage of the nth chip source, is the impedance of the first lower tube chip Kelvin source, is the impedance of the qth lower tube chip Kelvin source, is the impedance of the nth lower tube chip Kelvin source, is the impedance of the pth lower tube chip Kelvin source.

[0094] Step 204, coupling the loop voltage model and the node voltage model to obtain a corresponding electric network matrix model.

[0095] In the embodiment of the present application, the loop voltage model and the node voltage model are coupled to obtain a corresponding electrical network matrix model.

[0096] It should be noted that the electrical network matrix model is specifically:

[0097]

[0098]

[0099]

[0100] wherein, is the impedance of the first lower tube chip gate, is the impedance of the second lower tube chip gate, is the impedance of the qth lower tube chip gate, is the impedance of the n-1th lower tube chip gate, is the impedance of the nth lower tube chip gate, is the driving resistance, is the driving voltage.

[0101] Step 205, matrix operation is performed on the electrical network matrix model based on the chip transfer characteristics of the power module, to obtain a corresponding chip drain current model.

[0102] Further, step 205 includes the following sub-steps:

[0103] S21, based on the chip transfer characteristics of the power module, a corresponding transfer characteristic model is constructed.

[0104] In the embodiment of the present application, based on the chip transfer characteristics of the power module (i.e. the transfer characteristics of SiC MOSFET), a corresponding transfer characteristic model is constructed.

[0105] It should be noted that the transfer characteristic model is specifically:

[0106]

[0107]

[0108] wherein, V th = [V th1 , V th2 , …, V thn ] T , V th1 is the first chip conduction threshold voltage, V th2 is the second chip conduction threshold voltage, V thn is the nth chip conduction threshold voltage, is the transconductance of each chip, =[v gs1 gsn T is an input capacitance voltage vector of the chip, gs1 is an input capacitance voltage of the first chip, gsn is an input capacitance voltage of the n-th chip.

[0109] S22, performing matrix operation on the electrical network matrix model according to the transfer characteristic model to obtain a corresponding chip drain current model.

[0110] In the embodiment of the present application, the loop voltage model in the electrical network matrix model is converted into a matrix form to obtain a loop voltage matrix equation, and a first relationship equation between a chip source current vector and a chip Kelvin source current vector can be obtained according to a node voltage model in the electrical network matrix model. The preset node current model is converted into a matrix form to obtain a node current matrix equation. The loop voltage matrix equation, the first relationship equation, the node current matrix equation and the transfer characteristic model are coupled to obtain a corresponding chip drain current model.

[0111] It should be noted that the loop voltage matrix equation is specifically as follows:

[0112]

[0113]

[0114] wherein, is an input capacitance voltage vector of the chip, =[v g1 gn T is a chip gate current vector.

[0115] It should be noted that the first relationship equation is specifically as follows:

[0116]

[0117]

[0118] wherein, =[i k1 kn T is a chip Kelvin source current vector, =[i s1 sn T ​​​​​​​​​​​​​is a chip drain current vector.

[0119] It should be noted that the node current matrix equation is specifically:

[0120]

[0121] wherein, =[i d1 ,… i dn ] T is a chip drain current vector.

[0122] It should be noted that the chip drain current model is specifically:

[0123] .

[0124] .

[0125] .

[0126] wherein, is a chip drain current, is a first coefficient matrix, is an identity matrix, is an impedance matrix of a chip gate, is an impedance matrix of a chip source, is an impedance matrix of a chip Kelvin source, is an admittance matrix of a chip input capacitance, is a second coefficient matrix, is a matrix of a chip conduction threshold voltage, is a loop voltage vector, is a matrix of a chip transconductance.

[0127] Step 206, generating a corresponding three-dimensional structure model according to the electrical network structure, and determining a corresponding electrical network model of the power module according to the three-dimensional structure model and the chip drain current model.

[0128] Further, step 206 includes the following sub-steps:

[0129] S31, calling a preset three-dimensional tool to perform an open test on the three-dimensional structure model to obtain corresponding parasitic parameters.

[0130] It should be noted that the parasitic parameters include but are not limited to the impedance matrix of the chip gate, the impedance matrix of the chip source, and the impedance matrix of the chip Kelvin source, etc.

[0131] In the embodiment of the present application, a preset three-dimensional tool (such as Ansys Q3D software) is called to perform a turn-on test on the three-dimensional structure model based on a preset frequency (generally, the highest frequency component contained in the current waveform of the power device in the on process is about 10 MHz, therefore, the frequency is 10 MHz) to obtain the corresponding parasitic parameters.

[0132] In the embodiment of the present application, the parasitic parameters and the preset chip parameters are substituted into the chip drain current model to obtain the corresponding target chip drain current model.

[0133] The chip parameters refer to the transconductance matrix, the chip conduction threshold voltage matrix and the admittance matrix of the chip input capacitance of the chip obtained through the chip data manual.

[0134] In the embodiment of the present application, the parasitic parameters and the preset chip parameters are substituted into the chip drain current model to obtain the corresponding target chip drain current model.

[0135] In the embodiment of the present application, the target chip drain current model is subjected to Laplace inverse transformation to obtain the corresponding electrical network model of the power module.

[0136] In the embodiment of the present application, a preset mathematical calculation tool (such as MATLAB software) is called to perform Laplace inverse transformation on the target chip drain current model to obtain the corresponding electrical network model of the power module.

[0137] In the embodiment of the present application, the electrical network structure of the power module is obtained, the electrical network structure is subjected to complex frequency domain conversion to obtain the corresponding target electrical network structure, the target electrical network structure is used to generate the corresponding electrical network matrix model based on the Kirchhoff's law, the electrical network matrix model is subjected to matrix operation based on the chip transfer characteristics of the power module to obtain the corresponding chip drain current model, the three-dimensional structure model is generated according to the electrical network structure, and the electrical network model corresponding to the power module is determined according to the three-dimensional structure model and the chip drain current model. The technical problem that the existing electrical network modeling method of the power module mainly constructs the electrical network model of the power module through the SPICE software, cannot intuitively describe the current distribution in the module, and reduces the reliability of the power module operation is overcome. Compared with the traditional electrical network modeling method, the present application converts the electrical network structure to obtain the corresponding target electrical network structure through complex frequency domain conversion, converts the complex current path in the target electrical network structure into the chip drain current model based on the Kirchhoff's law and the chip transfer characteristics of the power module, and finally determines the electrical network model corresponding to the power module according to the three-dimensional structure model and the chip drain current model, so that the user can intuitively understand the current distribution in the module through the electrical network model, and the reliability of the power module operation is improved.

[0138] Please refer toFigure 6 , Figure 6 A structural block diagram of a multi-chip parallel power module electrical network modeling system provided for embodiment three of the application.

[0139] The application provides a multi-chip parallel power module electrical network modeling system, which comprises:

[0140] The acquisition module 301 is configured to acquire an electrical network structure of a power module, perform complex frequency domain conversion on the electrical network structure, and obtain a corresponding target electrical network structure.

[0141] The simplification module 302 is configured to generate a corresponding electrical network matrix model based on the target electrical network structure according to the Kirchhoff's law.

[0142] The operation module 303 is configured to perform matrix operation on the electrical network matrix model based on the chip transfer characteristics of the power module, and obtain a corresponding chip drain current model.

[0143] The construction module 304 is configured to generate a corresponding three-dimensional structure model according to the electrical network structure, and determine a corresponding electrical network model of the power module according to the three-dimensional structure model and the chip drain current model.

[0144] Further, the acquisition module 301 comprises:

[0145] The first equivalent submodule is configured to perform non-target chip equivalent processing on the electrical network structure based on a pre-acquired dynamic scene, and obtain a corresponding first simplified electrical network structure.

[0146] The second equivalent submodule is configured to perform bus capacitor equivalent processing on the first simplified electrical network structure, and obtain a corresponding second simplified electrical network structure.

[0147] The complex frequency domain conversion submodule is configured to perform complex frequency domain conversion operation on the second simplified electrical network structure, and obtain a corresponding target electrical network structure.

[0148] Further, the simplification module 302 comprises:

[0149] The loop voltage submodule is configured to construct a loop voltage model corresponding to the target electrical network structure based on the Kirchhoff's law.

[0150] The node voltage submodule is configured to determine a node voltage model corresponding to the target electrical network structure based on a pre-set node current model.

[0151] The first coupling submodule is configured to couple the loop voltage model and the node voltage model, and obtain a corresponding electrical network matrix model.

[0152] Further, the operation module 303 comprises:

[0153] The transfer characteristic submodule is configured to construct a corresponding transfer characteristic model based on a chip transfer characteristic of the power module.

[0154] The matrix operation submodule is configured to perform matrix operation on the electrical network matrix model according to the transfer characteristic model, to obtain a corresponding chip drain current model.

[0155] Further, the construction module 304 comprises:

[0156] The opening test submodule is configured to call a preset three-dimensional tool to perform an opening test on the three-dimensional structure model, to obtain corresponding parasitic parameters.

[0157] The update submodule is configured to input the parasitic parameters and preset chip parameters into the chip drain current model, to obtain a corresponding target chip drain current model.

[0158] The Laplace inverse transform submodule is configured to perform Laplace inverse transform on the target chip drain current model, to obtain an electrical network model corresponding to the power module.

[0159] Further, the chip drain current model is specifically:

[0160] ;

[0161] ;

[0162] ;

[0163] wherein, is a chip drain current, is a first coefficient matrix, is an identity matrix, is an impedance matrix of a chip gate, is an impedance matrix of a chip source, is an impedance matrix of a chip Kelvin source, is an admittance matrix of a chip input capacitance, is a second coefficient matrix, is a matrix of a chip conduction threshold voltage, is a loop voltage vector, is a transconductance matrix of the chip.

[0164] Please refer to Figure 7 , Figure 7 is a structural block diagram of an electronic device provided in the fourth embodiment of the present application.

[0165] An electronic device according to an embodiment of the present application comprises a memory 401 and a processor 402, the memory 401 storing a computer program, and the computer program, when executed by the processor 402, causing the processor 402 to perform the method for modeling a multi-chip parallel power module electrical network according to any of the above embodiments.

[0166] The memory 401 can be an electronic memory such as a flash memory, an EEPROM (Electrically Erasable Programmable Read-Only Memory), an EPROM, a hard disk, or a ROM. The memory 401 has a storage space 403 for program codes 413 for performing any of the method steps described above. For example, the storage space 403 for program codes can include individual program codes 413 for implementing the various steps in the above method, respectively. These program codes can be read from or written to one or more computer program products. These computer program products include program code carriers such as a hard disk, a compact disk (CD), a memory card, or a floppy disk. The program codes can be compressed in a suitable form, for example. These codes, when run by a computing processing device, cause the computing processing device to perform the various steps in the above described method. These program codes can be read from or written to one or more computer program products. These computer program products include program code carriers such as a hard disk, a compact disk (CD), a memory card, or a floppy disk. The program codes can be compressed in a suitable form, for example. These codes, when run by a computing processing device, cause the computing processing device to perform the various steps in the above described method for modeling a multi-chip parallel power module electrical network.

[0167] The embodiment five of the present application further provides a computer readable storage medium, having stored thereon a computer program, which, when executed by a processor, implements the method for modeling a multi-chip parallel power module electrical network according to any of the above embodiments.

[0168] The embodiment six of the present application further provides a computer program product, comprising a computer program stored on a non-transitory computer readable storage medium, the computer program comprising program instructions, wherein the program instructions, when executed by a computer, cause the computer to perform the method for modeling a multi-chip parallel power module electrical network according to any of the above embodiments.

[0169] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the above described system, device and unit can refer to the corresponding processes in the above method embodiments, which will not be described herein.

[0170] In several embodiments provided in the present application, it should be understood that the disclosed system, device and method can be implemented in other manners. For example, the division of the units is only a logical function division, and there can be another division manner for the actual implementation, for example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the displayed or discussed mutual couplings or direct couplings or communication connections between different units, can be indirect couplings or communication connections through some interfaces, devices or units, and can be electrical, mechanical or in other forms.

[0171] The units described as separated components can or can not be physically separated, and the components displayed as units can or can not be physical units, i.e., can be located in one place, or can be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purposes of the embodiments of the present application.

[0172] In addition, each functional unit in the various embodiments of the present application can be integrated in a processing unit, or each unit can exist physically as a separate unit, or two or more units can be integrated in one unit. The integrated unit can be implemented in the form of hardware, or in the form of a software functional unit.

[0173] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer readable storage medium. Based on such an understanding, the technical solutions of the present application essentially or substantially, or all or part of the technical solutions, can be embodied in the form of a software product. The computer software product is stored in a storage medium, and includes a plurality of instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the methods in the various embodiments of the present application. The foregoing storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), magnetic disk or optical disk, and various media that can store program codes.

[0174] The above embodiments are only used to illustrate the technical solutions of the present application, rather than limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: it can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacements for some technical features; and these modifications or replacements do not make the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A method of modeling a multi-chip parallel power module electrical network, the method comprising: The method comprises the following steps: obtaining an electrical network structure of a power module, performing complex frequency domain conversion on the electrical network structure to obtain a corresponding target electrical network structure; based on Kirchhoff's law, generating a corresponding electrical network matrix model using the target electrical network structure; based on the chip transfer characteristics of the power module, performing matrix operation on the electrical network matrix model to obtain a corresponding chip drain current model; generating a corresponding three-dimensional structure model according to the electrical network structure, and determining the corresponding electrical network model of the power module according to the three-dimensional structure model and the chip drain current model; the step of generating a corresponding electrical network matrix model using the target electrical network structure based on Kirchhoff's law comprises: based on Kirchhoff's law, constructing a loop voltage model corresponding to the target electrical network structure; based on a preset node current model, determining a node voltage model corresponding to the target electrical network structure; coupling the loop voltage model and the node voltage model to obtain a corresponding electrical network matrix model; the step of performing matrix operation on the electrical network matrix model based on the chip transfer characteristics of the power module to obtain a corresponding chip drain current model comprises: based on the chip transfer characteristics of the power module, constructing a corresponding transfer characteristic model; performing matrix operation on the electrical network matrix model according to the transfer characteristic model to obtain a corresponding chip drain current model; the step of determining the corresponding electrical network model of the power module according to the three-dimensional structure model and the chip drain current model comprises: calling a preset three-dimensional tool to perform an open test on the three-dimensional structure model to obtain a corresponding parasitic parameter; inputting the parasitic parameter and a preset chip parameter into the chip drain current model to obtain a corresponding target chip drain current model; performing Laplace inverse transform on the target chip drain current model to obtain the corresponding electrical network model of the power module.

2. The multi-chip parallel power module electrical network modeling method of claim 1, wherein, the step of performing complex frequency domain conversion on the electrical network structure to obtain a corresponding target electrical network structure comprises: based on a pre-acquired dynamic scene, performing non-target chip equivalent processing on the electrical network structure to obtain a corresponding first simplified electrical network structure; performing bus capacitance equivalent processing on the first simplified electrical network structure to obtain a corresponding second simplified electrical network structure; performing complex frequency domain conversion on the second simplified electrical network structure to obtain a corresponding target electrical network structure.

3. The multi-chip parallel power module electrical network modeling method of claim 1, wherein, The chip drain current model specifically comprises: ； ； ； wherein is a chip drain current, is a first coefficient matrix, is an identity matrix, is an impedance matrix of the chip gate, is an impedance matrix of the chip source, is an impedance matrix of the chip Kelvin source, is an admittance matrix of the chip input capacitance, is a second coefficient matrix, is a matrix of the chip conduction threshold voltage, is a loop voltage vector, is a transconductance matrix of the chip.

4. A multi-chip parallel power module electrical network modeling system, characterized by, The method comprises the following steps: a collection module is configured to obtain an electrical network structure of a power module, perform complex frequency domain conversion on the electrical network structure, and obtain a corresponding target electrical network structure; a simplification module is configured to generate a corresponding electrical network matrix model using the target electrical network structure based on Kirchhoff's law; an operation module is configured to perform matrix operation on the electrical network matrix model based on the chip transfer characteristics of the power module to obtain a corresponding chip drain current model; a construction module is configured to generate a corresponding three-dimensional structure model according to the electrical network structure, and determine the corresponding electrical network model of the power module according to the three-dimensional structure model and the chip drain current model; The simplification module comprises: a loop voltage submodule for constructing a loop voltage model corresponding to the target electric network structure based on Kirchhoff's law; a node voltage submodule for determining a node voltage model corresponding to the target electric network structure based on a preset node current model; a first coupling submodule for coupling the loop voltage model and the node voltage model to obtain a corresponding electric network matrix model; The operation module comprises: a transfer characteristic submodule for constructing a corresponding transfer characteristic model based on the chip transfer characteristic of the power module; a matrix operation submodule for performing matrix operation on the electric network matrix model according to the transfer characteristic model to obtain a corresponding chip drain current model; The construction module comprises: an opening test submodule for calling a preset three-dimensional tool to perform an opening test on the three-dimensional structure model to obtain corresponding parasitic parameters; an updating submodule for inputting the parasitic parameters and preset chip parameters into the chip drain current model to obtain a corresponding target chip drain current model; a Laplace inverse transform submodule for performing Laplace inverse transform on the target chip drain current model to obtain an electric network model corresponding to the power module.

5. An electronic device, comprising: The computer program is executed to implement the multi-chip parallel power module electric network modeling method according to any one of claims 1-3.

6. A computer-readable storage medium having stored thereon a computer program, characterized in that, The computer program is executed to implement the multi-chip parallel power module electric network modeling method according to any one of claims 1-3.

7. A computer program product, characterised in that, The computer program product comprises a computer program stored on a non-transitory computer-readable storage medium, and the computer program comprises program instructions, wherein when the program instructions are executed by a computer, the computer executes the multi-chip parallel power module electric network modeling method according to any one of claims 1-3.

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