Packaging structure of magnetic isolation chip

Abstract

The invention discloses a packaging structure of a magnetic isolation chip, and relates to the technical field of semiconductor manufacturing, and the packaging structure comprises at least one control end lead frame, each control end lead frame is provided with a control end base island, and each control end base island is provided with a control end chip; at least one application end lead frame, each application end lead frame is provided with an application end base island, and each application end base island is provided with an application end chip; the isolation assembly is located in a gap between the application end base island and the control end base island; wherein the isolation assembly is internally provided with a control end coil and an application end coil which are used for transmitting signals, the control end coil and the application end coil are respectively routed to a control end chip and an application end chip, and the control end chip and the application end chip are respectively routed to respective pins of the control end lead frame and the application end lead frame. According to the invention, the defect that electric breakdown is easy to occur in a traditional packaging structure in-chip voltage-withstanding manufacturing process is overcome, and the high voltage-withstanding characteristic of the magnetic isolation chip can be realized.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and more specifically, to a packaging structure for a magnetically isolated chip. Background Technology

[0002] In fields such as automotive electronics and industrial control, chips with high withstand voltage values ​​play a crucial role: they can more effectively resist voltage surges, thereby reducing internal losses and improving operating efficiency; they also possess stronger voltage stress resistance, thus extending the chip's lifespan and ensuring long-term stable operation of equipment in harsh environments. In summary, withstand voltage is a critical indicator in the electrical parameters of isolation chips, typically determined by the chip's materials, manufacturing process, and structural design. To ensure the stability and reliability of the chip, its withstand voltage design is paramount.

[0003] Currently, the traditional internal packaging structure of magnetically isolated chips is as follows: the magnetic isolation devices used for signal transmission (control coil and application coil) are designed on-chip, and the control chip and application chip within the isolation chip are directly connected by gold wires. This traditional magnetically isolated chip internal packaging structure has two pathways where electrical breakdown is likely to occur: like Figure 1 As shown, since the base island spacing is likely the closest distance between the control and application ends, and the material used for this distance is a low-dielectric-strength molding compound, the value of this distance multiplied by the dielectric strength of the molding compound must be greater than the chip's design withstand voltage. However, since the control and application chips are directly connected by gold wires, if the base island spacing is too large, the gold wires will be very long, which will greatly increase the probability of wire breakage during molding, thus causing chip reliability issues.

[0004] like Figure 2 As shown, the thickness of the polyimide material between the coils of the on-chip isolator in traditional packaging structures determines the voltage withstand capability. However, the manufacturing process of the polyimide layer inside the wafer is complex and costly, and the thickness is at most 40µm (only a few factories can achieve this thickness). Its withstand voltage is at most 16kV (calculated based on the dielectric strength of the on-chip polyimide layer being 400V / µm). Therefore, traditional packaging structures are very likely to experience electrical breakdown, making it impossible for the packaging structure to meet higher withstand voltage requirements. Summary of the Invention

[0005] The purpose of this invention is to provide a packaging structure for a magnetic separator chip that solves the problem of electrical breakdown that easily occurs in the on-chip withstand voltage manufacturing process of traditional packaging structures, thereby achieving high withstand voltage characteristics for the magnetic separator chip.

[0006] The above-mentioned technical objective of the present invention is achieved through the following technical solution: This invention provides a packaging structure for a magnetic isolation chip, comprising: At least one control terminal lead frame, each control terminal lead frame is provided with a control terminal base island, and each control terminal base island is provided with a control terminal chip; At least one application-side lead frame, each application-side lead frame having an application-side base island, and each application-side base island having an application-side chip; and An isolation component is located between the application-side base island and the control-side base island; wherein, the isolation component is provided with a control-side coil and an application-side coil for transmitting signals, the control-side coil and the application-side coil are respectively wired to the control-side chip and the application-side chip, and the control-side chip and the application-side chip are respectively wired to the pins of the control-side lead frame and the application-side lead frame.

[0007] In one implementation, the top layer of the isolation component is provided with a first wire bonding pad from which the control coil is wound and a second wire bonding pad from which the application coil is wound. The control coil is wired to the control chip via the first wire bonding pad, and the application coil is wired to the application chip via the second wire bonding pad. The first wire bonding pad is close to the control lead frame, and the second wire bonding pad is close to the application lead frame.

[0008] In one implementation, the withstand voltage at the nearest point between the first and second wire bonding pads is greater than or equal to the chip's withstand voltage.

[0009] In one implementation, the isolation component comprises, from top to bottom, a first panel, a first thin film layer, a second panel, a second thin film layer, a third thin film layer, a third panel, a fourth thin film layer, a fourth panel, and a bottom film layer; wherein the first thin film layer and the second panel are joined by adhesive, the second thin film layer and the third thin film layer are joined by adhesive, the third panel and the fourth thin film layer are joined by adhesive, and the fourth panel and the bottom film layer are joined by adhesive.

[0010] In one implementation, the control coil is arranged on the second panel, and the application coil is arranged on the third panel.

[0011] In one implementation, the application-side coil is arranged on the second panel, and the control-side coil is arranged on the third panel.

[0012] In one implementation, the first, second, third, and fourth thin film layers are all composed of a polyimide film and copper.

[0013] In one implementation, the polyimide film has a thickness of 150 micrometers, and the adhesive has a thickness of 50 micrometers.

[0014] In one implementation, the bottom film layer is a polyimide film.

[0015] In one implementation, the isolation component is connected between the application-side base island and the control-side base island.

[0016] Compared with the prior art, the present invention has the following beneficial effects: This invention provides a packaging structure for a magnetic isolation chip, comprising: at least one control lead frame, each control lead frame having a control base island, and each control base island having a control chip; at least one application lead frame, each application lead frame having an application base island, and each application base island having an application chip; and an isolation component located between the application base island and the control base island; wherein the isolation component contains a control coil and an application coil for signal transmission, the control coil and the application coil being wired to the control chip and the application chip respectively, and the control chip and the application chip being wired to their respective pins on the control lead frame and the application lead frame respectively. The packaging structure provided by this invention, by moving the isolation component, which plays a voltage withstand role on-chip, to an off-chip design, overcomes the limitation of the on-chip polyimide layer thickness fabrication process (maximum thickness of 40µm, with a maximum voltage withstand of only 16kV), reducing the difficulty and cost of wafer fabrication. The isolation components can be fabricated using commercially available panel (one layer of copper and one layer of polyimide film) or double-sided panels (two layers of copper with a polyimide film sandwiched in between, the polyimide film thickness can be selected in various ways). The polyimide film thickness in its structure can reach 150um, and its dielectric strength is as high as 200V / um, enabling the isolation device to withstand voltages exceeding 16kV and avoiding electrical breakdown. Through a "bridging" process, the control-end chip and the application-end chip are not directly connected, but only connected to the isolation components on the base islands in their respective directions. The distance between the control-end base islands and the application-end base islands can be increased without affecting the wire bonding length, preventing electrical breakdown caused by excessively close base island spacing. In summary, this invention overcomes the limitations of on-chip withstand voltage fabrication processes and improves the high withstand voltage characteristics of magnetically isolated chips. Attached Figure Description

[0017] The accompanying drawings, which are included to provide a further understanding of embodiments of the invention and form part of this application, do not constitute a limitation thereof. In the drawings: Figure 1 A schematic diagram of the breakdown path of the packaging structure provided by the prior art; Figure 2 A schematic diagram of the breakdown path 2 of the packaging structure provided by the prior art; Figure 3 A schematic diagram of the packaging structure of a magnetic isolation chip provided in an embodiment of the present invention; Figure 4This is a schematic diagram of the structure of the isolation component provided in an embodiment of the present invention; Figure 5 A wire bonding diagram illustrating the packaging structure of a magnetic separator chip provided in an embodiment of the present invention; Figure 6 This is a schematic diagram of the lead frame and creepage distance provided in an embodiment of the present invention; Figure 7 A schematic diagram of the breakdown path 1 of the packaging structure of a magnetic barrier chip provided in an embodiment of the present invention; Figure 8 A schematic diagram of the breakdown path 2 of the packaging structure of a magnetic barrier chip provided in an embodiment of the present invention; Figure 9 A schematic diagram of the breakdown path 3 of the packaging structure of a magnetic barrier chip provided in an embodiment of the present invention; Figure 10 A schematic diagram of the breakdown path 1 of the packaging structure provided in an embodiment of the present invention; Figure 11 This is a schematic diagram of the breakdown path 2 of the bottom metal exposed in the molding compound of the packaging structure provided in an embodiment of the present invention; Figure 12 A schematic diagram of the breakdown path 2 of the bottom layer of the encapsulation structure provided in the embodiment of the present invention; Figure 13 A schematic diagram of the breakdown path 3 of the double-sided panel packaging structure provided in the embodiments of the present invention; Figure 14 The diagram shows the breakdown path 3 of the single-sided panel packaging structure provided in the embodiment of the present invention.

[0018] Figure labels and descriptions: 1. Control terminal base island; 2. Application terminal base island; 3. Pin; 4. Connecting rib; 5. Independent pin; 6. Control terminal chip; 7. Application terminal chip; 8. Isolation component; 9a. First wire bonding pad; 9b. Second wire bonding pad. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the embodiments and accompanying drawings. The illustrative embodiments and descriptions of the present invention are only used to explain the present invention and are not intended to limit the present invention.

[0020] It should be noted that the terms "comprising" or "may include" used in the various embodiments of this application indicate the presence of the claimed function, operation, or element, and do not limit the addition of one or more functions, operations, or elements. Furthermore, as used in the various embodiments of this application, the terms "comprising," "having," and their cognates are intended only to indicate a specific feature, number, step, operation, element, component, or combination of the foregoing, and should not be construed as primarily excluding the presence of one or more other features, numbers, steps, operations, elements, components, or combinations of the foregoing, or adding one or more combinations of the foregoing.

[0021] It should be understood that terms such as "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0022] Please refer to Figure 3 , Figure 3 This is a schematic diagram of the packaging structure of a magnetic isolation chip provided in an embodiment of the present invention, as shown below. Figure 3 As shown, the packaging structure includes: At least one control terminal lead frame, each control terminal lead frame is provided with a control terminal base island 1, and each control terminal base island 1 is provided with a control terminal chip 6; At least one application-side lead frame, each application-side lead frame having an application-side base island 2, and each application-side base island 2 having an application-side chip 7; and An isolation component 8 is located between the application-side base island 2 and the control-side base island 1. The isolation component 8 contains a control-side coil and an application-side coil for transmitting signals. The control-side coil and the application-side coil are respectively wired to the control-side chip 6 and the application-side chip 7. The control-side chip 6 and the application-side chip 7 are respectively wired to the pin 3 and the independent pin 5 of the control-side lead frame and the application-side lead frame, respectively.

[0023] In this embodiment, the packaging structure includes at least one control terminal lead frame and at least one application terminal lead frame. Thus, the packaging structure includes at least two independent lead frames. The number of lead frames depends on the number and wiring method of the internally packaged control terminal chip 6 and application terminal chip 7. The base island portion of the independent lead frames serves to mount chips and isolate devices. That is, the control terminal lead frame is equipped with a control terminal base island 1, and the application terminal lead frame is equipped with an application terminal base island 2.

[0024] The final withstand voltage of the magnetically shielded chip depends on the minimum of the withstand voltage values ​​of the external and internal packaging structures. The overall length of the lead frame must be designed to account for the creepage distance after external molding. Figure 6 As shown, it is necessary to ensure that the withstand voltage of the external structure (creep distance * air dielectric strength 1V / um) is greater than or equal to the expected withstand voltage of the chip.

[0025] In some embodiments, the isolation component 8 is sandwiched between the application-side base island 2 and the control-side base island 1.

[0026] Specifically, the lead frames are connected by an isolation component 8 in a "bridging" manner. Since the isolation component 8 has both voltage withstand capability and signal transmission function, signal transmission between the lead frames is achieved. This embodiment utilizes a "bridging" method, placing the isolation component 8 between two independent base islands. The control chip 6 and the application chip 7 are connected through the isolation component 8, resulting in a more flexible and versatile structure: based on a unified chip manufacturing process, independent isolation components 8 and diverse packages can be designed according to voltage withstand requirements.

[0027] like Figure 5 As shown, the isolation component 8 includes a control coil and an application coil for signal transmission. By design, the control coil and application coil can be led to the first wire bonding pad 9a and the second wire bonding pad 9b on both sides of the top layer of the isolation component 8 via blind vias / through-holes and metal wires. The first and second wire bonding pads 9a and 9b are used for wire bonding to the control chip 6 and the application chip 7, respectively. The control chip 6 and the application chip 7 are then wire bonded to the pins 3 and 5 of their respective lead frames, respectively, achieving signal transmission and isolation withstand voltage from the control end to the application end. The first wire bonding pad 9a is close to the control end lead frame, and the second wire bonding pad 9b is close to the application end lead frame.

[0028] At once Figure 3 The internal framework of the package includes independent control base island 1 and application base island 2, pins 3 and connecting ribs 4 supporting the base islands, and multiple independent pins 5 for wiring. The independent base islands respectively house the control chip 6 and the application chip 7. The isolation component 8 is located between the gaps of the two independent base islands. The first wire bonding pad 9a and the second wire bonding pad 9b of the top metal of the isolation component 8 are respectively placed on the two base islands. The two base islands provide support to facilitate the wire bonding of the control chip 6 and the application chip 7 on the isolation component 8, completing the signal transmission from the control end to the application end.

[0029] Wire bonding refers to the process of using metal wires (gold wire, palladium-copper wire, etc.) and employing heat pressing or ultrasonic energy to complete the interconnection of solid-state circuits in microelectronic devices, that is, the connection between the chip and the circuit or lead frame.

[0030] Overall, the isolation component 8 is composed of four panels spliced ​​together, with the panels joined by a high dielectric strength adhesive (110V / um) to ensure the overall durability of the isolation component 8.

[0031] like Figure 4 As shown, Figure 4 This is a schematic diagram of the structure of the isolation component 8 provided in an embodiment of the present invention. The isolation component 8, from top to bottom, includes a first panel, a first thin film layer, a second panel, a second thin film layer, a third thin film layer, a third panel, a fourth thin film layer, a fourth panel, and a bottom film layer. The first thin film layer and the second panel are joined by adhesive, the second thin film layer and the third thin film layer are joined by adhesive, the third panel and the fourth thin film layer are joined by adhesive, and the fourth panel and the bottom film layer are joined by adhesive. The first, second, third, and fourth thin film layers are all composed of polyimide film and copper.

[0032] The control coil and the application coil are located on the second and third panels, respectively. The first and fourth panels are for the coils to be wound to the wire bonding pads on both sides of the top layer, facilitating wire bonding to the chip and achieving signal transmission. Figure 5 The wiring method shown.

[0033] The isolation component 8 primarily serves a voltage withstand function. Its voltage withstand structure is located between the control coil and the application coil using a polyimide film. The voltage withstand value depends on the thickness of the polyimide film and the dielectric strength of the substrate used. For optimization, the polyimide film can be selected from commercially available and technologically mature finished products spliced ​​together to achieve the required thickness. Polyimide film is a conventional encapsulation material in this technical field, and will not be described further in this embodiment. This invention separates the isolation component 8, which realizes signal transmission and voltage withstand functions, from the on-chip structure, simplifying the wafer fabrication process and saving manufacturing costs.

[0034] There are three potential electrical breakdown paths in the structure of the isolation component 8 provided in this embodiment of the invention, and measures need to be taken at these three locations to enhance the withstand voltage standard: (1) For example Figure 7As shown, inside the magnetic isolation chip, the top metal structure of the isolation component 8 is exposed to a molding compound (because the top metal structure requires wire bonding). Therefore, if the first wire bonding pad 9a at the center of the top metal is too close to the second wire bonding pad 9b on the side of the top metal, the molding compound will break down. Thus, in some embodiments, the withstand voltage at the closest point between the first wire bonding pad 9a and the second wire bonding pad 9b is greater than or equal to the chip's withstand voltage. Specifically, when the control terminal structure and the application terminal structure are located in an environment with low dielectric strength (such as being exposed in molding compound with a dielectric strength of 20V / µm, which is 1 / 10 of that of polyimide film), the distance multiplied by the dielectric strength should be greater than or equal to the expected chip withstand voltage to avoid electrical breakdown.

[0035] (2) For example Figure 8 As shown, the lateral distance from the PAD (application-side structure) at the center of the bottom metal of the isolation component 8 to the base island 1 of the control end is such that, to prevent molded material breakdown (due to the bridging process, the suspended length of the isolation device cannot be too long, otherwise it will collapse, so the distance from the PAD at the center of the bottom metal of the isolation component 8 to the base island 1 of the control end should not exceed 1.5mm, but the withstand voltage will be limited to within 30kV), a layer of polyimide cover film is spliced ​​onto the bottom of the isolation component 8 with high dielectric strength adhesive, thus increasing the longitudinal distance between the two (the thickness of the polyimide cover film + the thickness of the adhesive). The withstand voltage value determined by the structure of the above-mentioned isolation component 8 after adding the bottom cover film is: polyimide bottom film thickness * polyimide cover film dielectric strength + adhesive thickness * adhesive dielectric strength + lateral distance * molded material dielectric strength, and its withstand voltage value is much greater than lateral distance * molded material dielectric strength.

[0036] (3) For example Figure 9 As shown, since the panels are generally single-sided or double-sided (single-sided panels consist of one layer of copper and one layer of polyimide film, while double-sided panels consist of two layers of copper with a polyimide film sandwiched in between), the maximum thickness of the polyimide film is 150µm. To increase the vertical spacing between the control coil and the application coil, and to overcome the limitations of the common thickness of the board material, this invention uses two single-sided panels, with one side of the polyimide film joined by a high-dielectric-strength adhesive. Therefore, the overall vertical spacing can reach 350µm (two 150µm polyimide films + 50µm adhesive). Since the high-dielectric-strength adhesive has lower dielectric strength than the polyimide film, the weak distance at which electrical breakdown is likely to occur in this structure is: the thickness of a single polyimide film + the distance from the outermost part of the second metal coil structure (control end) to the through hole (application end).

[0037] Based on the design described in this embodiment, the thickness of the polyimide film between the isolation components 8 can be flexibly selected and designed according to the pressure resistance requirements, thereby solving the limitations of the in-sheet polyimide layer thickness manufacturing process.

[0038] like Figure 4 As shown, the control coil is arranged on the second panel, and the application coil is arranged on the third panel.

[0039] refer to Figure 4 Using the same principle, the application coil can be placed on the second panel, and the control coil can be placed on the third panel.

[0040] Based on the packaging structure described above, this embodiment uses an ultra-wide body 36 package as an example to more accurately describe how to design the package structure parameters to meet the high voltage withstand requirements of the chip. It should be noted that the chip's voltage withstand value depends on both the external and internal voltage withstand of the package structure. The external voltage withstand of the package structure depends on the shortest distance from the control pin 35a (the part exposed to the air environment) along the surface of the molded package to the application pin 35b (the part exposed to the air environment). This shortest distance should be designed to be as far as possible within the limits of manufacturing process and acceptable cost. In this embodiment, the expected minimum voltage withstand value of the magnetically shielded chip is 30kV. Based on the air dielectric strength of 1V / µm, this minimum distance is not less than 30mm. Considering some unforeseen factors, such as the lower air dielectric strength in humid environments, in this embodiment, the overall lateral length of the lead frame is 32.5mm, and the estimated voltage withstand of the external package structure is >32.5kV.

[0041] The internal withstand voltage of the package structure depends on the shortest distance between the control end structure and the application end structure. A high dielectric strength material is used at the shortest distance structure to prevent breakdown between the control end and the application end.

[0042] In this embodiment, since the control chip 6 and the application chip 7 are not directly connected (they are far apart), they are connected by an isolation component 8 between independent base islands to complete signal transmission. Therefore, the closest distance between the control structure and the application structure exists in the isolation component 8.

[0043] In isolation component 8, there are three distances where withstand voltage needs to be considered, and withstand voltage measures should be taken at these three paths: 1. For example Figure 10As shown, inside the chip, the top metal structure of the isolation device is exposed to molding compound (because the top metal structure needs to be wire bonded). Therefore, if the distance between the center PAD (control end structure) and the side PAD (application end structure) of the top metal is too close, it will cause the molding compound to break down. Considering that the isolation component 8 adopts a "bridging" process with a suspended middle, the suspended size cannot be very large. Therefore, in this embodiment, based on process experience, the length of the isolation chip is limited to 4.55mm (designed for a base island spacing of 3mm). This allows the distance between the first wire bonding pad 9a at the center of the top metal and the second wire bonding pad 9b on the side of the top metal to reach 1.65mm. According to the withstand voltage calculation formula, the withstand voltage value at this distance is 33kV, which meets the expected withstand voltage of the chip's internal structure.

[0044] 2. For example Figure 11 As shown, to prevent breakdown between the bottom metal center pad (application / control structure) of the isolation component 8 and the lateral distance between the control base island 1 / application base island 2 (if the bottom of the isolation component 8 does not have a base film layer, the path between the lower metal and the control base island 1 will be exposed in the molding compound), as... Figure 12 As shown, the bottom of the isolation component 8 will be further bonded with a polyimide cover film (i.e., a bottom film layer) using a high dielectric strength adhesive. In this embodiment, a 125µm thick polyimide film is used as the bottom film, bonded with a 100µm high dielectric strength adhesive. This significantly increases the chance of... Figure 11 The withstand pressure value determined by path 2 shown.

[0045] 3. For example Figure 14 As shown, in this embodiment, to enhance the withstand voltage distance between the control coil and the application coil in the vertical direction, and without being limited by the thickness of the polyimide film in the double-sided board, two single-sided boards (each with a polyimide film thickness of 150µm) are spliced ​​together using a 50µm thick high-dielectric-strength adhesive. Compared to... Figure 13 For double-sided boards, the withstand voltage distance between the control coil and the application coil is increased, thereby increasing the withstand voltage value between the two.

[0046] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A packaging structure for a magnetic isolation chip, characterized in that, include: At least one control terminal lead frame, each control terminal lead frame is provided with a control terminal base island, and each control terminal base island is provided with a control terminal chip; At least one application-side lead frame, each application-side lead frame having an application-side base island, and each application-side base island having an application-side chip; and An isolation component is located between the application-side base island and the control-side base island; wherein, the isolation component is provided with a control-side coil and an application-side coil for transmitting signals, the control-side coil and the application-side coil are respectively wired to the control-side chip and the application-side chip, and the control-side chip and the application-side chip are respectively wired to the pins of the control-side lead frame and the application-side lead frame.

2. The packaging structure of a magnetic isolation chip according to claim 1, characterized in that, The top layer of the isolation component is provided with a first wire bonding pad from which the control coil is wound and a second wire bonding pad from which the application coil is wound. The control coil is wired to the control chip via the first wire bonding pad, and the application coil is wired to the application chip via the second wire bonding pad. The first wire bonding pad is close to the control lead frame, and the second wire bonding pad is close to the application lead frame.

3. The packaging structure of a magnetic isolation chip according to claim 2, characterized in that, The withstand voltage at the closest position between the first and second wire bonding pads is greater than or equal to the chip's withstand voltage.

4. The packaging structure of a magnetic isolation chip according to claim 1, characterized in that, The isolation component comprises, from top to bottom, a first panel, a first thin film layer, a second panel, a second thin film layer, a third thin film layer, a third panel, a fourth thin film layer, a fourth panel, and a bottom film layer; wherein, the first thin film layer and the second panel are joined by adhesive, the second thin film layer and the third thin film layer are joined by adhesive, the third panel and the fourth thin film layer are joined by adhesive, and the fourth panel and the bottom film layer are joined by adhesive.

5. The packaging structure of a magnetic isolation chip according to claim 4, characterized in that, The control coil is arranged on the second panel, and the application coil is arranged on the third panel.

6. The packaging structure of a magnetic isolation chip according to claim 4, characterized in that, The application-side coil is arranged on the second panel, and the control-side coil is arranged on the third panel.

7. The packaging structure of a magnetic isolation chip according to claim 4, characterized in that, The first, second, third, and fourth thin film layers are all composed of polyimide film and copper.

8. The packaging structure of a magnetic isolation chip according to claim 7, characterized in that, The polyimide film has a thickness of 150 micrometers, and the adhesive has a thickness of 50 micrometers.

9. The packaging structure of a magnetic isolation chip according to claim 4, characterized in that, The bottom film layer is a polyimide film.

10. The packaging structure of a magnetic isolation chip according to claim 1, characterized in that, The isolation component is connected between the application-side base island and the control-side base island.

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