Bidirectional switch MOSFET device and manufacturing method thereof

Abstract

The invention belongs to the technical field of semiconductors, and particularly relates to a bidirectional switch MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) device and a manufacturing method thereof. The device is provided with two drain electrodes, in a bidirectional conduction mode, enough driving voltage is applied to grid electrodes of two MOSFETs at the same time, a channel at the bottom of a groove is formed, one drain electrode is connected with a high potential, the other drain electrode is connected with a low potential, and electrons start from one drain electrode, flow through an N well, a channel region and an N well region on the other side of the groove and finally return to the other drain electrode. Reverse opening only needs reverse connection of two drain electrode potentials, and an electron flowing path is opposite to a forward direction. In the bidirectional blocking mode, low level is applied to the grids of the two MOSFETs, no channel is formed, the directions of body diodes of the two MOSFETs are opposite, current cannot be conducted, and a bidirectional blocking state is formed. According to the invention, the requirement of a bidirectional switch is met, the on-resistance is relatively small, and the application range and the integration level of the device are widened.

Description

TECHNICAL FIELD

[0001] The present application belongs to the field of semiconductor technology, and particularly relates to a bidirectional switch MOSFET device and a manufacturing method thereof. BACKGROUND

[0002] When charging the battery, it is necessary to ensure that the battery is fully charged and not overcharged. Overcharging can cause the voltage drop across the battery to rise, the battery to deform and leak, and the performance of the battery to be significantly reduced and damaged. When discharging, the voltage slowly decreases, and when the voltage decreases to a certain value, the discharging should be stopped. If the discharging continues, the active material of the electrode will be damaged, and the service life of the battery will be shortened. The traditional solution to this bidirectional control of current flow is to use a pair of back-to-back series MOSFETs to realize bidirectional conduction and blocking. The structure is shown in Figure 1 The two MOSFET drains are connected, and in the bidirectional conduction mode, the gates of the two MOSFETs are simultaneously applied with sufficient driving voltage, the channels are opened, and both enter the conduction state. The forward current flows from the source to the drain of MOSFET1, and the body diode of MOSFET2 can also be conductive to allow current to flow. The reverse current is exactly opposite to the path of the forward current. In the bidirectional blocking mode, the gates of the two MOSFETs are both low, no channel is formed, and the body diodes of the two MOSFETs are in opposite directions, so that the current cannot be conducted, forming a bidirectional blocking state. The MOS circuit described above can meet the demand of bidirectional switch, but the on-resistance and power consumption are still large, and some unconventional measures to reduce the substrate resistance often have high process difficulty and cost. SUMMARY

[0003] In view of the above problems, a bidirectional switch MOSFET device and a manufacturing method thereof are provided.

[0004] The technical scheme is as follows:

[0005] A bidirectional switch MOSFET device, as shown in Figure 2As shown, it comprises back metal 1, P-type substrate 2, P-type epitaxial layer 3, first oxide layer 9, second oxide layer 12 which are sequentially stacked from bottom to top along the vertical direction of the device; N-type well region 4 is in P-type epitaxial layer 3, the upper surface of P-type epitaxial layer 3 and the upper surface of N-type well region 4 are flush, P-type epitaxial layer 3 completely covers the side surface of N-type well region 4; a plurality of trenches are in N-type well region 4, which are sequentially and side by side arranged along the horizontal direction of the device, the top of the trench is in contact with the bottom of the first oxide layer 9, the bottom of the trench extends into the P-type epitaxial layer 3, the part of the trench extending into the P-type epitaxial layer 3 is covered by P-type well region 15, thick field oxide layer 7 is on the inner wall of the trench, first polysilicon 6 and second polysilicon 8 are in thick field oxide layer 7, in the vertical direction of the device, second polysilicon 8 is above first polysilicon 6, second polysilicon 8 and first polysilicon 6 are separated by thick field oxide layer 7; part of first polysilicon 6 is in N-type well region 4, and the other part is in P-type epitaxial layer 3; peripheral well region 14 formed by multi-step implantation of P-type impurities is in P-type epitaxial layer 3 on both sides of N-type well region 4, the upper surface of peripheral well region 14 is in contact with first oxide layer 9, the lower surface of peripheral well region 14 has a lower junction depth than that of N-type well region 4, and there is a spacing between peripheral well region 14 and N-type well region 4;

[0006] In first oxide layer 9 and second oxide layer 12, metal layer 10 is discontinuously arranged, and the specific arrangement is as follows: in first oxide layer 9, the part connected with peripheral well region 14 and the part connected with N-type well region 4 between every two adjacent trenches in N-type well region 4 all have metal layer 10, metal layer 10 penetrates first oxide layer 9 and is connected with peripheral well region 14 and N-type well region 4, at the same time, metal layer 10 extends upward in the vertical direction into second oxide layer 12, the transverse width of the part of metal layer 10 in second oxide layer 12 is greater than that in first oxide layer 9, and the transverse width of the metal layer 10 connected with peripheral well region 14 is greater than that of the other metal layers 10; and the vertical thickness of the part of metal layer 10 in second oxide layer 12 is half of the vertical thickness of second oxide layer 12, and it is in contact with the upper surface of first oxide layer 9; selectively, the part of metal layer 10 in second oxide layer 12 continues to extend in the vertical direction and penetrates second oxide layer 12, the selection is that one metal layer 10 connected with peripheral well region 14 is selected every one metal layer 10 connected with N-type well region 4, and the extension is that the same transverse width as that of the metal layer 10 in first oxide layer 9 is adopted for extension, and the part extending in the vertical direction is directly above the metal layer 10 in first oxide layer 9;

[0007] A passivation layer 13 is formed on the surface of the second oxide layer 12, and the passivation layer 13 is etched to form four windows, two of which are directly above the peripheral well region 14 and have the same lateral width as the metal layer 10 directly below, and the device substrate 11 is arranged in the two windows; the other two windows are directly above the N-type well region 4, and the first drain 16 and the second drain 17 of the device are arranged in the two windows respectively.

[0008] Further, the thickness of the P-type epitaxial layer 3 is 1um-15um, and the resistivity is 1mR·cm - 10mR·cm; the depth of the trench is 1um-10um.

[0009] A manufacturing method of a bidirectional switch MOSFET device, comprising the following steps:

[0010] First step: preparing a P-type substrate 2;

[0011] Second step: depositing a P-type epitaxial layer 3 above the P-type substrate 2;

[0012] Third step: depositing thick field oxide above the P-type epitaxial layer 3, and then etching away part of the region oxide layer;

[0013] Fourth step: forming an N-type well region 4 in the P-type epitaxial layer 3 by ion implantation in the region of the etched oxide layer, and then removing the thick field oxide by etching;

[0014] Fifth step: depositing an oxide layer, and then etching away part of the region oxide layer;

[0015] Sixth step: forming a plurality of trenches in the N-type well region 4 by etching after etching the oxide layer, and high-temperature annealing to grow a thin oxide layer as a mask layer for the next step of trench bottom implantation;

[0016] Seventh step: forming a P-type well region 15 by P-type impurity implantation at the bottom of the trench;

[0017] Eighth step: high-temperature growth of a sacrificial oxide layer, and then removing the oxide layer;

[0018] Ninth step: high-temperature growth of a gate oxide layer 5 in the trench;

[0019] Tenth step: depositing polysilicon in the trench and then etching to form a gate polysilicon 6, and then high-temperature annealing;

[0020] Eleventh step: high-temperature growth of a thick field oxide layer 7 in the trench;

[0021] Twelfth step: depositing polysilicon in the trench and then etching to form a gate polysilicon 8, and then high-temperature annealing;

[0022] Thirteenth step: depositing an oxide layer 9 on the surface of the device and etching all the contact hole windows;

[0023] Fourteenth step: expose all the oxide layer except the hole above the well 14 by photoetching with photoresist as a mask, then etch, N-type ion implantation, remove photoresist, and anneal.

[0024] Fifteenth step: expose the oxide layer of the hole above the well 14 by photoetching with photoresist as a mask, then etch, multi-step P-type ion implantation, remove photoresist, and anneal to obtain the peripheral well area 14;

[0025] Sixteenth step: fill the metal in the window etched in the oxide layer 9 to obtain the metal layer 10;

[0026] Seventeenth step: deposit the oxide layer 12 on the oxide layer 9, and etch the required window in the oxide layer 12;

[0027] Eighteenth step: fill the metal in the window etched in the oxide layer 12 to connect with the metal layer 10 in the oxide layer 9 to obtain the new metal layer 10;

[0028] Nineteenth step: deposit the passivation layer 13 on the surface of the oxide layer 12, and etch the required window of the device substrate and the device drain in the passivation layer 13;

[0029] Twentieth step: thin the P-type substrate 2 from the back, and deposit the back metal 1.

[0030] Up to now, the wafer process is completed, and then the related process of CSP packaging is performed.

[0031] The application has the advantages of meeting the demand of bidirectional switch and having relatively small conduction resistance, and widening the application range and integration of the device. BRIEF DESCRIPTION OF DRAWINGS

[0032] Figure 1 is an equivalent circuit diagram of two MOSFETs back-to-back in series to form a bidirectional switch structure;

[0033] Figure 2 is a longitudinal sectional structure schematic diagram of the application;

[0034] Figure 3 is a breakdown voltage curve of the N30V example;

[0035] Figure 4 is a threshold voltage curve of the N30V example;

[0036] Figure 5 is two kinds of lead-out modes of the drain 1 and the drain 2 of the N30V example;

[0037] Figures 6 to 23 is a simple process flow diagram of the N30V example. DETAILED DESCRIPTION

[0038] The technical method of the present application is described in detail below with reference to the accompanying drawings.

[0039] The present application provides a bidirectional switch MOSFET device, the structural schematic diagram is as shown in Figure 2 , which solves the problem of limiting the application range of the conventional scheme by adopting a pair of independent MOSFET devices in back-to-back series. The main method is as follows: the required bidirectional switch function is realized in one device by adopting a new structure, and the present application comprises a back metal 1, a P-type substrate 2, a P-type epitaxial layer 3 arranged on the upper surface of the P-type substrate 2, an N-type well region 4 arranged on the P-type epitaxial layer 3, and a trench etched in the inside and edge of the N-type well region 4; a P-type well region 15 is arranged at the bottom of the trench for forming a channel region; a gate oxide 5 is grown at the bottom of the trench by high temperature, a polysilicon 6 is deposited above the gate oxide 5 for connecting a gate electrode, a thick field oxide 7 is grown above the polysilicon 6 by high temperature for isolating the polysilicon 6 and a polysilicon 8; the polysilicon 8 is arranged above the polysilicon 6 for connecting the gate electrode; an oxide layer 9 is deposited above the trench for electrical isolation, a metal 10 is deposited above the oxide layer 9 for leading out a drain electrode; an oxide layer 12 is deposited above the metal 10; a metal 11 is deposited above the oxide layer 12 for connecting a substrate electrode, a metal 16 is deposited for connecting a drain electrode 1, a metal 17 is deposited for connecting a drain electrode 2, and a passivation layer 13 is deposited above the metal 11. Then, the passivation layer is etched to form a matrix window, a copper RDL process is deposited, a PI layer, a UBM layer, a tin BALL, a TEST, a chip thinning BG, and a coating on the back of the chip are deposited, and finally the overall thickness meets the design target.

[0040] The working principle of the present application is as follows: in the bidirectional conduction mode, a sufficient driving voltage is applied to the gates of the two MOSFETs at the same time, a channel is formed at the bottom of the trench, the drain electrode 1 is connected to a high potential, the drain electrode 2 is connected to a low potential, and the electrons flow from the drain electrode 1, pass through the N well 4, the channel region, the N well region on the other side of the trench, and finally return to the drain electrode 2. The reverse opening only needs to reverse the potentials of the drain electrode 1 and the drain electrode 2, and the electrons flow through a path opposite to that in the forward direction. In the bidirectional blocking mode, low-level voltages are applied to the gates of the two MOSFETs, no channel is formed, and the body diodes of the two MOSFETs are in opposite directions, so that the current cannot be conducted, and a bidirectional blocking state is formed.

[0041] Examples:

[0042] For example, the N30V bidirectional switch is as shown in Figure 3 The breakdown voltage curve of the N30V product is as shown in Figure 4 The threshold voltage curve of the N30V product is as shown in Figures 6 to 23 The manufacturing process of the N30V product is as shown in

[0043] First step: preparing a P-type substrate 2;

[0044] Second step: depositing a P-type epitaxial layer 3 above the P-type substrate 2;

[0045] Third step: Grow thick field oxide on P-type epitaxial layer 3, then perform active region lithography and etch away part of the oxide layer;

[0046] Fourth step: N-well region 4 multi-step ion implantation, no annealing, remove field oxide;

[0047] Fifth step: Deposit oxide layer, then trench layer lithography, etch away part of the oxide layer;

[0048] Sixth step: Etch silicon to form trench, etch depth 1um-10um, then high temperature annealing to grow thin oxide layer for masking;

[0049] Seventh step: Trench bottom implantation of P-type impurities to form P-type well region 15;

[0050] Eighth step: High temperature growth of sacrificial oxide layer, remove sacrificial oxide layer;

[0051] Ninth step: High temperature growth of gate oxide layer 5, thickness 200A-800A;

[0052] Tenth step: Trench bottom gate polysilicon deposition and etching to a certain depth to form gate polysilicon 6, then high temperature annealing, oxide layer etching to remove oxide layer on trench sidewall;

[0053] Eleventh step: High temperature growth of thick field oxide 7;

[0054] Twelfth step: Deposition of polysilicon and etching to form gate polysilicon 8, then high temperature annealing;

[0055] Thirteenth step: Deposition of oxide layer 9 and hole lithography, then etching;

[0056] Fourteenth step: Through lithography, use photoresist as a masking layer to expose all hole regions of the oxide layer except the hole above well 14, then etching, N-type implantation, photoresist removal, and annealing;

[0057] Fifteenth step: Through lithography, use photoresist as a masking layer to expose only the hole region of the oxide layer above well 14, then etching, multi-step P-type ion implantation, photoresist removal, and annealing to obtain peripheral well region 14;

[0058] Sixteenth step: Lower hole region metal 10 filling, connecting gate polysilicon of each strip-shaped trench, N-well periphery substrate, and drain 1 and drain 2 of each strip-shaped trench on both sides of the mesa region;

[0059] Seventeenth step: Deposition of oxide layer 12 and etching;

[0060] Eighteenth step: Upper hole region metal 11 filling and etching, connecting all gate polysilicon, all substrates, all drain 1, and all drain 2. Another connection method of drain 1 and drain 2 is shown inFigure 5 ;

[0061] Nineteenth step: after the deposition of the passivation layer 13, a small window matrix is etched;

[0062] Twentieth step: the copper RDL process, PI layer, UBM layer, tin BALL, TEST, chip thinning BG, and chip back coating are deposited, and the final overall thickness meets the design target;

[0063] Twenty-first step: scribing, testing, printing, and banding.

Claims

1. A bidirectional switching MOSFET device, characterized in that, The device comprises a back metal (1), a P-type substrate (2), a P-type epitaxial layer (3), a first oxide layer (9), and a second oxide layer (12) stacked sequentially from bottom to top along the vertical direction of the device. The P-type epitaxial layer (3) contains an N-type well region (4), with the upper surface of the P-type epitaxial layer (3) flush with the upper surface of the N-type well region (4). The P-type epitaxial layer (3) completely covers the sidewalls of the N-type well region (4). The N-type well region (4) contains multiple trenches arranged in parallel along the horizontal direction of the device. The top of the trenches contacts the bottom of the first oxide layer (9), and the bottom of the trenches extends into the P-type epitaxial layer (3). The portion of the trenches extending into the P-type epitaxial layer (3) is covered by the P-type well region (15). A thick field oxide layer (7) is present on the inner wall of the trenches. The thick field oxide layer (7) contains a first polysilicon (6) and a second polysilicon (8). In the vertical direction of the device, the second polysilicon (8) is located above the first polysilicon (6), and the second polysilicon (8) and the first polysilicon (6) are separated by the thick field oxide layer (7). The first polysilicon (6) is partially located in the N-type well region (4), and the other part is located in the P-type epitaxial layer (3). The P-type epitaxial layer (3) on both sides of the N-type well region (4) contains a peripheral well region (14) formed by multi-step implantation of P-type impurities. The upper surface of the peripheral well region (14) is in contact with the first oxide layer (9), and the junction depth of the lower surface of the peripheral well region (14) is lower than the junction depth of the N-type well region (4). There is a gap between the peripheral well region (14) and the N-type well region (4). In the first oxide layer (9) and the second oxide layer (12), there are intermittently arranged metal layers (10). Specifically, in the first oxide layer (9), the portion connected to the outer well region (14) and the portion connected to the N-type well region (4) between every two adjacent trenches in the N-type well region (4) both have metal layers (10). The metal layers (10) penetrate the first oxide layer (9) and are connected to the outer well region (14) and the N-type well region (4). At the same time, the metal layers (10) extend vertically upward into the second oxide layer (12). The lateral width of the portion of the metal layer (10) in the second oxide layer (12) is greater than that in the portion in the first oxide layer (9). The lateral width of the metal layer (10) connected to the outer well region (14) is greater than that in the second oxide layer (12). His metal layer (10); and the vertical thickness of the portion of the metal layer (10) in the second oxide layer (12) is half the vertical thickness of the second oxide layer (12), while contacting the upper surface of the first oxide layer (9); the portion of the metal layer (10) in the second oxide layer (12) selectively continues to extend vertically and penetrates the second oxide layer (12), selectively meaning that the metal layer (10) connected to the peripheral well region (14) is selected, and the metal layer (10) connected to the N-type well region (4) is selected one at a time, and the extension method is to extend with the same lateral width as the metal layer (10) in the first oxide layer (9), and the portion extending vertically is located directly above the metal layer (10) in the first oxide layer (9); A passivation layer (13) is provided on the upper surface of the second oxide layer (12). The passivation layer (13) is etched with four windows, two of which are located directly above the peripheral well region (14), and the lateral width of these two windows is consistent with the lateral width of the metal layer (10) directly below it. The device substrate (11) is disposed in these two windows. The other two windows are located directly above the N-type well region (4), and the first drain (16) and the second drain (17) of the device are disposed in these two windows respectively.

2. The bidirectional switching MOSFET device according to claim 1, characterized in that, The thickness of the P-type epitaxial layer (3) is 1um-15um, and the resistivity is 1mR·cm - 10mR·cm; the depth of the trench is 1um-10um.

3. A method for manufacturing a bidirectional switching MOSFET device as described in claim 1, characterized in that, Includes the following steps: Step 1: Prepare a P-type substrate (2); Step 2: Deposit a P-type epitaxial layer (3) on top of the P-type substrate (2); Step 3: Deposit a thick field oxygen layer on top of the P-type epitaxial layer (3), and then etch away part of the oxide layer; Step 4: By ion implantation, an N-type well region (4) is formed in the P-type epitaxial layer (3) where the oxide layer region is etched away, and the thick field oxygen is removed by etching; Step 5: Deposit an oxide layer, then etch away a portion of the oxide layer; Step 6: In the N-type well region (4) where the oxide layer has been etched away, multiple trenches are formed by etching, and a thin oxide layer is grown by high-temperature annealing; Step 7: Inject P-type impurities into the bottom of the trench to form a P-type well region (15); Step 8: High-temperature growth of a sacrificial oxide layer, followed by removal of the oxide layer; Step 9: High-temperature growth of the gate oxide layer in the trench (5); Step 10: After depositing polysilicon in the trench, etch to form gate polysilicon (6), followed by high-temperature annealing; Step 11: High-temperature growth of a thick field oxygen layer in the trench (7); Step 12: After depositing polysilicon in the trench, etch to form gate polysilicon (8), followed by high-temperature annealing; Step 13: Deposit an oxide layer (9) on the device surface and etch out the required window; Step 14: Using photoresist as a masking layer, expose the oxide layer of all hole areas except the hole above well 14, followed by etching, N-type implantation, resist removal, and annealing; Step 15: Using photoresist as a masking layer, only the oxide layer of the hole region above the well 14 is exposed. Then, etching, multi-step P-type ion implantation, resist removal, and annealing are performed to obtain the outer well region 14. Step 16: Fill the etched window in the oxide layer (9) with metal to obtain the metal layer (10); Step 17: Deposit oxide layer (12) on oxide layer (9) and etch the required window in oxide layer (12); Step 18: Fill the window etched in the oxide layer (12) with metal and connect it with the metal layer (10) in the oxide layer (9) to obtain a new metal layer (10). Step 19: Deposit a passivation layer (13) on the upper surface of the oxide layer (12), and etch out the required window for the device substrate and the device drain on the passivation layer (13); Step 20: Thin the P-type substrate (2) from the back side and deposit the back side metal (1).

Images