Silicon wafer and processing method thereof, solar cell and photovoltaic module

Abstract

The invention provides a silicon wafer and a processing method thereof, a solar cell and a photovoltaic module. The silicon wafer processing method comprises the steps that a to-be-processed silicon wafer is provided, the surface of the to-be-processed silicon wafer is provided with a plurality of line mark grooves, and each line mark groove comprises a bottom wall and a side wall; identifying the surface of the to-be-processed silicon wafer to obtain a first area and a second area, the first area comprising a bottom wall and a part of side wall close to the bottom wall, and the second area comprising a plane area between the line mark grooves and the other part of side wall close to the plane area; the second area is subjected to laser etching, the height difference between the surface and the bottom wall of the etched plane area is smaller than or equal to 0.5 micrometer, and an etched silicon wafer is obtained; and carrying out alkali liquor polishing on the etched silicon wafer to obtain a target silicon wafer. By performing laser etching on the specific area of the to-be-processed silicon wafer, namely etching the bulge opposite to the bottom wall of the line mark groove in the surface of the to-be-processed silicon wafer, the height difference of the uneven part of the surface of the silicon wafer is reduced, and the flatness of the surface of the silicon wafer is further improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of solar cells, in particular to a silicon wafer, a processing method thereof, a solar cell and a photovoltaic module. BACKGROUND

[0002] The perovskite / crystalline silicon stacked cell is a structure in which a crystalline silicon solar cell and a perovskite solar cell are stacked together. Through complementary advantages and synergistic effects, the conversion efficiency is improved. On the one hand, the crystalline silicon solar cell can absorb part of the visible light spectrum, while the perovskite solar cell can absorb visible and near-infrared light spectrum. The two cell layers are stacked together to more fully utilize each band of the solar spectrum, achieving spectral complementation. On the other hand, the crystalline silicon solar cell has high electron collection efficiency, and the perovskite cell has high photoelectric conversion efficiency. The two cell layers are stacked together to fully utilize light absorption and electron transport, achieving effect complementation and thus improving overall performance. However, the surface of the crystalline silicon bottom cell is uneven, for example, the surface has obvious lines, which causes the top cell film to be discontinuous, directly affecting the deposition of the top cell film and the overall efficiency of the stacked cell. SUMMARY

[0003] The present application aims to at least partially solve one of the problems in the related art. To this end, one object of the present application is to provide a method for processing a silicon wafer.

[0004] In one aspect of the present application, a method for processing a silicon wafer is provided. According to an embodiment of the present application, the method for processing a silicon wafer comprises: providing a silicon wafer to be processed, the surface of the silicon wafer to be processed having a plurality of line groove, the line groove comprising a bottom wall and a side wall; identifying the surface of the silicon wafer to be processed to obtain a first region and a second region, the first region comprising the bottom wall and a part of the side wall close to the bottom wall, and the second region comprising a planar region between the line grooves and another part of the side wall close to the planar region; laser etching the second region, the height difference between the surface of the etched planar region and the bottom wall being less than or equal to 0.5 μm, to obtain an etched silicon wafer; and alkali polishing the etched silicon wafer to obtain a target silicon wafer. Thus, by laser etching a specific region of the silicon wafer to be processed, i.e. etching the protrusions on the surface of the silicon wafer to be processed opposite the bottom wall of the line groove, the height difference of the uneven surface of the silicon wafer is reduced (less than or equal to 0.5 μm), and the flatness of the surface of the silicon wafer is improved.

[0005] According to an embodiment of the present application, the height difference between the surface of the etched planar region and the bottom wall is less than or equal to 0.3 μm.

[0006] According to an embodiment of the present application, the identification is performed by an image acquisition method.

[0007] According to an embodiment of the present application, the conditions of the laser etching include at least one of the following: the direction of the laser etching is parallel to the line scratch groove; the wavelength of the laser is 532 nm; the frequency of the laser is 300-600 kHz; the power of the laser is 15-30 W; the pulse span of the laser is 15-25 ps; and the spot size of the laser is 20-50 μm.

[0008] According to an embodiment of the present application, the plurality of line scratch grooves on the surface of the silicon wafer to be processed are regularly arranged.

[0009] According to an embodiment of the present application, the conditions of the alkali solution polishing include: the mass concentration of alkali in the alkali solution is 1.5%-3%; the temperature of the alkali solution is 60-75 °C; and the time of the alkali solution polishing is 250-400 s.

[0010] In another aspect of the present application, the present application provides a silicon wafer. According to an embodiment of the present application, the silicon wafer is obtained by using the method for processing a silicon wafer as described above. Thus, the surface of the silicon wafer has a better flatness, thereby ensuring the continuous film-forming property of the film layer deposited thereon and ensuring the good working performance of the film layer. It can be understood by those skilled in the art that the silicon wafer has all the features and advantages of the method for processing a silicon wafer as described above, which will not be described in more details herein.

[0011] In yet another aspect of the present application, the present application provides a solar cell. According to an embodiment of the present application, the solar cell comprises the silicon wafer as described above. Thus, the solar cell has a better cell efficiency.

[0012] According to an embodiment of the present application, the solar cell is a single-crystal silicon solar cell, or the solar cell is a crystalline silicon-perovskite laminated cell.

[0013] In yet another aspect of the present application, the present application provides a photovoltaic module. According to an embodiment of the present application, the photovoltaic module comprises the solar cell as described above. Thus, the photovoltaic module has a good photoelectric conversion efficiency.

[0014] Additional aspects and advantages of the present application will be made apparent from the following description of embodiments of the present application, which will be given for the purpose of illustration and without limitation. BRIEF DESCRIPTION OF DRAWINGS

[0015] The above and / or additional aspects and advantages of the present application will become apparent and be readily understood from the following description of embodiments, given for the purpose of illustration and without limitation, in conjunction with the accompanying drawings, in which:

[0016] Figure 1 is a flow chart of a method for processing a silicon wafer in an embodiment of the present application;

[0017] Figure 2 is a structural schematic diagram of a silicon wafer to be processed in another embodiment of the present application;

[0018] Figure 3 is a structural schematic diagram of a silicon wafer to be processed in another embodiment of the present application;

[0019] Figure 4 is a structural schematic diagram of an etched silicon wafer after laser etching in yet another embodiment of the present application;

[0020] Figure 5 is a structural schematic diagram of a target silicon wafer obtained after processing in yet another embodiment of the present application;

[0021] Figure 6 is a structural schematic diagram of a silicon perovskite tandem cell in yet another embodiment of the present application. DETAILED DESCRIPTION

[0022] The schemes of the present application will be explained in connection with the embodiments. Those skilled in the art will understand that the following embodiments are only for illustration of the present application and should not be regarded as limiting the scope of the present application. The specific techniques or conditions not mentioned in the embodiments are carried out according to the techniques or conditions described in the literature in the art or according to the product instructions. The reagents or instruments not mentioned by the manufacturer are all conventional products that can be obtained by purchase.

[0023] The present application will be described below with reference to specific embodiments. It should be noted that these embodiments are merely descriptive and do not limit the present application in any way.

[0024] In one aspect of the present application, a method for processing a silicon wafer is provided. According to embodiments of the present application, with reference to Figure 1 , the method for processing a silicon wafer comprises:

[0025] S100: providing a silicon wafer to be processed 10, the surface of the silicon wafer to be processed 10 having a plurality of line scratch grooves 11, the line scratch groove 11 comprising a bottom wall 111 and a side wall 112, as shown in Figure 2 . Among them, Figure 2 only the line scratch groove of one surface of the silicon wafer is taken as an example, both surfaces of the silicon wafer can have line scratch grooves as shown in the figure, and both surfaces are processed by subsequent laser etching.

[0026] According to some embodiments of the present application, the plurality of line scratch grooves 11 on the surface of the silicon wafer to be processed 10 are regularly arranged, as shown in A and B in Figure 3 . Thus, in subsequent steps, it is convenient to identify the surface of the silicon wafer to be processed and its line scratch groove, and it is convenient to control the laser irradiation area.

[0027] In some embodiments, the above regular arrangement can refer to that the line scratch grooves are substantially equally spaced, the widths of the line scratch grooves are substantially uniform, the depths of the line scratch grooves are substantially uniform, and the shapes of the line scratch grooves are substantially uniform.

[0028] In some embodiments, the line scratch grooves on the surface of the silicon wafer are mainly caused by friction, impurities or abnormal parameters in the mechanical processing process, in which slicing (multi-wire cutting) and grinding / polishing are the most critical links causing the line scratch grooves. The depth of the line scratch groove is about 2 microns.

[0029] S200: identifying the surface of the silicon wafer 10 to be processed to obtain a first region S1 and a second region S2, the first region S1 including a bottom wall 111 and a part of the side wall close to the bottom wall, and the second region S2 including a planar region 113 between the line scratch grooves 11 and another part of the side wall close to the planar region 113, as shown in Figure 2 .

[0030] According to some embodiments of the present application, the image acquisition method is used for identification. In some specific embodiments, a high-resolution camera can be selected for line scratch groove identification, such as a camera with a pixel greater than or equal to 50 million and / or a pixel size less than or equal to 3 μm. In some embodiments, the camera can be further matched with a ≥2x optical lens (the optical zoom ratio of the lens is 2 times), so that line scratch grooves of 4 μm and above can be effectively identified.

[0031] According to some embodiments of the present application, the specific position of the boundary line between the first region S1 and the second region S2 has no special requirement, and a person skilled in the art can flexibly set it according to the actual needs, as long as the requirement that the height difference between the surface of the planar region after laser etching and the bottom wall is less than or equal to 0.5 μm can be met after laser etching.

[0032] S300: laser etching the second region, the height difference D between the surface of the planar region after etching and the bottom wall 111 of the line scratch groove 11 is less than or equal to 0.5 μm, to obtain an etched silicon wafer 20, as shown in Figure 4 .

[0033] In the process, only the second area is subjected to laser etching, and the first area is not subjected to laser etching, that is, the etching is performed on the protruding part of the surface of the silicon wafer opposite to the bottom wall of the line mark groove, so that the surface height of the second area of the silicon wafer is reduced by etching, and then the height difference (less than or equal to 0.5 μm) of the uneven part of the surface of the silicon wafer is reduced, thereby improving the flatness of the surface of the silicon wafer. If the first area and the second area are subjected to laser etching without distinction, that is, the area subjected to laser etching includes not only the flat area 113 but also the bottom wall 111 of the line mark groove 11, so that the depth of the bottom wall is deepened after etching, and then the size of the distance D between the flat area and the bottom wall of the line mark groove after etching is larger than that between the flat area and the bottom wall of the silicon wafer to be processed, but is still larger than that of the silicon wafer obtained by using the processing method of the present application. As can be seen, in the scheme of the present application, the surface of the silicon wafer to be processed is identified in advance before laser etching, and then laser etching is performed on the specific second area, and etching of the first area is avoided, so that the height difference of the uneven part of the surface of the silicon wafer can be better reduced, that is, the flatness of the surface of the silicon wafer can be better improved. When the silicon wafer processed by the present application is applied to a solar cell, the flatness of the film layer can be improved, especially for a crystalline silicon-perovskite stacked cell, the film forming property and flatness of the perovskite light-absorbing layer in the perovskite top cell can be well improved, thereby helping to improve the cell efficiency of the cell.

[0034] According to some embodiments of the present application, the height difference D between the surface of the flat area and the bottom wall 111 after etching is less than or equal to 0.3 μm. Thus, the flatness of the surface of the silicon wafer can be better improved.

[0035] In some embodiments, the depth of the line mark groove is about 2 μm, and the depth of laser etching can be controlled to be 1.7-2.3 μm, so that the height difference between the flat area and the bottom wall of the line mark groove of the surface of the silicon wafer can be reduced from 2 μm to 0-0.3 μm.

[0036] According to some embodiments of the present application, the direction of laser etching is parallel to the line mark groove, so that the etching of the second area can be better controlled, and etching of the first area can be avoided.

[0037] According to some embodiments of the present application, the laser is a green skin laser with a wavelength of 532 nm, or the laser is a purple skin laser with a wavelength of 405 nm. Under the action of the wavelength, effective etching can be achieved, and the silicon wafer will not be damaged.

[0038] According to some embodiments of the present invention, the laser frequency is 300–600 kHz, such as 300 kHz, 350 kHz, 400 kHz, 450 kHz, 500 kHz, 550 kHz, 600 kHz, etc. At these frequencies, effective etching of the silicon wafer can be achieved without causing significant damage. If the laser frequency is too low, the silicon wafer etching process is slow; if the laser frequency is too high, continuous bombardment causes severe dust splashing from the silicon wafer. In some specific embodiments, a 500 kHz laser can be used for etching.

[0039] According to some embodiments of the present invention, the laser power is 15-30W, such as 15W, 16W, 18W, 20W, 22W, 24W, 25W, 26W, 28W, 30W, etc. At these power levels, a suitable etching depth can be achieved without causing further damage. If the laser power is too low, the energy may be insufficient to reach the target etching depth; if the laser power is too high, over-etching may occur, forming deep pits or grooves in the etched area of ​​the silicon wafer.

[0040] According to some embodiments of the present invention, the laser pulse width is 15-25 ps, such as 15 ps, 16 ps, 17 ps, 18 ps, 19 ps, 20 ps, ​​21 ps, 22 ps, 23 ps, 24 ps, 25 ps, etc. If the laser pulse width is too low, the single pulse energy is low, which may lead to unstable actual etching depth and poor process repeatability; if the laser pulse width is too high, molten silicon dust will splash during the process, easily forming burrs in the etching area; the aforementioned pulse widths can effectively etch the silicon wafer.

[0041] According to some embodiments of the present invention, the laser spot size is 20–50 μm, such as 20 μm, 23 μm, 25 μm, 28 μm, 30 μm, 32 μm, 35 μm, 38 μm, 40 μm, 42 μm, 45 μm, 48 μm, and 50 μm. The smaller laser spot size allows for more precise positioning during etching, avoiding etching of the bottom wall of the line groove, thereby improving the accuracy of laser etching.

[0042] S400: Alkali polishing is performed on the etched silicon wafer to obtain the target silicon wafer 30, such as... Figure 5 As shown. Thus, alkaline polishing can effectively repair the mechanical damage caused by laser etching on the silicon wafer surface and further improve the flatness of the silicon wafer surface.

[0043] According to some embodiments of the present application, the conditions of the alkaline polishing include: the mass concentration of the alkali in the alkaline solution is 1.5% to 3%, such as 1.5%, 1.8%, 2.0%, 2.1%, 2.2%, 2.5%, 2.8%, 3.0%, etc.; the temperature of the alkaline solution is 60°C to 75°C, such as 60°C, 62°C, 65°C, 67°C, 70°C, 72°C, 75°C, etc.; the time of the alkaline polishing is 250 to 400 seconds, such as 250 seconds, 280 seconds, 300 seconds, 320 seconds, 350 seconds, 380 seconds, 400 seconds, etc. Under the above conditions of the alkaline polishing, the mechanical damage caused by the laser etching on the surface of the silicon wafer can be effectively repaired.

[0044] In some embodiments, the alkali in the alkaline solution can be sodium hydroxide or potassium hydroxide.

[0045] In some embodiments, the alkaline solution can further include an additive. The specific type of the additive can be selected by those skilled in the art according to the prior art, and is not limited herein. Further, the volume ratio of the alkali to the additive in the alkaline solution can be 11:3.

[0046] In another aspect of the present application, the present application provides a silicon wafer. According to embodiments of the present application, the silicon wafer is obtained by the method described above. Therefore, the surface of the silicon wafer has a better flatness, which further ensures the continuous film formation of the film layer deposited thereon and the good working performance of the film layer. Those skilled in the art can understand that the silicon wafer has all the features and advantages of the method for processing the silicon wafer described above, and will not be described in more detail herein.

[0047] In yet another aspect of the present application, the present application provides a solar cell. According to embodiments of the present application, the solar cell includes the silicon wafer described above. Therefore, the cell efficiency of the solar cell is better.

[0048] According to some embodiments of the present application, the solar cell is a single-crystal silicon solar cell. The film layers in the solar cell can be continuously formed, and the uniformity of the film layers is better, which is beneficial to improving the cell efficiency of the solar cell.

[0049] In some embodiments, the solar cell can be a BC cell, a heterojunction cell, a TOPCon cell, or other crystalline silicon solar cell.

[0050] According to some embodiments of the present application, the solar cell is a crystalline silicon-perovskite stacked cell. The silicon wafer with a relatively flat surface can make the perovskite light-absorbing layer in the perovskite top cell have good continuous film formation, improve the film formation quality, and thus help to improve the cell efficiency of the stacked cell.

[0051] According to some embodiments of the present application, a schematic diagram of a structure of a crystalline silicon-perovskite tandem cell is shown in FIG. 1, which comprises: Figure 6

[0052] The target silicon wafer 30 obtained by the above processing method has a front surface and a back surface arranged oppositely;

[0053] The first tunneling layer 41 is arranged on the back surface of the target silicon wafer 30, and the p-type doped polysilicon layer 42 is arranged on the side of the first tunneling layer 41 away from the silicon wafer. The thickness of the first tunneling layer 41 can be 1.9-2.3 nm, and the p-type doped polysilicon layer can be a boron-doped polysilicon layer with a thickness of 230-360 nm and a surface concentration of (2-8) x 10<19> cm<- -3 ;

[0054] The second tunneling layer 43 is arranged on the front surface of the target silicon wafer 30, and the n-type doped polysilicon layer 44 is arranged on the side of the second tunneling layer 43 away from the silicon wafer. The thickness of the second tunneling layer 43 can be 1.9-2.3 nm, and the n-type doped polysilicon layer can be a phosphorus-doped polysilicon layer with a thickness of 100-280 nm and a surface concentration of (2-8) x 10<20> cm<- -3 ;

[0055] The passivation layer 45 is arranged on the side of the n-type doped polysilicon layer 44 away from the silicon wafer. The material of the passivation layer can be aluminum oxide with a thickness of 3.3-5.3 nm;

[0056] The anti-reflection film 46 is arranged on the side of the passivation layer 45 away from the silicon wafer. The material of the anti-reflection film 46 can include silicon nitride, silicon oxide, or silicon oxynitride. The anti-reflection film 46 can have a multilayer structure, each layer having a thickness of 10-30 nm, the total thickness of the anti-reflection film 46 being 84±6 nm, and the refractive index being 2.12±0.05;

[0057] The back electrode 47 is arranged on the side of the anti-reflection layer 46 and is in contact with the p-type doped polysilicon layer. The material of the back electrode 47 can be silver;

[0058] The composite layer 51 is arranged on the side of the n-type doped polysilicon layer 44 away from the silicon wafer. The material of the composite layer 51 can be a transparent conductive material, such as TCO, specifically ITO, with a thickness of 5-10 nm;

[0059] The hole transport layer 52 is arranged on the side of the composite layer away from the silicon wafer. The material of the hole transport layer 52 can be a hole transport material in the conventional art, such as nickel oxide (NiOx), with a thickness of 5-30 nm;

[0060] ​A perovskite light-absorbing layer 53 is disposed on the side of the hole transport layer 52 away from the silicon wafer, and the material thereof is a light-absorbing layer material in the conventional art, and the thickness thereof can be 500-900 nm.

[0061] An electron transport layer 54 is disposed on the side of the perovskite light-absorbing layer 53 away from the silicon wafer, and the material thereof is an electron transport material in the conventional art, such as C60, and the thickness thereof is 5-20 nm.

[0062] A buffer layer 55 is disposed on the side of the electron transport layer 54 away from the silicon wafer, and the material thereof is an electron transport material in the conventional art, such as SnO2, and the thickness thereof is 10-30 nm.

[0063] A transparent conductive layer 56 is disposed on the side of the buffer layer 55 away from the silicon wafer, and the material thereof is a transparent conductive material in the conventional art, such as TCO, and specifically ITO, and the thickness thereof is 30-100 nm.

[0064] A top electrode 57 is disposed on the side of the transparent conductive layer 56 away from the silicon wafer, and the material thereof can be a silver electrode, and the thickness thereof is 50-120 nm.

[0065] An anti-reflection layer 58 is disposed on the side of the transparent conductive layer 56 away from the silicon wafer, and the material thereof can be MgF2, and the thickness thereof is 50-100 nm.

[0066] In another aspect of the present application, a photovoltaic module is provided. According to an embodiment of the present application, the photovoltaic module comprises the solar cell described above. Thus, the photovoltaic module has good photoelectric conversion efficiency.

[0067] Embodiment

[0068] Embodiment 1

[0069] The method for preparing the crystalline silicon-perovskite stacked cell comprises the following steps:

[0070] Step 1: screen the silicon wafer to be processed with regular line scratch grooves, the depth of the line scratch groove is 2 μm, and the silicon wafer is an n-type silicon wafer.

[0071] Step 2: use a camera with a pixel of 50 million to collect and identify images, identify the first region S1 and the second region S2, and then perform laser etching on the second region along a direction parallel to the line scratch groove, and the etching depth is 1.8 μm. After etching, the height difference between the planar region on the surface of the etched silicon wafer and the bottom wall of the line scratch groove is reduced to 0.2 μm, wherein the wavelength of the laser is 532 nm, the frequency is 500 kHz, the power is 20 W, the pulse span is 20 ps, and the spot size is 20 μm.

[0072] Step 3, the silicon wafer obtained in step 2 is polished with sodium hydroxide lye to obtain a target silicon wafer (hereinafter referred to as a silicon wafer), wherein the concentration of NaOH is 2.1%, the solution temperature is 67°C, and the process time is 320s.

[0073] Step 4, a first tunneling layer with a thickness of 2.1 nm and a first polysilicon layer with a thickness of 300 nm are sequentially deposited on the back surface of the silicon wafer by LPCVD deposition method, wherein the deposition conditions of the first tunneling layer are: oxygen flow rate is 30000sccm, temperature is 600°C, process time is 1000s, and tube soaking time is 500s; the deposition conditions of the first polysilicon layer are: deposition temperature is 550°C, process time is 11100s, and the silane flow rates in the three-stage gas feeding mode are 190sccm, 440sccm and 620sccm, respectively.

[0074] Step 5, boron diffusion is performed on the first polysilicon layer by using boron source boron trichloride, the boron source flow rate is 250sccm, the temperature is 855°C, and the process time is 1000s; the push temperature is 950°C, the process time is 1100s; the oxidation temperature is 950°C, the oxygen flow rate is 8000sccm, and the oxidation time is 1600s, finally forming a boron-doped polysilicon layer + borosilicate glass (BSG) structure, and a PN junction is formed between the boron-doped polysilicon layer and the n-type substrate silicon wafer, wherein the surface concentration of the boron-doped polysilicon layer is 6.4×10^19cm -3 , the BSG thickness is 50nm, and the sheet resistance of the boron-doped polysilicon layer is 80.

[0075] Step 6, the BSG formed by the boron diffusion is removed from the front surface and the side surface by a wet chain-type machine (HF solution).

[0076] Step 7, alkali washing is performed by a wet tank-type machine to remove the boron-doped polysilicon layer on the front and side surfaces.

[0077] Step 8, a second tunneling layer with a thickness of 2.1 nm and a second polysilicon layer with a thickness of 235 nm are sequentially deposited on the front surface of the silicon wafer by LPCVD deposition method, wherein the deposition conditions of the second tunneling layer are: oxygen flow rate is 30000sccm, temperature is 600°C, process time is 1000s, and tube soaking time is 500s; the deposition conditions of the second polysilicon layer are: deposition temperature is 600°C, process time is 3000s, and the silane flow rates in the three-stage gas feeding mode are 190sccm, 440sccm and 620sccm, respectively.

[0078] Step 9, phosphorus diffusion to the second polysilicon layer: phosphorus source is phosphorus pentachloride, the flow rate of the phosphorus source is 1200sccm, the temperature is 810℃, the process time is 1200s; the push temperature is 880℃, the process time is 1100s; the oxidation temperature is 870℃, the oxygen flow rate is 2100sccm, and the oxidation time is 820s, finally forming a phosphorus-doped polysilicon layer + phosphosilicate glass (PSG) structure, wherein the surface concentration of the boron-doped polysilicon layer is 5.7×10^20cm -3 , the thickness of the PSG is 50nm, and the sheet resistance of the phosphorus-doped polysilicon layer is 20.

[0079] Step 10, removing the back and side surfaces by a wet chain machine (HF solution) to form a PSG around the diffusion.

[0080] Step 11, removing the phosphorus-doped polysilicon layer around the deposition and the back BSG and the front PSG deposited on the back side surface by a wet alkali tank and an acid tank, respectively.

[0081] Step 12, depositing an aluminum oxide passivation layer by a back-to-back double-insertion method by ALD, the ALD process temperature is 300℃, the process time is 900s, and the thickness of the passivation layer is 4.3nm.

[0082] Step 13, depositing to form an anti-reflective film, the film deposition process temperature is 530℃, and the film is divided into 3 layers, in the direction away from the silicon wafer, the deposition sequence is silicon nitride 1, silicon nitride 2, and silicon nitride 3 in turn, the thickness of the 3 layers of film is between 28nm, 29nm, and 30nm respectively, and the overall thickness of the film is 87nm, and the refractive index is 2.12.

[0083] Step 14, forming a silver metal grid line on the back surface by a screen printing method, that is, a back electrode, forming an ohmic contact between the sintered metal and the boron-doped polysilicon layer, collecting and leading out the current, the sintering peak temperature is 710℃, thereby obtaining a crystalline silicon bottom cell.

[0084] Step 15, depositing an ITO conductive layer, that is, a composite layer, on the upper surface of the crystalline silicon bottom cell (that is, on the surface of the n-type doped polysilicon layer) by a magnetron sputtering method, the thickness is 7nm.

[0085] Step 16, preparing a hole transport layer on the side surface of the composite layer away from the crystalline silicon bottom cell by a magnetron sputtering method, the material of the hole transport layer is NiOx, and the thickness of the hole transport layer is 18nm.

[0086] Step 17, preparing a perovskite light-absorbing layer on the upper surface of the hole transport layer by a spin coating method, the composition of the perovskite light-absorbing layer is Cs 0.22 FA 0.78 Pb(I 0.85 Br 0.15 )3, and the thickness is 700nm.

[0087] Step 18, an electron transport layer is prepared on the surface of the perovskite light-absorbing layer away from the hole transport layer by a thermal evaporation method, and the material is C60 and the thickness is 15 nm.

[0088] Step 19, a buffer layer with a thickness of 20 nm is prepared on the surface of the prepared electron transport layer away from the perovskite light-absorbing layer by an atomic layer deposition method, and the material is SnO2.

[0089] Step 20, an ITO transparent conductive layer is deposited on the surface of the prepared buffer layer away from the electron transport layer by a sputtering method, and the thickness is 60 nm.

[0090] Step 21, an Ag electrode with a thickness of 80 nm is deposited on the surface of the transparent conductive layer by a thermal evaporation method.

[0091] Step 22, an MgF2 anti-reflection layer with a thickness of 80 nm is deposited on the surface of the cell away from the transparent conductive layer by a thermal evaporation method, so as to obtain a crystalline silicon-perovskite stacked cell.

[0092] Comparative Example 1

[0093] The method for preparing the crystalline silicon-perovskite stacked cell is basically the same as that in Embodiment 1, and the difference lies in that:

[0094] Step 2, the surface of the to-be-processed silicon wafer is indiscriminately laser etched, and the etching depth is 1.8 μm. After etching, the height difference between the planar region of the surface of the etched silicon wafer and the bottom wall of the line scratch groove is reduced to 1.68 μm, wherein the wavelength of the laser is 532 nm, the frequency is 500 kHz, the power is 20 W, the pulse span is 20 ps, and the spot size is 20 μm.

[0095] It can be seen from the height difference between the planar region of the surface of the silicon wafer and the bottom wall of the line scratch groove after laser etching in Comparative Example 1 and Comparative Example 1 that the height difference between the planar region of the surface of the silicon wafer and the bottom wall of the line scratch groove in Embodiment 1 is smaller, that is, the flatness is better, that is, the silicon wafer processing process of the present application can obtain a silicon wafer with better surface flatness.

[0096] The stacked cells obtained in Embodiment 1 and Comparative Example 1 are tested for performance, and the specific test method is as follows: using a solar simulator and an I-V tester, under 1 standard solar intensity, the electrical performance of the cells obtained in the above examples and comparative examples is tested by steady-state power output test, and the test results are shown in Table 1.

[0097] Table 1

[0098]

[0099] It can be seen that, when the silicon wafer obtained by the processing method is used as the substrate of the crystalline silicon bottom cell, the flatness of the silicon wafer in the embodiment 1 is better, the film forming quality of the perovskite light-absorbing layer in the top cell can be improved, and the conversion efficiency of the cell can be improved.

[0100] The terms "first", "second", etc. are used only for the purpose of description and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the technical features indicated. Therefore, the features defined with "first", "second" can explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of "a plurality of" is two or more, unless otherwise specifically limited.

[0101] In the description of the present application, the description of the terms "one embodiment", "some embodiments", "an example", "a specific example", or "some examples" means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In the present application, the illustrative description of the above terms is not necessarily for the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any appropriate manner in any one or more embodiments or examples. In addition, the person skilled in the art can combine and combine the different embodiments or examples described in the present application and the features of the different embodiments or examples without contradiction.

[0102] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limiting the present application, and the person skilled in the art can make changes, modifications, replacements and variations to the above embodiments within the scope of the present application.

Claims

1. A method for processing silicon wafers, characterized in that, include: A silicon wafer to be processed is provided, the surface of which has a plurality of line grooves, the line grooves including a bottom wall and a side wall; The surface of the silicon wafer to be processed is identified to obtain a first region and a second region. The first region includes the bottom wall and a portion of the sidewall near the bottom wall. The second region includes a planar region between the line grooves and another portion of the sidewall near the planar region. The second region is laser etched, and the height difference between the surface of the etched planar region and the bottom wall is less than or equal to 0.5 μm, thus obtaining an etched silicon wafer; The etched silicon wafer is polished with an alkaline solution to obtain the target silicon wafer.

2. The method according to claim 1, characterized in that, The height difference between the surface of the etched planar region and the bottom wall is less than or equal to 0.3 μm.

3. The method according to claim 1, characterized in that, The recognition is performed using an image acquisition method.

4. The method according to any one of claims 1 to 3, characterized in that, The conditions for laser etching include at least one of the following: The direction of laser etching is parallel to the line groove; The laser is a green laser with a wavelength of 532nm, or the laser is a purple laser with a wavelength of 405nm; The frequency of the laser is 300–600 kHz; The power of the laser is 15-30W; The pulse width of the laser is 15–25 ps; The laser spot size is 20–50 μm.

5. The method according to any one of claims 1 to 3, characterized in that, The multiple line grooves on the surface of the silicon wafer to be processed are arranged in a regular manner.

6. The method according to claim 1, characterized in that, The conditions for alkaline polishing include: The mass concentration of alkali in the alkaline solution is 1.5% to 3%. The temperature of the alkaline solution is 60℃~75℃; The alkaline polishing time is 250–400 seconds.

7. A silicon wafer, characterized in that, It is obtained by processing using any one of claims 1 to 6.

8. A solar cell, characterized in that, Includes the silicon wafer as described in claim 7.

9. The solar cell according to claim 8, characterized in that, The solar cell is a single crystalline silicon solar cell, or the solar cell is a crystalline silicon-perovskite tandem cell.

10. A photovoltaic module, characterized in that, Includes the solar cell described in claim 8 or 9.

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