Method and system for testing and analyzing reliability of integrated circuit under extreme working condition

Abstract

The invention provides a method and a system for testing and analyzing reliability of an integrated circuit under an extreme working condition, and relates to the technical field of testing. Identifying a limit working condition point under the critical state of the circuit function constraint condition; injecting random deviation to simulate circuit behaviors under different process corners to obtain reliability characteristic parameters; establishing a correlation model of a device degradation state and circuit function margin attenuation to predict life distribution; and determining a reliability level according to the life distribution and a preset threshold and generating a test report. The failure mode under the limit working condition can be accurately positioned, and the integrated circuit life prediction accuracy is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of testing, in particular to an integrated circuit limit condition reliability test and analysis method and system. BACKGROUND

[0002] With the continuous advancement of integrated circuit manufacturing technology to nanometer scale, the chip integration has been greatly improved, and the working environment has become increasingly complex and variable. Integrated circuits often face challenges such as high temperature, high frequency, high voltage and other limit conditions in actual application. These limit conditions not only affect the instantaneous performance of the circuit, but also accelerate the aging and degradation process of the device, eventually leading to reliability problems. Traditional reliability evaluation mainly relies on test data under standard conditions for prediction, which cannot accurately reflect the reliability performance under limit conditions.

[0003] The existing integrated circuit reliability test and analysis technology mainly has the following deficiencies: there is a lack of systematic identification method for limit conditions, which often relies on empirical condition selection, resulting in missing of key limit condition points and inability to comprehensively evaluate the reliability risk of the circuit under boundary conditions. SUMMARY

[0004] The embodiments of the present application provide an integrated circuit limit condition reliability test and analysis method and system, which can solve the problems in the prior art.

[0005] In a first aspect, the embodiments of the present application provide an integrated circuit limit condition reliability test and analysis method, comprising: Obtaining circuit topological structure information and process parameter distribution characteristics of an integrated circuit, and constructing a circuit simulation model containing a device-level stress response model; Based on the circuit simulation model, limit condition points that make the circuit function constraint condition reach a critical state are identified by traversing the combination space of working voltage, working temperature and working frequency, wherein the function constraint condition is determined by the timing margin constraint and the power consumption margin constraint; For each limit condition point in the limit condition point set, random deviations associated with the process parameter distribution characteristics are injected into the circuit simulation model to simulate the circuit behavior under multiple process angles, and reliability characteristic parameters reflecting the functional failure probability distribution of the circuit under the limit condition point are statistically obtained; The reliability characteristic parameters are time-domain mapped with the device degradation trajectory obtained by applying an accelerated aging stress, an association model from the device degradation state to the circuit function margin attenuation is established, and the life distribution of the circuit under the limit condition is predicted; According to the life distribution and the preset reliability index threshold, the reliability level of the integrated circuit under the limit condition is determined, and a test report containing failure mode positioning information is generated.

[0006] The circuit topology information and the process parameter distribution characteristics of the integrated circuit are acquired, and a circuit simulation model including a device-level stress response model is constructed, including: Device geometry size information and interconnection line parasitic parameter information in integrated circuit layout data are extracted, and circuit topology information is established according to the device geometry size information and the interconnection line parasitic parameter information. Based on the process parameter statistical data obtained from wafer-level testing, the threshold voltage, carrier mobility and gate oxide thickness deviation are probabilistically modeled, and the process parameter distribution characteristics representing the process parameter spatial distribution law are obtained. For each device in the circuit topology information, the device electrical characteristic variation law under different stress conditions is determined according to the process parameter distribution characteristics, and a device-level stress response model is established, which takes the stress amplitude and stress duration as input and the device electrical characteristic parameter variation as output. The circuit topology information and the device-level stress response model are integrated to generate a circuit simulation model including a device-level stress response model.

[0007] Based on the circuit simulation model, by traversing the combination space of working voltage, working temperature and working frequency, a set of limit working condition points that make the circuit function constraint condition reach the critical state is identified, including: The value range of working voltage, the value range of working temperature and the value range of working frequency are determined according to the design specifications of the integrated circuit, and discrete sampling points are set in each value range to construct a combination space composed of discrete sampling points of working voltage, working temperature and working frequency. For each sampling point combination in the combination space, the working voltage value, working temperature value and working frequency value corresponding to the sampling point combination are input as simulation parameters into the circuit simulation model for simulation operation, and the timing margin value and power consumption margin value of the circuit under the sampling point combination are obtained. The timing margin value and the power consumption margin value are used to determine whether the circuit function constraint condition is met. The sampling point combination that makes the timing margin value decrease to the timing margin threshold or makes the power consumption margin value increase to the power consumption margin threshold is identified, and the identified sampling point combination is marked as a critical sampling point, wherein the timing margin threshold and the power consumption margin threshold jointly define the boundary of the critical state of the circuit function constraint condition. The distribution of the critical sampling points in the combination space is clustered, and the critical sampling points with adjacent spatial positions are merged into the same limit working condition region. The center point of each limit working condition region is extracted as a representative limit working condition point to form a set of limit working condition points that make the circuit function constraint condition reach the critical state.

[0008] For each limit operating point in the limit operating point set, simulate the circuit behavior under multiple process corners by injecting random deviations associated with the process parameter distribution characteristics into the circuit simulation model, and statistically obtain reliability characteristic parameters reflecting the functional failure probability distribution of the circuit at the limit operating point, including: For each limit operating point in the limit operating point set, obtain the working voltage value, working temperature value and working frequency value corresponding to the limit operating point, and set the working voltage value, working temperature value and working frequency value as the simulation operating condition of the circuit simulation model; According to the probability distribution function of the process parameter distribution characteristics, generate multiple sets of random deviation samples by random sampling, each set of random deviation samples containing threshold voltage deviation, carrier mobility deviation and gate oxide layer thickness deviation for each device in the circuit, inject each set of random deviation samples into the process parameters of the corresponding device in the circuit simulation model to form multiple process corners; For each process corner, run the circuit simulation model under the simulation operating condition, detect whether the circuit output signal meets the functional correctness criterion, record the functional state under the process corner as failure or normal, and after traversing all process corners, statistically obtain the ratio of the number of functional failure process corners to the total number of process corners to obtain the functional failure probability under the limit operating point; Based on the functional failure probability, calculate the reliability characteristic parameters representing the reliability level of the circuit at the limit operating point, including the functional failure probability and the reliability confidence index derived from the functional failure probability.

[0009] Map the reliability characteristic parameters and the device degradation trajectory obtained by applying accelerated aging stress in the time domain to establish a correlation model from the device degradation state to the attenuation of the circuit functional margin, and predict the lifetime distribution of the circuit under the limit operating condition, including: Apply accelerated aging stress to the key devices in the integrated circuit, measure the electrical characteristic parameters of the devices at multiple time nodes, and obtain the device degradation trajectory describing the relationship between the electrical characteristic parameters of the devices and time; Take the change amount of the electrical characteristic parameters of the devices in the device degradation trajectory as the process parameter correction amount of the corresponding devices in the circuit simulation model, re-run the circuit simulation model under the simulation operating condition of the limit operating point, obtain the circuit functional margin value corresponding to different device degradation degrees, and establish the mapping relationship between the device degradation state and the circuit functional margin; Based on the mapping relationship, convert the time coordinates of the device degradation trajectory into the attenuation trajectory of the circuit functional margin, combine the functional failure probability in the reliability characteristic parameters, determine the time distribution that makes the circuit functional margin decay to the functional failure critical point, and establish the correlation model from the device degradation state to the attenuation of the circuit functional margin. According to the correlation model, the device degradation trajectory is extrapolated to a device degradation state corresponding to a circuit functional failure critical point, a time prediction value of the circuit reaching functional failure under the limit working condition point is obtained, and a life distribution of the circuit under the limit working condition is calculated by combining statistical distribution characteristics of the functional failure probability.

[0010] Based on the mapping relationship, the time coordinate of the device degradation trajectory is converted into a circuit functional margin decay trajectory, and a time distribution of the circuit functional margin decaying to a functional failure critical point is determined by combining the functional failure probability in the reliability characteristic parameter, including: A time node sequence and a corresponding device electrical characteristic parameter value sequence in the device degradation trajectory are extracted, the device electrical characteristic parameter value corresponding to each time node is converted into a circuit functional margin value at the corresponding time through the mapping relationship, and a circuit functional margin decay trajectory with time as the horizontal coordinate and the circuit functional margin as the vertical coordinate is formed; The critical time when the circuit functional margin reaches the functional failure critical point is identified from the circuit functional margin decay trajectory, the functional failure critical point is determined by the circuit functional margin threshold corresponding to the functional failure probability in the reliability characteristic parameter, and the circuit functional margin threshold represents the functional margin boundary value of the circuit changing from a normal state to a failure state under the limit working condition point; According to the statistical distribution characteristics of the functional failure probability in the reliability characteristic parameter, the circuit functional margin threshold corresponding to different probability levels is respectively substituted into the circuit functional margin decay trajectory, the critical time corresponding to multiple probability levels is obtained, and a time distribution of the circuit functional margin decaying to the functional failure critical point is constructed according to the multiple probability levels and the corresponding critical time. Statistical parameter extraction is performed on the time distribution, the average life value and the life standard deviation value representing the life characteristics of the circuit under the limit working condition point are obtained, and the time distribution is used as basic data for predicting the life distribution of the circuit under the limit working condition.

[0011] The second aspect of the embodiment of the application provides an integrated circuit limit working condition reliability test and analysis system, including: A first unit is configured to obtain circuit topological structure information and process parameter distribution characteristics of an integrated circuit, and construct a circuit simulation model including a device-level stress response model. A second unit is configured to identify a limit working condition point set that makes a circuit functional constraint condition reach a critical state based on the circuit simulation model by traversing a combination space of working voltage, working temperature and working frequency, wherein the functional constraint condition is determined by a timing margin constraint and a power consumption margin constraint. The third unit is used to simulate the circuit behavior under multiple process angles for each extreme operating point in the set of extreme operating points by injecting random deviations related to the distribution characteristics of process parameters into the circuit simulation model, and statistically obtaining reliability characteristic parameters that reflect the probability distribution of functional failure of the circuit under that extreme operating point; The fourth unit is used to perform time-domain mapping between the reliability characteristic parameters and the device degradation trajectory obtained by applying accelerated aging stress, establish a correlation model from the device degradation state to the decay of circuit functional margin, and predict the lifetime distribution of the circuit under extreme operating conditions; The fifth unit is used to determine the reliability level of the integrated circuit under extreme operating conditions based on the lifetime distribution and the preset reliability index threshold, and to generate a test report containing failure mode location information.

[0012] A third aspect of the present invention, An electronic device is provided, comprising: processor; Memory used to store processor-executable instructions; The processor is configured to invoke instructions stored in the memory to execute the aforementioned method.

[0013] Fourth aspect of the embodiments of the present invention, A computer-readable storage medium is provided, having stored thereon computer program instructions that, when executed by a processor, implement the aforementioned method.

[0014] The beneficial effects of this application are as follows: By constructing a circuit simulation model that includes a device-level stress response model and traversing the combination space of operating voltage, temperature and frequency to identify extreme operating conditions, the reliability of integrated circuits under critical conditions is accurately assessed, avoiding the evaluation bias caused by blindly setting test conditions in traditional testing methods.

[0015] By employing a random deviation injection method for process parameters to simulate circuit behavior under multiple process angles, reliability characteristic parameters of the functional failure probability distribution are obtained. This method can comprehensively consider the impact of process fluctuations on circuit reliability under extreme operating conditions, thereby improving the accuracy and coverage of reliability assessment.

[0016] By establishing a correlation model between device degradation state and circuit functional margin decay, a time-domain mapping from device aging to circuit performance degradation is realized. This model can not only predict the lifetime distribution of the circuit under extreme operating conditions, but also accurately locate the failure mode, providing effective guidance for integrated circuit design optimization and reliability improvement. Attached Figure Description

[0017] Figure 1A flowchart of the integrated circuit extreme working condition reliability test and analysis method of the embodiment of the present application is shown in DETAILED DESCRIPTION

[0018] To make the objectives, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described below in connection with the drawings of the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by a person of ordinary skill in the art without creative effort belong to the scope of protection of the present application.

[0019] The technical solutions of the present application will be described in detail below with specific embodiments. The following specific embodiments can be combined with each other, and the same or similar concepts or processes can not be described in some embodiments.

[0020] Figure 1 A flowchart of the integrated circuit extreme working condition reliability test and analysis method of the embodiment of the present application is shown in Figure 1 The method comprises: obtaining circuit topological structure information and process parameter distribution characteristics of an integrated circuit, and constructing a circuit simulation model containing a device-level stress response model; based on the circuit simulation model, identifying a set of extreme working condition points that make a functional constraint condition of the circuit reach a critical state by traversing a combination space of working voltage, working temperature and working frequency, wherein the functional constraint condition is determined by a timing margin constraint and a power consumption margin constraint; for each extreme working condition point in the set of extreme working condition points, simulating circuit behavior under multiple process corners by injecting random deviations associated with the process parameter distribution characteristics in the circuit simulation model, and statistically obtaining reliability characteristic parameters reflecting a functional failure probability distribution of the circuit under the extreme working condition point; mapping the reliability characteristic parameters and a device degradation trajectory obtained by applying an accelerated aging stress in time domain, establishing a correlation model from a device degradation state to a circuit functional margin decay, and predicting a lifetime distribution of the circuit under the extreme working condition; determining a reliability level of the integrated circuit under the extreme working condition according to the lifetime distribution and a preset reliability index threshold, and generating a test report containing failure mode positioning information.

[0021] In an alternative embodiment, obtaining circuit topological structure information and process parameter distribution characteristics of an integrated circuit, and constructing a circuit simulation model containing a device-level stress response model comprises: Extracting device geometry information and interconnect parasitic parameter information from integrated circuit layout data, and establishing circuit topology information according to the device geometry information and the interconnect parasitic parameter information; Based on the process parameter statistical data obtained from wafer level testing, the threshold voltage, carrier mobility and gate oxide thickness deviation are modeled by probability distribution to obtain process parameter distribution characteristics representing the process parameter spatial distribution law; For each device in the circuit topology information, the device electrical property variation law under different stress conditions is determined according to the process parameter distribution characteristics, and a device-level stress response model is established, which takes stress amplitude and stress duration as input and device electrical property parameter variation as output. The circuit topology information and the device-level stress response model are integrated to generate a circuit simulation model containing the device-level stress response model.

[0022] When extracting integrated circuit layout data, an electronic design automation tool can be used to parse standard layout file formats such as GDS-II or OASIS. For a 28-nanometer process SRAM cell, the geometry size of the NMOS transistor extracted from the layout file includes a gate length of 30 nanometers, a gate width of 60 nanometers, a source / drain region length of 40 nanometers each, and a contact hole diameter of 25 nanometers. At the same time, interconnect line information is extracted, such as a metal 1 layer line width of 40 nanometers, a line thickness of 50 nanometers, and an interlayer dielectric thickness of 60 nanometers. During the extraction process, the layout information at each level is identified: active area, polysilicon gate, metal interconnection, via, and contact hole, and the spatial position relationship between devices and interconnect lines is established. The system uses a scanning algorithm to scan the entire layout, classifies the same graphic patterns, identifies repeated units and key devices, especially input / output buffer zones, standard cells, and memory cells, etc.

[0023] When modeling the circuit topology, the connection relationship between the components is identified based on the extracted layout data. For example, in a dual-input NAND gate circuit, two NMOS transistors (M1, M2) are connected in series, two PMOS transistors (M3, M4) are connected in parallel, and the output node is connected to the four transistors through a metal line. Based on the connection relationship identification, the parasitic parameters of the interconnect lines are calculated. For a metal wire with a length of 100 microns and a width of 0.5 microns, its resistance value is 0.5 ohms, its capacitance to ground is 20 femtofarads, and its coupling capacitance to adjacent lines is 15 femtofarads. These parasitic parameters are stored in the netlist file together with the device topology relationship to form complete circuit topology information.

[0024] The process parameter distribution modeling is based on wafer-level test data. 25 test points are selected on a 300 mm wafer, and 100 transistor samples are measured for key electrical parameters at each test point. The test data shows that the average threshold voltage of NMOS transistors is 0.35 volts, and the standard deviation is 0.015 volts; the average carrier mobility is 350 square centimeters / volt-second, and the standard deviation is 17.5 square centimeters / volt-second; the average gate oxide thickness is 1.2 nanometers, and the standard deviation is 0.05 nanometers. Statistical analysis of these test data shows that the threshold voltage distribution is approximately normally distributed, the carrier mobility is logarithmically normally distributed, and the gate oxide thickness is uniformly distributed. Further analysis of the parameter correlation at different locations on the wafer shows that the device parameters of adjacent regions have a positive correlation, and the correlation coefficient is about 0.7, while the correlation between devices at a distance is significantly reduced to below 0.3. Based on these statistical characteristics, a parameter distribution model including spatial correlation is established, which can accurately represent the distribution of process parameters on the wafer.

[0025] In the process of constructing the device-level stress response model, the aging behavior of the device under different stress conditions is first characterized. For NMOS transistors, under positive gate voltage stress (2.0 volts) for 168 hours, the average threshold voltage increases by 30 millivolts, and the average carrier mobility decreases by 7%. For PMOS transistors, under negative gate voltage stress (-2.0 volts) for 168 hours, the absolute value of the average threshold voltage increases by 25 millivolts, and the average carrier mobility decreases by 5%. Based on these experimental data, it is found that the degradation of device parameters is proportional to the 0.25 power of stress time and proportional to the square of stress voltage. Therefore, a response model including stress amplitude and stress duration is established, which can predict the change of device parameters under any stress condition. For example, when the NMOS transistor is stressed at 1.8 volts for 1000 hours, the predicted threshold voltage increases by about 36 millivolts, and the carrier mobility decreases by about 8.5%.

[0026] The final circuit simulation model integrates the circuit topology information and the device-level stress response model. Based on the SPICE netlist, a parameter aging model is added to each transistor, so that its electrical parameters can be dynamically adjusted according to the stress conditions. For example, for an amplifier circuit containing 100 transistors, the model can simulate the parameter changes of each transistor at different time points under different working conditions and calculate the changes of circuit performance. The simulation results show that after running for 10 years under standard working conditions, the gain of the amplifier circuit decreases by about 5.2%, the bandwidth decreases by about 3.8%, and the power consumption increases by about 4.5%. This simulation model including stress response can effectively predict the performance changes of integrated circuits during long-term use, providing an important reference for the reliability design and evaluation of integrated circuits.

[0027] In an alternative embodiment, based on the circuit simulation model, the set of limit operating condition points that make the circuit function constraint condition reach a critical state is identified by traversing the combination space of operating voltage, operating temperature and operating frequency, comprising: The value range of operating voltage, the value range of operating temperature and the value range of operating frequency are determined according to the design specification of the integrated circuit, and discrete sampling points are set in each value range to construct a combination space composed of discrete sampling points of operating voltage, operating temperature and operating frequency; For each sampling point combination in the combination space, the operating voltage value, operating temperature value and operating frequency value corresponding to the sampling point combination are input as simulation parameters into the circuit simulation model for simulation operation, to obtain the timing margin value and power consumption margin value of the circuit under the sampling point combination, and to determine whether the circuit function constraint condition is met according to the timing margin value and power consumption margin value; The sampling point combination that makes the timing margin value decrease to the timing margin threshold or makes the power consumption margin value increase to the power consumption margin threshold is identified, and the identified sampling point combination is marked as a critical sampling point, wherein the timing margin threshold and the power consumption margin threshold jointly define the boundary of the critical state of the circuit function constraint condition; The distribution of the critical sampling points in the combination space is clustered, and the critical sampling points with adjacent spatial positions are merged into the same limit operating condition region, and the center point of each limit operating condition region is extracted as a representative limit operating condition point to form a set of limit operating condition points that make the circuit function constraint condition reach a critical state.

[0028] In this embodiment, according to the design specification of the integrated circuit, the value range of operating voltage is determined to be 0.8V to 1.2V, the value range of operating temperature is determined to be -40℃ to 125℃, and the value range of operating frequency is determined to be 100MHz to 500MHz. Discrete sampling points are set in each value range. Specifically, the operating voltage is set with a step size of 0.05V to obtain the voltage sampling point set {0.8V, 0.85V, 0.9V,..., 1.2V}; the operating temperature is set with a step size of 15℃ to obtain the temperature sampling point set {-40℃, -25℃, -10℃,..., 125℃}; and the operating frequency is set with a step size of 50MHz to obtain the frequency sampling point set {100MHz, 150MHz, 200MHz,..., 500MHz}. The three sampling point sets constitute a three-dimensional combination space, which contains a total of 9x12x9=972 sampling point combinations.

[0029] For each sample point combination in the combination space, simulation analysis is performed using a pre-established circuit simulation model. The circuit simulation model is built based on the SPICE tool and includes information such as transistor-level circuit topology, device characteristic parameters, and parasitic parameters. Taking the sample point combination (0.9V, 25℃, 300MHz) as an example, the working voltage value 0.9V, the working temperature value 25℃, and the working frequency value 300MHz corresponding to this combination are input as simulation parameters into the circuit simulation model. Through static timing analysis, the setup time margin and the hold time margin of the critical path are obtained, and the smaller value is selected as the timing margin value. In this example, the timing margin value is 42ps; through dynamic power consumption analysis, the power consumption value of the circuit is obtained, and the maximum allowed power consumption value specified in the design specification is subtracted from the actual power consumption value to obtain the power consumption margin value. In this example, the power consumption margin value is 15mW.

[0030] The timing margin threshold is set to 20ps, and the power consumption margin threshold is set to 5mW. When the timing margin value of a sample point combination is less than or equal to 20ps, or the power consumption margin value is less than or equal to 5mW, it is considered that the circuit function constraint condition reaches a critical state, and the sample point combination is marked as a critical sample point. For example, the timing margin value of the sample point combination (0.85V, 85℃, 450MHz) is 18ps, which is less than the timing margin threshold 20ps, so it is marked as a critical sample point; the power consumption margin value of the sample point combination (1.15V, 100℃, 500MHz) is 3mW, which is less than the power consumption margin threshold 5mW, so it is also marked as a critical sample point.

[0031] By traversing the entire combination space, 65 critical sample points are identified. These critical sample points exhibit certain clustering characteristics in the three-dimensional parameter space. A density-based spatial clustering algorithm is used to analyze the clustering of these critical sample points, and critical sample points with a Euclidean distance less than a preset threshold of 0.2 (distance in normalized parameter space) are classified into the same class, resulting in a total of 4 clusters.

[0032] For each cluster, the geometric center point is calculated as a representative corner point of the cluster. Take the first cluster as an example, the cluster contains 23 critical sampling points, mainly distributed in the low voltage, high temperature and high frequency region, and the calculated center point is (0.85V, 95℃, 450MHz), which is determined as a representative corner point; the second cluster contains 18 critical sampling points, mainly distributed in the high voltage, high temperature and high frequency region, and the calculated center point is (1.15V, 110℃, 475MHz), which is determined as another representative corner point; the third cluster contains 15 critical sampling points, mainly distributed in the low voltage, low temperature and high frequency region, and the calculated center point is (0.85V, -25℃, 425MHz); the fourth cluster contains 9 critical sampling points, distributed in the high voltage, low temperature and medium frequency region, and the calculated center point is (1.15V, -20℃, 300MHz).

[0033] To verify the accuracy of the obtained representative corner points, fine simulation analysis is performed on the four points. Take the first representative corner point (0.85V, 95℃, 450MHz) as an example, fine simulation shows that the timing margin value is 19.5ps and the power consumption margin value is 8.2mW, confirming that the point is indeed near the critical state; fine simulation is performed on the second representative corner point (1.15V, 110℃, 475MHz), and the timing margin value is 23.5ps and the power consumption margin value is 4.3mW, also verifying that the point is near the critical state.

[0034] Through the above method, a set of four representative corner points is finally determined: {(0.85V, 95℃, 450MHz), (1.15V, 110℃, 475MHz), (0.85V, -25℃, 425MHz), (1.15V, -20℃, 300MHz)}. These corner points represent the circuit reaching the functional constraint critical state under different condition combinations, providing clear test targets for the limit performance verification and reliability design of integrated circuits, effectively reducing the verification workload and improving the design efficiency and product quality.

[0035] In an optional implementation, for each corner point in the set of corner points, the circuit behavior under multiple process angles is simulated by injecting random deviations associated with process parameter distribution characteristics in the circuit simulation model, and the reliability characteristic parameters reflecting the functional failure probability distribution of the circuit at the corner point are statistically obtained, including: For each limit corner point in the limit corner point set, obtain the working voltage value, working temperature value and working frequency value corresponding to the limit corner point, and set the working voltage value, working temperature value and working frequency value as the simulation working condition of the circuit simulation model. According to the probability distribution function of the process parameter distribution characteristics, generate a plurality of sets of random deviation samples through random sampling, each set of random deviation samples containing threshold voltage deviation, carrier mobility deviation and gate oxide layer thickness deviation of each device in the circuit, inject each set of random deviation samples into the process parameters of the corresponding device in the circuit simulation model to form a plurality of process corners; For each process corner, run the circuit simulation model under the simulation working condition, detect whether the circuit output signal meets the functional correctness criterion, record the functional state of the process corner as failure or normal, and after traversing all process corners, count the ratio of the number of functional failure process corners to the total number of process corners to obtain the functional failure probability under the limit corner point. Based on the functional failure probability, calculate the reliability characteristic parameter representing the reliability level of the circuit under the limit corner point, the reliability characteristic parameter including the functional failure probability and a reliability confidence index derived from the functional failure probability.

[0036] In this embodiment, the reliability characteristics of integrated circuits under extreme conditions are evaluated by a systematic method. This method first identifies a set of limit corner points of the circuit, then for each limit corner point, simulates the behavior of the circuit under a plurality of process corners by using random process parameter deviation, and finally obtains the reliability characteristic parameter reflecting the probability distribution of the functional failure of the circuit.

[0037] For each limit corner point in the limit corner point set, obtain the working voltage value, working temperature value and working frequency value corresponding to the limit corner point, and set the working voltage value, working temperature value and working frequency value as the simulation working condition of the circuit simulation model. For example, for a processor core circuit, a limit corner point may correspond to a working voltage of 0.75V, a working temperature of 125℃ and a working frequency of 1.8GHz. These parameter values are directly input into the circuit simulation software as the environmental conditions for this simulation run.

[0038] According to the probability distribution function of the process parameter distribution characteristics, a plurality of sets of random deviation samples are generated by a Monte Carlo random sampling method. Each set of random deviation samples includes threshold voltage deviation, carrier mobility deviation and gate oxide layer thickness deviation for each device in the circuit. For an integrated circuit of a certain 65 nm process node, the threshold voltage deviation can follow a normal distribution with a mean of 0 and a standard deviation of 30 mV; the carrier mobility deviation can follow a normal distribution with a mean of 0 and a standard deviation of 5%; and the gate oxide layer thickness deviation can follow a normal distribution with a mean of 0 and a standard deviation of 2%. Through a random number generator, 10,000 sets of random deviation samples are generated according to the above distribution characteristics, and each set of samples includes the above three types of process parameter deviation values of all transistors in the circuit.

[0039] Each set of random deviation samples is injected into the process parameters of the corresponding devices in the circuit simulation model to form different process corners. Taking a digital circuit containing 1 million transistors as an example, for the first set of random deviation samples obtained by sampling, the deviation values in the first set of random samples are added to the nominal process parameters of the corresponding transistors. For example, the threshold voltage of the 53265th transistor is 0.45V, and the threshold voltage deviation of the transistor in the first set of random samples is +25mV, so the threshold voltage of the transistor is set to 0.475V in the simulation model. Similarly, the carrier mobility and the gate oxide layer thickness are adjusted accordingly. In this way, 10,000 different process corners are generated, and each process corner represents a possible combination of manufacturing process deviations.

[0040] For each process corner, the circuit simulation model is run under the set simulation condition to detect whether the circuit output signal meets the functional correctness criterion. For a clock data recovery circuit, the functional correctness criterion can include: clock jitter less than 50 picoseconds, bit error rate less than 10^-12, lock time less than 500 nanoseconds, etc. The functional state under the process corner is recorded as failure or normal during the simulation process. For example, for the first process corner, if the simulation result shows that the clock jitter is 47 picoseconds, the bit error rate is 10^-13, and the lock time is 480 nanoseconds, then the circuit function is normal under the process corner; if the simulation result of the second process corner shows that the clock jitter is 55 picoseconds, which exceeds the threshold of 50 picoseconds, then the circuit function fails under the process corner. After traversing all 10,000 process corners, the ratio of the number of functional failure process corners to the total number of process corners is calculated to obtain the functional failure probability under the extreme condition point. If 87 process corners have failed under the circuit function in 10,000 process corners, then the functional failure probability under the extreme condition point is 0.87%.

[0041] Based on the functional failure probability, a reliability characteristic parameter representing the reliability level of the circuit at the limit operating point is calculated. The reliability characteristic parameter includes the functional failure probability and a reliability confidence index derived from the functional failure probability. For example, for the limit operating point with a functional failure probability of 0.87%, the reliability confidence of the point can be calculated as 99.13%. In addition, a reliability target threshold, such as 99.9%, can be set and compared with the calculated reliability confidence to determine whether the circuit meets the reliability requirement at the limit operating point. If 99.13% is lower than the target threshold 99.9%, it is determined that the circuit does not meet the reliability requirement at the limit operating point, and the circuit design or working condition needs to be adjusted.

[0042] Through the above method, the reliability characteristics of the integrated circuit at each limit operating point can be comprehensively evaluated. For a high-performance processor circuit, there can be 25 limit operating points, and the functional failure probabilities of each limit operating point obtained by the above method are 0.87%, 0.65%, 1.23%, etc., and the corresponding reliability confidences are 99.13%, 99.35%, 98.77%, etc. These data can be used to guide the circuit design optimization and working condition setting to ensure that the circuit has a high enough reliability level in actual application.

[0043] In an optional embodiment, the reliability characteristic parameter is time-domain mapped with a device degradation trajectory obtained by applying an accelerated aging stress, a correlation model from device degradation state to circuit functional margin decay is established, and the lifetime distribution of the circuit at the limit operating point is predicted, including: An accelerated aging stress is applied to a key device in an integrated circuit, and the electrical characteristic parameters of the device are measured at multiple time nodes to obtain a device degradation trajectory describing the relationship between the electrical characteristic parameters of the device and time; The change amount of the electrical characteristic parameters of the device in the device degradation trajectory is used as the process parameter correction amount of the corresponding device in the circuit simulation model, the circuit simulation model is re-run under the simulation operating condition of the limit operating point, the circuit functional margin values corresponding to different device degradation degrees are obtained, and a mapping relationship between the device degradation state and the circuit functional margin is established; Based on the mapping relationship, the time coordinates of the device degradation trajectory are converted into a decay trajectory of the circuit functional margin, the functional failure probability in the reliability characteristic parameter is combined to determine the time distribution of the decay of the circuit functional margin to the functional failure critical point, and a correlation model from the device degradation state to the decay of the circuit functional margin is established; According to the correlation model, the device degradation trajectory is extrapolated to a device degradation state corresponding to a circuit functional failure critical point, a time prediction value of the circuit reaching functional failure under the limit working condition point is obtained, and a life distribution of the circuit under the limit working condition is calculated in combination with statistical distribution characteristics of the functional failure probability.

[0044] In the embodiment, the reliability life prediction is performed on the integrated circuit product with timing failure risk. The integrated circuit product contains several key transistor devices, and the working frequency is 3.5 GHz and the core voltage is 1.2 V. First, the functional margin of the circuit is determined as the setup time margin, and the setup time margin of the flip-flop in the timing path is set as the reliability characteristic parameter of the circuit. Through the static timing analysis tool, the 10 most critical timing paths in the circuit are identified, and the setup time margin on each path is extracted, and the minimum value is 150 ps.

[0045] The accelerated aging stress is applied to the key transistor devices in the integrated circuit, and the acceleration condition is temperature 125℃ and voltage 1.8V. At 0 hours, 24 hours, 48 hours, 96 hours, 192 hours and 384 hours, the threshold voltage, carrier mobility and drain current and other electrical characteristic parameters of the transistor are measured. For example, the threshold voltage of an NMOS transistor gradually increases from the initial value 0.45V to 0.51V with time, and the mobility decreases from the initial value 180cm² / Vs to 160cm² / Vs, and the device degradation trajectory describing the relationship between the electrical characteristic parameters of the device and time is obtained.

[0046] The change amount of the electrical characteristic parameters in the device degradation trajectory is used as the process parameter correction amount of the corresponding device in the circuit simulation model. Taking the above NMOS transistor as an example, the threshold voltage parameter VTH0 is increased by 0.06V and the mobility parameter U0 is reduced by 11% in the SPICE model. The circuit simulation model is re-run under the simulation working condition of the limit working condition point (temperature 85℃, voltage 1.0V), and the circuit functional margin value corresponding to different device degradation degrees is obtained. Through the simulation result analysis of each time point, it is found that the setup time margin of the circuit gradually decreases from the initial value 150 ps to 96 ps with the device degradation, and the mapping relationship table between the device degradation state and the circuit functional margin is established.

[0047] Based on the mapping relationship, the time coordinate of the device degradation trajectory is converted into the decay trajectory of the circuit functional margin. For example, when the device aging time is 0, 24, 48, 96, 192, and 384 hours, the corresponding circuit setup time margin is 150 ps, 145 ps, 138 ps, 125 ps, 110 ps, and 96 ps, respectively. According to the circuit function requirement, the functional failure critical point of the setup time margin is determined to be 50 ps, i.e., when the setup time margin is less than 50 ps, the circuit will not work normally. By curve fitting the decay trajectory, a function of the setup time margin changing with the device aging time is obtained. Combined with the functional failure probability distribution characteristics (subject to lognormal distribution, mean μ = 50 ps, standard deviation σ = 5 ps) in the reliability characteristic parameters, the time distribution that makes the circuit functional margin decay to the functional failure critical point is determined, and the correlation model from the device degradation state to the circuit functional margin decay is established.

[0048] According to the established correlation model, the device degradation trajectory is extrapolated to the device degradation state corresponding to the circuit functional failure critical point. Through extrapolation calculation, when the setup time margin decays to 50 ps, the corresponding accelerated aging time is about 850 hours. Based on the stress conversion relationship of the accelerated aging model and the actual working conditions, the time prediction value of the circuit reaching functional failure under the extreme working condition point is calculated to be about 7.5 years. Considering the statistical distribution characteristics of the functional failure probability, the life distribution of the circuit under the extreme working condition is calculated: the life corresponding to a 10% failure probability is 6.2 years, the life corresponding to a 50% failure probability is 7.5 years, and the life corresponding to a 90% failure probability is 9.1 years.

[0049] For a microprocessor chip with a working frequency of 2.8 GHz and a supply voltage of 0.9 V, the functional margin is identified as the clock skew margin, and the initial value is 85 ps. The key PMOS transistor in the chip is selected, and the accelerated aging stress condition is temperature 150℃ and voltage 1.5V. The electrical characteristic parameters of the PMOS transistor are measured at six time points of 0, 48, 120, 240, 480, and 960 hours to obtain the device degradation trajectory. It is observed that the absolute value of the threshold voltage of the PMOS transistor increases from the initial 0.42 V to 0.51 V, and the mobility decreases from the initial 90 cm² / Vs to 72 cm² / Vs.

[0050] The measured device electrical characteristic parameter variation is input into a circuit simulation model, and simulation is performed at a limit working condition point (temperature 100℃, voltage 0.8V). Clock skew margins at different aging time points are obtained as 85ps, 80ps, 76ps, 70ps, 62ps and 53ps, and a mapping relationship between the device degradation state and the circuit clock skew margin is established. A functional failure critical point of the clock skew margin is set as 25ps, and a functional failure probability distribution (subject to normal distribution, mean μ=25ps, standard deviation σ=3ps) is combined to establish a correlation model from the device degradation state to the circuit functional margin decay.

[0051] Through extrapolation of the model, when the clock skew margin decays to 25ps, the corresponding accelerated aging time is about 1850 hours. Based on the acceleration factor conversion of temperature and voltage, the time prediction value of the circuit reaching functional failure under the limit working condition is calculated as about 5.3 years. Combined with the statistical distribution characteristics of the functional failure probability, the life corresponding to 10% failure probability under the limit working condition is 4.6 years, the life corresponding to 50% failure probability is 5.3 years, and the life corresponding to 90% failure probability is 6.1 years.

[0052] In an alternative embodiment, based on the mapping relationship, the time coordinate of the device degradation trajectory is converted into the decay trajectory of the circuit functional margin, and the time distribution of the circuit functional margin decaying to the functional failure critical point is determined in combination with the functional failure probability in the reliability characteristic parameter, including: A sequence of time nodes in the device degradation trajectory and a corresponding sequence of device electrical characteristic parameter values are extracted, and each device electrical characteristic parameter value corresponding to a time node is converted into a circuit functional margin value at the corresponding time through the mapping relationship, forming a decay trajectory of the circuit functional margin with time as the horizontal coordinate and the circuit functional margin as the vertical coordinate; A critical time at which the circuit functional margin reaches the functional failure critical point is identified from the decay trajectory of the circuit functional margin, the functional failure critical point being determined by a circuit functional margin threshold corresponding to the functional failure probability in the reliability characteristic parameter, the circuit functional margin threshold representing a functional margin boundary value at which the circuit changes from a normal state to a failure state under the limit working condition point; According to the statistical distribution characteristics of the functional failure probability in the reliability characteristic parameter, the circuit functional margin threshold corresponding to different probability levels is respectively substituted into the decay trajectory of the circuit functional margin, a plurality of critical times corresponding to the plurality of probability levels are obtained, and a time distribution of the circuit functional margin decaying to the functional failure critical point is constructed according to the plurality of probability levels and the corresponding critical times; Statistical parameter extraction is performed on the time distribution to obtain an average life value and a life standard deviation value representing the life characteristics of the circuit at the limit operating point, and the time distribution is taken as basic data for predicting the life distribution of the circuit at the limit operating point.

[0053] In the embodiment, first, time coordinates of a device degradation trajectory and corresponding sequences of device electrical characteristic parameter values are required. For example, for a MOS transistor device, sequences of threshold voltage Vth values (e.g., 0.5V, 0.52V, 0.54V, 0.58V, 0.63V) at different time points (e.g., 0h, 100h, 200h, 500h, 1000h) are obtained through an aging experiment. These data constitute sequences of time nodes and corresponding sequences of device electrical characteristic parameter values in the device degradation trajectory.

[0054] Based on a pre-established mapping relationship between device electrical characteristic parameters and circuit function margins, the device electrical characteristic parameter value corresponding to each time node can be converted into a circuit function margin value at the corresponding time. Specifically, it is assumed that a mapping relationship table between MOS transistor threshold voltage Vth and amplifier gain margin GM has been established through circuit simulation or theoretical analysis, such as: when Vth is 0.5V, GM is 10dB, when Vth is 0.52V, GM is 9.8dB, when Vth is 0.54V, GM is 9.5dB, when Vth is 0.58V, GM is 9.0dB, and when Vth is 0.63V, GM is 8.3dB. Through this mapping conversion, a circuit function margin decay trajectory with time as the horizontal coordinate (0h, 100h, 200h, 500h, 1000h) and circuit function margin as the vertical coordinate (10dB, 9.8dB, 9.5dB, 9.0dB, 8.3dB) is obtained.

[0055] A critical time at which the circuit function margin reaches a function failure critical point is identified from the circuit function margin decay trajectory. The function failure critical point is determined by a circuit function margin threshold corresponding to a function failure probability in the reliability characteristic parameter. In the embodiment, it is assumed that through system requirement analysis, it is determined that the function failure probability of the amplifier is 10% and the corresponding gain margin threshold is 8.5dB, which represents the function margin boundary value at which the circuit changes from a normal state to a failure state at the limit operating point. Through lookup or interpolation calculation on the function margin decay trajectory, it is known that the critical time at which the amplifier gain margin decreases to 8.5dB is about 750h.

[0056] For the statistical distribution characteristics of the functional failure probability in the reliability characteristic parameter, the circuit function margin threshold corresponding to different probability levels is substituted into the decay trajectory of the circuit function margin, respectively. For example, for the amplifier gain margin, the gain margin thresholds corresponding to the functional failure probabilities of 1%, 5%, 10%, 20% and 50% are 9.2 dB, 8.8 dB, 8.5 dB, 8.2 dB and 7.5 dB, respectively. These thresholds are substituted into the gain margin decay trajectory, and the critical time corresponding to each probability level is obtained by looking up or interpolating calculation, such as 350h for 1% failure probability, 550h for 5% failure probability, 750h for 10% failure probability, 850h for 20% failure probability, and 1200h for 50% failure probability. According to the probability levels and the corresponding critical time, a time distribution table is constructed to make the circuit function margin decay to the functional failure critical point.

[0057] The statistical parameters of the time distribution are extracted to obtain the average life value and the life standard deviation value representing the life characteristics of the circuit under the limit working condition point. In this embodiment, according to the data points composed of the above-mentioned multiple probability levels and corresponding critical time, the life distribution parameters can be extracted by statistical analysis method (such as normal distribution fitting), and the average life value μ = 880h and the standard deviation σ = 310h are obtained. This means that under the specified limit working condition, the average life of the circuit is 880 hours, and the standard deviation of the life distribution is 310 hours.

[0058] This time distribution can be used as the basic data for predicting the life distribution of the circuit under the limit working condition. According to the actual application requirements, the life prediction value can be further extracted for different probability quantile points. For example, it can be predicted that the service life of the amplifier circuit under the 99% reliability requirement (i.e. only 1% failure probability) is 350 hours, and the service life under the 90% reliability requirement (i.e. 10% failure probability) is 750 hours.

[0059] In actual application, a more complex circuit function margin decay trajectory can be constructed by combining multiple device degradation mechanisms and multiple circuit function indicators. For example, for a radio frequency amplifier circuit, the effects of threshold voltage drift and gate capacitance decay of MOS transistor on multiple function indicators such as gain, linearity and noise figure can be considered simultaneously, and the corresponding function margin decay trajectories are constructed, and the most stringent function margin limit is taken as the basis for circuit life prediction.

[0060] Through this method, the effective conversion from device-level degradation characteristics to circuit-level life prediction is realized, which provides a practical tool for integrated circuit reliability analysis and life prediction. This method is particularly suitable for circuit life evaluation under limit working condition, which can find reliability hidden trouble in advance at chip design stage, guide reliability optimization design, and improve product quality and reliability level.

[0061] The integrated circuit extreme condition reliability test and analysis system of the embodiment of the present application comprises: The first unit is configured to acquire circuit topology structure information and process parameter distribution characteristics of the integrated circuit, and construct a circuit simulation model comprising a device-level stress response model. The second unit is configured to identify a set of extreme condition points that make a functional constraint condition of the circuit reach a critical state by traversing a combination space of working voltage, working temperature and working frequency based on the circuit simulation model, wherein the functional constraint condition is determined by a timing margin constraint and a power consumption margin constraint. The third unit is configured to simulate circuit behaviors under a plurality of process angles by injecting random deviations associated with the process parameter distribution characteristics in the circuit simulation model for each extreme condition point in the set of extreme condition points, and statistically obtain reliability characteristic parameters reflecting a functional failure probability distribution of the circuit under the extreme condition point. The fourth unit is configured to perform time domain mapping of the reliability characteristic parameters and a device degradation trajectory obtained by applying an accelerated aging stress, establish an associated model from a device degradation state to a circuit functional margin attenuation, and predict a lifetime distribution of the circuit under the extreme condition. The fifth unit is configured to determine a reliability level of the integrated circuit under the extreme condition according to the lifetime distribution and a preset reliability index threshold, and generate a test report comprising failure mode positioning information.

[0062] In a third aspect, the embodiment of the present application provides an electronic device, comprising: a processor; a memory for storing processor-executable instructions; The processor is configured to invoke the instructions stored in the memory to execute the method described above.

[0063] In a fourth aspect, the embodiment of the present application provides a computer readable storage medium having computer program instructions stored thereon, wherein the computer program instructions are executed by a processor to implement the method described above.

[0064] The present application can be a method, device, system and / or computer program product. The computer program product can include a computer readable storage medium having computer readable program instructions loaded thereon for executing various aspects of the present application.

[0065] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, and are not intended to limit the present application; although the present application has been described in detail with reference to the above embodiments, those skilled in the art should understand that the technical solutions recorded in the above embodiments can be modified, or some or all of the technical features can be replaced by equivalents; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A method for reliability testing and analysis of integrated circuits under extreme operating conditions, characterized in that, include: Obtain information on the circuit topology and process parameter distribution characteristics of integrated circuits, and construct a circuit simulation model that includes a device-level stress response model; Based on the circuit simulation model, by traversing the combination space of operating voltage, operating temperature, and operating frequency, the set of extreme operating points that cause the circuit functional constraints to reach a critical state is identified, wherein the functional constraints are jointly determined by timing margin constraints and power consumption margin constraints; For each extreme operating point in the set of extreme operating points, by injecting random deviations associated with the distribution characteristics of process parameters into the circuit simulation model, the circuit behavior under multiple process angles is simulated, and reliability characteristic parameters reflecting the probability distribution of functional failure of the circuit under that extreme operating point are statistically obtained; The reliability characteristic parameters are mapped in the time domain to the device degradation trajectory obtained by applying accelerated aging stress, and a correlation model from the device degradation state to the decay of the circuit functional margin is established to predict the lifetime distribution of the circuit under extreme conditions. Based on the lifetime distribution and the preset reliability index threshold, the reliability level of the integrated circuit under extreme conditions is determined, and a test report containing failure mode location information is generated.

2. The method according to claim 1, characterized in that, Obtaining information on the circuit topology and process parameter distribution characteristics of integrated circuits, and constructing a circuit simulation model that includes a device-level stress response model includes: Extract device geometry and interconnect parasitic parameters from integrated circuit layout data, and establish circuit topology information based on the device geometry and interconnect parasitic parameters. Based on the statistical data of process parameters obtained from wafer-level testing, a probability distribution model was performed on the deviations of threshold voltage, carrier mobility, and gate oxide thickness to obtain the process parameter distribution characteristics that characterize the spatial distribution of process parameters; For each device in the circuit topology information, the variation law of the electrical characteristics of the device under different stress conditions is determined based on the distribution characteristics of the process parameters. A device-level stress response model is established with stress amplitude and stress duration as inputs and the change of device electrical characteristic parameters as outputs. The circuit topology information is integrated with the device-level stress response model to generate a circuit simulation model that includes the device-level stress response model.

3. The method according to claim 1, characterized in that, Based on the circuit simulation model, by traversing the combination space of operating voltage, operating temperature, and operating frequency, the set of extreme operating points that cause the circuit functional constraints to reach a critical state is identified, including: Based on the integrated circuit design specifications, determine the range of operating voltage, operating temperature, and operating frequency, and set discrete sampling points within each range to construct a combined space consisting of discrete sampling points of operating voltage, operating temperature, and operating frequency. For each combination of sampling points in the combination space, the corresponding operating voltage, operating temperature, and operating frequency values ​​are used as simulation parameters and input into the circuit simulation model for simulation calculation. The timing margin and power consumption margin values ​​of the circuit under the sampling point combination are obtained, and the functional constraints of the circuit are determined based on the timing margin and power consumption margin values. Identify sampling point combinations that reduce the timing margin value to a timing margin threshold or increase the power margin value to a power margin threshold, and mark the identified sampling point combinations as critical sampling points, wherein the timing margin threshold and the power margin threshold together define the boundary where the circuit functional constraints reach a critical state; The distribution of the critical sampling points in the combined space is clustered, and the critical sampling points that are spatially adjacent are grouped into the same extreme operating condition region. The center point of each extreme operating condition region is extracted as a representative extreme operating condition point, forming a set of extreme operating condition points that make the circuit functional constraints reach the critical state.

4. The method according to claim 1, characterized in that, For each extreme operating point in the set of extreme operating points, by injecting random deviations associated with the distribution characteristics of process parameters into the circuit simulation model, the circuit behavior under multiple process angles is simulated, and the reliability characteristic parameters reflecting the probability distribution of functional failure of the circuit under that extreme operating point are statistically obtained, including: For each extreme operating point in the set of extreme operating points, obtain the corresponding operating voltage, operating temperature, and operating frequency values, and set the operating voltage, operating temperature, and operating frequency values ​​as the simulation operating conditions of the circuit simulation model; Based on the probability distribution function of the process parameter distribution characteristics, multiple sets of random deviation samples are generated through random sampling. Each set of random deviation samples includes the threshold voltage deviation, carrier mobility deviation, and gate oxide thickness deviation for each device in the circuit. Each set of random deviation samples is injected into the process parameters of the corresponding device in the circuit simulation model to form multiple process corners. For each process corner, the circuit simulation model is run under the simulated operating conditions to check whether the circuit output signal meets the functional correctness criteria. The functional state under that process corner is recorded as either failed or normal. After traversing all process corners, the ratio of the number of process corners with functional failures to the total number of process corners is calculated to obtain the functional failure probability under that extreme operating condition. Based on the functional failure probability, reliability characteristic parameters characterizing the reliability level of the circuit at the extreme operating point are calculated. The reliability characteristic parameters include the functional failure probability and the reliability confidence index derived from the functional failure probability.

5. The method according to claim 1, characterized in that, The reliability characteristic parameters are mapped in the time domain to the device degradation trajectory obtained by applying accelerated aging stress, establishing a correlation model from the device degradation state to the decay of circuit functional margin, and predicting the lifetime distribution of the circuit under extreme operating conditions, including: Accelerated aging stress is applied to key components in integrated circuits, and the electrical characteristic parameters of the components are measured at multiple time points to obtain the device degradation trajectory describing the relationship between the electrical characteristic parameters of the components and time. The changes in the electrical characteristic parameters of the device in the device degradation trajectory are used as the correction amount of the process parameters of the corresponding device in the circuit simulation model. The circuit simulation model is rerun under the simulation conditions of the extreme operating point to obtain the circuit functional margin value corresponding to different device degradation degrees, and to establish the mapping relationship between device degradation state and circuit functional margin. Based on the mapping relationship, the time coordinates of the device degradation trajectory are converted into the decay trajectory of the circuit functional margin. Combined with the functional failure probability in the reliability characteristic parameters, the time distribution that causes the circuit functional margin to decay to the functional failure critical point is determined, and a correlation model from the device degradation state to the decay of the circuit functional margin is established. Based on the correlation model, the device degradation trajectory is extrapolated to the device degradation state corresponding to the critical point of circuit functional failure, and the predicted time of the circuit reaching functional failure under the extreme operating condition is obtained. Combined with the statistical distribution characteristics of the functional failure probability, the lifetime distribution of the circuit under extreme operating conditions is calculated.

6. The method according to claim 5, characterized in that, Based on the mapping relationship, the time coordinates of the device degradation trajectory are converted into the decay trajectory of the circuit functional margin. Combined with the functional failure probability in the reliability characteristic parameters, the time distribution that causes the circuit functional margin to decay to the functional failure critical point is determined, including: Extract the time node sequence and the corresponding device electrical characteristic parameter value sequence from the device degradation trajectory. Convert the device electrical characteristic parameter value corresponding to each time node into the circuit functional margin value at the corresponding time through the mapping relationship, forming a decay trajectory of the circuit functional margin with time as the horizontal axis and circuit functional margin as the vertical axis. The critical moment when the circuit functional margin reaches the functional failure threshold is identified from the decay trajectory of the circuit functional margin. The functional failure threshold is determined by the circuit functional margin threshold corresponding to the functional failure probability in the reliability characteristic parameters. The circuit functional margin threshold characterizes the functional margin boundary value of the circuit from normal state to failure state at this extreme operating point. Based on the statistical distribution characteristics of the functional failure probability in the reliability characteristic parameters, the circuit functional margin thresholds corresponding to different probability levels are substituted into the decay trajectory of the circuit functional margin to obtain the critical moments corresponding to multiple probability levels. Based on the multiple probability levels and the corresponding critical moments, a time distribution that causes the circuit functional margin to decay to the functional failure critical point is constructed. Statistical parameters are extracted from the time distribution to obtain the average lifetime value and lifetime standard deviation that characterize the lifetime characteristics of the circuit under the extreme operating condition. The time distribution is then used as the basic data for predicting the lifetime distribution of the circuit under the extreme operating condition.

7. An integrated circuit extreme condition reliability testing and analysis system, used to implement the method as described in any one of claims 1-6, characterized in that, include: The first unit is used to obtain information on the circuit topology and process parameter distribution characteristics of integrated circuits, and to construct a circuit simulation model that includes a device-level stress response model. The second unit is used to identify the set of extreme operating points that cause the circuit functional constraints to reach a critical state based on the circuit simulation model by traversing the combination space of operating voltage, operating temperature and operating frequency, wherein the functional constraints are jointly determined by timing margin constraints and power consumption margin constraints; The third unit is used to simulate the circuit behavior under multiple process angles for each extreme operating point in the set of extreme operating points by injecting random deviations related to the distribution characteristics of process parameters into the circuit simulation model, and statistically obtaining reliability characteristic parameters that reflect the probability distribution of functional failure of the circuit under that extreme operating point; The fourth unit is used to perform time-domain mapping between the reliability characteristic parameters and the device degradation trajectory obtained by applying accelerated aging stress, establish a correlation model from the device degradation state to the decay of circuit functional margin, and predict the lifetime distribution of the circuit under extreme operating conditions; The fifth unit is used to determine the reliability level of the integrated circuit under extreme operating conditions based on the lifetime distribution and the preset reliability index threshold, and to generate a test report containing failure mode location information.

8. An electronic device, characterized in that, include: processor; Memory used to store processor-executable instructions; The processor is configured to invoke instructions stored in the memory to execute the method according to any one of claims 1 to 6.

9. A computer-readable storage medium having computer program instructions stored thereon, characterized in that, When the computer program instructions are executed by the processor, they implement the method described in any one of claims 1 to 6.

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