Test methods and test circuits for chip failure types

Abstract

This application discloses a chip failure type testing method and test circuit. The testing method includes: performing column mode testing on the chip with multiple different test voltages and obtaining a first test result containing failure bit information; activating a first auxiliary module and performing column mode testing on the chip with multiple different test voltages, obtaining a second test result containing failure bit information; wherein, when testing the chip with a test voltage greater than or equal to the chip's operating voltage, if a failure point that was disabled under the first auxiliary module is effective when the first auxiliary module is activated, then the failure point belongs to a soft failure. The chip failure type testing method and test circuit of this application, with the auxiliary module activated or disabled, performs column mode testing on the chip at different test voltages and classifies soft and hard failures based on the output results.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor technology, and in particular to a chip failure type testing method and testing circuit. BACKGROUND

[0002] In the field of semiconductor manufacturing, the yield of static random-access memory (SRAM) is a key factor affecting production efficiency and cost. Among them, DLY (Defect Limited Yield) and PLY (Parametric Limited Yield) are two main causes of SRAM yield loss. Accurately distinguishing the failure proportion of DLY and PLY is crucial for quickly identifying the root cause of failure and improving SRAM yield. The traditional SRAM yield testing method performs read and write operations on SRAM at different operating voltage points to obtain SRAM yield data at different voltages. However, as the process technology continues to develop in an advanced direction, some advanced process SRAMs in the factory have Device Shooting Issue (Device Shooting Issue). For example, due to the reduction of device size, the ion implantation position is inaccurate. This problem makes it impossible to efficiently and quickly distinguish between DLY and PLY by relying solely on different operating voltage point testing, which seriously hinders the progress of yield improvement work.

[0003] At the same time, SBHF (Single Bit Hard / Soft Fail) as one of the main failure models of SRAM yield loss is a key breakthrough point for process improvement and yield improvement. However, in actual operation, due to the existence of Device Shooting Issue, when selecting SBHF samples for analysis, it is very likely to select failure samples affected by Device Shooting Issue. This not only reduces the analysis efficiency of hard failure / soft failure, but also misleads the improvement direction of device defects, ultimately hindering the yield improvement of SRAM. SUMMARY

[0004] In view of the above problems, the purpose of the present application is to provide a chip failure type testing method and testing circuit, which performs column testing on the chip at different test voltages with the auxiliary module turned on or off, and classifies soft failure and hard failure according to the output results.

[0005] According to a first aspect of the present application, a test method for chip failure type is provided, comprising: testing the chip with a plurality of different test voltages and obtaining a first test result containing failure bit information, the plurality of different test voltages comprising at least one test voltage less than the working voltage of the chip, a test voltage equal to the working voltage of the chip and at least one test voltage greater than the working voltage of the chip; turning on a first auxiliary module, testing the chip with a plurality of different test voltages and obtaining a second test result containing failure bit information; wherein when the chip is tested with a test voltage greater than or equal to the working voltage of the chip, if the failure point under the first auxiliary module is effective when the first auxiliary module is turned on, the failure point belongs to soft failure.

[0006] Optionally, after the step of turning on the first auxiliary module, testing the chip with a plurality of different test voltages and obtaining a second test result containing failure bit information, the method further comprises: turning on a second auxiliary module, testing the chip with a plurality of different test voltages and obtaining a third test result containing failure bit information.

[0007] Optionally, after the step of turning on the second auxiliary module, testing the chip with a plurality of different test voltages and obtaining a third test result containing failure bit information, the method further comprises: turning on the first auxiliary module and the second auxiliary module, testing the chip with a plurality of different test voltages and obtaining a fourth test result containing failure bit information; comparing and analyzing at least two of the first test result to the fourth test result, and classifying the failure points according to failure causes.

[0008] Optionally, the first auxiliary module is one of a bit line auxiliary module and a word line auxiliary module, and the second auxiliary module is the other of the bit line auxiliary module and the word line auxiliary module.

[0009] Optionally, the failure causes include soft failure and hard failure, and the soft failure includes read failure and write failure.

[0010] Optionally, the first test result to the fourth test result further comprises yield of the chip under different storage sizes.

[0011] Optionally, the comparing and analyzing according to at least two of the first test result to the fourth test result, and classifying the failure points according to failure causes comprises: judging whether the yield difference in the test results is greater than a threshold when the first auxiliary module and / or the second auxiliary module is turned on and off, and the test is performed at a test voltage greater than the working voltage of the chip; if the yield difference in the test results is greater than or equal to the threshold, the proportion of the failure points of the chip caused by soft failure is large; and if the yield difference in the test results is less than the threshold, the proportion of the failure points of the chip caused by hard failure is large.

[0012] Optionally, after the step of the yield difference in the test results being greater than or equal to the threshold, further comprising: judging whether the first auxiliary module or the second auxiliary module is turned on; if the yield difference is greater than or equal to the threshold and the first auxiliary module is turned on, the failure points of the chip are caused by read failure or write failure corresponding to the first auxiliary module in soft failure; and if the yield difference is greater than or equal to the threshold and the second auxiliary module is turned on, the failure points of the chip are caused by write failure or read failure corresponding to the second auxiliary module in soft failure.

[0013] According to another aspect of the present application, a test circuit for chip failure type is provided for performing the test method described above, the test circuit comprising: a storage module; a first auxiliary module connected with one of the bit line and the word line, and compensating the voltage of the bit line or the word line when the storage module is tested; wherein the first test result when the first auxiliary module is turned off is obtained at a plurality of different test voltages, and the second test result when the first auxiliary module is turned on is obtained at a plurality of different test voltages.

[0014] Optionally, further comprising: a second auxiliary module connected with the other of the bit line or the word line, and compensating the voltage of the bit line or the word line when the storage module is tested; the third test result when the second auxiliary module is turned on is obtained at a plurality of different test voltages; and the fourth test result when the first auxiliary module and the second auxiliary module are both turned on is obtained at a plurality of different test voltages.

[0015] The unexpected technical effects of the present application are:

[0016] The chip failure type testing method and testing circuit of the application, the first auxiliary module and the second auxiliary module are arranged in the testing circuit, different test voltages are used to test the chip under the condition that the first auxiliary module and / or the second auxiliary module is turned on or turned off, and the failure bit information and the failure ratio (yield) under the column mode test are obtained, the influence of turning on or turning off the first auxiliary module and / or the second auxiliary module on the yield of the chip is compared, and then it is judged whether the failure of the chip belongs to soft failure or hard failure, and then the direction for improving the chip is provided. Wherein, whether the auxiliary module is turned on or not has no effect on the hard failure of the chip, that is, the failure caused by the hard failure does not change, and at least part of the soft failure is compensated under the condition that the auxiliary module is turned on, so that the failure caused by the soft failure becomes non-failure, which will affect the yield of the chip.

[0017] Further, under the condition that the first auxiliary module and / or the second auxiliary module is turned on, the soft failure of the chip is compensated to a certain extent, and then the soft failure of the chip is reduced, therefore, by analyzing whether the storage unit in the chip shows failure under different states, the failure reason of the chip can be classified, and according to the type of the turned-on auxiliary module, the failure reason in the soft failure can be further classified as read failure or write failure, so as to guide the improvement of the chip in more detail. BRIEF DESCRIPTION OF DRAWINGS

[0018] The above and other objects, features and advantages of the application will be more clearly understood from the following description of the embodiments of the application with reference to the drawings, in which:

[0019] Figure 1a A yield ratio comparison chart of storage blocks in two storage chips under different test voltages in the prior art is shown;

[0020] Figure 1b A yield ratio comparison chart of storage units in two storage chips under different test voltages in the prior art is shown;

[0021] Figure 1c And Figure 1d A voltage-current test result chart of two storage units under the same test voltage in the prior art is shown when the source end is pressurized and the drain end is pressurized;

[0022] Figure 2 A structure schematic diagram of the chip failure type testing circuit according to the first embodiment of the application is shown;

[0023] Figure 3 A structure schematic diagram of the chip failure type testing circuit according to the second embodiment of the application is shown;

[0024] Figure 4A schematic diagram of a test circuit for chip failure types according to a third embodiment of the present invention is shown;

[0025] Figures 5a to 5e A schematic diagram of the test results of a test circuit for chip failure types according to a third embodiment of the present invention is shown;

[0026] Figure 6 A flowchart of a test method for chip failure types according to a third embodiment of the present invention is shown;

[0027] Figure 7 A schematic diagram of the power management module in a chip failure type test circuit according to an embodiment of the present invention is shown. Detailed Implementation

[0028] The present application will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements are indicated by similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale. Furthermore, some well-known parts may not be shown.

[0029] This application may be presented in various forms, some of which will be described below.

[0030] In chip testing, DLY (Defect Limited Yield) refers to the hard failure of a chip. Hard failures are mainly related to physical defects generated during chip manufacturing, such as photolithography defects, short circuits or open circuits in metal interconnects, and cracks in the gate oxide layer of transistors. These defects cause the chip to fail functional testing and constitute permanent hardware damage, which is the main cause of hard failures. For example, if an open circuit occurs in a metal interconnect in a chip, current cannot flow normally, and the related circuit function will be lost. Even if retested or the operating environment is changed, the chip cannot return to normal operation. This situation directly affects DLY.

[0031] PLY (Parametric Limited Yield) refers to soft failures in a chip. Soft failures are primarily related to fluctuations in chip parameters, such as transistor threshold voltage, carrier mobility, and capacitance, which deviate from design specifications. Although the chip may not show obvious physical damage, parameter changes can lead to performance degradation or malfunction under certain operating conditions, consistent with the characteristics of soft failures. For example, when the chip's operating voltage decreases, fluctuations in transistor threshold voltage can cause signal delays or errors in some previously functioning circuits, resulting in a soft failure. However, adjusting the operating voltage or other external conditions may allow the chip to resume normal operation; the impact of these parameter fluctuations on chip performance is primarily reflected in PLY.

[0032] Furthermore, chip failures can be categorized into read failures and write failures. Read failures refer to the inability to correctly retrieve the originally stored data when reading data from a memory cell; the read data may be inconsistent with the actual stored data, or data may be completely unreadable, manifesting as read errors or read timeouts. Write failures occur when data cannot be successfully written to the specified storage location, or the data in the memory cell is incorrect after writing, potentially resulting in data loss or incorrect data being written. Read and write failures caused by soft failures can be classified through analysis, while read and write failures caused by hard failures cannot be classified through analysis. Therefore, this application primarily addresses read and write failures caused by soft failures.

[0033] Figure 1a The diagram shows a comparison of the yield ratios of memory blocks in two memory chips under different test voltages in the prior art. Figure 1b A comparison chart showing the yield ratio of memory cells in two memory chips under different test voltages in the prior art is presented. Figure 1c and Figure 1d The diagram shows the test results of two memory cells under the same test voltage in the prior art when the source end is energized and the drain end is energized. For example, a memory block is a part of a memory cell, and a memory unit is a part of a memory block, which is also the smallest memory area.

[0034] In chip probing (CP), a lower yield indicates fewer qualified wafers. Typically, soft failures in wafer probing show a yield increase with increasing voltage, while hard failures show no change in yield under either high or low voltage conditions. Furthermore, for failures caused by device shooting issues, yield may decrease even under high voltage, making it impossible to quickly distinguish between them simply by relying on different test voltages.

[0035] For example, the yield varies depending on the applied test voltage for different memory cells within the same memory chip and different memory blocks within the same memory cell. (See reference...) Figure 1a As the test voltage gradually increases, the yield of the first memory cell shows a trend of gradually increasing and then decreasing, while the yield of the second memory cell shows a trend of gradually increasing; further reference... Figure 1b As the test voltage gradually increases, the yield of the first and second memory blocks shows a gradual increasing trend.

[0036] Furthermore, voltages are applied to the drain and source of the first memory cell PDL and the second memory cell PDR, respectively, to obtain... Figure 1cThe voltage-current (VD-ID) relationship diagram shown and Figure 1d The voltage-current logarithmic relationship (VD-logID) graph is shown. 0.9 indicates that the forward scan voltage is 0.9V, that is, the voltage applied to the drain is 0.9V, and 0.9REV indicates that the reverse scan voltage is 0.9V, that is, the voltage applied to the source is 0.9V. The curves in the voltage-current relationship graphs of the first memory cell PDL or the second memory cell PDR for forward and reverse scans are basically the same.

[0037] Specifically, in Figure 1c In one embodiment shown, the vertical axis current of the second memory cell PDR is approximately 20uA at a voltage of 0.9V, which is less than the target value of 54uA. Therefore, in the test, other memory cells have reached the target value of 54uA at the same voltage (e.g., the first memory cell PDL), and the second memory cell PDR is marked as faulty because it has not started. Figure 1d The diagram shows the difference in drive voltage between the first memory cell PDL and the second memory cell PDR when the first memory cell PDL and the second memory cell PDR reach the same current. This difference (i.e., the threshold voltage mismatch) is approximately 260mV.

[0038] Therefore, it is not possible to classify chip failure points directly based on the yield under different test voltages.

[0039] Figure 2 A schematic diagram of a chip failure type test circuit according to a first embodiment of the present invention is shown. When testing a chip using this chip failure type test circuit, not only can the chip yield be obtained, but also the specific location (memory unit) of the failure point can be obtained, so as to better improve the chip.

[0040] refer to Figure 2 The chip failure type test circuit of the first embodiment of this application includes: a storage module 110 and a first auxiliary module 120. Figure 2 The illustration shows an embodiment where the storage module 110 is the most basic storage unit with a 6T (6 transistors) structure. In other embodiments, the storage module 110 may also be a storage block, storage cell, etc., composed of multiple 6T structure storage units.

[0041] The storage module 110 includes a first transistor PG1, a second transistor PG2, a third transistor PU1, a fourth transistor PU2, a fifth transistor PD1, and a sixth transistor PD2. The first terminal of the first transistor PG1 is connected to the bit line BL, and its control terminal is connected to the word line WL. The second terminal of the second transistor PG2 is connected to the negative bit line BLB, and its control terminal is connected to the word line WL. The first terminal of the third transistor PU1 is connected to the power supply voltage VDD, and its second terminal is connected to the second terminal of the first transistor PG1. Its control terminal is connected to the first terminal of the second transistor PG2. The first terminal of the fourth transistor PU2 is connected to the first terminal of the third transistor PU1, and its second terminal is connected to the first terminal of the second transistor PG2. Its control terminal is connected to the second terminal of the first transistor PG1. The first terminal of the fifth transistor PD1 is connected to the second terminal of the third transistor PU1, and its second terminal is connected to the ground terminal GND. Its control terminal is connected to the control terminal of the third transistor PU1. The first terminal of the sixth transistor PD2 is connected to the second terminal of the fourth transistor PU2, and its second terminal is connected to the second terminal of the fifth transistor PD1. Its control terminal is connected to the control terminal of the fourth transistor PU2.

[0042] In this application, the first terminal of the transistor is, for example, one of the source and drain terminals, and the second terminal of the transistor is the other of the source and drain terminals. The negative bit line BLB is the complementary signal line to the bit line BL. Generally, the bit line BL and the negative bit line BLB are set to complementary logic levels, and data is written to the memory cell through the transmission gate transistor.

[0043] The first auxiliary module 120 is a module for compensating the bit line BL, which can compensate for insufficient SNM (Static Noise Margin) of the chip. The first auxiliary module 120 includes: a seventh transistor M1, a first capacitor C1, and a logic unit U1. The first terminal of the seventh transistor M1 is connected to the ground terminal GND; the first terminal of the first capacitor C1 is connected to the ground terminal GND, and the second terminal is connected to the second terminal of the seventh transistor M1; the control terminal of the logic unit U1 is connected to the second terminal of the first capacitor C1, and the output terminal is connected to the bit line BL.

[0044] The first auxiliary module 120 adjusts the voltage state of the bit line BL to regulate the voltage difference between the bit line BL and the negative bit line BLB, thereby assisting the storage module 110 in completing the write operation better.

[0045] Furthermore, in the chip failure type testing method of this application, when the first auxiliary module 120 is enabled, it can compensate the word line WL or bit line BL of the memory module 110 during testing. This makes some failure points that are tested without the first auxiliary module 120 enabled become valid points, thereby confirming that the failure point is a soft failure, specifically a read / write failure within the soft failure category. Therefore, by enabling or disabling the first auxiliary module 120 and testing the memory module 110 with different test voltages, the changes in some failure points under different states can be used to classify soft and hard failures. Furthermore, based on the type of auxiliary module, it is possible to further filter whether the soft failure point belongs to a read failure or a write failure, thus guiding the chip improvement process.

[0046] also, Figure 2 Only one circuit structure diagram of the first auxiliary module 120 as a bit line BL auxiliary module is shown. In other embodiments, the circuit structure of the first auxiliary module 120 can also be other circuit structures that can achieve the same purpose. This application does not limit the circuit structure of the first auxiliary module 120.

[0047] The first auxiliary module 120 increases the drive capability of the write operation by applying a negative voltage to the bit line BL, making the flip-flop easier to reverse and thus facilitating the write operation.

[0048] Figure 3 A schematic diagram of a test circuit for chip failure types according to a second embodiment of the present invention is shown. Unlike the first embodiment, the auxiliary module in the second embodiment is a word line auxiliary module. Similarities will not be repeated here; only the differences will be described.

[0049] refer to Figure 3 The chip failure type test circuit of the second embodiment of this application includes: a storage module 110 and a second auxiliary module 130. The storage module 110 is related to the first embodiment and will not be described again here.

[0050] The second auxiliary module 130 is a module for compensating for the word line WL, which can compensate for insufficient SNM (Static Noise Margin) of the chip. It includes: the eighth transistor M2, the ninth transistor M3, the tenth transistor M4, and the eleventh transistor M5. The first terminal of the eighth transistor M2 is connected to the power supply voltage VDD, and the second terminal is connected to the word line WL. The first terminal of the ninth transistor M3 is connected to the second terminal of the eighth transistor M2, and the second terminal is connected to the ground terminal GND. Its control terminal is connected to the control terminal of the eighth transistor M2. The first terminal of the tenth transistor M4 is connected to the second terminal of the eighth transistor M2, and its control terminal is connected to the ground terminal GND. The first terminal of the eleventh transistor M5 is connected to the second terminal of the tenth transistor M4, and the second terminal is connected to the ground terminal GND. Its control terminal is connected to the second terminal of the eighth transistor M2.

[0051] The second auxiliary module 130 adjusts the voltage state of the word line WL to reduce power consumption and improve stability, thereby assisting the storage module 110 in performing read operations better.

[0052] Furthermore, in the chip failure type testing method of this application, when the second auxiliary module 130 is enabled, it can compensate for the read and / or write operations of the storage module 110 during testing, making some failure points that are tested without the second auxiliary module 130 enabled become valid points, thereby confirming that the failure point is a soft failure. Therefore, by enabling or disabling the second auxiliary module 130 and testing the storage module 110 with different test voltages, the changes in some failure points under different states can be used to classify soft and hard failures. Furthermore, based on the type of auxiliary module, it is possible to further filter whether a soft failure point is a read failure or a write failure, thereby guiding the chip improvement process.

[0053] also, Figure 3 This paper only shows a schematic diagram of the circuit structure of the second auxiliary module 130 as a word line WL auxiliary module. In other embodiments, the circuit structure of the second auxiliary module 130 can also be other circuit structures that can achieve the same purpose. This application does not limit the circuit structure of the second auxiliary module 130.

[0054] The second auxiliary module 130 under-drives the word line WL after the bit line is pre-charged during the read operation, so that the driving voltage of the word line WL is lower than the standard power supply voltage VDD. This reduces interference to the internal state of the memory flip-flop during the read process, increases read stability, and avoids the phenomenon of disturbance fail of the memory unit during the read operation.

[0055] Figure 4A schematic diagram of a test circuit for chip failure types according to a third embodiment of the present invention is shown; Figures 5a to 5e A schematic diagram of the test results of a chip failure type test circuit according to a third embodiment of the present invention is shown. Compared with the first and second embodiments, the chip failure type test circuit of the third embodiment includes a first auxiliary module 120 and a second auxiliary module 130, and the similarities will not be repeated here.

[0056] refer to Figure 4 The chip failure type test circuit in the third embodiment includes a storage module 110, a first auxiliary module 120 and a second auxiliary module 130. By turning the first auxiliary module 120 and the second auxiliary module 130 on and off during the test, a better failure point classification process can be achieved compared with the first embodiment and the second embodiment.

[0057] In other embodiments, the functions of the first auxiliary module 120 and the second auxiliary module 130 can be interchanged. For example, the first auxiliary module 120 can be a word line (WL) auxiliary module, and the second auxiliary module 130 can be a bit line (BL) auxiliary module. Therefore,

[0058] Figures 5a to 5e This indicates that with the auxiliary circuit enabled, more soft failure points are identified and correctly classified, thereby improving the accuracy of the improvement direction during chip improvement.

[0059] refer to Figure 5a Without the auxiliary module enabled, the yield of the memory cells in a chip was 0% at test voltages of 0.81V, 0.9V, and 1.08V. However, with the auxiliary module enabled, the yield of the memory cells increased to 21.9% and 26.6%, respectively. This indicates that some failure points become effective when the auxiliary module is enabled, meaning that these failure points can be compensated for, and these failure points belong to soft failures. Similarly, at test voltages higher than the operating voltage of 1.26V and 1.44V, the yield of the chip with the auxiliary module enabled is significantly higher than that without it. Therefore, enabling the auxiliary module can better help classify the types of chip failure points, correctly classifying failure points that were originally incorrectly classified as hard failures into soft failures. This allows for better improvement of the chip based on the proportion and location of hard and soft failures, making the improvement direction more accurate and the improvement effect better.

[0060] Furthermore, Figure 5b The graph shows the yield results of the memory block in a chip under multiple test voltages with and without the auxiliary module enabled. It is also clear that the yield of the chip is significantly higher when the auxiliary module is enabled than when it is not enabled, thus allowing for better classification of chip failure points.

[0061] Figure 5c The graph shows the yield results of memory cells and memory blocks under the same test conditions. It is clear that the yield of memory blocks is higher than that of memory cells, meaning that the yield of chips decreases as the storage space increases.

[0062] Figure 5d and Figure 5e An electron microscope image of a failure point on the chip is shown.

[0063] Figure 6 A flowchart illustrating a chip failure type testing method according to a third embodiment of this application is shown, wherein the first auxiliary module 120 is one of a bit line (BL) auxiliary module and a word line (WL) auxiliary module, and the second auxiliary module 130 is the other of a bit line (BL) auxiliary module and a word line (WL) auxiliary module. The chip failure type testing method specifically includes:

[0064] Step S01: Test the chip with multiple different test voltages and obtain the first test result containing the failure bit information.

[0065] In this step, when testing the chip using different test voltages, the multiple different test voltages include at least one test voltage less than the operating voltage, one test voltage equal to the operating voltage, and at least one test voltage greater than the operating voltage. In this application, for example, five test voltages are used: 60% of the operating voltage, 90% of the operating voltage, the operating voltage, 110% of the operating voltage, and 140% of the operating voltage. The operating voltage is, for example, 0.9V. In other embodiments, the different test voltages can also be 75%, 125%, etc., of the operating voltage, and those skilled in the art can make appropriate adjustments as needed.

[0066] The memory module in the chip includes multiple memory cells (memory strings), each memory cell includes multiple memory blocks, and each memory block includes multiple memory units. A column-mode testing method is used, that is, failure detection is performed sequentially on each memory unit in the memory string (each column). When outputting test results, it can output test results at the memory unit level, or at the memory block or memory cell level, which can be selected or all output as needed. This allows for failure analysis of the chip based on the yield under different memory sizes. Figure 5a and Figure 5b The test results are at the storage unit and storage block levels, respectively.

[0067] This column-based testing method allows for the acquisition of yield information for each storage unit. Furthermore, when a storage unit fails, the corresponding failure location (i.e., the location of the failed storage unit) can be recorded. Therefore, in this step, the first test result includes at least the yield of different storage levels under multiple test voltages and the location information of failure points under multiple test voltages.

[0068] In other embodiments, other testing methods may be used, as long as the location of the failure point can be obtained, and this application does not limit this method.

[0069] Step S02: Turn on the first auxiliary module, test the chip with multiple different test voltages, and obtain a second test result containing failure bit information.

[0070] In this step, with the first auxiliary module 120 turned on, the storage module 110 is tested again under multiple test voltages to obtain the second test result. Since the test result includes information about the failure bit, when a failure point is found, its location information is also recorded.

[0071] Because the first auxiliary module 120 is activated, under the same test voltage as in step S01, locations that were originally considered faulty may become effective due to the compensation from the first auxiliary module 120, or vice versa. These locations where a fault becomes effective or an effective fault becomes faulty due to the activation of the first auxiliary module 120 can all be classified as soft faults. Therefore, when testing the chip with a test voltage greater than or equal to the chip's operating voltage, if a fault point with the first auxiliary module 120 disabled becomes effective when the first auxiliary module 120 is enabled, then that fault point is a soft fault.

[0072] After completing the test, shut down the first auxiliary module 120.

[0073] Step S03: Activate the second auxiliary module to test the chip with multiple different test voltages and obtain a third test result containing failure bit information.

[0074] In this step, the second auxiliary module 130 is activated, and the storage module 110 is tested again under multiple test voltages to obtain the third test result. The third test result includes the valid or invalid information of each storage unit under each test voltage, as well as the location information of the storage unit when it is invalid.

[0075] Because the second auxiliary module 130 is activated, under the same test voltage as in step S01, a position that was originally ineffective may become effective, or a position that was originally effective may become ineffective.

[0076] The positions of these valid and invalid changes are not the same as those when the first auxiliary module 120 is turned on, but they are still considered soft failures. This is because the first auxiliary module 120 and the second auxiliary module 130 are the word line WL compensation module and the bit line BL compensation module, respectively. Therefore, the test results obtained when the first auxiliary module 120 and the second auxiliary module 130 are turned on are not exactly the same.

[0077] After completing the test, shut down the second auxiliary module 130.

[0078] Step S04: Turn on the first auxiliary module and the second auxiliary module, test the chip with multiple different test voltages, and obtain a fourth test result containing failure bit information.

[0079] In this step, the first auxiliary module 120 and the second auxiliary module 130 are activated simultaneously to perform tests on the storage module 110 under multiple test voltages again to obtain a fourth test result. The fourth test result includes the validity or invalidity information of each storage unit under each test voltage, as well as the location information of the storage unit when it is invalid.

[0080] Since the first auxiliary module 120 and the second auxiliary module 130 are activated simultaneously, the test results obtained under the same test voltage as in steps S01-S03 are not exactly the same.

[0081] Step S05: Compare and analyze at least two of the first to fourth test results, and classify the failure points according to the cause of failure.

[0082] In this step, failure points are classified by comparing and analyzing information from at least two of the first to fourth test results.

[0083] For example, if a storage unit fails in all tests from steps S01 to S04, the failure point is classified as a hard failure. If a storage unit sometimes fails and sometimes functions in the tests from steps S01 to S04, the failure point is classified as a soft failure. Furthermore, based on whether the failure point functions when the first auxiliary module 120 and / or the second auxiliary module 130 is activated, the failure point can be specifically classified as a write failure or a read failure.

[0084] Furthermore, since the test results also include the overall yield of storage units, storage blocks, and storage cells, comparative analysis is conducted to determine whether the yield difference between at least two test results is greater than a threshold when the first auxiliary module 120 and / or the second auxiliary module 130 are turned on and off, and the test is performed at a test voltage greater than the chip's operating voltage. If the yield difference is greater than or equal to the threshold, then the proportion of failures caused by soft failures in the chip's failure points is relatively large; if the yield difference is less than the threshold, then the proportion of failures caused by hard failures in the chip's failure points is relatively large.

[0085] Furthermore, after determining that it is a soft failure, the cause of the failure point can be further classified as a read failure or a write failure by determining whether the first auxiliary module 120 or the second auxiliary module 130 is activated. For example, if the yield difference is greater than or equal to the threshold and the first auxiliary module 120 is activated, then the failure point of the chip is a read failure or write failure corresponding to the first auxiliary module 120 in the soft failure category. That is, when the first auxiliary module 120 is a bit line BL auxiliary module, it is a read failure. If the yield difference is greater than or equal to the threshold and the second auxiliary module 130 is activated, then the failure point of the chip is a write failure or read failure corresponding to the second auxiliary module 130 in the soft failure category. That is, when the second auxiliary module 130 is a word line WL auxiliary module, it is a write failure.

[0086] Figure 7 A schematic diagram of the power management module in a chip failure type test circuit according to an embodiment of the present invention is shown.

[0087] refer to Figure 7 The power management module includes at least four power supplies: VDDP1, VDDP2, VDDP3, and VDDC. The power management module is connected to the memory unit under test via switch S2. Additionally, the auxiliary module is also connected to the power management module via switch S1, and to the memory unit under test via both switches S1 and S2. During testing, the aforementioned power supplies are set to a high level.

[0088] Among them, VDDP1 is the interface power (IO power), VDDP2 is the macrocircuit power, VDDP3 is the word line power (macro WL power), and VDDC is the macroarray power. A first auxiliary module 120 and a second auxiliary module 130 are set in the peripheral area of ​​the power management module. During testing, the first auxiliary module 120 and / or the second auxiliary module 130 are selected to be provided to the currently tested storage unit by controlling switches S1 and S2.

[0089] The chip failure testing method and test circuit of this application include a first auxiliary module and a second auxiliary module. When the first auxiliary module and / or the second auxiliary module are turned on or off, the chip is tested with different test voltages, and the failure bit information and failure ratio (yield) under column mode test are obtained. By comparing the impact of turning the first auxiliary module and / or the second auxiliary module on the chip yield, it is determined whether the chip failure is a soft failure or a hard failure, thereby providing direction for chip improvement.

[0090] Furthermore, when the first auxiliary module and / or the second auxiliary module are enabled, certain compensations will be made for the causes of soft failures in the chip, thereby reducing the number of soft failures. Therefore, by analyzing whether the storage units in the chip exhibit failures under different states, the causes of chip failures can be classified. At the same time, depending on the type of auxiliary module enabled, the causes of soft failures can be further classified into read failures or write failures, thus providing more detailed guidance for chip improvement.

[0091] Finally, it should be noted that the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance. The embodiments described above, as per the implementation of this application, do not exhaustively describe all details, nor do they limit the application to only the specific embodiments described. Clearly, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of this application, thereby enabling those skilled in the art to make good use of this application and modifications based on it. This application is limited only by the claims and their full scope and equivalents.

Claims

1. A chip failure type testing method, comprising: testing the chip with a plurality of different test voltages to obtain a first test result containing failure bit information, the plurality of different test voltages including at least one test voltage less than a working voltage of the chip, a test voltage equal to the working voltage of the chip, and at least one test voltage greater than the working voltage of the chip; turning on a first auxiliary module, testing the chip with a plurality of different test voltages to obtain a second test result containing failure bit information, the first auxiliary module being one of a bit line auxiliary module and a word line auxiliary module; wherein, when the chip is tested with a test voltage greater than or equal to the working voltage of the chip, if a failure point under the first auxiliary module is valid when the first auxiliary module is turned on, the failure point belongs to soft failure.

2. The test method of claim 1, wherein, After the step of turning on the first auxiliary module, testing the chip with a plurality of different test voltages to obtain a second test result containing failure bit information, further comprising: turning on a second auxiliary module, testing the chip with a plurality of different test voltages to obtain a third test result containing failure bit information.

3. The test method of claim 2, wherein, After the step of turning on the second auxiliary module, testing the chip with a plurality of different test voltages to obtain a third test result containing failure bit information, further comprising: turning on the first auxiliary module and the second auxiliary module, testing the chip with a plurality of different test voltages to obtain a fourth test result containing failure bit information; comparing and analyzing at least two of the first test result to the fourth test result to classify the failure points according to failure causes.

4. The test method of claim 3, wherein, The second auxiliary module is the other of the bit line auxiliary module and the word line auxiliary module.

5. The test method of claim 4, wherein, The failure causes include soft failure and hard failure, and the soft failure includes read failure and write failure.

6. The test method of claim 5, wherein, The first test result to the fourth test result further includes yield rates of the chip under different storage sizes.

7. The test method of claim 6, wherein, The step of comparing and analyzing at least two of the first test result to the fourth test result to classify the failure points according to failure causes includes: determining whether a yield rate difference in the test result is greater than a threshold value when the chip is tested with a test voltage greater than the working voltage of the chip with the first auxiliary module and / or the second auxiliary module turned on and turned off; if the yield rate difference in the test result is greater than or equal to the threshold value, a proportion of the failure points of the chip with soft failure as the failure cause is large; if the yield rate difference in the test result is less than the threshold value, a proportion of the failure points of the chip with hard failure as the failure cause is large.

8. The test method of claim 7, wherein, After the step of determining that the yield rate difference in the test result is greater than or equal to the threshold value, further comprising: determining whether the first auxiliary module or the second auxiliary module is turned on; if the yield rate difference is greater than or equal to the threshold value and the first auxiliary module is turned on, the failure points of the chip have read failure or write failure corresponding to the first auxiliary module as the soft failure. If the yield difference is greater than or equal to the threshold value and the second auxiliary module is turned on, the failure cause of the failure point of the chip is a write failure or a read failure corresponding to the second auxiliary module in the soft failure.

9. A chip failure type test circuit for performing the test method of any one of claims 1-8, the test circuit comprising: a storage module; a first auxiliary module connected to one of the bit line and the word line, compensating for the voltage of the bit line or the word line during the test of the storage module; wherein a first test result is obtained when the first auxiliary module is turned off at a plurality of different test voltages, and a second test result is obtained when the first auxiliary module is turned on at a plurality of different test voltages.

10. The test circuit of claim 9, wherein, Further comprising: a second auxiliary module connected to the other of the bit line or the word line, compensating for the voltage of the bit line or the word line during the test of the storage module, a third test result is obtained when the second auxiliary module is turned on at a plurality of different test voltages; a fourth test result is obtained when the first auxiliary module and the second auxiliary module are both turned on at a plurality of different test voltages.

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