Verification method, device, system and equipment of low-power consumption scheme and storage medium

Abstract

The application discloses a low-power-consumption scheme verification method, device, system, equipment and storage medium, and relates to the chip technical field. The method comprises the following steps: acquiring a low-power-consumption scheme; bypassing, by a software module, a write operation on a register of a PMU in a chip based on the low-power-consumption scheme, generating and sending a first request signal to a subsystem; bypassing, by the software module, a read operation on the register of the PMU, receiving a first response signal sent by the subsystem; and determining that the low-power-consumption scheme passes the verification in a case where the first response signal meets a preset state. The method can bypass the read and write operations on the register of the PMU, directly generate and send a request signal to the subsystem, and read a response signal returned by the subsystem, thereby realizing verification of the low-power-consumption scheme. The method avoids the problem of low verification efficiency caused by a long access path in the prior art, and achieves the technical effect of accelerating the verification speed of the low-power-consumption scheme.

Description

Technical Field

[0001] This application relates to the field of chip technology, and in particular to a verification method, apparatus, system, device, and storage medium for a low-power solution. Background Technology

[0002] In related technologies, the verification process of low power solutions may include the following steps: (1) Based on the low power solution, the HOST sends a write instruction to the CPU (Central Processing Unit) of the chip via HSIO (High-Speed ​​Input / Output Interface), and then the CPU writes data to the register in the PMU (Power Management Unit) through the internal bus, thereby requesting the subsystem to power on or off; (2) Based on the low power solution, the HOST sends a read instruction to the CPU of the chip via HSIO, and then the CPU reads the data in the register in the PMU, thereby obtaining the response signal sent by the subsystem; (3) If the response signal meets the preset state, the low power solution is verified.

[0003] However, since the above instructions need to go through the HSIO->CPU->PMU path, the access path is too long, which leads to the problem of low efficiency in low-power solution verification. Summary of the Invention

[0004] This application provides a method, apparatus, system, device, and storage medium for verifying low-power solutions. The technical solutions provided by this application include the following aspects.

[0005] According to one aspect of the embodiments of this application, a method for verifying a low-power scheme is provided, the method comprising:

[0006] A low-power solution is obtained, which is used to power on or power off a subsystem in the chip;

[0007] Based on the low-power scheme, the software module bypasses the write operation to the register of the PMU in the chip, generates and sends a first request signal to the subsystem, and the first request signal is used to request the subsystem to power on or power off.

[0008] The software module bypasses the read operation of the PMU's register and receives the first response signal sent by the subsystem.

[0009] If the first response signal is determined to meet the preset state, the low-power scheme is determined to have passed the verification.

[0010] According to one aspect of the embodiments of this application, a verification apparatus for a low-power scheme is provided, the apparatus comprising:

[0011] An acquisition module is used to acquire a low-power scheme, which is used to power on or power off a subsystem in the chip.

[0012] The generation module is used to generate and send a first request signal to the subsystem by bypassing the write operation to the register of the PMU in the chip based on the low power scheme through the software module. The first request signal is used to request the subsystem to power on or power off.

[0013] The receiving module is used to receive the first response signal sent by the subsystem by bypassing the read operation of the PMU's register through the software module;

[0014] The determination module is used to determine that the low-power scheme has passed verification if the first response signal meets the preset state.

[0015] According to one aspect of the embodiments of this application, a verification system for a low-power scheme is provided, the system comprising: a software module and a subsystem;

[0016] The software module is used to obtain a low-power scheme, which is used to power on or power off the subsystem in the chip.

[0017] The software module is also used to bypass the write operation to the register of the PMU in the chip based on the low power scheme, generate and send a first request signal to the subsystem, the first request signal being used to request the subsystem to power on or power off;

[0018] The subsystem is used to send a first response signal to the software module;

[0019] The software module is also used to bypass the read operation of the PMU's register and receive the first response signal;

[0020] The software module is further configured to determine that the low-power scheme has passed verification if the first response signal meets the preset state.

[0021] According to one aspect of the embodiments of this application, a computer device is provided, the computer device including a processor and a memory, the memory storing a computer program, the computer program being loaded and executed by the processor to implement the verification method of the low-power scheme described above.

[0022] According to one aspect of the embodiments of this application, a computer-readable storage medium is provided, wherein a computer program is stored in the computer-readable storage medium, the computer program being loaded and executed by a processor to implement the verification method of the low-power scheme described above.

[0023] According to one aspect of the embodiments of this application, a computer program product is provided, the computer program product including a computer program stored in a computer-readable storage medium, and a processor reading from the computer-readable storage medium and executing the computer program to implement the verification method of the low-power scheme described above.

[0024] The technical solution provided in this application can bring the following beneficial effects:

[0025] It can bypass read / write operations on PMU registers, directly generate and send request signals to the subsystem, and read the returned response signals, thereby enabling the verification of low-power solutions. This avoids the problem of low verification efficiency caused by excessively long access paths in related technologies, achieving the technical effect of accelerating the verification speed of low-power solutions. Attached Figure Description

[0026] Figure 1 This is a flowchart of a verification method for a low-power scheme in one possible implementation of this application;

[0027] Figure 2 This is a schematic diagram of a chip in one possible implementation of this application;

[0028] Figure 3 This is a timing diagram of the first request signal and the first response signal in one possible implementation of this application;

[0029] Figure 4 This is a flowchart of a verification method for a low-power scheme in another possible implementation of this application;

[0030] Figure 5 This is a flowchart of a verification method for a low-power scheme in another possible implementation of this application;

[0031] Figure 6 This is a block diagram of a verification device for a low-power scheme in one possible implementation of this application;

[0032] Figure 7 This is a structural block diagram of a computer device in one possible implementation of this application. Detailed Implementation

[0033] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0034] Please refer to Figure 1 The diagram illustrates a flowchart of a verification method for a low-power scheme in one possible implementation of this application. The execution entity for each step of this method can be a computer device. The method may include at least one of the following steps 110-140.

[0035] Step 110: Obtain a low-power scheme, which is used to power on or off the subsystems in the chip.

[0036] A chip subsystem refers to a functional module within the chip that can be independently powered. Optionally, the chip may include a SoC (System on a Chip). A chip subsystem may include at least one of the following: GPU (Graphics Processing Unit), CPU, Video codec, DDR (Double Data Rate) controller, and Cache, which are not limited in this application.

[0037] Powering on a subsystem refers to the process of restoring the subsystem from a low-power state or a power-off state to a normal operating state. Powering off a subsystem is the opposite of powering on; it refers to the process of transitioning the subsystem from a normal operating state to a low-power state or a power-off state.

[0038] In some embodiments, a subsystem includes at least one node, where each node is the smallest functional unit or power domain in the subsystem that can be independently powered. When powering on or off the subsystem, the states of multiple nodes within the subsystem need to be controlled in a specific sequence to complete the state transition of the entire subsystem.

[0039] Low-power schemes are used to indicate the specific procedures for powering on or off a subsystem. Specifically, low-power schemes are used to indicate the specific procedures for powering on or off at least one node included in the subsystem, thereby enabling the subsystem to be powered on or off.

[0040] Step 120: Based on a low-power scheme, the software module bypasses the write operation to the register of the PMU in the chip, generates and sends a first request signal to the subsystem. The first request signal is used to request the subsystem to power on or power off.

[0041] In this application, the request signal (including the first request signal and the second request signal) can be denoted as IdleReq, and is used to request the subsystem to power on or off. The software module is used to simulate the interface interaction between the PMU and the subsystem. This method is a backdoor access method, that is, the software module can bypass the normal hardware function path to directly set or read the state of internal hardware signals (such as request signals and response signals).

[0042] In some embodiments, a software module, based on a low-power scheme, bypasses the write operation to the register of the power management unit (PMU) in the chip to generate and send a first request signal to the subsystem, including: generating and sending a first request signal to the subsystem based on a low-power scheme using a signal assignment function of the software module.

[0043] Optionally, the software module can be script code. Alternatively, the software module can be a DPI (Direct Programming Interface) force module. This DPI force can be constructed using the backdoor force function uvm_hdl_force (which can also be referred to as the signal assignment function in this application) of the Universal Verification Methodology (UVM) to implement the interface timing for simulating PMU power-on and power-off. Here, uvm_hdl_force refers to the function provided in the UVM verification library that can bypass the normal hardware function path to directly set or read the internal signal states of the hardware. This interface timing conforms to the AXI_LPI (Advanced eXtensible Interface - Low Power Interface) protocol.

[0044] A write operation to the PMU registers refers to a frontdoor access method, where access and control are achieved through a pre-defined functional path in the real-world operation of the chip. Specifically, the frontdoor access method involves the host sending a write command to the chip's CPU via a high-speed input / output interface (HSIO), and then the CPU writing a data value to a register at a specific address within the PMU via its internal bus, thereby driving the PMU's hardware logic to generate a request signal. However, step 120 bypasses the write operation to the PMU registers within the chip, avoiding the complete functional path from HSIO to CPU and then to PMU, and directly generating the first request signal on the signal lines connecting the subsystem. For example, as shown... Figure 2The diagram shows a schematic of chip 20 in one possible implementation of this application. A first request signal is generated and sent to subsystem 22 through the backdoor force function uvm_hdl_force (which can also be referred to as the signal assignment function in this application) of DPI force 21.

[0045] The above method can directly generate and send the first request signal to the subsystem through the signal assignment function of the software module, avoiding the problem of low verification efficiency caused by excessively long access paths in related technologies, and achieving the technical effect of accelerating the verification speed of low power solutions.

[0046] Step 130: By bypassing the read operation of the PMU register through the software module, the first response signal sent by the subsystem is received.

[0047] In some embodiments, the first response signal sent by the subsystem is received by bypassing the read operation of the PMU register through a software module, including: receiving the first response signal sent by the subsystem through the signal reading function of the software module.

[0048] Similarly, the software module can be a DPI force module. This DPI force can be constructed using the backdoor read function uvm_hdl_read (also referred to as the signal read function in this application) of the verification methodology to implement the interface timing for simulating PMU power-on and power-off. Here, uvm_hdl_read refers to the functions provided in the UVM verification library that can bypass the normal hardware function path to directly set or read the internal signal states of the hardware. This interface timing conforms to the AXI_LPI protocol.

[0049] A read operation on the PMU registers refers to a front-door access method. Similarly, a front-door access method involves the host sending a read command to the chip's CPU via HSIO, and then the CPU reading the data value of a register at a specific address within the PMU via the internal bus to obtain a response signal. However, in step 130 above, the read operation on the PMU registers can be bypassed, avoiding the complete functional path from HSIO to the CPU and then to the PMU, and instead directly reading the first response signal returned from the signal lines connecting the subsystem. For example, as... Figure 2 As shown, the first response signal sent by subsystem 22 is read through the backdoor read function uvm_hdl_read (also referred to as the signal read function in this application) of DPI force 21.

[0050] The method described above, through the signal reading function of the software module, can directly receive the first response signal sent by the subsystem. This method also avoids the problem of low verification efficiency caused by excessively long access paths in related technologies, thus achieving the technical effect of accelerating the verification speed of low-power solutions.

[0051] In some embodiments, the first response signal includes an acknowledgment signal and a status signal; wherein the acknowledgment signal is used to characterize whether the subsystem is ready to enter a low-power state, and the status signal is used to characterize whether the subsystem is in a low-power state.

[0052] In this application, the response signal can be denoted as IdleAck, and can include whether the subsystem is ready to enter a low-power state or not. A subsystem being ready to enter a low-power state means that the subsystem has received and agreed to the power-down request and has completed all preparations before executing the power-down request, indicating that it can enter the next low-power state. A subsystem not being ready to enter a low-power state means that the subsystem has not yet agreed or completed the preparations, indicating that it cannot currently enter a low-power state.

[0053] The response signal can be represented in binary. Optionally, a bit 1 can indicate readiness to enter a low-power state, while a bit 0 can indicate readiness not to enter a low-power state. Alternatively, a bit 0 can indicate readiness to enter a low-power state, while a bit 1 can indicate readiness not to enter a low-power state. This application does not limit the representation of this signal.

[0054] In this application, the state signal can be denoted as Idle, and can include whether the subsystem is in a low-power state or not, or in a non-low-power state or a normal operating state. A subsystem being in a low-power state means that the subsystem has completed its state transition and stabilized in a preset low-power mode. A subsystem not being in a low-power state means that the subsystem is in a normal operating state or a non-low-power state.

[0055] The status signal can be represented in binary. Optionally, a bit 1 can represent the state when it is in a low-power state, and a bit 0 can represent the state when it is not in a low-power state. Alternatively, a bit 0 can represent the state when it is in a low-power state, and a bit 1 can represent the state when it is not in a low-power state. This application does not limit this.

[0056] The above method improves the accuracy and reliability of subsequent verification by distinguishing the response signal into an acknowledgment signal (IdleAck) and a status signal (Idle). Specifically, the low-power handshake is a process, not an instantaneous action. Taking subsystem power-down as an example, it includes two phases: agreeing to power-down and completing power-down. By splitting the response signal into IdleAck (acknowledgment signal) and Idle (status signal), the handshake process is decoupled. IdleAck is used to verify the first phase of the handshake protocol, confirming whether the request has been successfully received and agreed upon. Idle is used to verify the second phase of the handshake protocol, confirming whether the subsystem has successfully transitioned to the target state. By first checking the IdleAck signal, verification engineers can quickly determine whether the most basic communication link is normal. If a correct IdleAck response is not received for a long time after the request is sent, engineers can immediately pinpoint the problem to the point where the request was not correctly received or processed, without waiting for the entire process to time out. Even if the IdleAck response is correct, it does not guarantee that the subsystem will ultimately successfully enter the low-power state. The Idle signal provides a final, decisive checkpoint. Only when the Idle signal also changes to the expected value can it be confirmed that the subsystem has successfully powered on or off.

[0057] Step 140: If the first response signal meets the preset state, the low-power scheme is verified.

[0058] The first response signal conforms to a preset state, indicating that the actual state of the first response signal read by the software module is consistent with the preset state.

[0059] In some embodiments, if it is determined that the first response signal does not meet the preset state, the low power scheme is adjusted to obtain the adjusted low power scheme, and the above steps 110 to 140 are performed again on the adjusted low power scheme until a verified low power scheme is obtained.

[0060] In some embodiments, determining that a low-power scheme has passed verification when the first response signal meets a preset state includes: when the first request signal is used to request the subsystem to power on, and when the response signal is used to indicate that the subsystem is not ready to enter a low-power state, and the state signal is used to indicate that the subsystem is not in a low-power state, determining that a low-power scheme has passed verification.

[0061] In some embodiments, when the first request signal is used to request the subsystem to power on, and when the response signal indicates that the subsystem is ready to enter a low-power state, and / or the status signal indicates that the subsystem is in a low-power state, the response signal and / or status signal are repeatedly acquired at least once. If the response signal and / or status signal are acquired N times, and none of the N acquired response signals and / or status signals meet the expected state described above, it is determined that the low-power scheme has failed verification. N is a positive integer, and the specific value of N can be set by the experience of the operator and is not limited here. Simultaneously, the low-power verification scheme is adjusted to obtain an adjusted low-power scheme, and steps 110-140 above are repeated on the adjusted low-power scheme until a verified low-power scheme is obtained.

[0062] In some embodiments, the subsystem includes at least one node, and the first request signal includes at least one request sub-signal, each request sub-signal being used to request power-on or power-off of a node in the subsystem. Correspondingly, the first response signal includes at least one response sub-signal. Specifically, the response signal includes at least one response sub-signal, and the status signal includes at least one status sub-signal. It is understood that one request sub-signal corresponds to one response sub-signal and one status sub-signal.

[0063] like Figure 4 As shown, for any one of the request sub-signals included in the first request signal, when the request sub-signal is used to request a node of the subsystem to power on, if the response sub-signal indicates that the node of the subsystem is not ready to enter a low-power state, and the status sub-signal indicates that the node of the subsystem is not in a low-power state, then the request sub-signal is determined to have been correctly responded to. For example, the request sub-signal can be bit 0, used to request a node of the subsystem to power on; the response sub-signal can be bit 0, used to indicate that the node of the subsystem is not ready to enter a low-power state; and the status sub-signal can also be bit 0, used to indicate that the node of the subsystem is not in a low-power state. In this case, the request sub-signal is determined to have been correctly responded to. The above operation is performed for each request sub-signal. When it is determined that all request sub-signals have been correctly responded to, the low-power scheme is determined to have passed verification.

[0064] In some embodiments, when the first request signal is used to request the subsystem to power down, and the response signal is used to indicate that the subsystem is ready to enter a low-power state, and the status signal is used to indicate that the subsystem is in a low-power state, it is determined that the low-power scheme has been verified.

[0065] Similarly, when the first request signal is used to request the subsystem to power down, and the response signal is used to indicate that the subsystem is not ready to enter a low-power state, and / or the status signal is used to indicate that the subsystem is not in a low-power state, the response signal and / or status signal are repeatedly acquired at least once. If the response signal and / or status signal are repeatedly acquired N times, and none of the N acquired response signals and / or status signals meet the above-mentioned expected state, it is determined that the low-power scheme has failed verification. At the same time, the low-power verification scheme is adjusted to obtain an adjusted low-power scheme, and steps 110 to 140 above are repeated on the adjusted low-power scheme until a verified low-power scheme is obtained.

[0066] like Figure 4 As shown, for any one of the request sub-signals included in the first request signal, when the request sub-signal is used to request a node of the subsystem to power down, if the response sub-signal indicates that the node of the subsystem is ready to enter a low-power state, and the status sub-signal indicates that the node of the subsystem is in a low-power state, then it is determined that the request sub-signal has been correctly responded to. For example, the request sub-signal can be bit 1, used to request a node of the subsystem to power down; the response sub-signal can be bit 1, used to indicate that the node of the subsystem is ready to enter a low-power state; and the status sub-signal can also be bit 1, used to indicate that the node of the subsystem is in a low-power state, then it is determined that the request sub-signal has been correctly responded to. Please refer to... Figure 3 During clock cycles 3 to 7, the request sub-signal can be bit 1 (i.e., high level) to request a node in the subsystem to power down; during clock cycles 5 to 9, the response sub-signal can also be bit 1 (i.e., high level) to indicate that the node in the subsystem is ready to enter a low-power state; during clock cycles 7 to 11, the status sub-signal can also be bit 1 (i.e., high level) to indicate that the node in the subsystem is in a low-power state, thus confirming that the request sub-signal has been correctly responded to.

[0067] Perform the above operation for each request sub-signal. Once it is determined that all request sub-signals have been responded to correctly, the low-power scheme is considered to have passed verification.

[0068] The above method improves the accuracy and reliability of verification. Specifically, this method not only checks whether the subsystem returns a response, but also precisely defines the exact states that IdleAck (acknowledgment signal) and Idle (status signal) must reach under different requests for power-on and power-off (e.g., both bit 0 or both bit 1). This precise, protocol-based judgment criterion avoids vague or incomplete checks, ensuring that verification only passes when the subsystem strictly follows the handshake protocol to complete the entire process, thus greatly improving the accuracy and reliability of the verification results. Furthermore, this method also improves debugging efficiency. Specifically, when verification fails, this explicit judgment logic provides clear failure information. For example, if a power-down request is issued (IdleReq=1, used to request the subsystem to power down), but only IdleAck=1 is received (meaning the subsystem is ready to enter a low-power state) while Idle remains at 0 (meaning the subsystem is not in a low-power state), the engineer can immediately pinpoint the problem: the subsystem agreed to the power-down request and was ready to enter a low-power state, but failed to do so. This allows the engineer to specifically debug the subsystem's internal logic.

[0069] In summary, the technical solution provided in this application can bypass the read / write operations on the PMU registers, directly generate and send request signals to the subsystem, and read the returned response signals, thereby realizing the verification of low-power solutions. This avoids the problem of low verification efficiency caused by excessively long access paths in related technologies, achieving the technical effect of accelerating the verification speed of low-power solutions.

[0070] In some embodiments, steps 150 to 180 are included after step 140. Figure 1 (Not shown in the image).

[0071] Step 150: Based on the low-power scheme, establish the mapping relationship between the first request signal and the register, and establish the mapping relationship between the first response signal and the register.

[0072] In real chip systems, powering on or off a subsystem requires reading and writing registers. Therefore, the aforementioned mapping relationship needs to be established. Establishing the mapping relationship between the first request signal and the register means associating a logic-level first request signal (i.e., IdleReq) with a specific bit in a register within the PMU. Establishing the mapping relationship between the first response signal and the register means associating a logic-level first response signal with a specific bit in a register within the PMU.

[0073] The above method, by establishing a mapping relationship between the first request signal and the register, and establishing a mapping relationship between the first response signal and the register, enables the generation of a request signal by performing a write operation on the PMU register, and enables the receipt of a response signal sent by the subsystem by performing a read operation on the PMU register, which is equivalent to realizing the power-on and power-off of the subsystem through the real PMU.

[0074] In some embodiments, step 150 includes: establishing a mapping relationship between a first request signal and a first bit of a register based on a low-power scheme, and establishing a mapping relationship between a first response signal and a second bit of a register.

[0075] In some embodiments, the mapping relationship between the first request signal and the first bit refers to associating the first request signal (i.e., IdleReq) with the first bit of a register in the PMU.

[0076] In some embodiments, the mapping relationship between the first response signal and the second bit refers to associating the first response signal (IdleAck and Idle) with the second bit of a register in the PMU.

[0077] In some embodiments, the first request signal includes at least one request sub-signal, and the first response signal includes at least one response sub-signal. Each request sub-signal is used to request the power-on or power-off of a node of the subsystem. The low-power scheme includes at least one instruction message, which indicates a write operation to a first bit of a register, or an instruction message indicates a read operation to a second bit of a register.

[0078] The first bit refers to one or more bits in the register used to generate the request signal. The second bit refers to one or more bits in the register used to reflect the status of the response signal. See Table 1 below:

[0079] Table 1

[0080]

[0081] As shown in Table 1 above, one instruction message can correspond to one row in the table. For example, based on the bit field, the first bit can be determined to include [25:21] and [18:15]. The second bit includes

[19] and [8:5].

[0082] In some embodiments, establishing a mapping relationship between a first request signal and a first bit of a register based on a low-power scheme includes: in some embodiments, establishing a mapping relationship between at least one request sub-signal and a first bit of a register based on at least one instruction information; wherein, a request sub-signal corresponds to a bit of the first bit.

[0083] In some embodiments, there is a one-to-one correspondence between the request sub-signal and a bit in the first bit position; that is, one request sub-signal corresponds to one bit position, and different request sub-signals correspond to different bits. For example, in Table 1 above, assuming it includes request sub-signals 1 to 9, and the first bit position includes bits 25 to 21, and bits 18 to 15, then the correspondence between the request sub-signals and the first bit position can be: request sub-signal 1 corresponds to bit 25, request sub-signal 2 corresponds to bit 24, ..., request sub-signal 8 corresponds to bit 16, and request sub-signal 9 corresponds to bit 15.

[0084] In some embodiments, based on a low-power scheme, establishing a mapping relationship between a first response signal and a second bit of a register includes: establishing a mapping relationship between at least one response sub-signal and a second bit of a register based on at least one instruction information; wherein, one response sub-signal corresponds to one bit of the second bit.

[0085] In some embodiments, there is a one-to-one correspondence between the response sub-signal and a bit in the second bit position; that is, one response sub-signal corresponds to one bit position, and different response sub-signals correspond to different bits. For example, in Table 1 above, assuming it includes response sub-signals 1 to 5, and the second bit position includes bit 19, and bits 8 to 5, then the correspondence between the response sub-signals and the second bit position can be: response sub-signal 1 corresponds to bit 19, response sub-signal 2 corresponds to bit 8, response sub-signal 3 corresponds to bit 7, response sub-signal 4 corresponds to bit 6, and response sub-signal 5 corresponds to bit 5.

[0086] The above method establishes a mapping relationship between the first request signal and the first bit of the register, and a mapping relationship between at least one response sub-signal and the second bit of the register, enabling the subsequent power-on and power-off of the subsystem through a real PMU module. Specifically, it allows for fine-grained control of multiple nodes within the subsystem by manipulating the corresponding first and second bits, thereby achieving the power-on and power-off of the subsystem. Furthermore, it lays the foundation for the subsequent steps of converting script code into program code (details will be provided later).

[0087] Step 160: Based on the low-power scheme and the mapping relationship between the first request signal and the register, write at least one first value into the register to generate a second request signal, which is used to request the subsystem to power on or off.

[0088] In some embodiments, step 160 includes: writing at least one first value to a first bit of a register based on a low-power scheme to generate a second request signal.

[0089] The first value can be represented in binary and can be either bit 1 or bit 0. Optionally, when at least one first value includes at least one bit 1, it is used to request the subsystem to power down; then, when at least one first value includes at least one bit 0, it is used to request the subsystem to power on. Alternatively, when at least one first value includes at least one bit 0, it is used to request the subsystem to power down; then, when at least one first value includes at least one bit 1, it is used to request the subsystem to power on. This application does not limit this.

[0090] In some embodiments, the instruction information further includes numerical information indicating a first value to be written to the first bit. Exemplarily, the numerical information includes at least one bit 0 to indicate writing at least one bit 0 to the first bit. The numerical information also includes at least one bit 1 to indicate writing at least one bit 1 to the first bit.

[0091] In some embodiments, based on a low-power scheme, writing at least one first value to the first bit of a register to generate a second request signal includes: sending a write instruction determined based on the low-power scheme to the CPU via HSIO through the HOST, the write instruction being used to instruct the writing of at least one first value to the first bit of the register; and writing at least one first value to the first bit of the register through the CPU to generate a second request signal.

[0092] HOST refers to the host, which is an external computer device used to run the script code of software modules, such as a server or workstation. HSIO refers to High-Speed ​​Input / Output Interface, which is a physical communication link used for data transmission between the HOST and the chip, such as PCIe (Peripheral Component Interconnect express) or USB (Universal Serial Bus) interfaces.

[0093] In some embodiments, the second request signal includes at least one request sub-signal. A request sub-signal is generated by the CPU writing a first value to a bit of the first bit. The first value can be bit 1 or bit 0, which is not limited in this application.

[0094] The above method, by verifying the PMU under the front-door access path, ensures the completeness of the verification. Specifically, it ensures the correctness of the entire real functional chain from the issuance of software instructions (including write and read instructions) to the CPU, and the CPU's read and write operations on registers. Secondly, it improves the reliability of the low-power solution verification results. Specifically, by implementing the power-on and power-off of the subsystem using a real PMU module, potential problems that would only surface under real system interaction can be discovered, thereby improving the reliability of the low-power solution verification results.

[0095] Specifically, the first verification and the second verification are two complementary stages in the overall verification process of this application. The first verification is a rapid verification of the low-power solution based on software modules. The second verification is a full-link hardware verification based on a complete, traditional front-door access path. The second verification scheme means that instead of "bypassing" the PMU, it verifies the low-power solution through the actual front-door access path. Specifically, it no longer uses backdoor functions (such as uvm_hdl_force), but actually writes a value to the first bit of the PMU register to generate a second request signal, and reads a value from the second bit of the PMU register to obtain a second response signal. The first verification can only ensure the logical correctness of the low-power solution at the software level, but it cannot guarantee that it is also correct on the actual hardware link. The second verification can guarantee that the low-power solution is also correct on the actual hardware link.

[0096] Step 170: Based on the low-power scheme and the mapping relationship between the first response signal and the register, read the value of the register to obtain the second response signal sent by the subsystem.

[0097] In some embodiments, step 170 above includes: reading the value of the second bit of the register based on a low-power scheme to obtain the second response signal sent by the subsystem.

[0098] Similarly, the second response signal also includes the aforementioned acknowledgement signal and status signal. Likewise, the second response signal includes at least one response sub-signal. A response sub-signal is obtained by reading the value of one bit of the second bit of the register. For more details, please refer to the corresponding description above; it will not be repeated here.

[0099] In some embodiments, the instruction information further includes numerical information, which is also used to indicate a preset value of the second response signal. It is understood that one preset value corresponds to one preset state, and different preset values ​​correspond to different preset states. Indicating a preset value for the second response signal with numerical information is equivalent to indicating a preset state of the second response signal.

[0100] Similarly, as with writing at least one first value to a register, based on a low-power scheme, reading the value of the second bit of the register to obtain the second response signal sent by the subsystem includes: sending a read instruction determined based on the low-power scheme to the CPU via HSIO through the HOST, the read instruction indicating that the value of the second bit of the register should be read; and reading the value of the second bit of the register in the PMU through the CPU to obtain the second response signal. For more details, please refer to the corresponding description above, which will not be repeated here.

[0101] Step 180: If the second response signal is found to meet the preset state, the low-power scheme is determined to have passed the secondary verification.

[0102] The process of verifying the second response signal is similar in principle to the verification process of the first response signal described above. Please refer to the corresponding description above for details, which will not be repeated here.

[0103] The above method, through secondary verification of the low-power solution, ensures the completeness of the verification. Specifically, by implementing the power-on and power-off of the subsystem using a real PMU module, potential problems that would only surface under real system interaction can be discovered, thereby improving the reliability of the low-power solution verification results. Furthermore, it significantly improves verification efficiency. By using a fast backdoor approach to iterate repeatedly on the low-power solution in the early stages of verification, the slow end-to-end simulation during the initial debugging phase is avoided, thus improving verification efficiency.

[0104] In some embodiments, steps 160 to 180 (i.e., the secondary verification process) can be performed only after determining that the first response signal meets the preset state. A fast backdoor approach (i.e., the first verification) is used first to ensure the logic of the low-power solution is correct, and then a slow frontdoor approach (i.e., the second verification) is executed to ensure the hardware link is correct.

[0105] In some embodiments, step 180 is further included after step 190. Figure 1 (Not shown in the image).

[0106] Step 190: If the second response signal meets the preset state, determine that the write instruction and read instruction have passed the verification through the link from the HOST to the CPU via HSIO, and determine that the CPU can correctly perform read and write operations on the registers in the PMU based on the write instruction and read instruction.

[0107] The above method, through the second response signal, can also verify the correctness of the front-door access link (HOST->HSIO->CPU->PMU). Specifically, the secondary verification not only confirms the correctness of the low-power scheme logic again, but also verifies step 190 above. This is because the first verification cannot detect problems on the HSIO link, errors in the CPU's register read / write instructions, or hardware defects in the PMU registers themselves. Therefore, the secondary verification ensures the correctness of the front-door access link (HOST->HSIO->CPU->PMU).

[0108] Please refer to Figure 5 The diagram illustrates a flowchart of a verification method for a low-power scheme in another possible implementation of this application. It may include the following steps 510-530.

[0109] Step 510: Bypass the PMU and verify the low-power solution through a software module. Please refer to the corresponding description above for details; it will not be repeated here.

[0110] Step 520: Convert the script code into program code; where the script code refers to the signal-based test code used to perform the first backdoor verification, and the program code refers to the register-based test code used to perform the second verification (and also corresponds to...). Figure 4 The corresponding steps in the process convert the script code into program code.

[0111] Optionally, the script code can be a SystemVerilog-based UVM verification script, and the program code can be C code.

[0112] The script code can include signal assignment and signal read functions, and the program code can include register write and register read functions. The following describes the specific implementation method for converting signal assignment and signal read functions into register write and register read functions. This can include the following steps 521-522 (…). Figure 5 (Not shown in the image).

[0113] Step 521: Based on the mapping relationship between the first request signal and the first bit of the register and the signal assignment function in the script code, a register write function is obtained; wherein, the signal assignment function is used to send the first request signal to the subsystem, and the register write function is used to write at least one first value to the first bit of the register.

[0114] In some embodiments, the signal assignment sub-function is also the backdoor forcing function uvm_hdl_force described above.

[0115] Step 521 above establishes an automated conversion process to automatically convert the signal assignment function used for backdoor verification into a register write function used for frontdoor verification. Specifically, the script code written by the verification engineer in the first stage (including the aforementioned UVM_HDL_FORCE function) and the program code needed in the second stage (e.g., the register write function) are completely different in syntax and operands. Manually performing this conversion is repetitive, tedious, and highly error-prone, especially in cases of complex low-power solutions involving numerous registers. Step 521 proposes a method for automatically converting signal assignment functions into register write functions based on a predetermined mapping relationship. This method frees verification engineers from repetitive register writing coding work, automates the verification process, and significantly improves the transition efficiency from the first verification to the second verification. Simultaneously, machine-based automatic conversion avoids errors that may be introduced by manual conversion, ensuring the consistency and reliability of the verification logic.

[0116] In some embodiments, the signal assignment function includes at least one signal assignment sub-function, each signal assignment sub-function being used to send a request sub-signal to a node of the subsystem, and the register write function includes at least one register write sub-function, each register write sub-function being used to write a first value to a bit of the first bit.

[0117] In some embodiments, the signal assignment sub-function includes a write identifier parameter, which is used to indicate the identifier information of the request sub-signal.

[0118] In some embodiments, a register write function is obtained based on the mapping relationship between the first request signal and the first bit of the register and the signal assignment function in the script code. The function includes: for any request sub-signal included in the first request signal, determining the first register identifier parameter and the first bit identifier parameter corresponding to the request sub-signal, wherein the first register identifier parameter is used to indicate the identifier information of the register corresponding to the request sub-signal and the first bit identifier parameter is used to indicate the bit corresponding to the request sub-signal; replacing the write identifier parameter with the first register identifier parameter and the first bit identifier parameter to obtain a replaced signal assignment sub-function; and obtaining the register write sub-function based on the replaced signal assignment sub-function.

[0119] Register identification information refers to an identifier that uniquely identifies a register and is used to distinguish different registers. Register identification information may include at least one of the following: register name, register address, etc., which are not limited in this application. The bit corresponding to the request sub-signal refers to the position index of a specific bit in the register used to control the request sub-signal.

[0120] In some embodiments, determining the first register identifier parameter corresponding to the request sub-signal may include the following steps: parsing a low-power scheme, finding instruction information associated with the request sub-signal, and extracting register identifier information, such as register name and register address, from the instruction information to determine the first register identifier parameter.

[0121] In some embodiments, determining the first bit identifier parameter corresponding to the request sub-signal may include the following steps: parsing a low-power scheme, finding instruction information associated with the request sub-signal, and extracting the first bit from the instruction information to determine the first bit identifier parameter.

[0122] For example, as shown below:

[0123] The signal assignment sub-function is shown below:

[0124] UVM_HDL_FORCE("tb_top.u_chip.xxx.xxx.IdleReq",0);

[0125] The register write sub-function is shown below:

[0126] reg_write(IdleReq_Register, bit_pos, 0); / / Write 0 to bit_pos in the IdleReq_Register register;

[0127] The write identifier parameter of the signal assignment subfunction is "tb_top.u_chip.xxx.xxx.IdleReq", the first register identifier parameter of the register write function is "IdleReq_Register", and the first bit identifier parameter is "bit_pos".

[0128] The above method can convert the write flag parameter into the first register flag parameter and the first bit flag parameter, thereby accurately obtaining at least one register write sub-function.

[0129] Step 522: Based on the mapping relationship between the first response signal and the second bit of the register and the signal reading function in the script code, the register reading function is obtained; wherein, the signal reading function is used to receive the first response signal, and the register reading function is used to read the value of the second bit of the register.

[0130] In some embodiments, the signal reading sub-function is also the backdoor reading function uvm_hdl_read described above.

[0131] Step 522 above establishes an automated conversion process to automatically convert the signal read function used for backdoor verification into a register read function used for frontdoor verification. Specifically, the script code written by the verification engineer in the first stage (including the aforementioned UVM_HDL_READ function) and the program code needed in the second stage (e.g., the register read function) are completely different in syntax and operands. Manually performing this conversion is repetitive, tedious, and highly error-prone, especially in cases of complex low-power solutions involving numerous registers. Step 522 proposes a method for automatically converting signal read functions into register read functions based on a predetermined mapping relationship. This method frees verification engineers from repetitive register read coding work, automates the verification process, and significantly improves the transition efficiency from the first verification to the second. Simultaneously, machine-based automatic conversion avoids errors that may be introduced by manual conversion, ensuring the consistency and reliability of the verification logic.

[0132] In some embodiments, the signal reading function includes at least one signal reading sub-function, each signal reading sub-function being used to receive a response sub-signal sent by a node of the subsystem; the register reading function includes at least one register reading sub-function, each register reading sub-function being used to read the value of one bit in the second bit; the signal reading sub-function includes a read identifier parameter, the read identifier parameter being used to indicate the identifier information of the response sub-signal.

[0133] In some embodiments, a register read function is obtained based on the mapping relationship between the first response signal and the second bit of the register and the signal read function in the script code. The function includes: for any response sub-signal included in the first response signal, determining the second register identifier parameter and the second bit identifier parameter corresponding to the response sub-signal, wherein the second register identifier parameter is used to indicate the identifier information of the register corresponding to the response sub-signal and the second bit identifier parameter is used to indicate the bit corresponding to the response sub-signal; replacing the read identifier parameter with the second register identifier parameter and the second bit identifier parameter to obtain the replaced signal read sub-function; and obtaining the register read sub-function based on the replaced signal read sub-function.

[0134] The bit corresponding to the response sub-signal refers to the position index of the specific bit in the register used to control that response sub-signal.

[0135] In some embodiments, determining the second register identifier parameter corresponding to the response sub-signal may include the following steps: parsing a low-power scheme, finding instruction information associated with the response sub-signal, and extracting register identifier information, such as register name and register address, from the instruction information to determine the second register identifier parameter.

[0136] In some embodiments, determining the second bit identifier parameter corresponding to the response sub-signal may include the following steps: parsing a low-power scheme, finding instruction information associated with the response sub-signal, and extracting the second bit from the instruction information to determine the second bit identifier parameter.

[0137] For example, the signal reading sub-function is shown below:

[0138] While(1) {

[0139] UVM_HDL_READ("tb_top.u_chip.xxx.xxx.Idle",idle); / / Reads the Idle signal of the corresponding interface "tb_top.u_chip.xxx.xxx.Idle";

[0140] UVM_HDL_READ("tb_top.u_chip.xxx.xxx.Idleack",idleack); / / Read the IdleAck signal of the corresponding interface "tb_top.u_chip.xxx.xxx.Idleack";

[0141] if(idle&&idleack == 0) { / / If both the Idle and IdleAck signals are the expected values, then the verification is successful;

[0142] print("success");

[0143] break;

[0144] };

[0145] else{

[0146] delay(1); / / If the expected value is not read, it will be read again after a delay;

[0147] };

[0148] };

[0149] The register read sub-function is shown below:

[0150] While(1) {

[0151] reg_read(Idleack_Register, bit_pos, 0); / / Query IdleAck through the front door;

[0152] reg_read(Idle_Register, bit_pos, 0); / / Query the Idle register through the front door;

[0153] if(idle&&idleack == 0){

[0154] print("success");

[0155] break;

[0156] };

[0157] else {

[0158] delay(1); / / If the expected value is not read, it will be read again after a delay;

[0159] };

[0160] };

[0161] The above method can convert the read identifier parameter into the second register identifier parameter and the second bit identifier parameter, thereby accurately obtaining at least one register read sub-function.

[0162] The method described above establishes an automated conversion process to automatically convert signal assignment and read functions used for backdoor verification into register write and read functions used for frontdoor verification. This method avoids repetitive write and read register encoding operations by verification engineers, improving the efficiency of program code conversion. Furthermore, machine-based automatic conversion avoids errors that might be introduced by manual conversion.

[0163] Step 530: Based on the program code, the power-on and power-off of the subsystem is implemented through the PMU (which also corresponds to...). Figure 4 The corresponding steps are based on program code, and the power-on and power-off of the subsystem are implemented through the PMU.

[0164] In some embodiments, program code (e.g., C code) runs on the host and generates read / write instructions. These instructions are sent to the on-chip central processing unit (CPU) via a high-speed input / output interface (HSIO). The CPU receives and executes the write and read instructions, performing read / write operations on registers within the PMU that are associated with the low-power scheme via an internal bus. Based on the state changes of its internal registers, the PMU generates corresponding request signals (e.g., IdleReq) or response signals from the read subsystem (e.g., IdleAck, Idle), thereby completing the power-on or power-off process for the subsystem.

[0165] The following are embodiments of the apparatus of this application. For details not described in the apparatus embodiments of this application, please refer to the method embodiments above.

[0166] Please refer to Figure 6This diagram illustrates a block diagram of a verification apparatus for a low-power scheme according to one possible implementation of this application. The apparatus has the function of implementing the verification method for the aforementioned low-power scheme; this function can be implemented in hardware or by hardware executing corresponding software. The apparatus 600 can be a computer device or can be installed within a computer device. The apparatus 600 may include: an acquisition module 610, a generation module 620, a receiving module 630, and a determination module 640.

[0167] The acquisition module 610 is used to acquire a low-power scheme, which is used to power on or power off the subsystem in the chip.

[0168] The generation module 620 is used to generate and send a first request signal to the subsystem by bypassing the write operation to the register of the PMU in the chip based on the low power scheme through the software module. The first request signal is used to request the subsystem to power on or power off.

[0169] The receiving module 630 is used to receive the first response signal sent by the subsystem by bypassing the read operation of the PMU's register through the software module.

[0170] The determining module 640 is used to determine that the low-power scheme has passed verification when the first response signal meets the preset state.

[0171] In some embodiments, the first response signal includes an acknowledgment signal and a status signal; wherein the acknowledgment signal is used to characterize whether the subsystem is ready to enter a low-power state, and the status signal is used to characterize whether the subsystem is in a low-power state.

[0172] In some embodiments, the determining module 640 is configured to determine that the low-power scheme has passed verification when the response signal indicates that the subsystem is not ready to enter a low-power state and the status signal indicates that the subsystem is not in a low-power state, in the case where the first request signal is used to request the subsystem to power on; or, when the first request signal is used to request the subsystem to power off, the response signal indicates that the subsystem is ready to enter a low-power state and the status signal indicates that the subsystem is in a low-power state, the determining module 640 is configured to determine that the low-power scheme has passed verification.

[0173] In some embodiments, the generation module 620 is used to generate and send the first request signal to the subsystem based on the low-power scheme using the signal assignment function of the software module; the receiving module 630 is used to receive the first response signal sent by the subsystem using the signal reading function of the software module.

[0174] In some embodiments, the device 600 further includes: a mapping module ( Figure 6 (Not shown in the image).

[0175] The mapping module is used to establish a mapping relationship between the first request signal and the register, and to establish a mapping relationship between the first response signal and the register, based on the low-power scheme.

[0176] In some embodiments, the device 600 further includes: a writing module and a reading module ( Figure 6 (Not shown in the image).

[0177] The writing module is used to write at least one first value into the register based on the low-power scheme and the mapping relationship between the first request signal and the register, so as to generate a second request signal, which is used to request the subsystem to be powered on or off.

[0178] The reading module reads the value of the register based on the low-power scheme and the mapping relationship between the first response signal and the register, in order to obtain the second response signal sent by the subsystem.

[0179] The determining module 640 is used to determine, when the second response signal meets the preset state, that the low-power scheme has passed the secondary verification.

[0180] In some embodiments, the mapping module is further configured to establish a mapping relationship between the first request signal and the first bit of the register, and to establish a mapping relationship between the first response signal and the second bit of the register, based on the low-power scheme; the writing module is further configured to write at least one first value to the first bit of the register based on the low-power scheme to generate a second request signal, the second request signal being used to request the subsystem to power on or off; the reading module is further configured to read the value of the second bit of the register based on the low-power scheme to obtain the second response signal sent by the subsystem.

[0181] In some embodiments, the first request signal includes at least one request sub-signal, and the first response signal includes at least one response sub-signal. Each request sub-signal is used to request power-on or power-off of a node of the subsystem. The low-power scheme includes at least one instruction message, which indicates a write operation to a first bit of the register, or an instruction message indicates a read operation to a second bit of the register. The mapping module is used to establish a mapping relationship between the at least one request sub-signal and the first bit of the register based on the at least one instruction message, wherein one request sub-signal corresponds to one bit of the first bit. Based on the at least one instruction message, a mapping relationship is established between the at least one response sub-signal and the second bit of the register, wherein one response sub-signal corresponds to one bit of the second bit.

[0182] In some embodiments, the write module is configured to send a write instruction determined based on the low-power scheme to the CPU via the HOST and HSIO, the write instruction indicating that at least one first value be written to the first bit of the register; and the CPU writes the at least one first value to the first bit of the register to generate the second request signal; the read module is configured to send a read instruction determined based on the low-power scheme to the CPU via the HOST and HSIO, the read instruction indicating that the value of the second bit of the register be read; and the CPU reads the value of the second bit of the register in the PMU to obtain the second response signal.

[0183] In some embodiments, the determining module 640 is further configured to, when determining that the second response signal conforms to a preset state, determine that the write instruction and the read instruction have passed verification through the link from the HOST to the CPU via the HSIO, and determine that the CPU can correctly perform read and write operations on the registers in the PMU based on the write instruction and the read instruction.

[0184] In some embodiments, the device 600 further includes a first conversion module and a second conversion module. Figure 6 (Not shown in the image).

[0185] The first conversion module is used to obtain a register write function based on the mapping relationship between the first request signal and the first bit of the register and the signal assignment function in the script code; wherein, the signal assignment function is used to send the first request signal to the subsystem, and the register write function is used to write at least one first value to the first bit of the register.

[0186] The second conversion module is used to obtain a register read function based on the mapping relationship between the first response signal and the second bit of the register and the signal read function in the script code; wherein, the signal read function is used to receive the first response signal, and the register read function is used to read the value of the second bit of the register.

[0187] In some embodiments, the first request signal includes at least one request sub-signal, each request sub-signal being used to request the power-on or power-off of a node in the subsystem; the signal assignment function includes at least one signal assignment sub-function, each signal assignment sub-function being used to send the request sub-signal to a node in the subsystem; the register write function includes at least one register write sub-function, each register write sub-function being used to write a first value to one bit of the first bit; the signal assignment sub-function includes a write identifier parameter, the write identifier parameter being used to indicate the identifier information of the request sub-signal; the first conversion module is used to, for any request sub-signal included in the first request signal, determine the first register identifier parameter and the first bit identifier parameter corresponding to the request sub-signal, the first register identifier parameter being used to indicate the identifier information of the register corresponding to the request sub-signal, and the first bit identifier parameter being used to indicate the bit corresponding to the request sub-signal; replace the write identifier parameter with the first register identifier parameter and the first bit identifier parameter to obtain a replaced signal assignment sub-function; and obtain the register write sub-function based on the replaced signal assignment sub-function.

[0188] In some embodiments, the first response signal includes at least one response sub-signal; the signal reading function includes at least one signal reading sub-function, each of which is used to receive the response sub-signal sent by a node of the subsystem; the register reading function includes at least one register reading sub-function, each of which is used to read the value of one bit in the second bit; the signal reading sub-function includes a read identifier parameter, which is used to indicate the identifier information of the response sub-signal;

[0189] The second conversion module is used to determine, for any one of the response sub-signals included in the first response signal, the second register identifier parameter and the second bit identifier parameter corresponding to the response sub-signal, wherein the second register identifier parameter is used to indicate the identifier information of the register corresponding to the response sub-signal, and the second bit identifier parameter is used to indicate the bit corresponding to the response sub-signal; replace the read identifier parameter with the second register identifier parameter and the second bit identifier parameter to obtain the replaced signal read sub-function; and obtain the register read sub-function based on the replaced signal read sub-function.

[0190] It should be noted that the apparatus provided in the above embodiments is only illustrated by the division of the above functional modules when implementing its functions. In actual applications, the above functions can be assigned to different functional modules as needed, that is, the content structure of the device can be divided into different functional modules to complete all or part of the functions described above. In addition, the apparatus and method embodiments provided in the above embodiments belong to the same concept, and the specific implementation process can be found in the method embodiments, which will not be repeated here.

[0191] The following are system embodiments of this application. For details not described in detail in the system embodiments of this application, please refer to the method embodiments above. This application provides a verification system for a low-power solution, the system comprising: software modules and subsystems.

[0192] The software module is used to obtain a low-power scheme, which is used to power on or power off the subsystems in the chip.

[0193] The software module is also used to, based on the low-power scheme, bypass the write operation to the register of the power management unit (PMU) in the chip, generate and send a first request signal to the subsystem, the first request signal being used to request the subsystem to power on or power off.

[0194] The subsystem is used to send a first response signal to the software module.

[0195] The software module is also used to bypass the read operation of the PMU's register and receive the first response signal.

[0196] The software module is further configured to determine that the low-power scheme has passed verification if the first response signal meets the preset state.

[0197] Please refer to Figure 7 The diagram shows a structural block diagram of a computer device 700 in one possible implementation of this application.

[0198] Typically, computer device 700 includes a processor 710 and a memory 720.

[0199] Processor 710 may include one or more processing cores, such as a quad-core processor, an octa-core processor, etc. Processor 710 may be implemented using at least one hardware form selected from DSP (Digital Signal Processing), FPGA (Field Programmable Gate Array), and PLA (Programmable Logic Array). Processor 710 may also include a main processor and a coprocessor. The main processor, also known as a CPU (Central Processing Unit), is used to process data in the wake-up state; the coprocessor is a low-power processor used to process data in the standby state. In some embodiments, processor 710 may integrate a GPU, which is responsible for rendering and drawing the content to be displayed on the screen. In some embodiments, processor 710 may also include an AI processor for handling computational operations related to machine learning.

[0200] The memory 720 may include one or more computer-readable storage media, which may be non-transitory. The memory 720 may also include high-speed random access memory and non-volatile memory, such as one or more disk storage devices or flash memory devices. In some embodiments, the non-transitory computer-readable storage media in the memory 720 is used to store a computer program configured to be executed by one or more processors to implement the verification method of the low-power scheme described above.

[0201] Those skilled in the art will understand that Figure 7 The structure shown does not constitute a limitation on the computer device 700, and may include more or fewer components than shown, or combine certain components, or use different component arrangements.

[0202] In some embodiments, a computer-readable storage medium is also provided, wherein a computer program is stored in the storage medium, the computer program being loaded and executed by a processor to implement the verification method of the low-power scheme described above.

[0203] Optionally, the computer-readable storage medium may include: ROM (Read-Only Memory), RAM (Random-Access Memory), SSD (Solid State Drives), or optical disc, etc. The random access memory may include ReRAM (Resistance Random Access Memory) and DRAM (Dynamic Random Access Memory).

[0204] In some embodiments, a computer program product is also provided, the computer program product including a computer program stored in a computer-readable storage medium, and a processor reading from the computer-readable storage medium and executing the computer program to implement the verification method of the low-power scheme described above.

[0205] It should be understood that "multiple" as used herein refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. Furthermore, the step numbers described herein are merely illustrative of one possible execution order. In some other embodiments, the steps may not be executed in numerical order, such as two steps with different numbers being executed simultaneously, or two steps with different numbers being executed in the reverse order of the illustration. This application does not limit this.

[0206] The above description is merely an exemplary embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A verification method for a low-power scheme, characterized in that, The method includes: A low-power solution is obtained, which is used to power on or power off a subsystem in the chip; Based on the low-power scheme, the software module bypasses the write operation to the register of the power management unit (PMU) in the chip, generates and sends a first request signal to the subsystem, and the first request signal is used to request the subsystem to power on or power off. The software module bypasses the read operation of the PMU's register and receives the first response signal sent by the subsystem. If the first response signal is determined to meet the preset state, the low-power solution is determined to have passed the verification. The software module is built using backdoor forced function and backdoor read function of the verification methodology to simulate the interface timing of PMU power-on and power-off.

2. The method according to claim 1, characterized in that, The first response signal includes an acknowledgment signal and a status signal; wherein the acknowledgment signal is used to characterize whether the subsystem is ready to enter a low-power state, and the status signal is used to characterize whether the subsystem is in a low-power state.

3. The method according to claim 2, characterized in that, The step of determining that the low-power scheme passes verification when the first response signal meets the preset state includes: When the first request signal is used to request the subsystem to power on, and the response signal indicates that the subsystem is not ready to enter a low-power state, and the status signal indicates that the subsystem is not in a low-power state, then the low-power scheme is determined to have passed verification; or, When the first request signal is used to request the subsystem to power down, and the response signal is used to indicate that the subsystem is ready to enter a low-power state, and the status signal is used to indicate that the subsystem is in a low-power state, the low-power scheme is determined to have passed verification.

4. The method according to claim 1, characterized in that, The step of generating and sending a first request signal to the subsystem via a software module, based on the low-power scheme, bypassing write operations to the registers of the power management unit (PMU) in the chip, includes: The software module generates and sends the first request signal to the subsystem based on the low-power scheme using the signal assignment function of the software module. The step of bypassing the read operation of the PMU's registers through the software module and receiving the first response signal sent by the subsystem includes: The software module receives the first response signal sent by the subsystem through its signal reading function.

5. The method according to claim 1, characterized in that, The method further includes: Based on the low-power scheme, a mapping relationship is established between the first request signal and the register, and a mapping relationship is established between the first response signal and the register.

6. The method according to claim 5, characterized in that, The method further includes: Based on the low-power scheme and the mapping relationship between the first request signal and the register, at least one first value is written to the register to generate a second request signal, which is used to request the subsystem to power on or off. Based on the low-power scheme and the mapping relationship between the first response signal and the register, the value of the register is read to obtain the second response signal sent by the subsystem; If the second response signal is determined to meet the preset state, the low-power scheme is determined to have passed the secondary verification.

7. The method according to claim 6, characterized in that, The step of establishing a mapping relationship between the first request signal and the register, and establishing a mapping relationship between the first response signal and the register based on the low-power scheme, includes: Based on the low-power scheme, a mapping relationship is established between the first request signal and the first bit of the register, and a mapping relationship is established between the first response signal and the second bit of the register; The step of writing at least one first value into the register based on the low-power scheme and the mapping relationship between the first request signal and the register to generate the second request signal includes: Based on the low-power scheme, at least one first value is written to the first bit of the register to generate the second request signal; The step of reading the value of the register based on the low-power scheme and the mapping relationship between the first response signal and the register to obtain the second response signal sent by the subsystem includes: Based on the low-power scheme, the value of the second bit of the register is read to obtain the second response signal sent by the subsystem.

8. The method according to claim 7, characterized in that, The step of writing at least one first value to the first bit of the register based on the low-power scheme to generate a second request signal includes: The host sends a write instruction to the central processing unit (CPU) via the high-speed input / output interface HSIO. The write instruction is used to instruct the writing of at least one first value to the first bit of the register. The CPU writes at least one first value to the first bit of the register to generate the second request signal; The step of reading the value of the second bit of the register based on the low-power scheme to obtain the second response signal sent by the subsystem includes: The host sends a read instruction to the CPU via the HSIO, which is determined based on the low-power scheme. The read instruction is used to indicate the value of the second bit of the register to be read. The CPU reads the value of the second bit of the register in the PMU to obtain the second response signal.

9. The method according to claim 8, characterized in that, The method further includes: If the second response signal meets the preset state, it is determined that the write instruction and the read instruction pass the verification through the link from the HOST to the CPU via the HSIO, and it is determined that the CPU can correctly perform read and write operations on the register in the PMU based on the write instruction and the read instruction.

10. The method according to claim 7, characterized in that, The method further includes: Based on the mapping relationship between the first request signal and the first bit of the register and the signal assignment function in the script code, a register write function is obtained; wherein, the signal assignment function is used to send the first request signal to the subsystem, and the register write function is used to write at least one first value to the first bit of the register; Based on the mapping relationship between the first response signal and the second bit of the register, and the signal reading function in the script code, a register reading function is obtained; wherein, the signal reading function is used to receive the first response signal, and the register reading function is used to read the value of the second bit of the register.

11. The method according to claim 10, characterized in that, The first request signal includes at least one request sub-signal, each of which is used to request a node of the subsystem to power on or power off; the signal assignment function includes at least one signal assignment sub-function, each of which is used to send the request sub-signal to a node of the subsystem; the register write function includes at least one register write sub-function, each of which is used to write a first value to one bit of the first bit. The signal assignment sub-function includes a write identifier parameter, which is used to indicate the identifier information of the request sub-signal; The register write function is obtained based on the mapping relationship between the first request signal and the first bit of the register, and the signal assignment function in the script code, including: For any one of the request sub-signals included in the first request signal, determine the first register identifier parameter and the first bit identifier parameter corresponding to the request sub-signal. The first register identifier parameter is used to indicate the identifier information of the register corresponding to the request sub-signal, and the first bit identifier parameter is used to indicate the bit corresponding to the request sub-signal. The write flag parameter is replaced with the first register flag parameter and the first bit flag parameter to obtain the replaced signal assignment subfunction; Based on the replaced signal assignment subfunction, the register write subfunction is obtained.

12. The method according to claim 10, characterized in that, The first response signal includes at least one response sub-signal; the signal reading function includes at least one signal reading sub-function, each of which is used to receive the response sub-signal sent by a node of the subsystem; the register reading function includes at least one register reading sub-function, each of which is used to read the value of one bit in the second bit. The signal reading sub-function includes a reading identifier parameter, which is used to indicate the identifier information of the response sub-signal; The register read function is obtained based on the mapping relationship between the first response signal and the second bit of the register, and the signal read function in the script code, including: For any one of the response sub-signals included in the first response signal, determine the second register identifier parameter and the second bit identifier parameter corresponding to the response sub-signal. The second register identifier parameter is used to indicate the identifier information of the register corresponding to the response sub-signal, and the second bit identifier parameter is used to indicate the bit corresponding to the response sub-signal. The read identifier parameter is replaced with the second register identifier parameter and the second bit identifier parameter to obtain the replaced signal read subfunction; Based on the replaced signal reading subfunction, the register reading subfunction is obtained.

13. A verification device for a low-power scheme, characterized in that, The device includes: An acquisition module is used to acquire a low-power scheme, which is used to power on or power off a subsystem in the chip. The generation module is used to generate and send a first request signal to the subsystem by bypassing the write operation to the register of the power management unit (PMU) in the chip based on the low power scheme through the software module. The first request signal is used to request the subsystem to power on or power off. The receiving module is used to receive the first response signal sent by the subsystem by bypassing the read operation of the PMU's register through the software module; The determination module is used to determine that the low-power scheme has passed verification when the first response signal meets the preset state; wherein, the software module is built using the backdoor forcing function and backdoor reading function of the verification methodology to simulate the interface timing of PMU power-on and power-off.

14. A verification system for a low-power scheme, characterized in that, The system includes: a software module and a subsystem; wherein, the software module is built using a backdoor forcing function and a backdoor reading function of the verification methodology, and is used to simulate the interface timing of the power management unit (PMU) power-on and power-off; The software module is used to obtain a low-power scheme, which is used to power on or power off the subsystem in the chip. The software module is also used to bypass the write operation to the register of the PMU in the chip based on the low power scheme, generate and send a first request signal to the subsystem, the first request signal being used to request the subsystem to power on or power off; The subsystem is used to send a first response signal to the software module; The software module is also used to bypass the read operation of the PMU's register and receive the first response signal; The software module is further configured to determine that the low-power scheme has passed verification if the first response signal meets the preset state.

15. A computer device, characterized in that, The computer device includes a processor and a memory, the memory storing a computer program that is loaded and executed by the processor to implement the method as claimed in any one of claims 1 to 12.

16. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, which is loaded and executed by a processor to implement the method as described in any one of claims 1 to 12.

17. A computer program product, characterized in that, The computer program product includes a computer program that is loaded and executed by a processor to implement the method as described in any one of claims 1 to 12.

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