Clock domain signal synchronization circuit and system on chip

Abstract

The invention provides a clock domain signal synchronization circuit and a system on chip, and relates to the technical field of semiconductors. The clock domain signal synchronization circuit comprises a first clock domain edge sampling module which comprises a first input end, a second input end and a first output end, the first input end is used for accessing a first clock signal of a first clock domain, and the second input end is used for accessing a second clock signal of a second clock domain; the first output end is used for receiving a first indication signal; the synchronous clock generation module comprises a third input end, a fourth input end and a second output end, the third input end is used for accessing a first indication signal, and the fourth input end is used for accessing a second clock signal; the first indication signal is used for enabling the second output end to output a synchronous clock signal for synchronizing the second clock domain signal to the first clock domain based on the second clock signal. Through the technical scheme of the invention, the time overhead for synchronizing the fast clock domain signal to the slow clock domain is shortened.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more particularly to a clock domain signal synchronization circuit and a system-on-a-chip. Background Technology

[0002] A System-on-a-Chip (SoC) is a highly integrated chip design. An asynchronous clock refers to a clock signal in an integrated circuit that has the same frequency but a different phase, or that has both frequency and phase differences. Due to the increase in asynchronous clocks within the chip, signals controlled by different asynchronous clocks are transmitted between different clock domains. In particular, when synchronizing a fast clock domain signal to a slow clock domain, at least two slow clock cycles are required to complete the synchronization process, resulting in a large overhead in synchronization time.

[0003] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0004] The purpose of this disclosure is to provide a synchronization circuit for clock domain signals and an on-chip system, which at least to some extent overcomes the problem of large synchronization time overhead when synchronizing fast clock domain signals to slow clock domains in related technologies.

[0005] Other features and advantages of this disclosure will become apparent from the following detailed description, or may be learned in part from practice of this disclosure.

[0006] According to one aspect of this disclosure, a synchronization circuit for a clock domain signal is provided, comprising: a first clock domain edge sampling module, including a first input terminal, a second input terminal, and a first output terminal, wherein the first input terminal is used to receive a first clock signal of a first clock domain, the second input terminal is used to receive a second clock signal of a second clock domain, the second clock signal is used to synchronize the first clock signal to the second clock domain to obtain a first signal, and to sample the edge of the first signal to obtain a first indication signal, and the first output terminal is used to output the first indication signal; and a synchronization clock generation module, including a third input terminal, a fourth input terminal, and a second output terminal, wherein the third input terminal is used to receive the first indication signal, the fourth input terminal is used to receive the second clock signal, and the first indication signal is used to determine a timing reference for clock domain synchronization based on the second clock signal, so that the second output terminal outputs a synchronization clock signal for synchronizing the second clock domain signal to the first clock domain based on the timing reference.

[0007] In one embodiment of this disclosure, the first clock domain edge sampling module includes: a first clock synchronization circuit, including a first input terminal, a second input terminal, and a third output terminal, wherein the first input terminal is used to receive the first clock signal, the second input terminal is used to receive the second clock signal, and the third output terminal is used to output the first signal; and a first clock sampling circuit, including a fifth input terminal, a sixth input terminal, and a first output terminal, wherein the fifth input terminal is used to receive the first signal, the sixth input terminal is used to receive the second clock signal, and the first output terminal is used to output the first indication signal.

[0008] In one embodiment of this disclosure, if the effective edge of the first clock sampling circuit is a rising edge, the edge of the first signal is the rising edge; if the effective edge of the first clock sampling circuit is a falling edge, the edge of the first signal is the falling edge.

[0009] In one embodiment of this disclosure, the synchronization clock generation module includes: a second indication signal generation circuit, including a third input terminal, a fourth input terminal, and a fourth output terminal, wherein the third input terminal is used to receive the first indication signal, the fourth input terminal is used to receive the second clock signal, and the fourth output terminal is used to output the second indication signal as the timing reference, wherein the second indication signal is an indication signal generated by triggering the first indication signal at the edge of the second clock signal; and a synchronization clock generation circuit, including a seventh input terminal, an eighth input terminal, and a second output terminal, wherein the seventh input terminal is used to receive the first clock signal, the eighth input terminal is used to receive the second indication signal, and the second output terminal is used to output the synchronization clock signal.

[0010] In one embodiment of this disclosure, the edge of the second clock signal is a rising edge or a falling edge.

[0011] In one embodiment of this disclosure, the first clock synchronization circuit includes: a multi-stage flip-flop, wherein the data input terminal of the first stage flip-flop in the multi-stage flip-flop is the first input terminal, the clock terminal of each stage flip-flop in the multi-stage flip-flop is the second input terminal, the output terminal of the previous stage flip-flop in the multi-stage flip-flop is connected to the data input terminal of the next stage flip-flop, and the output terminal of the last stage flip-flop in the multi-stage flip-flop is the third output terminal, wherein the multi-stage flip-flop is used to cascade sample the access signal of the corresponding data input terminal at the edge of the second clock signal so that the first signal is received by the output terminal of the last stage flip-flop.

[0012] In one embodiment of this disclosure, the first clock sampling circuit includes: a sampling trigger, wherein the data input terminal of the sampling trigger is the fifth input terminal, the clock terminal of the sampling trigger is the sixth input terminal, and the output terminal of the sampling trigger outputs a delayed signal, wherein the delayed signal is delayed relative to the first signal by one period of the second clock signal; and a logic gate, including a first terminal, a second terminal, and a first output terminal, wherein the first terminal is used to connect to the first signal, the second terminal is used to connect to the delayed signal, and the logic gate performs logical operations on the first signal and the delayed signal to obtain the first indication signal.

[0013] In one embodiment of this disclosure, the edge of the first signal is a falling edge, the logic gate includes a NAND gate, and the first indication signal output from the NAND gate is switched from a first level to a second level, the duration of the second level being equal to one cycle of the second clock signal.

[0014] In one embodiment of this disclosure, the second indication signal generating circuit includes: a counter having a third input terminal and a fourth input terminal, and an enable output terminal, wherein the first indication signal is used to trigger the counter to count, and the count is incremented by one every cycle of the second clock signal, and the enable output terminal outputs an enable signal when the count reaches a preset value; an inverter having the second clock signal at its input terminal and an inverted signal at its output terminal; and a clock gating system including a tenth input terminal, an eleventh input terminal, and the fourth output terminal, wherein the tenth input terminal is used to receive the enable signal, the eleventh input terminal is used to receive the inverted signal, and the clock gating system allows the inverted signal to be output when the enable signal is valid, thereby enabling the fourth output terminal to output the second indication signal synchronized with the falling edge of the second clock signal.

[0015] In one embodiment of this disclosure, the preset value satisfies n=T1 / T2, or the preset value is an integer such that the edge interval between the second indication signal and the first signal does not exceed T2 / 2, where T1 is the period of the first clock signal and T2 is the period of the second clock signal.

[0016] In one embodiment of this disclosure, the synchronous clock generation circuit includes: a D flip-flop, wherein the data input terminal and the clock terminal of the D flip-flop are the seventh input terminal and the eighth input terminal, respectively, the D flip-flop is used to sample the first clock signal based on the second indication signal, and the output terminal of the D flip-flop is connected to the sampled signal; and an OR gate, wherein the two input terminals of the OR gate are used to receive the sampled signal and the first clock signal, respectively, and the output terminal of the OR gate is the second output terminal.

[0017] In one embodiment of this disclosure, the synchronous clock generation circuit includes: a NOR gate having a seventh input terminal, an eighth input terminal, and a second output terminal, wherein the first clock signal is high or the second indicator signal is high, and the synchronous clock signal is low; when the first clock signal is low and the second indicator signal is low, the synchronous clock signal is high.

[0018] In one embodiment of this disclosure, the frequency of the first clock signal is lower than the frequency of the second clock signal.

[0019] In one embodiment of this disclosure, the second indication signal is synchronized with the falling edge of the second clock signal, and the pulse width of the second indication signal does not exceed the period of the second clock signal.

[0020] According to another aspect of this disclosure, a system-on-a-chip is provided, including: a synchronization circuit for a clock domain signal provided in the above embodiments.

[0021] The clock domain signal synchronization scheme provided in the embodiments of this disclosure involves a first clock domain edge sampling module that uses a second clock signal to synchronize the first clock signal to the second clock domain to obtain a first signal, i.e., using a fast clock to sample the slow clock at high frequency. This allows the slow clock edge to be captured within one fast clock cycle and a first indication signal to be generated. The synchronization clock generation module determines the timing reference for cross-domain synchronization based on the first indication signal and the second clock signal. This reference does not need to wait for the complete cycle of the slow clock, but instead locks the effective edge time of the slow clock at the frequency of the fast clock, thereby generating a synchronization clock signal adapted to the first clock domain, i.e., the slow clock domain, in real time. This ensures that the process from capturing the slow clock edge to generating the synchronization clock will not exceed one slow clock cycle, thus shortening the time overhead for synchronizing the fast clock domain signal to the slow clock domain. This is especially beneficial in scenarios where the frequency of the second clock signal is much higher than that of the first clock signal, thereby meeting the needs of frequent asynchronous clock domain communication in highly integrated SoCs.

[0022] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0023] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0024] Figure 1A schematic diagram of a clock domain signal synchronization circuit is shown in the related art; Figure 2 The diagram shows a signal timing diagram of a clock domain signal synchronization circuit in the related art; Figure 3 A schematic diagram of another clock domain signal synchronization circuit is shown in the related art; Figure 4 A schematic block diagram of a clock domain signal synchronization circuit is shown in an embodiment of this disclosure; Figure 5 A signal timing diagram of a synchronization circuit for another clock domain signal is shown in an embodiment of this disclosure; Figure 6 A signal timing diagram of a synchronization circuit for another clock domain signal according to an embodiment of the present disclosure is shown; Figure 7 A schematic block diagram of a synchronization circuit for another clock domain signal in an embodiment of this disclosure is shown; Figure 8 A schematic diagram of a first clock synchronization circuit according to an embodiment of the present disclosure is shown; Figure 9 A schematic diagram of a first clock sampling circuit according to an embodiment of the present disclosure is shown; Figure 10 A schematic diagram of a second indication signal generation circuit according to an embodiment of the present disclosure is shown; Figure 11 A schematic diagram of a synchronous clock generation circuit according to an embodiment of the present disclosure is shown; Figure 12 A signal timing diagram of a synchronization circuit for a clock domain signal is shown in another embodiment of this disclosure; Figure 13 A signal timing diagram of a synchronization circuit for a clock domain signal is shown in another embodiment of this disclosure; Figure 14 The following is a signal timing diagram of a synchronization circuit for a clock domain signal according to another embodiment of the present disclosure. Detailed Implementation

[0025] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, they are provided so that this disclosure will be more comprehensive and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0026] Furthermore, the accompanying drawings are merely illustrative of this disclosure and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and therefore repeated descriptions of them will be omitted. Some block diagrams shown in the drawings are functional entities and do not necessarily correspond to physically or logically independent entities. These functional entities may be implemented in software, in one or more hardware modules or integrated circuits, or in different network and / or processor devices and / or microcontroller devices.

[0027] With the continuous development of integrated circuit design and manufacturing processes, system integration has been continuously improved. System-on-a-chip (SoC), as a solution that integrates the entire system onto a single chip, is being used more and more widely. Against this backdrop, the number of asynchronous clocks inside the chip has increased accordingly. This directly leads to the signal synchronization process consuming more time and area overhead when asynchronous signals communicate across clock domains. Among them, the time overhead problem of synchronizing signals from the fast clock domain to the slow clock domain is particularly prominent. When the fast clock frequency is much higher than the slow clock frequency, for example, the fast clock is 100MHz while the slow clock is only 30KHz, and the frequency ratio is more than 1000 times, this synchronization overhead becomes exceptionally huge.

[0028] In related technologies, asynchronous signal processing methods for synchronizing fast clock domain signals to slow clock domains include two-level synchronization, handshaking, and first-in-first-out (FIFO) queues.

[0029] Two-stage synchronization is often used for synchronizing single-bit signals. Figure 1 A two-stage synchronization circuit scheme for a fast clock domain signal to a slow clock domain is shown. This circuit includes two cascaded D flip-flops. The fast clock domain signal is input to the D terminal of the first-stage D flip-flop, and the slow clock serves as the clock signal for both flip-flops. The fast clock domain signal first passes through the first-stage flip-flop for a "clock cycle," then is input to the second-stage flip-flop, ultimately outputting a synchronization signal. This two-stage flip-flop system achieves signal synchronization across clock domains.

[0030] Figure 2 The working timing of the two-stage synchronization scheme is shown. The fast clock frequency is higher and the fast clock domain signal is a single pulse signal. The slow clock frequency is lower. Under the trigger of the slow clock, the fast clock domain signal first generates a one-beat signal, and then generates a synchronization signal through the second-stage trigger. Through the two-stage trigger in timing, the synchronization of the fast clock domain signal to the slow clock domain is achieved.

[0031] Handshakes and FIFOs are commonly used for synchronizing multi-bit signals. Handshakes convert the cross-clock domain transmission of multi-bit signals into single-bit signals, synchronizing request and response signals, such as... Figure 3As shown, the sending end first sends data and pulls the request signal high (the sent data cannot be changed while the request signal is valid). The receiving end receives the request signal, receives the data (after the request signal is synchronized at least twice), and pulls the acknowledgment signal high. After the sending end receives the acknowledgment signal, it pulls the request signal low (after the acknowledgment signal is synchronized at least twice). After the receiving end receives the request signal and pulls it low, it pulls the acknowledgment signal low. The half-handshake is based on the full handshake described above, but the receiving signal is omitted.

[0032] A FIFO includes a dual-port memory and read / write pointers. The write pointer increments and writes data to the memory, while the read pointer increments and retrieves data. The read and write pointers are located in different clock domains. The pointers need to be converted to Gray code, and then synchronized to the other clock domain through two-level synchronization for empty / full determination.

[0033] The above synchronization methods all require at least two slow clock cycles for synchronization, resulting in significant time and area overhead.

[0034] Therefore, there is an urgent need for a cross-clock domain signal synchronization scheme that reduces time and area overhead.

[0035] like Figure 4 As shown, a clock domain signal synchronization circuit according to an embodiment of the present disclosure includes: The first clock domain edge sampling module 402 includes a first input terminal, a second input terminal, and a first output terminal. The first input terminal is used to receive a first clock signal from the first clock domain, the second input terminal is used to receive a second clock signal from the second clock domain, the second clock signal is used to synchronize the first clock signal to the second clock domain to obtain a first signal, and the edge of the first signal is sampled to obtain a first indication signal. The first output terminal is used to output the first indication signal.

[0036] In some embodiments, the first clock domain can be a slow clock domain, the first clock signal can be a slow clock signal, the second clock domain can be a fast clock domain, and the second clock signal can be a fast clock signal.

[0037] In some embodiments, the first clock signal is a clock signal in the slow clock domain and is asynchronous with the second clock signal in the second clock domain. The second clock signal, as the reference clock in the fast clock domain, has a higher frequency and denser edges, and can perform high-frequency sampling on the first clock signal. It can capture the edge of the slow clock within one fast clock cycle and generate a first indication signal. Through the sampling action, the first clock signal, which originally belonged to the slow clock domain, is converted into a signal adapted to the timing of the fast clock domain, namely the first signal, so as to realize the synchronization of the first clock signal to the second clock domain.

[0038] In some embodiments, the first signal is the signal after the first clock signal is synchronized to the second clock domain. Its edge changes reflect the timing characteristics of the first clock signal in the fast clock domain. By sampling the edge of the first signal, such as the rising edge or the falling edge, the level switching time of the first clock signal in the fast clock domain can be captured, thereby generating a pulse signal that characterizes the level switching event, namely the first indication signal. The first indication signal can characterize the key timing nodes of the slow clock domain signal in the fast clock domain.

[0039] The synchronization clock generation module 404 includes a third input terminal, a fourth input terminal, and a second output terminal. The third input terminal is used to receive a first indication signal, and the fourth input terminal is used to receive a second clock signal. The first indication signal is used to determine the timing reference for clock domain synchronization based on the second clock signal, so that the second output terminal outputs a synchronization clock signal to synchronize the second clock domain signal to the first clock domain based on the timing reference.

[0040] In some embodiments, since the first indication signal represents the key timing node of the slow clock domain signal in the fast clock domain, the slow clock is first synchronized to the fast clock domain through the fast clock, and then the falling edge node of the slow clock in the fast clock domain is captured. This is equivalent to marking the timing rhythm of the slow clock in the fast clock domain, so that the subsequent synchronization logic can first follow the rhythm of the slow clock, then determine the matching relationship between the fast clock period and the slow clock period, and finally generate a synchronization clock based on the matching relationship. Therefore, it can carry the timing association information between the slow clock domain and the fast clock domain. Based on the second clock signal, i.e. the fast clock, the first indication signal can be converted into a timing reference recognized by both clock domains, such as a specific moment synchronized with the edge of the fast clock. With the help of the timing reference, a synchronization clock signal that matches the timing of the slow clock domain can be generated, so that when the second clock domain signal is transmitted to the first clock domain, it is sampled under the control of the synchronization clock signal, thereby realizing cross-clock domain synchronization.

[0041] Those skilled in the art will understand that in this disclosure, slow clock, slow clock signal, and first clock signal represent the same signal, and fast clock, fast clock signal, and second clock signal represent the same signal, such as... Figure 5As shown, the slow clock is connected to the first clock domain edge sampling module as the first input terminal. It is the original clock signal to be synchronized to the second clock domain. Its edge characteristics need to be captured by the fast clock to generate a timing anchor point for cross-domain synchronization. The fast clock is connected to the first clock domain edge sampling module as the second input terminal. It is used to synchronize the first clock signal (slow clock) to the second clock domain and generate the first signal. At the same time, it provides timing drive for the edge detection of the first clock sampling circuit. The low-frequency synchronization clock is the synchronization clock signal. It is generated by the synchronization clock generation module based on the first indication signal (the fast clock domain's capture signal of the slow clock edge) and the fast clock to determine the timing reference. It is used to synchronize the second clock domain signal to the first clock domain. The level duration can cover (3-n) fast clock cycles. The frequency is consistent with the slow clock. It is the timing bridge for synchronizing the fast clock domain signal to the slow clock domain.

[0042] like Figure 6 As shown, the fast clock corresponds to the fast clock domain, and the slow clock corresponds to the slow clock domain. The fast clock domain signal can be understood as the source signal, which is the data or control signal to be synchronized generated in the fast clock domain. Its change rhythm is driven by the fast clock. The low-frequency synchronous clock is a signal generated by the synchronization circuit of the clock domain signal based on the characteristics of the fast and slow clocks. Its frequency is consistent with the slow clock, its phase difference is 180°, and its rising edge is synchronized with the rising edge of the fast clock. It can be understood as the "timing controller" for the conversion of the fast clock domain signal to the slow clock domain. The synchronization signal can be understood as the result signal, which is the signal generated after the fast clock domain signal is processed by the trigger driven by the low-frequency synchronous clock.

[0043] In this embodiment, the first clock domain edge sampling module uses the second clock signal to synchronize the first clock signal to the second clock domain to obtain the first signal, i.e., using a fast clock to sample the slow clock at high frequency. It can capture the edge of the slow clock within one fast clock cycle and generate a first indication signal. The synchronization clock generation module determines the timing reference for cross-domain synchronization based on the first indication signal and the second clock signal. This reference does not need to wait for the complete cycle of the slow clock, but locks the effective edge time of the slow clock at the frequency of the fast clock, and then generates a synchronization clock signal that is adapted to the first clock domain, i.e. the slow clock domain, in real time. This ensures that the process from capturing the edge of the slow clock to generating the synchronization clock will not exceed one slow clock cycle at most, thereby shortening the time overhead of synchronizing the fast clock domain signal to the slow clock domain. This is especially useful in scenarios where the frequency of the second clock signal is much higher than the frequency of the first clock signal, thus meeting the needs of frequent asynchronous clock domain communication in highly integrated SoCs.

[0044] Furthermore, compared to the two-stage synchronization operation used for single-bit signal synchronization, and the handshake and FIFO operation used for multi-bit signal synchronization, the clock domain signal synchronization scheme disclosed herein establishes a unified timing reference for fast and slow clock domains through a first indication signal. The generated synchronization clock can serve as a globally unified driving source. Whether it is single-bit or multi-bit, it is synchronized with the low-frequency synchronization clock. Single-bit signals are used to drive single-channel flip-flops, and multi-bit signals are multiplexed in parallel to drive multiplexed flip-flops. Therefore, it can be applied to the synchronization of both single-bit and multi-bit fast clock domain signals.

[0045] like Figure 7 As shown, in one embodiment of this disclosure, the first clock domain edge sampling module includes: The first clock synchronization circuit 702 includes a first input terminal, a second input terminal, and a third output terminal. The first input terminal is used to receive a first clock signal (slow clock), the second input terminal is used to receive a second clock signal (fast clock), and the third output terminal is used to output the first signal.

[0046] In some embodiments, the first clock synchronization circuit may include a multi-level flip-flop to construct the synchronization circuit structure. The first clock signal, i.e., the slow clock domain signal, is connected to the first input terminal as the data input of the flip-flop. The second clock signal, i.e., the fast clock domain signal, is connected to the second input terminal as the clock drive signal for all flip-flops. At each effective edge of the second clock signal, the multi-level flip-flops will cascade sample the first clock signal to gradually eliminate the metastability that may be generated by cross-clock domain transmission, so as to stably output the first signal adapted to the timing of the second clock domain from the third output terminal, thereby realizing reliable synchronization of the first clock signal to the second clock domain.

[0047] The first clock sampling circuit 704 includes a fifth input terminal, a sixth input terminal, and a first output terminal. The fifth input terminal is used to receive a first signal, the sixth input terminal is used to receive a second clock signal (fast clock), and the first output terminal is used to output a first indication signal, which can be a first pulse signal.

[0048] In some embodiments, the first clock sampling circuit 704 may include a sampling flip-flop and a variety of logic gates. The first signal connected to the fifth input terminal and the second clock signal connected to the sixth input terminal serve as the sampling clock. The sampling flip-flop can perform delayed sampling on the first signal. Combined with the logical operation of the logic gates, when an edge change of the first signal is detected, a first indication signal is generated and output from the first output terminal to complete the capture of the edge of the first signal.

[0049] In this embodiment, the first clock synchronization circuit synchronizes the first clock signal to the second clock domain, providing a stable signal (i.e., the first signal) that is adapted to the timing of the fast clock domain for subsequent edge sampling. The first clock sampling circuit performs edge detection on the first signal based on the fast clock and generates a first indication signal that marks the edge of the slow clock. The two work together to realize the operation of synchronizing the slow clock signal to the fast clock domain and extracting the slow clock edge indication. There is no need to introduce additional complex clocks or storage units. Only through the unified driving and modular cooperation of the fast clock, the reliability of signal synchronization is guaranteed and the accuracy of edge detection is achieved, which helps to reduce the hardware area of ​​the circuit.

[0050] In one embodiment of this disclosure, if the effective edge of the first clock sampling circuit is a rising edge, the edge of the first signal is a rising edge.

[0051] In some embodiments, if the sampling trigger in the first clock sampling circuit takes the rising edge of the second clock signal as the effective trigger edge, and the first signal connected to the fifth input terminal is used as the data input of the trigger, when the first signal has a rising edge, the sampling trigger will sample the first signal at the rising edge of the next most recent second clock signal, output a delayed signal delayed by one fast clock cycle, and then generate a pulse signal corresponding to the rising edge of the first signal, i.e., the first indication signal, in order to capture the rising edge of the first signal.

[0052] In one embodiment of this disclosure, if the effective edge of the first clock sampling circuit is a falling edge, the edge of the first signal is a falling edge.

[0053] In some embodiments, if the sampling flip-flop in the first clock sampling circuit sets the falling edge of the second clock signal as the valid trigger edge, and the first signal connected to the fifth input terminal is used as the data input of the flip-flop, when the first signal has a falling edge, the sampling flip-flop will sample the first signal at the moment of the falling edge of the next most recent second clock signal, output a delayed signal delayed by one fast clock cycle, and further generate a first indication signal corresponding to the falling edge of the first signal, thereby realizing the capture of the falling edge of the first signal.

[0054] like Figure 7 As shown, in one embodiment of this disclosure, the synchronization clock generation module 404 includes: The second indicator signal generation circuit 706 includes a third input terminal, a fourth input terminal, and a fourth output terminal. The third input terminal is used to receive the first indicator signal (first pulse signal), the fourth input terminal is used to receive the second clock signal (fast clock), and the fourth output terminal is used to output the second indicator signal, which can be the second pulse signal, as a timing reference. The second indicator signal is the indicator signal generated by the first indicator signal triggered by the edge of the second clock signal.

[0055] In some embodiments, the first indication signal connected to the third input terminal serves as a trigger source, and the second clock signal (fast clock) connected to the fourth input terminal serves as a timing driver. The second indication signal generation circuit, based on the cooperation of internal circuit devices, triggers the generation of an enable signal from the first indication signal. When the enable signal is valid, the second indication signal, synchronized with the edge of the fast clock, is output from the fourth output terminal based on the second clock signal. This signal carries the timing reference information required for cross-domain synchronization.

[0056] The synchronous clock generation circuit 708 includes a seventh input terminal, an eighth input terminal, and a second output terminal. The seventh input terminal is used to receive a first clock signal, the eighth input terminal is used to receive a second indication signal (i.e., a second pulse signal), and the second output terminal is used to output a synchronous clock signal (i.e., a low-frequency synchronous clock).

[0057] In some embodiments, the first clock signal (slow clock) connected to the seventh input terminal serves as the base clock source, and the second indicator signal (timing reference) connected to the eighth input terminal serves as the sampling trigger signal. The synchronous clock generation circuit can sample the first clock signal based on the effective time of the second indicator signal to capture the key timing nodes of the slow clock and output the sampled signal. The sampled signal and the first clock signal are processed to eliminate the timing gaps that may occur during the sampling process, so that the second output terminal outputs a synchronous clock signal adapted to the first clock domain (slow clock domain), ensuring that the signal can stably receive the transmission signal of the second clock domain (fast clock domain).

[0058] In this embodiment, the second indicator signal generation circuit can generate a timing reference based on the first indicator signal and the fast clock, providing a fast clock-level timing anchor point for cross-domain synchronization. The synchronization clock generation circuit can use this reference as a guide to sample and synthesize the slow clock, generating a synchronization clock that can connect to the fast clock domain signal. Through the fast clock-level timing anchor point, the effective edge of the slow clock can be locked in real time within the fast clock domain, preventing the accumulation of synchronization delay caused by the excessively long slow clock period. Furthermore, by combining the reference-guided sampling and the slow clock synthesis method, the generated synchronization clock signal can provide a stable sampling window for the fast clock domain signal.

[0059] In one embodiment of this disclosure, the edge of the second clock signal is a rising edge.

[0060] In some embodiments, the second indication signal generation circuit includes a counter and an inverter. The counter uses the rising edge of the second clock signal as the counting trigger edge. It increments the count value by one for each rising edge detected until a preset value is reached, at which point an enable signal is output. The inverter inverts the second clock signal to obtain a falling edge signal. When the enable signal is valid, only the falling edge signal is allowed to pass through, so that the second indication signal output from the fourth output terminal is synchronized with the rising edge of the second clock signal, i.e., a timing reference is generated based on the rising edge trigger.

[0061] In one embodiment of this disclosure, the edge of the second clock signal is a falling edge.

[0062] In some embodiments, in the second indication signal generation circuit, the counter uses the falling edge of the second clock signal as the counting trigger edge. The count value increases with each falling edge. After the count reaches the target, an enable signal is output. The inverter inverts the second clock signal to obtain a rising edge signal. When the enable signal is valid, only the rising edge signal is allowed to pass, so that the second indication signal at the fourth output terminal is synchronized with the falling edge of the second clock signal, that is, a timing reference is generated based on the falling edge trigger.

[0063] like Figure 8 As shown, in one embodiment of this disclosure, the first clock synchronization circuit includes: The multi-stage flip-flop 802 has a first input terminal for the data input of the first stage flip-flop, which is connected to a slow clock signal. The clock terminal of each stage flip-flop in the multi-stage flip-flop 802 is a second input terminal. The output terminal of the previous stage flip-flop in the multi-stage flip-flop 802 is connected to the data input terminal of the next stage flip-flop. The output terminal of the last stage flip-flop in the multi-stage flip-flop 802 is a third output terminal. The multi-stage flip-flop 802 is used to cascade sample the input signal of the corresponding data input terminal at the edge of the second clock signal so that the first signal can be output from the output terminal of the last stage flip-flop.

[0064] In some embodiments, the first clock synchronization circuit may include multiple D flip-flops, such as four flip-flops connected in series. The D terminal of the first flip-flop is used as the first input terminal to connect to the signal to be synchronized. The CLK terminals of all flip-flops are used as the second input terminals to connect to the second clock signal. The Q terminal of the previous flip-flop is connected to the D terminal of the next flip-flop. The Q terminal of the last flip-flop is used as the first output terminal to output the first signal. Based on the clock edge sampling characteristics of the flip-flops, each flip-flop samples the input signal at the effective edge (such as the rising edge) of the second clock signal and delays it by one clock cycle. After multiple stages are cascaded, the input signal is delayed by a clock cycle equal to the number of stages. Finally, the first output signal is strictly synchronized with the second clock signal. A single flip-flop may produce metastability due to misalignment between the signal and the clock edge. Multiple stages can significantly reduce the probability of metastability to ensure the stability of the synchronized signal.

[0065] In some embodiments, a multi-stage flip-flop structure with an enable terminal can also be used, and the sampling timing of the flip-flop can be controlled by the enable signal to flexibly adjust the working state of the synchronization circuit.

[0066] In this embodiment, by cascading sampling with multiple flip-flops, the input signal is aligned with the second clock signal in terms of timing, eliminating the metastability risk of cross-clock domain transmission. Furthermore, a controllable delay level, such as two flip-flops, achieves a delay of two T2 cycles. This ensures the predictability of signal transmission, provides a stable and synchronous input signal for subsequent circuits (such as sampling circuits), and improves the reliability of the entire timing system.

[0067] like Figure 9 As shown, in one embodiment of this disclosure, the first clock sampling circuit includes: a sampling flip-flop 902, the data input terminal of which is the fifth input terminal, the clock input terminal of which is the sixth input terminal, and the output terminal of which outputs a delayed signal, the delayed signal being a delay of one second clock signal period relative to the first signal; and a logic gate 904, including a first terminal, a second terminal, and a first output terminal, the first terminal being used to input the first signal, the second terminal being used to input the delayed signal, and the logic gate 904 performing logical operations on the first signal and the delayed signal to obtain a first indication signal.

[0068] In one embodiment of this disclosure, the edge of the first signal is a falling edge, the logic gate includes a NAND gate, and the first indication signal output from the NAND gate switches from a first level to a second level, the duration of the second level being equal to the period of a second clock signal.

[0069] In some embodiments, the first clock sampling circuit includes a D flip-flop (sampling flip-flop) and a NAND gate. The D terminal (i.e., the fifth input terminal) of the sampling flip-flop is connected to the first signal, the CLK terminal (i.e., the sixth input terminal) is connected to the second clock signal, and the Q terminal outputs a delayed signal (delayed by 1 T2 cycle compared to the first signal). The two input terminals of the NAND gate are connected to the first signal and the delayed signal, respectively, and the output terminal is the first indicator signal. When the edge of the first signal is a falling edge, the first signal is at a high level before the falling edge, and the delayed signal is still at a high level due to the delay. The NAND gate outputs a low level (i.e., the first level). After the falling edge, the first signal becomes low, and the delayed signal remains at a high level (lasting for 1 T2 cycle). The NAND gate outputs a high level (i.e., the second level). After 1 T2 cycle, the delayed signal becomes low, and the NAND gate output returns to a low level. This is to extract the edge characteristics (such as falling edge) of the first signal and convert it into a pulse signal lasting for 1 T2 cycle, i.e., the first indicator signal, which is convenient for subsequent circuits (such as counters) to identify and trigger.

[0070] Where T1 is the period of the first clock signal and T2 is the period of the second clock signal.

[0071] In some embodiments, if the edge of the first signal is a rising edge, the NAND gate can be replaced with an AND gate to generate a high-level indication signal lasting for one T2 cycle through the AND operation of the original signal and the delayed signal. Alternatively, it can be replaced with an XOR gate for applications sensitive to dual edges.

[0072] In this embodiment, the edge of the first signal, such as the falling edge, is converted into a pulse signal with a fixed width (such as one T2 cycle) by the delay function of the sampling flip-flop and the operation of the logic gate. This is the first indicator signal. The first indicator signal retains the edge timing information of the original signal and simplifies the triggering logic of the subsequent circuit by configuring the pulse width, thus ensuring the accuracy and consistency of edge detection. It is suitable as the start signal of the counter in the subsequent circuit.

[0073] like Figure 10 As shown, in one embodiment of this disclosure, the second indication signal generating circuit includes: Counter 1002 has a third input terminal and a fourth input terminal, as well as an enable output terminal. A first indicator signal is used to trigger counter 1002 to count, and the count is incremented by one every time a second clock signal cycle passes. When the count reaches a preset value, the enable output terminal outputs an enable signal.

[0074] Inverter 1004 has a second clock signal connected to its input terminal and an inverted signal connected to its output terminal.

[0075] The clock gate 1006 includes a tenth input terminal, an eleventh input terminal, and a fourth output terminal. The tenth input terminal is used to receive an enable signal, and the eleventh input terminal is used to receive an inverting signal. When the enable signal is valid, the clock gate 1006 allows the output of an inverting signal, so that the fourth output terminal outputs a second indication signal synchronized with the falling edge of the second clock signal.

[0076] In some embodiments, the second indication signal generation circuit may include a counter, an inverter, and a clock gating unit. The trigger terminal (i.e., the third input terminal) of the counter is connected to the first indication signal, and the CLK terminal (i.e., the fourth input terminal) is connected to the second clock signal. When the first indication signal is valid, counting begins, and the count increments by 1 every T2 cycle. When the preset value n is reached, a high-level enable signal is output from the enable output terminal. The inverter inverts the second clock signal (e.g., rising edge valid) into an inverted signal (i.e., falling edge valid). The control terminal (i.e., the tenth input terminal) of the clock gating unit is connected to the enable signal, and the input terminal (i.e., the eleventh input terminal) is connected to the inverted signal. When the enable signal is valid, the inverted signal is output through the gating unit to form a second indication signal synchronized with the falling edge of the second clock. The counter is used to control the timing of the generation of the second indication signal, while the inverter and the clock gating unit can ensure the synchronization of the second indication signal with the falling edge of the second clock, thereby meeting the timing requirements of the subsequent synchronization circuit.

[0077] In some embodiments, a shift register can be used instead of a counter, and the delay time can be controlled by a preset shift stage, or the gating can be triggered by a synchronous clock generated by a PLL (phase-locked loop), which helps to simplify the delay control logic.

[0078] In this embodiment, the generation timing of the second indication signal can be adapted to different timing synchronization requirements by combining the preset value n with the delay function of the counter. In addition, the cooperation between the inverter and the clock gating can ensure that the second indication signal is synchronized with the falling edge of the second clock, which is beneficial to the timing conflict caused by the asynchronous signal of the box, so that the output second indication signal has both delay controllability and clock synchronization.

[0079] In one embodiment of this disclosure, the preset value satisfies n=T1 / T2, or the preset value is an integer such that the edge interval between the second indication signal and the first signal does not exceed T2 / 2, where T1 is the period of the first clock signal and T2 is the period of the second clock signal.

[0080] In this embodiment, since there is a frequency difference between the first clock signal (period T1) and the second clock signal (period T2), the preset value n satisfies n=T1 / T2, or the edge interval is ≤T2 / 2. By limiting n, the edge of the second indicator signal can be aligned with the edge of the first signal in time. When n=T1 / T2, the second indicator signal is delayed by exactly one T1 period and synchronized with the period of the first clock signal. When the interval is ≤T2 / 2, it can be guaranteed that the second indicator signal falls within the window established by the edge of the first signal, thereby eliminating the timing deviation between clocks of different frequencies and ensuring the timing matching of the edge of the second indicator signal with the first signal, providing a reliable phase reference for the subsequent generation of the synchronization clock.

[0081] In one embodiment of this disclosure, the synchronous clock generation circuit includes: The D flip-flop has a data input terminal and a clock input terminal, which are the seventh and eighth input terminals, respectively. The D flip-flop is used to sample the first clock signal based on the second indicator signal, and the output terminal of the D flip-flop is connected to the sampled signal.

[0082] The OR gate has two inputs, which are used to receive the sampling signal and the first clock signal, respectively, and its output is the second output.

[0083] In some embodiments, the synchronous clock generation circuit includes a D flip-flop and an OR gate. The D terminal (i.e., the seventh input terminal) of the D flip-flop is connected to a first clock signal, and the CLK terminal (i.e., the eighth input terminal) is connected to a second indicator signal. The first clock signal is sampled at the effective edge of the second indicator signal, and the Q terminal outputs the sampled signal, which can retain the level state of the first clock signal. The two input terminals of the OR gate are respectively connected to the sampled signal and the first clock signal, and the output terminal is the synchronous clock signal. Specifically, when the second indicator signal is triggered, the D flip-flop samples the current level of the first clock signal and holds it. The OR gate fuses the timing characteristics of the first clock signal and the second indicator signal. If the first clock signal is high, the OR gate outputs a high level. If the first clock signal is low but the sampled signal is high, the OR gate still outputs a high level until the first clock signal becomes high again. Thus, by sampling and OR operation, the first clock signal can be forced to maintain an effective level after the second indicator signal is triggered, so as to achieve synchronization between the two.

[0084] In this embodiment, by merging the timing of the first clock signal and the second indication signal, the generated synchronous clock signal retains the periodic characteristics of the first clock signal and maintains an effective level at the critical moment when the second indication signal is triggered, thus ensuring the switching of the asynchronous clock and the stability of the obtained synchronous clock, making it suitable as a control clock for cross-clock domain data transmission.

[0085] like Figure 11 As shown, in one embodiment of this disclosure, the synchronous clock generation circuit includes: NOR gate 1102 has a seventh input terminal, an eighth input terminal, and a second output terminal. When the first clock signal is high or the second indicator signal is high, the synchronous clock signal is low. When the first clock signal is low and the second indicator signal is low, the synchronous clock signal is high.

[0086] In some embodiments, the synchronous clock generation circuit may include only one NOR gate, with two input terminals connected to a first clock signal (i.e., the seventh input terminal) and a second indicator signal (i.e., the eighth input terminal), and the output terminal being a synchronous clock signal. Specifically, when the first clock signal is high or the second indicator signal is high, the output is low; when both signals are low, the output is high. This can adapt to scenarios requiring reverse synchronization, such as when neither the first clock nor the second indicator signal is triggered, the synchronous clock starts operation, simplifying the control logic under specific timing conditions.

[0087] In this embodiment, based on the configuration of NOR gates, the reverse synchronization of the first clock signal and the second indication signal is directly achieved through logical operations, which prevents the delay and noise caused by complex circuits. The output synchronous clock signal can accurately reflect the joint state of the two input signals, which is especially suitable for scenarios that are sensitive to circuit area and power consumption, while ensuring the accuracy of timing control.

[0088] In one embodiment of this disclosure, the frequency of the first clock signal is lower than the frequency of the second clock signal.

[0089] In one embodiment of this disclosure, the second indication signal is synchronized with the falling edge of the second clock signal, and the pulse width of the second indication signal does not exceed the period of the second clock signal.

[0090] In this embodiment, by configuring the second indication signal to be synchronized with the falling edge of the second clock, the timing node of the second indication signal can be aligned with the timing node of the second clock, and the pulse width is limited to no more than T2. ​​This prevents a single indication signal from occupying multiple clock cycles and prevents interference with the timing of subsequent circuits, thereby improving the stability and reliability of the entire clock synchronization system.

[0091] In some embodiments, such as two-level synchronization, handshake, and FIFO schemes, each signal to be synchronized requires an independent multi-stage flip-flop to handle metastability. For example, if there are N cross-clock domain signals, each signal corresponding to 2 flip-flops, then 2×N flip-flops are needed. The larger N is, the more significant the increase in the area overhead of the flip-flops.

[0092] In some embodiments, based on the first clock synchronization circuit, the first clock sampling circuit, the second indicator signal generation circuit, and the synchronization clock generation circuit in this disclosure, the first clock synchronization circuit is responsible for the core synchronization of the clock domain (such as multi-level flip-flop cascade, sampling and counting control, etc.), and the number of its flip-flops is fixed (at least 4, regardless of the number of signals) and does not change with the increase of the number of signals to be synchronized.

[0093] In the synchronous clock generation circuit, each signal only needs one flip-flop to temporarily store the sampled value of the signal in the target clock domain, instead of two corresponding flip-flops. Therefore, N signals only need N flip-flops, that is, the total overhead is 4+N flip-flops, which is much less than the number of 2N flip-flops. Moreover, the more signals there are, the more obvious the area saving is.

[0094] A clock domain signal synchronization circuit according to another embodiment of the present disclosure includes: a first clock synchronization circuit, a first clock sampling circuit, a second indication signal generation circuit, and a synchronization clock generation circuit.

[0095] The first clock synchronization circuit synchronizes the slow clock to the fast clock domain through multiple levels of fast clock synchronization. The first signal is the slow clock synchronized to the fast clock domain. It includes multiple flip-flops, with the clock input of the flip-flop input being the fast clock and the data input D input being the slow clock. The data output Q after passing through multiple flip-flops is the first signal.

[0096] The first clock sampling circuit is an edge sampling circuit. It samples the falling edge of the slow clock using a fast clock, which is the falling edge of the first signal, and generates the first indication signal. The fast clock is input at the clock terminal, the first signal is input at the data input D terminal, and the first indication signal is output at the output terminal.

[0097] The second indicator signal generation circuit includes a counter, an inverter, and a clock gate. It is used to sample the fast clock by using the inverted clock of the fast clock and the falling edge of the slow clock in the fast clock domain, and generate the falling edge pulse of the fast clock. It starts counting based on the pulse characteristics of the first indicator signal. When the count reaches n fast clocks, it outputs an enable signal to enable the clock gate and generate the second indicator signal, which is the falling edge pulse signal of the fast clock.

[0098] The low-frequency synchronous clock generated by the synchronous clock generation circuit is used for synchronizing signals from the fast clock domain to the slow clock domain. It includes data logic gates, which input a slow clock and a second pulse signal, and output a low-frequency synchronous clock as the synchronous clock signal.

[0099] like Figure 12As shown, the fast clock is the second clock signal, and the slow clock is the first clock signal. The first signal is generated by cascading sampling of the slow clock by multi-stage flip-flops in the first clock synchronization circuit. The first pulse signal (i.e., the first indicator signal) is generated by sampling the falling edge of the first signal by the first clock sampling circuit. The second pulse signal (i.e., the second indicator signal) is generated by the second indicator signal generation circuit based on the first indicator signal. The low-frequency synchronization clock is generated by inputting the slow clock and the second indicator signal into the low-frequency clock generation circuit (data logic gate). Its frequency is consistent with the slow clock, and its level duration covers (3-n) fast clock cycles. It serves as a timing bridge for synchronizing the fast clock domain signal to the slow clock domain and can be directly used to drive flip-flops to transmit fast clock domain signals, ensuring stable synchronization between the output synchronization signal and the slow clock.

[0100] like Figure 13 As shown, the effective edge (rising edge) of the low-frequency synchronization clock is synchronized with the rising edge of the fast clock. The fast clock domain signal is already in a stable state before the arrival of this edge. The fast clock domain signal is immediately sampled by the low-frequency synchronization clock within one cycle of the fast clock. The synchronization time is only Tfast, which is only one cycle of the fast clock, thus realizing fast synchronization triggering in the fast clock domain and making the generation time of the synchronization signal short.

[0101] like Figure 14 As shown, the effective edge (rising edge) of the synchronous clock is significantly misaligned with the rising edge of the fast clock. The fast clock domain signal has stabilized, but the effective edge of the synchronous clock has not yet aligned with the stable range of the signal. The fast clock domain signal needs to wait for the effective edge of the synchronous clock to trigger, and sampling is not completed until it is close to one cycle of the slow clock. This results in a synchronization time of Tslow. Even if the synchronization time is Tslow, it is still lower than the synchronization time of at least two slow clock cycles in two-level synchronization, handshake, and FIFO schemes.

[0102] A system-on-chip according to an embodiment of the present disclosure includes: a synchronization circuit for a clock domain signal as described in any of the preceding embodiments.

[0103] In this embodiment, the system-on-a-chip (SoC) with the clock domain signal synchronization circuit achieves stable alignment and coordinated operation of clock signals of different frequencies (especially low-frequency control clocks and high-frequency sampling clocks) through multi-level flip-flop synchronization, precise edge sampling, programmable delay control, and logic gating. This ensures the timing accuracy and reliability of cross-clock domain signal transmission. Simultaneously, the circuit structure balances flexibility (such as preset-adjustable delay control) with low power consumption (low-frequency clocks reduce control link power consumption), adapting to the complex timing requirements of the SoC (such as high-precision sampling and logic control coordination in ultrasonic fingerprint detection). This improves the overall stability, anti-interference capability, and resource utilization efficiency of the system, providing a solid clock synchronization foundation for the high-performance operation of the SoC.

[0104] In this disclosure, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance; the term "multiple" refers to two or more unless otherwise expressly defined. The terms "install," "connect," "link," and "fix" should be interpreted broadly. For example, "connect" can be a fixed connection, a detachable connection, or an integral connection; "link" can be a direct connection or an indirect connection through an intermediate medium. Those skilled in the art can understand the specific meaning of the above terms in this disclosure according to the specific circumstances.

[0105] In the description of this disclosure, it should be understood that the terms "upper," "lower," "left," "right," "front," "rear," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this disclosure and simplifying the description, and do not indicate or imply that the device or unit referred to must have a specific orientation or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this disclosure.

[0106] In the description of this specification, the terms "one embodiment," "some embodiments," "specific embodiment," etc., refer to a specific feature, structure, material, or characteristic described in connection with that embodiment or example, which is included in at least one embodiment or example of this disclosure. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0107] The above description is merely a preferred embodiment of this disclosure and is not intended to limit the scope of this disclosure. Various modifications and variations can be made to this disclosure by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure. Other embodiments of this disclosure will be readily apparent to those skilled in the art upon consideration of the specification and practice of the disclosure herein. This disclosure is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and embodiments are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the appended claims.

Claims

1. A synchronization circuit for a clock domain signal, characterized in that, include: The first clock domain edge sampling module includes a first input terminal, a second input terminal, and a first output terminal. The first input terminal is used to receive a first clock signal of the first clock domain, the second input terminal is used to receive a second clock signal of the second clock domain, the second clock signal is used to synchronize the first clock signal to the second clock domain to obtain a first signal, and to sample the edge of the first signal to obtain a first indication signal, and the first output terminal is used to output the first indication signal. The synchronization clock generation module includes a third input terminal, a fourth input terminal, and a second output terminal. The third input terminal is used to connect to the first indication signal, and the fourth input terminal is used to connect to the second clock signal. The first indication signal is used to determine the timing reference for clock domain synchronization based on the second clock signal, so that the second output terminal outputs a synchronization clock signal to synchronize the second clock domain signal to the first clock domain based on the timing reference.

2. The synchronization circuit for the clock domain signal according to claim 1, characterized in that, The first clock domain edge sampling module includes: A first clock synchronization circuit includes a first input terminal, a second input terminal, and a third output terminal. The first input terminal is used to receive the first clock signal, the second input terminal is used to receive the second clock signal, and the third output terminal is used to output the first signal. The first clock sampling circuit includes a fifth input terminal, a sixth input terminal, and a first output terminal. The fifth input terminal is used to receive the first signal, the sixth input terminal is used to receive the second clock signal, and the first output terminal is used to output the first indication signal.

3. The synchronization circuit for the clock domain signal according to claim 2, characterized in that, If the effective edge of the first clock sampling circuit is a rising edge, then the edge of the first signal is the rising edge; If the effective edge of the first clock sampling circuit is a falling edge, then the edge of the first signal is the falling edge.

4. The synchronization circuit for the clock domain signal according to claim 1, characterized in that, The synchronization clock generation module includes: The second indication signal generation circuit includes a third input terminal, a fourth input terminal, and a fourth output terminal. The third input terminal is used to receive the first indication signal, the fourth input terminal is used to receive the second clock signal, and the fourth output terminal is used to output the second indication signal as the timing reference. The second indication signal is an indication signal generated by triggering the first indication signal at the edge of the second clock signal. The synchronous clock generation circuit includes a seventh input terminal, an eighth input terminal, and a second output terminal. The seventh input terminal is used to receive the first clock signal, the eighth input terminal is used to receive the second indication signal, and the second output terminal is used to output the synchronous clock signal.

5. The synchronization circuit for the clock domain signal according to claim 4, characterized in that, The edge of the second clock signal is either a rising edge or a falling edge.

6. The synchronization circuit for the clock domain signal according to claim 2, characterized in that, The first clock synchronization circuit includes: A multi-stage flip-flop is described, wherein the data input terminal of the first stage flip-flop is the first input terminal, the clock terminal of each stage flip-flop is the second input terminal, the output terminal of the preceding stage flip-flop is connected to the data input terminal of the following stage flip-flop, and the output terminal of the last stage flip-flop serves as the third output terminal. The multi-stage flip-flop is used to cascade the access signal of the corresponding data input terminal at the edge of the second clock signal so that the first signal can be output from the output terminal of the last stage flip-flop.

7. The synchronization circuit for the clock domain signal according to claim 2, characterized in that, The first clock sampling circuit includes: A sampling trigger, wherein the data input terminal of the sampling trigger is the fifth input terminal, the clock terminal of the sampling trigger is the sixth input terminal, and the output terminal of the sampling trigger is connected to a delayed signal, wherein the delayed signal is delayed relative to the first signal by one cycle of the second clock signal; A logic gate includes a first terminal, a second terminal, and a first output terminal. The first terminal is used to receive the first signal, and the second terminal is used to receive the delayed signal. The logic gate performs logical operations on the first signal and the delayed signal to obtain the first indication signal.

8. The synchronization circuit for the clock domain signal according to claim 7, characterized in that, The first signal has a falling edge, the logic gate includes a NAND gate, and the first indication signal output from the NAND gate switches from a first level to a second level. The duration of the second level is equal to one cycle of the second clock signal.

9. The synchronization circuit for the clock domain signal according to claim 4, characterized in that, The second indication signal generation circuit includes: The counter has the third input terminal and the fourth input terminal, and an enable output terminal. The first indication signal is used to trigger the counter to count, and the count is incremented by one every time a second clock signal cycle passes. When the count reaches a preset value, the enable output terminal outputs an enable signal. An inverter, wherein the input terminal of the inverter is connected to the second clock signal, and the output terminal of the inverter is connected to the inverted signal; The clock gating includes a tenth input terminal, an eleventh input terminal, and a fourth output terminal. The tenth input terminal is used to receive the enable signal, and the eleventh input terminal is used to receive the inverted signal. When the enable signal is valid, the clock gating allows the inverted signal to be output, so that the fourth output terminal outputs the second indication signal synchronized with the falling edge of the second clock signal.

10. The synchronization circuit for the clock domain signal according to claim 9, characterized in that, The preset value satisfies n=T1 / T2, or the preset value is an integer such that the edge interval between the second indication signal and the first signal does not exceed T2 / 2, where T1 is the period of the first clock signal and T2 is the period of the second clock signal.

11. The synchronization circuit for the clock domain signal according to claim 4, characterized in that, The synchronous clock generation circuit includes: The D flip-flop has its data input terminal and clock terminal as the seventh input terminal and the eighth input terminal, respectively. The D flip-flop is used to sample the first clock signal based on the second indication signal, and the output terminal of the D flip-flop is connected to the sampled signal. An OR gate, wherein the two inputs of the OR gate are used to receive the sampling signal and the first clock signal respectively, and the output of the OR gate is the second output.

12. The synchronization circuit for the clock domain signal according to claim 4, characterized in that, The synchronous clock generation circuit includes: The NOR gate has the seventh input terminal, the eighth input terminal, and the second output terminal. Wherein, when the first clock signal is high or the second indicator signal is high, the synchronization clock signal is low; when the first clock signal is low and the second indicator signal is low, the synchronization clock signal is high.

13. The synchronization circuit for the clock domain signal according to claim 1, characterized in that, The frequency of the first clock signal is lower than the frequency of the second clock signal.

14. The synchronization circuit for the clock domain signal according to claim 4, characterized in that, The second indication signal is synchronized with the falling edge of the second clock signal, and the pulse width of the second indication signal does not exceed the period of the second clock signal.

15. A system-on-a-chip, characterized in that, include: Synchronization circuit for clock domain signals as described in any one of claims 1 to 14.

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