Chip TSV deep hole and preparation method thereof

Abstract

The invention discloses a chip TSV (Through Silicon Via) deep hole and a preparation method thereof. The method comprises the following steps: depositing a hard mask on the surface of a silicon substrate, coating photoresist on the hard mask, forming a target hole site after exposure and development, etching the hard mask exposed at the target hole site, and forming a hole structure on the hard mask; depositing a polymer layer in the exposed pore structure; etching the polymer layer to expose the bottom surface of the hole structure; etching the silicon substrate corresponding to the bottom surface exposed in the hole structure; depositing a polymer layer on the part, exposing the pore structure, of the silicon substrate; the etching-protection process is repeated, when the etching depth reaches 80%-90% of the target depth, etching parameters are adjusted for etching until the target depth of the TSV deep hole is reached, and construction of the chip TSV deep hole is completed, the deep hole angle control precision is greatly improved, and the process adaptability is enhanced.

Description

Technical Field

[0001] This invention belongs to the field of advanced packaging technology and relates to a deep hole for chip TSV and its preparation method. Background Technology

[0002] Through-Silicon Via (TSV) technology is a core supporting technology in the field of advanced integrated circuit packaging. It involves vertically etching deep holes in a silicon substrate and filling them with conductive materials (such as copper), pushing the traditional two-dimensional planar chip packaging model towards three-dimensional integration, significantly improving system integration density and performance. TSV technology enables vertical interconnection between upper and lower layers within the chip, allowing data signals to be transmitted efficiently through shorter paths. This not only reduces signal latency and power consumption but also overcomes the physical limitations of two-dimensional packaging.

[0003] In the TSV (Through-the-Video) process, copper (Cu) plating is a core step in achieving vertical interconnects. Before plating, a copper seed layer needs to be deposited on the inner wall of the deep via to provide a conductive substrate for plating. Seed layer deposition typically employs Physical Vapor Deposition (PVD) technology, using physical processes such as evaporation or sputtering to uniformly cover the sidewalls and bottom of the deep via with copper atoms. However, the geometry of the TSV deep via (especially the sidewall tilt angle) is crucial to the PVD deposition effect: if the sidewalls are too steep (tilt angle close to 90°), the uniformity of PVD coverage will significantly decrease, resulting in thin areas or voids in the seed layer at the bottom or lower part of the sidewalls; if the sidewall tilt angle is too small (close to horizontal), although coverage can be improved, it will occupy more chip area and reduce integration density. Therefore, precise control of the deep via sidewall tilt angle is key to process optimization.

[0004] In actual production, the deep hole angle is controlled through plasma etching, requiring a balance of parameters such as etching rate, gas ratio, and power to form the required sidewall morphology. An optimized angle ensures uniform coverage of the PVD seed layer while avoiding "pinch-off" or void defects during electroplating, ensuring the density and conductivity of the copper fill. Furthermore, the quality of the seed layer affects the uniformity, adhesion, and long-term reliability of subsequent electroplating. Therefore, controlling the deep hole angle in TSV (Through-the-Vacuum) is crucial throughout the entire process from etching to deposition and electroplating, and is one of the core parameters that require strict monitoring in advanced packaging processes. As integrated circuits evolve towards smaller linewidths and higher aspect ratios, the challenges of TSV technology are increasing, with more stringent requirements for controlling deep hole angle, seed layer uniformity, and electroplating filling defects. However, current deep hole angle control processes have relatively poor precision and cannot effectively meet the application requirements. Summary of the Invention

[0005] To address the problems existing in the prior art, this invention provides a deep hole for chip TSV and its fabrication method, thereby solving the technical problem of poor controllability of deep hole angle in the prior art.

[0006] This invention is achieved through the following technical solution: A method for fabricating deep vias in a chip TSV includes the following steps: S1: A hard mask is deposited on the surface of a silicon substrate, and photoresist is coated on the hard mask. After exposure and development, the target hole is formed. The hard mask exposed by the target hole is etched to form a hole structure on the hard mask. S2: Deposit a polymer layer in the exposed porous structure; S3: Etch the polymer layer to expose the bottom surface of the pore structure; S4: Etch the silicon substrate corresponding to the exposed bottom surface in the hole structure; S5: Partially deposited polymer layer on a silicon substrate exposing a porous structure; S6: Repeat steps S3 to S5. When the etching depth reaches 80% to 90% of the target depth, adjust the parameters of steps S3 to S5 to continue etching until the target depth of the TSV deep hole is reached, thus completing the construction of the chip TSV deep hole.

[0007] Preferably, in step S1, during the etching process of the hard mask exposing the target hole, the power is 170~5000W, the bias voltage is 1100~1700W, and the single step time is 50~85s.

[0008] Preferably, in step S2, during the deposition of the polymer layer, the power is 2200~3400W, the bias voltage is 300~1000W, and the single-step time is 20~40s.

[0009] Preferably, in step S3, during the etching of the polymer layer, the power is 2000~3000W, the bias voltage is 90~150W, and the single-step time is 0.2~0.4s.

[0010] Preferably, in step S4, during the etching process of the silicon substrate corresponding to the exposed bottom surface in the hole structure, the power is 2000~3000W, the bias voltage is 20~60W, and the single step time is 0.2~0.8s.

[0011] Preferably, in step S5, during the partial deposition of the polymer layer on the silicon substrate to expose the porous structure: the power is 2000~3000W, the bias voltage is 20~40W, and the single step time is 0.3~0.8s.

[0012] Preferably, in step S6, when the etching depth reaches 80% of the target depth, the parameters of steps S3 to S5 are adjusted for etching.

[0013] Preferably, in step S6, when the etching depth reaches 80%~90% of the target depth, the parameters of steps S3~S5 are adjusted for etching. The adjustment process specifically includes: reducing the power of step S3 or step S4, increasing the bias voltage of step S3 or step S4, reducing the single-step time of step S3 or step S4, increasing the power of step S5, and reducing the bias voltage of step S5 or increasing the single-step time of step S5.

[0014] A chip TSV deep hole, which is made by the above method, has a hole sidewall inclination angle of 82°~92°.

[0015] A chip comprising a TSV deep via, the TSV deep via being fabricated by the aforementioned method for fabricating a chip TSV deep via.

[0016] Compared with the prior art, the present invention has the following beneficial technical effects: This invention discloses a method for fabricating deep vias in a chip TSV (Through-Semiconductor Via). The method first deposits a hard mask on a silicon substrate and coats it with photoresist. After exposure and development to form the target via location, the hard mask is etched to obtain the initial via structure, laying the foundation for precise positioning of the deep via. Step S2 deposits a polymer layer in the via structure to effectively protect the initial via structure formed on the hard mask. Step S3 etches the polymer layer to expose the bottom surface of the via structure. By precisely controlling the etching parameters, the polymer removal rate can be adjusted, thereby controlling the sidewall exposure time and avoiding excessive lateral etching due to prolonged exposure time. Step S4 etches the exposed silicon substrate to allow the deep via to extend downwards. Step S5 deposits a polymer layer again on the exposed via structure to suppress lateral etching. Steps S3-S5 are repeated. When the etching depth reaches 80%-90% of the target depth, the parameters are adjusted to continue etching to the target depth. This cyclical and dynamically adjusted parameter method achieves precise control of the anisotropy of silicon etching, ensuring that etching mainly proceeds along the depth direction and effectively determining the sidewall tilt trend. Meanwhile, the repeated deposition and etching of the polymer layer continuously protects the sidewalls, maintaining angular stability. Ultimately, this application can stably control the sidewall tilt angle of TSV deep holes within 82°~92°, greatly improving the accuracy of deep hole angle control and enhancing process adaptability.

[0017] Furthermore, during step S1, when etching the hard mask exposing the target hole, a power of 170~5000W can excite the etching gas to generate highly active plasma for rapid and effective etching of the hard mask. Different power levels are suitable for hard masks with different characteristics, improving versatility. A bias voltage of 1100~1700W can guide ions to bombard vertically, enhancing etching anisotropy and making the hole sidewalls more vertical. A single step time of 50~85s ensures etching depth and avoids over-etching and damage to non-target areas, improving process stability and yield.

[0018] Further, in step S2, a polymer layer is deposited. The power of 2200~3400W helps to decompose the gas and generate active groups to promote rapid, uniform and dense deposition. The bias voltage of 300~1000W controls the deposition directionality and enhances sidewall protection. The single step time of 20~40s ensures that the appropriate thickness provides protection without affecting the etching efficiency.

[0019] Furthermore, in step S3, the polymer layer is etched. A power of 2000~3000W provides energy to ensure etching selectivity, and a bias voltage of 90~150W reduces ion bombardment of the hole wall, making the etching gentle and maintaining flatness. The single step time is 0.2s~0.4s, which realizes fast and accurate etching and avoids over-etching.

[0020] Furthermore, in step S4, the silicon substrate is etched. The power of 2000~3000W is used to excite the gas to generate active species, achieving efficient and uniform etching. The bias voltage of 20~60W enhances the isotropic control of the hole shape and size accuracy in chemical etching. The single step time of 0.2~0.8s precisely controls the etching depth to ensure the stability of deep holes.

[0021] Furthermore, in step S5, a polymer layer is deposited. The power is 2000~3000W to promote rapid and uniform deposition to protect the hole walls. The bias voltage is 20~40W to make the deposition more uniform and improve the quality of the protective layer. The single step time is 0.3~0.8s to ensure that the appropriate thickness can play a protective role without affecting the process efficiency.

[0022] Furthermore, step S6 adjusts the parameters when the etching depth reaches 80% of the target depth, which can optimize the process according to the actual situation to deal with later problems and ensure that the hole parameters meet the requirements when the target depth is reached.

[0023] Furthermore, in step S6, when the etching depth reaches 80%~90% of the target depth, the parameters of steps S3~S5 are adjusted for etching. The adjustment process is as follows: reduce the power of step S3 or S4, increase the bias voltage of step S3 or S4, reduce the single-step time of step S3 or S4, increase the power of step S5, and reduce the bias voltage or increase the single-step time of step S5. When the etching depth reaches 80%~90%, the parameters are adjusted. Reducing the power of S3 or S4 slows down the etching rate to achieve fine control, increasing the bias voltage enhances ion bombardment to improve selectivity and anisotropy, reducing the single-step time avoids over-etching, increasing the power of S5 accelerates deposition to form a thick protective layer in time, reducing the bias voltage makes the deposition uniform and improves the quality of the protective layer, and increasing the single-step time ensures sufficient thickness to meet the needs of later stages and ensure the final hole quality. Attached Figure Description

[0024] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0025] Figure 1 The TSV deep hole structure provided by the present invention is shown in (a) as a scanning electron microscope image after etching without a protection process; and (b) as a scanning electron microscope image after etching-protection cycle using the etching cycle method provided by the present invention. Figure 2 The image shows a scanning electron microscope (SEM) image of a TSV deep hole obtained using the process parameters of Example 1. Figure 3 The image shows a scanning electron microscope (SEM) image of a TSV deep hole obtained using the process parameters of Example 2. Detailed Implementation

[0026] To enable those skilled in the art to understand the features and effects of the present invention, the terms and expressions used in the specification and claims are explained and defined in general below. Unless otherwise specified, all technical and scientific terms used herein have the ordinary meaning understood by those skilled in the art regarding the present invention, and in case of conflict, the definitions in this specification shall prevail.

[0027] The theories or mechanisms described and disclosed herein, whether right or wrong, should not in any way limit the scope of the invention, that is, the contents of the invention can be implemented without being limited by any particular theory or mechanism.

[0028] In this document, all features defined by numerical ranges or percentage ranges, such as numerical values, quantities, contents, and concentrations, are for the sake of brevity and convenience only. Accordingly, descriptions of numerical ranges or percentage ranges should be considered as covering and specifically disclosing all possible sub-ranges and individual numerical values ​​(including integers and fractions) within those ranges.

[0029] In this article, unless otherwise specified, “contains,” “includes,” “containing,” “has,” or similar terms cover the meanings of “composed of” and “mainly composed of,” for example, “A contains a” covers the meanings of “A contains a and others” and “A contains only a.”

[0030] For the sake of brevity, not all possible combinations of the technical features in each implementation scheme or embodiment are described herein. Therefore, as long as there is no contradiction in the combination of these technical features, the technical features in each implementation scheme or embodiment can be combined arbitrarily, and all possible combinations should be considered within the scope of this specification.

[0031] This invention discloses a method for fabricating a deep via structure for a chip TSV (Through-Shipment Via) chip. The method employs a cyclic etching process, repeatedly performing an "etch-protect" cycle, combined with dynamic parameter adjustments, to achieve precise control of the deep via angle. Specifically, it includes the following steps: S1: Hard mask fabrication A hard mask is deposited on the surface of a silicon substrate, and photoresist is coated on the hard mask. After exposure and development, the target hole positions are formed. The hard mask exposed by the target hole positions is etched to form the hole structure on the hard mask. Specifically: On the silicon substrate, i.e. the wafer surface, a layer of SiO2 is deposited as a hard mask to define the pattern of TSV deep holes; then photoresist is coated on the SiO2, and the target deep hole pattern is formed by exposure and development; finally, dry etching is performed using CF4 to transfer the photoresist pattern to the hard mask SiO2 and form the initial hole structure on the hard mask, i.e., hard mask holes, also known as hole structures. The dry etching process specifically involves using high-frequency voltage to ionize etching gases such as CF4 and Ar into plasma and fluorine radicals. High-energy ions bombard the surface, breaking the SiO2 molecular bonds and providing more reaction sites for the radicals. This process also acts as a "directionist" mechanism, making the etching more anisotropic. The combination of CF4 providing fluorine radicals and Ar ion bombardment with chemical etching is essential to significantly improve etching efficiency. A single physical or chemical mechanism is insufficient to achieve highly efficient etching.

[0032] During this etching process, CHF3 can also be used as the gas. During this etching process, the power is 1700~5000W, the bias voltage is 1100~1700W, the pressure is 8~12mT, and the single step time is 50~85s; S2: Polymer protective layer deposition Depositing a polymer layer in the exposed pore structure involves using C4F8 gas to deposit a polymer protective layer within the initial pore structure, covering the pore walls to modulate the anisotropy of subsequent etching.

[0033] The polymer protective layer can also be formed by C3F6 deposition.

[0034] In this step, the deposition power is 2200~3400W, the bias voltage is 300~1000W, the pressure is 20-100mT, and the single step time is 20~40s; S3: Cyclic Etching Process In the cyclic etching process, a cycle consists of "first etching - second etching - protection treatment," and this cycle is repeated to etch the silicon substrate until the target depth is reached. In each cycle, the deep hole angle is controlled by adjusting the power, bias voltage, and single-step time. The power affects the plasma energy, which determines the etching rate; the bias voltage affects the ion bombardment direction and intensity, which determines the anisotropy; and the single-step time determines the etching or protection depth of each step.

[0035] in, One etching step involves etching the polymer layer to expose the bottom surface of the hole structure; specifically, SF6 gas is used to etch the polymer protective layer at the bottom of the initial hole structure to expose the silicon substrate. During this process, the polymer removal rate and sidewall protection effect can be adjusted by controlling the power, bias voltage, and single-step time.

[0036] Specifically, during this etching process, the power is 2000~3000W, the bias voltage is 90~150W, and the single step time is 0.2~0.4s; Secondary etching involves etching the silicon substrate corresponding to the exposed bottom surface in the hole structure; specifically, SF6 gas is used to etch the exposed silicon substrate to extend the depth of the deep hole. In this process, by optimizing power, bias voltage and single-step time, the sidewall etching and bottom vertical etching can be balanced, and the sidewall tilt angle can be controlled.

[0037] Specifically, in this secondary etching process, the power is 2000~3000W, the bias voltage is 20~60W, and the single step time is 0.2~0.8s; The protective treatment involves depositing a polymer layer on the exposed pore structure on the silicon substrate; specifically, a polymer protective layer is deposited again using C4F8 gas to cover the newly etched sidewalls and suppress excessive lateral etching.

[0038] During this process, the thickness and uniformity of the protective layer can be controlled by adjusting the power, bias voltage, and single-step time, which indirectly adjusts the etching angle of the next cycle.

[0039] Specifically, during the protection process, the power is 2000~3000W, the bias voltage is 20~40W, and the single-step time is 0.3~0.8s; In a preferred embodiment, during the later stages of etching (i.e., when the etching depth reaches 80% to 90% of the target depth), when the deep hole approaches the target depth, the inclination angle of the deep hole sidewall can be reduced by adjusting one or more of the following parameter combinations: More preferably, when the etching depth reaches 80% of the target depth, the parameters of the cyclic etching process are adjusted for etching; the adjustment process of the parameters of the cyclic etching process specifically includes: reducing the power of the first or second etching, increasing the bias voltage of the first or second etching, reducing the single-step time of the first or second etching, increasing the power of the protection treatment, and reducing the bias voltage of the protection treatment or increasing the single-step time of the protection treatment.

[0040] Furthermore, the adjustment of the etching parameters for a single etching step is as follows: (1) Reduce the power of a single etching step to reduce the polymer removal rate and reduce the sidewall exposure time; specifically, in the later stage of etching, the power of a single etching step is preferably 1600~2400W; (2) Increasing the bias voltage of a single etching step can enhance longitudinal ion bombardment and suppress lateral etching; specifically, in the later stage of etching, the bias voltage of a single etching step is preferably 110~180W. (3) Reducing the single-step time of one etching step can shorten the polymer removal step and reduce excessive exposure of the sidewalls; specifically, in the later stage of etching, the single-step time of one etching step is preferably 0.2~0.3s; Furthermore, the adjustments to the secondary etching parameters are as follows: (1) Reducing the power of the secondary etching can reduce the silicon etching rate and reduce the lateral erosion of the sidewalls; specifically, in the later stage of etching, the power of the secondary etching is preferably 1600~2400W. (2) Increasing the bias voltage of the secondary etching can enhance the etching in the vertical direction of the ions and improve anisotropy; specifically, in the later stage of etching, the bias voltage of the secondary etching is preferably 30~70W; (3) Reduce the single-step time of the secondary etching to shorten the silicon etching steps and avoid excessive tilting of the sidewalls; specifically, in the later stage of etching, the single-step time of the secondary etching is preferably 0.1~0.6s; Furthermore, the adjustments to the protection processing parameters are as follows: (1) Increase the power of the protective treatment to improve the polymer deposition rate and thicken the sidewall protective layer. Specifically, in the later stage of etching, the power of the protective treatment is preferably 2400~3600W. (2) Reduce the bias voltage of the protective treatment to reduce the bombardment of the protective layer by ions and improve the coverage uniformity. Specifically, in the later stage of etching, the bias voltage of the protective treatment is preferably 20~30W. (3) Increasing the single-step time of the protective treatment can prolong the deposition time of the protective layer and enhance the sidewall protection effect. Specifically, in the later stage of etching, the single-step time of the protective treatment is preferably 0.4~0.9s.

[0041] In addition, the present invention also discloses a chip TSV deep hole structure obtained by the above process, wherein the tilt angle of the hole sidewall is 82°~92°. This invention utilizes a cyclic etching-protection process, combining the alternating action of SF6 etching of silicon and C4F8 polymer deposition, and leverages dynamic adjustments to power, bias voltage, and time to achieve precise control of the sidewall tilt angle of deep vias. The core of this process lies in the first etching step controlling the polymer removal rate and adjusting the sidewall exposure time; the second etching step controlling the anisotropy of silicon etching and determining the sidewall tilt trend; and the protection treatment suppressing lateral etching through polymer coverage, maintaining angle stability. Through the synergistic effect of these mechanisms, this invention solves the problems of low angle control accuracy and poor process adaptability in existing technologies, providing an efficient and reliable angle control solution for TSV 3D integration.

[0042] This invention enables quantitative adjustment of the sidewall tilt angle of deep holes through cyclic process and dynamic parameter adjustment, meeting the differentiated angle requirements of various application scenarios. The optimized sidewall angle improves the uniformity of the PVD-deposited seed layer, reduces thin areas or voids at the bottom of the hole or lower part of the sidewall, and enhances the density of subsequent electroplating filling. A uniform seed layer and dense electroplated copper filling reduce signal transmission delay and power consumption, improving the long-term reliability of the 3D integrated system.

[0043] The present invention will be further illustrated below with reference to specific embodiments. It should be understood that these embodiments are for illustrative purposes only and are not intended to limit the scope of the invention. Furthermore, it should be understood that after reading the teachings of this invention, those skilled in the art can make various alterations or modifications to the invention, and these equivalent forms also fall within the scope defined by the appended claims.

[0044] The following examples use instruments and equipment conventional in the art. Experimental methods in the following examples, unless otherwise specified, are generally performed under conventional conditions or as recommended by the manufacturer. All raw materials used in the following examples are conventional commercially available products with specifications conventional in the art. In this specification and the following examples, unless otherwise specified, "%" refers to weight percentage, "parts" refers to parts by weight, and "ratio" refers to weight proportion.

[0045] Example 1 A method for preparing a TSV deep hole includes the following steps: S1: Hard mask fabrication On a silicon substrate, i.e. the wafer surface, a layer of SiO2 is deposited as a hard mask to define the pattern of TSV deep holes; then photoresist is coated on the SiO2, and the target deep hole pattern is formed by exposure and development; finally, dry etching is performed using CF4 to transfer the photoresist pattern onto the hard mask SiO2 and form the initial hole structure on the hard mask. During this etching process, the power is 2500W, the bias voltage is 1600W, the pressure is 9mT, and the single step time is 75s. S2: Polymer protective layer deposition Depositing a polymer layer in the exposed pore structure involves using C4F8 gas to deposit a polymer protective layer within the initial pore structure, covering the pore walls to modulate the anisotropy of subsequent etching.

[0046] The deposition power in this step is 2600W, the bias voltage is 500W, the pressure is 70mT, and the single step time is 35s. S3: Cyclic Etching Process In the cyclic etching process, a cycle consists of "first etching - second etching - protection treatment," and this cycle is repeated to etch the silicon substrate until the target depth is reached. In each cycle, the deep hole angle is controlled by adjusting the power, bias voltage, and single-step time. The power affects the plasma energy, which determines the etching rate; the bias voltage affects the ion bombardment direction and intensity, which determines the anisotropy; and the single-step time determines the etching or protection depth of each step.

[0047] In this embodiment, the single-step time for the first etching is 0.35s, the power is 2500W, the bias power is 100W, and the cavity pressure is 55mT; the single-step time for the second etching is 0.3s, the power is 2500W, the bias power is 30W, and the cavity pressure is 60mT; and the single-step time for the protection treatment is 0.4s, the power is 2500W, the bias power is 30W, and the cavity pressure is 30mT.

[0048] Figure 1 The TSV deep hole structure provided by the present invention is shown in (a) as a scanning electron microscope image after etching without a protection process. As can be seen from the image, vertical stripes appear on the TSV sidewall after etching. (b) is a scanning electron microscope image after etching-protection cycle using the etching cycle method provided by the present invention. After etching-protection cycle, the vertical stripes on the TSV sidewall are significantly reduced. That is, after etching, F free radicals will damage the sidewall, causing vertical stripes to appear on the TSV sidewall. After etching-protection cycle, the vertical stripes on the TSV sidewall are significantly reduced, which shows that etching-protection cycle effectively protects the TSV sidewall from over-etching.

[0049] Figure 2 The image shows a scanning electron microscope (SEM) image of the TSV deep hole obtained using the process parameters of Example 1. As can be seen from the image, the depth of the obtained TSV deep hole is 108.3 µm, and the sidewall tilt angle is 88.3°. It is evident that the scheme of this application achieves a sidewall tilt angle of 88.3° while maintaining the TSV hole depth, and the sidewall possesses a certain tilt angle, providing favorable conditions for subsequent PVD seed layer deposition.

[0050] Example 2 A method for preparing a TSV deep hole includes the following steps: S1: Hard mask fabrication On a silicon substrate, i.e. the wafer surface, a layer of SiO2 is deposited as a hard mask to define the pattern of TSV deep holes; then photoresist is coated on the SiO2, and the target deep hole pattern is formed by exposure and development; finally, dry etching is performed using CF4 to transfer the photoresist pattern onto the hard mask SiO2 and form the initial hole structure on the hard mask. During this etching process, the power is 2400W, the bias voltage is 1200W, the pressure is 12mT, and the single step time is 60s. S2: Polymer protective layer deposition Depositing a polymer layer in the exposed pore structure involves using C4F8 gas to deposit a polymer protective layer within the initial pore structure, covering the pore walls to modulate the anisotropy of subsequent etching.

[0051] The deposition power in this step is 3000W, the bias voltage is 800W, the pressure is 80mT, and the single step time is 25s. S3: Cyclic Etching Process In the cyclic etching process, a cycle consists of "first etching - second etching - protection treatment," and this cycle is repeated to etch the silicon substrate until the target depth is reached. In each cycle, the deep hole angle is controlled by adjusting the power, bias voltage, and single-step time. The power affects the plasma energy, which determines the etching rate; the bias voltage affects the ion bombardment direction and intensity, which determines the anisotropy; and the single-step time determines the etching or protection depth of each step.

[0052] In this embodiment, the single-step time for the first etching is 0.3s, the power is 2500W, the bias power is 100W, and the cavity pressure is 55mT; the single-step time for the second etching is 0.3s, the power is 2500W, the bias power is 30W, and the cavity pressure is 60mT; the single-step time for the protection treatment is 0.45s, the power is 2500W, the bias power is 30W, and the cavity pressure is 30mT.

[0053] Figure 3The image shows a scanning electron microscope (SEM) image of the TSV deep hole obtained using the process parameters of Example 2. As can be seen from the image, the TSV deep hole depth is 110 µm and the sidewall tilt angle is 89.2°. After changing the single-step time of one etching and protection treatment, both the TSV hole depth and the sidewall tilt angle changed, indicating that the experimental method proposed in this invention can change the TSV hole depth and sidewall tilt angle by adjusting the specific experimental parameters, thus proving the feasibility of the experimental method.

[0054] Example 3 A method for fabricating deep vias in a chip TSV includes the following steps: S1: A hard mask is deposited on the surface of a silicon substrate, and photoresist is coated on the hard mask. After exposure and development, the target hole is formed. The hard mask exposed by the target hole is etched to form a hole structure on the hard mask. During the etching process of the hard mask exposed by the target hole, the power is 1700W, the bias voltage is 1100W, and the single step time is 50s. S2: Deposit a polymer layer in the exposed porous structure; during the polymer layer deposition process, the power is 2200W, the bias voltage is 300W, and the single-step time is 20s; S3: Etch the polymer layer to expose the bottom surface of the hole structure; during the etching process, the power is 2000W, the bias voltage is 90W, and the single step time is 0.2s; S4: Etch the silicon substrate corresponding to the exposed bottom surface in the hole structure; During the etching process of the silicon substrate corresponding to the exposed bottom surface in the hole structure, the power is 2000W, the bias voltage is 20W, and the single step time is 0.2s. S5: Partial deposition of a polymer layer on a silicon substrate to expose the porous structure; During the partial deposition of a polymer layer on a silicon substrate to expose the porous structure: power is 2000W, bias is 20W, and single step time is 0.3s; S6: Repeat steps S3 to S5. When the etching depth reaches 90% of the target depth, adjust the parameters of steps S3 to S5 to continue etching until the target depth of the TSV deep hole is reached, thus completing the construction of the chip TSV deep hole.

[0055] The parameters for steps S3 to S5 are adjusted during etching. For each etching step, specifically step S3, the parameter adjustments are as follows: Reduce the power of step S3 to decrease the polymer removal rate and reduce the sidewall exposure time; specifically, in the later stage of etching, the power of step S3 is preferably 1600W. Increasing the bias voltage in step S3 can enhance longitudinal ion bombardment and suppress lateral etching; specifically, the bias voltage in step S3 is preferably 110W. For the second etching step, S4, the parameter adjustments are as follows: Reducing the power of step S4 can lower the silicon etching rate and reduce lateral erosion of the sidewalls; specifically, in the later stage of etching, the power of step S4 is preferably 1600W. Increasing the bias voltage in step S4 can enhance the etching perpendicular to the ions and improve anisotropy; specifically, in the later stage of etching, the bias voltage in step S4 is preferably 30W. Reduce the single-step time of step S4 to shorten the silicon etching steps and avoid excessive sidewall tilting; specifically, in the later stage of etching, the single-step time of step S4 is preferably 0.1s. The protection process, i.e., step S5, involves adjusting the parameters as follows: Increase the power of step S5 to improve the polymer deposition rate and thicken the sidewall protective layer. Specifically, in the later stage of etching, the power of step S5 is preferably 2400W. Increasing the single-step time of step S5 can prolong the protective layer deposition time and enhance the sidewall protection effect. Specifically, in the later stage of etching, the single-step time of step S5 is preferably 0.4s.

[0056] The inclination angle of the sidewall of the TSV deep hole obtained in this embodiment is 83°.

[0057] Example 4 A method for fabricating deep vias in a chip TSV includes the following steps: S1: A hard mask is deposited on the surface of a silicon substrate, and photoresist is coated on the hard mask. After exposure and development, the target hole is formed. The hard mask exposed by the target hole is etched to form a hole structure on the hard mask. During the etching process of the hard mask exposed by the target hole, the power is 5000W, the bias voltage is 1700W, and the single step time is 85s. S2: Deposit a polymer layer in the exposed porous structure; during the polymer layer deposition process, the power is 3400W, the bias voltage is 1000W, and the single step time is 40s; S3: Etch the polymer layer to expose the bottom surface of the hole structure; during the etching process, the power is 3000W, the bias voltage is 150W, and the single step time is 0.4s; S4: Etch the silicon substrate corresponding to the exposed bottom surface in the hole structure; During the etching process of the silicon substrate corresponding to the exposed bottom surface in the hole structure, the power is 3000W, the bias voltage is 60W, and the single step time is 0.8s. S5: Partial deposition of a polymer layer on a silicon substrate to expose the porous structure; During the partial deposition of a polymer layer on a silicon substrate to expose the porous structure: power is 3000W, bias is 40W, and single step time is 0.8s; S6: Repeat steps S3 to S5. When the etching depth reaches 80% of the target depth, adjust the parameters of steps S3 to S5 to continue etching until the target depth of the TSV deep hole is reached, thus completing the construction of the chip TSV deep hole.

[0058] The parameters for steps S3 to S5 are adjusted during etching. For each etching step, specifically step S3, the parameter adjustments are as follows: Reduce the power of step S3 to decrease the polymer removal rate and reduce the sidewall exposure time; specifically, in the later stage of etching, the power of step S3 is preferably 2400W. Increasing the bias voltage in step S3 can enhance longitudinal ion bombardment and suppress lateral etching; specifically, the bias voltage in step S3 is preferably 180W. Reducing the single-step time of step S3 can shorten the polymer removal step and reduce excessive exposure of the sidewalls; specifically, in the later stage of etching, the single-step time of step S3 is preferably 0.3s. For the second etching step, S4, the parameter adjustments are as follows: Reducing the power of step S4 can lower the silicon etching rate and reduce lateral erosion of the sidewalls; specifically, in the later stage of etching, the power of step S4 is preferably 2400W. Increasing the bias voltage in step S4 can enhance the etching perpendicular to the ions and improve anisotropy; specifically, in the later stage of etching, the bias voltage in step S4 is preferably 70W. Reduce the single-step time of step S4 to shorten the silicon etching steps and avoid excessive sidewall tilting; specifically, in the later stage of etching, the single-step time of step S4 is preferably 0.6s. The protection process, i.e., step S5, involves adjusting the parameters as follows: Increase the power of step S5 to improve the polymer deposition rate and thicken the sidewall protective layer. Specifically, in the later stage of etching, the power of step S5 is preferably 3600W. Reduce the bias voltage in step S5 to reduce the bombardment of the protective layer by ions and improve the uniformity of coverage. Specifically, in the later stage of etching, the bias voltage of step S5 is preferably 30W. Increasing the single-step time of step S5 can prolong the protective layer deposition time and enhance the sidewall protection effect. Specifically, in the later stage of etching, the single-step time of step S5 is preferably 0.9s.

[0059] The inclination angle of the sidewall of the TSV deep hole obtained in this embodiment is 91°.

[0060] Example 5 A method for fabricating deep vias in a chip TSV includes the following steps: S1: A hard mask is deposited on the surface of a silicon substrate, and photoresist is coated on the hard mask. After exposure and development, the target hole positions are formed. The hard mask exposed by the target hole positions is etched to form a hole structure on the hard mask. During the etching process of the hard mask exposed by the target hole positions, the power is 2500W, the bias voltage is 1500W, and the single step time is 60s. S2: Deposit a polymer layer in the exposed porous structure; during the polymer layer deposition process, the power is 3000W, the bias voltage is 600W, and the single step time is 30s; S3: Etch the polymer layer to expose the bottom surface of the hole structure; during the etching process, the power is 2500W, the bias voltage is 100W, and the single step time is 0.3s; S4: Etch the silicon substrate corresponding to the exposed bottom surface in the hole structure; During the etching process of the silicon substrate corresponding to the exposed bottom surface in the hole structure, the power is 2500W, the bias voltage is 40W, and the single step time is 0.6s. S5: Partial deposition of a polymer layer on a silicon substrate to expose the porous structure; During the partial deposition of the polymer layer on the silicon substrate to expose the porous structure: power is 2500W, bias is 30W, and single step time is 0.5s; S6: Repeat steps S3 to S5. When the etching depth reaches 85% of the target depth, adjust the parameters of steps S3 to S5 to continue etching until the target depth of the TSV deep hole is reached, thus completing the construction of the chip TSV deep hole.

[0061] The parameters for steps S3 to S5 are adjusted during etching. For each etching step, specifically step S3, the parameter adjustments are as follows: Reduce the power of step S3 to decrease the polymer removal rate and reduce the sidewall exposure time; specifically, in the later stage of etching, the power of step S3 is preferably 2000W. Increasing the bias voltage in step S3 can enhance longitudinal ion bombardment and suppress lateral etching; specifically, the bias voltage in step S3 is preferably 130W. Reducing the single-step time of step S3 can shorten the polymer removal step and reduce excessive exposure of the sidewalls; specifically, in the later stage of etching, the single-step time of step S3 is preferably 0.25s. For the second etching step, S4, the parameter adjustments are as follows: Reducing the power of step S4 can lower the silicon etching rate and reduce lateral erosion of the sidewalls; specifically, in the later stages of etching, the power of step S4 is preferably 2000W. Increasing the bias voltage in step S4 can enhance the etching in the vertical direction of ions and improve anisotropy; specifically, in the later stage of etching, the bias voltage in step S4 is preferably 60W. Reduce the single-step time of step S4 to shorten the silicon etching steps and avoid excessive sidewall tilting; specifically, in the later stage of etching, the single-step time of step S4 is preferably 0.4s. The protection process, i.e., step S5, involves adjusting the parameters as follows: Increase the power of step S5 to improve the polymer deposition rate and thicken the sidewall protective layer. Specifically, in the later stage of etching, the power of step S5 is preferably 3000W. Reduce the bias voltage in step S5 to reduce the bombardment of the protective layer by ions and improve the uniformity of coverage. Specifically, in the later stage of etching, the bias voltage of step S5 is preferably 25W. Increasing the single-step time of step S5 can prolong the protective layer deposition time and enhance the sidewall protection effect. Specifically, in the later stage of etching, the single-step time of step S5 is preferably 0.6s.

[0062] The inclination angle of the sidewall of the TSV deep hole obtained in this embodiment is 86°.

[0063] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit the scope of protection of the present invention. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the essence and scope of the technical solutions of the present invention.

Claims

1. A method for fabricating deep vias in a chip TSV, characterized in that, Includes the following steps: S1: A hard mask is deposited on the surface of a silicon substrate, and photoresist is coated on the hard mask. After exposure and development, the target hole is formed. The hard mask exposed by the target hole is etched to form a hole structure on the hard mask. S2: Deposit a polymer layer in the exposed porous structure; S3: Etch the polymer layer to expose the bottom surface of the pore structure; S4: Etch the silicon substrate corresponding to the exposed bottom surface in the hole structure; S5: Partially deposited polymer layer on a silicon substrate exposing a porous structure; S6: Repeat steps S3 to S5. When the etching depth reaches 80% to 90% of the target depth, adjust the parameters of steps S3 to S5 to continue etching until the target depth of the TSV deep hole is reached, thus completing the construction of the chip TSV deep hole.

2. The method for fabricating a deep via of a chip TSV according to claim 1, characterized in that, In step S1, during the etching process of the hard mask exposing the target hole, the power is 170~5000W, the bias voltage is 1100~1700W, and the single step time is 50~85s.

3. The method for fabricating a deep via of a chip TSV according to claim 1, characterized in that, In step S2, during the deposition of the polymer layer, the power is 2200~3400W, the bias voltage is 300~1000W, and the single-step time is 20~40s.

4. The method for fabricating a deep via of a chip TSV according to claim 1, characterized in that, In step S3, during the etching of the polymer layer, the power is 2000~3000W, the bias voltage is 90~150W, and the single step time is 0.2~0.4s.

5. The method for fabricating a deep via of a chip TSV according to claim 1, characterized in that, In step S4, during the etching process of the silicon substrate corresponding to the exposed bottom surface in the hole structure, the power is 2000~3000W, the bias voltage is 20~60W, and the single step time is 0.2~0.8s.

6. The method for fabricating a deep via of a chip TSV according to claim 1, characterized in that, In step S5, during the partial deposition of the polymer layer on the silicon substrate to expose the porous structure: the power is 2000~3000W, the bias voltage is 20~40W, and the single step time is 0.3~0.8s.

7. The method for fabricating a deep via of a chip TSV according to claim 1, characterized in that, In step S6, when the etching depth reaches 80% of the target depth, the parameters of steps S3 to S5 are adjusted to perform etching.

8. The method for fabricating a deep via of a chip TSV according to claim 1, characterized in that, In step S6, when the etching depth reaches 80%~90% of the target depth, the parameters of steps S3~S5 are adjusted for etching. The adjustment process is as follows: reduce the power of step S3 or step S4, increase the bias voltage of step S3 or step S4, reduce the single-step time of step S3 or step S4, increase the power of step S5, reduce the bias voltage of step S5 or increase the single-step time of step S5.

9. A deep via for a chip TSV, characterized in that, The TSV deep hole is prepared by the method described in any one of claims 1 to 8, and the inclination angle of the hole sidewall is 82° to 92°.

10. A chip, characterized in that, The chip includes a TSV deep via, which is prepared by a chip TSV deep via preparation method according to any one of claims 1 to 8.

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