NMOS (N-channel metal oxide semiconductor) tube for electrostatic discharge protection circuit
By designing a ring-shaped NMOS transistor, leakage current was suppressed under radiation conditions, solving the leakage current problem of CMOS chips in strong ionizing radiation environments and improving the electrical performance and reliability of the chip in reactors and hot chambers.
Patent Information
- Application Number
- CN202511267216.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-09-05
- Publication Date
- 2025-12-16
AI Technical Summary
In environments with strong ionizing radiation, the input/output PAD sections of CMOS chips are susceptible to the total dose effect, leading to leakage current and affecting electrical performance, especially the impedance of the input/output interfaces.
Design an NMOS transistor for electrostatic discharge protection circuit. The gate of the transistor is arranged in a ring structure, which completely surrounds the drain on the inside and the source on the outside. Combined with an asymmetric contact design and an RC coupling network, an effective current discharge path is formed, which suppresses the turn-on of the parasitic field region transistor and enhances the radiation resistance.
It effectively suppresses leakage current in radiation environments, improves the reliability and electrical performance of the chip in strong ionizing radiation environments, and is suitable for applications such as reactors and hot chambers.
Smart Images
Figure CN121149136A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of electrostatic discharge protection technology, and in particular to an NMOS transistor used in electrostatic discharge protection circuits. Background Technology
[0002] Currently, mainstream chips are designed and manufactured using CMOS (Complementary Metal Oxide Semiconductor) technology. In environments with strong ionizing radiation, such as reactors, hot chambers, and other ground-based nuclear facilities, conventional CMOS chips are susceptible to the total dose effect caused by strong gamma radiation, leading to performance degradation or even failure. Typically, CMOS chips include input / output pads and internal circuitry. The input / output pads have electrostatic discharge (ESD) protection structures to prevent damage from instantaneous high voltage ESD during chip manufacturing, assembly, and use. Therefore, radiation hardening design to address the total dose effect requires hardening both the internal circuitry and the ESD protection structures of the input / output pads.
[0003] Please see Figure 1 , Figure 1 This is a typical NMOS structure in related technologies. Figure 1 A strip gate 101 is disposed on the NMOS structure substrate 104, with the source 102 and drain 103 on both sides of the strip gate 101. The problem is that the accumulation of total dose will cause leakage current to be generated between the source 102 and the drain 103, and the leakage current roughly follows the direction of the source 102 and drain 103. Figure 1 The direction of the middle arrow will affect the electrical performance of the input / output interface, especially the input impedance. Summary of the Invention
[0004] In view of this, embodiments of this application provide an NMOS transistor for an electrostatic discharge protection circuit.
[0005] This application provides an NMOS transistor for use in an electrostatic discharge protection circuit, the NMOS transistor comprising:
[0006] Substrate;
[0007] A gate is disposed on the substrate, the gate including an annular portion, the annular portion having a closed annular structure;
[0008] A drain electrode is disposed on the substrate, and the annular portion surrounds the drain electrode.
[0009] A source electrode is disposed on the substrate, and the source electrode is located on the outer periphery of the annular portion.
[0010] In some embodiments, the NMOS transistor includes:
[0011] A gate contact is disposed on the gate, and the gate contact is used for electrical connection to the ground wire;
[0012] A drain contact is disposed at the drain electrode, and the distance between the drain contact and the annular portion is a first spacing.
[0013] A source contact is disposed at the source electrode, and the distance between the source contact and the annular portion is a second spacing, wherein the first spacing is greater than the second spacing.
[0014] In some embodiments, the drain contact is used to electrically connect to the input terminal, and the source contact is used to electrically connect to the ground wire.
[0015] In some embodiments, the NMOS transistor is a gate-coupled NMOS transistor, and the NMOS transistor includes:
[0016] A gate contact is disposed on the gate;
[0017] A drain contact is disposed at the drain electrode, and the distance between the drain contact and the annular portion is a first spacing.
[0018] A source contact is disposed at the source electrode, and the distance between the source contact and the annular portion is a second spacing, wherein the first spacing is equal to the second spacing.
[0019] In some embodiments, the drain contact is used to electrically connect to the input terminal, the gate contact is used to electrically connect to the input terminal via an RC coupling network, and the source contact is used to electrically connect to the ground wire.
[0020] In some embodiments, the NMOS transistor includes a first barrier layer and a second barrier layer, the first barrier layer being disposed above the drain, the annular portion surrounding the first barrier layer, and the second barrier layer being disposed above the source, the second barrier layer being located outside the annular portion.
[0021] In some embodiments, the ion implantation dose at the drain is 1.5 to 3 times the standard dose, and the ion implantation dose at the source is 1.5 to 3 times the standard dose, wherein the standard dose is 3 × 10⁻⁶. 13 cm -2 Up to 5×10 13 cm -2 .
[0022] In some embodiments, the thickness of the oxide layer of the gate is 5 nm to 10 nm.
[0023] In some embodiments, the gate includes a finger-shaped portion, one end of which is connected to the annular portion, and the other end of which extends in a direction away from the annular portion.
[0024] In some embodiments, the annular portion is a polygonal ring.
[0025] In some embodiments, there are multiple finger-shaped portions, which are spaced apart circumferentially along the annular portion.
[0026] The NMOS transistor provided in this application embodiment has a closed ring structure in the ring portion, which completely surrounds the drain on the inner side and the source surrounds the outer side of the ring portion. This ensures that all leakage channels that may be formed in a radiation environment are under the effective control of the gate, directly avoiding the existence of leakage paths in strip gates in related technologies. It fundamentally suppresses the turn-on of parasitic field region transistors, suppresses leakage current between the gate and source caused by total dose effect, and has good radiation resistance, which is beneficial for application in strong ionizing radiation environments such as reactors and hot chambers. Attached Figure Description
[0027] Figure 1 This is a schematic diagram of the structure of NMOS in related technologies;
[0028] Figure 2 This is a schematic diagram of the structure of an NMOS transistor used in an electrostatic discharge protection circuit in some embodiments of this application;
[0029] Figure 3 This is a schematic diagram of the structure of an NMOS transistor used in an electrostatic discharge protection circuit in some other embodiments of this application;
[0030] Figure 4 This is a partial cross-sectional schematic diagram of an NMOS transistor used in an electrostatic discharge protection circuit according to some embodiments of this application.
[0031] Explanation of reference numerals in the attached figures
[0032] 100, NMOS transistor; 110, substrate; 120, gate; 121, ring portion; 122, finger portion; 120a, oxide layer; 120b, gate dielectric; 130, drain; 140, source; 150, gate contact; 160, drain contact; 170, source contact; 180, first barrier layer; 190, second barrier layer. Detailed Implementation
[0033] The embodiments of this application will be described in further detail below with reference to the accompanying drawings and examples. The following examples are used to illustrate this application, but should not be used to limit the scope of this application.
[0034] The various specific technical features and embodiments described in the detailed embodiments can be combined in any suitable manner without contradiction. For example, different combinations of specific technical features / embodiments can form different implementation methods. To avoid unnecessary repetition, the various possible combinations of various specific technical features / embodiments in this application will not be described separately. In addition, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance. The application will be further described in detail below with reference to the accompanying drawings and specific embodiments.
[0035] Please see Figures 2 to 4 This application provides an NMOS transistor 100 for an electrostatic discharge protection circuit. The NMOS transistor 100 includes a substrate 110, a gate 120, a drain 130, and a source 140. The gate 120 is disposed on the substrate 110 and includes an annular portion 121, which has a closed annular structure. The drain 130 is disposed on the substrate 110 and is surrounded by the annular portion 121. The source 140 is disposed on the substrate 110 and is located on the outer periphery of the annular portion 121.
[0036] NMOS transistor 100, or N-channel Metal-Oxide-Semiconductor, is a metal-oxide-semiconductor field-effect transistor that uses electrons as channel carriers.
[0037] Both the source 140 and the drain 130 are formed by ion diffusion on the substrate 110. For example, the source 140 and the drain 130 can be formed by phosphorus ion implantation into the substrate 110.
[0038] The gate 120 is located above the substrate 110, and the substrate 110 below the gate 120 forms a channel.
[0039] The annular portion 121 surrounds the drain electrode 130, meaning that the projection of the annular portion 121 surrounds the projection of the drain electrode 130 with the plane perpendicular to the substrate 110 as the projection plane.
[0040] The source electrode 140 is located on the outer periphery of the annular portion 121, meaning that the projection of the source electrode 140 surrounds the projection of the annular portion 121, with the plane perpendicular to the substrate 110 as the projection plane.
[0041] The NMOS transistor 100 provided in this embodiment has a closed ring structure for the ring portion 121. The ring portion 121 completely surrounds the drain 130 on the inner side, and the source 140 surrounds the outer side of the ring portion 121. This ensures that all leakage channels that may be formed under radiation are under the effective control of the gate 120, directly avoiding the existence of leakage paths in the strip gate 120 in related technologies. This fundamentally suppresses the turn-on of parasitic field region transistors, suppresses the leakage current between the gate 120 and the source 140 caused by the total dose effect, and has good radiation resistance, which is beneficial for application in strong ionizing radiation environments such as reactors and hot chambers.
[0042] In some embodiments, please refer to Figure 2 The NMOS transistor 100 includes a gate contact 150, a drain contact 160, and a source contact 170. The gate contact 150 is disposed on the gate 120 and is used for electrical connection to the ground. The drain contact 160 is disposed on the drain 130, and the distance between the drain contact 160 and the ring portion 121 is a first gap Dd. The source contact 170 is disposed on the source 140, and the distance between the source contact 170 and the ring portion 121 is a second gap Ds. The first gap Dd is greater than the second gap Ds.
[0043] The first spacing is denoted as Dd, and the second spacing is denoted as Ds, where Dd > Ds.
[0044] In this embodiment, the gate contact 150 is electrically connected to the ground wire, the NMOS transistor 100 is a grounded-gate NMOS transistor, the first spacing Dd is greater than the second spacing Ds, forming an asymmetric design, and the ESD static current is discharged by using the opening of the body parasitic transistor, which helps to uniformly open all parasitic BJT (Bipolar Junction Transistor) fingers.
[0045] Gate contact 150, drain contact 160 and source contact 170 are used for electrical connection with other conductive components such as metal layers to enable the integrated circuit to conduct.
[0046] In some embodiments, the gate contact 150, drain contact 160, and source contact 170 can all be contact holes. A contact hole can be a conductive structure formed by a metallic material disposed within a through-hole or blind hole.
[0047] In some embodiments, the drain contact 160 is used to electrically connect to the input terminal, and the source contact 170 is used to electrically connect to the ground wire. The input terminal is used to input signals, and the drain 130 serves as the input port; the source contact 170 is electrically connected to the ground wire, and the source 140 is grounded to quickly discharge electrostatic current.
[0048] In some embodiments, please refer to Figure 3The NMOS transistor 100 is a gate-coupled NMOS transistor. The NMOS transistor 100 includes a gate contact 150, a drain contact 160, and a source contact 170. The gate contact 150 is disposed on the gate 120; the drain contact 160 is disposed on the drain 130, and the distance between the drain contact 160 and the ring portion 121 is a first spacing Dd; the source contact 170 is disposed on the source 140, and the distance between the source contact 170 and the ring portion 121 is a second spacing Ds. The first spacing Dd is equal to the second spacing Ds.
[0049] In this embodiment, the gate-coupled NMOS (GCNMOS) utilizes the channel of the NMOS device as a discharge path, without relying on the parasitic BJT effect.
[0050] In some embodiments, the drain contact 160 is used to electrically connect to the input terminal, the gate contact 150 is used to electrically connect to the input terminal via an RC coupling network, and the source contact 170 is used to electrically connect to the ground wire.
[0051] Specifically, the RC coupling network includes a resistor and a capacitor connected in series between the gate 120 and the input.
[0052] In this embodiment, the input terminal is used to input signals, the drain contact 160 is electrically connected to the input terminal, and the drain 130 serves as the input port. When an ESD event occurs, the reverse bias junction between the drain 130 and the substrate 110 first enters the avalanche breakdown state, forming a discharge channel. The high-frequency ESD pulse is coupled to the gate 120 through the capacitance of the RC coupling network, which quickly triggers protection. The source contact 170 is electrically connected to the ground wire to ensure stable discharge of electrostatic current when the circuit is turned on.
[0053] In some embodiments, please refer to Figure 4 The NMOS transistor 100 includes a first barrier layer 180 and a second barrier layer 190. The first barrier layer 180 is disposed above the drain 130, and an annular portion 121 surrounds the first barrier layer 180. The second barrier layer 190 is disposed above the source 140 and is located outside the annular portion 121.
[0054] In this embodiment, the first barrier layer 180 and the second barrier layer 190 have high resistance values to increase the series resistance of the ESD discharge path, disperse the current density, and improve ESD robustness.
[0055] The material of the first barrier layer 180 is not limited, and the first barrier layer 180 can be a silicide, such as at least one of silicon nitride and silicon oxide.
[0056] The material of the second barrier layer 190 is not limited, and the second barrier layer 190 can be a silicide, such as at least one of silicon nitride and silicon oxide.
[0057] In some embodiments, the NMOS transistor 100 includes a third barrier layer located between the gate 120 and the substrate 110.
[0058] The material of the third barrier layer is not limited, and the third barrier layer can be a silicide, such as at least one of silicon nitride and silicon oxide.
[0059] In some embodiments, the first barrier layer 180 and the second barrier layer 190 can be formed simultaneously by deposition. This simplifies the forming process of the first barrier layer 180 and the second barrier layer 190 and provides good CMOS process compatibility.
[0060] In some embodiments, the first barrier layer 180, the second barrier layer 190, and the third barrier layer can be formed simultaneously by deposition. Thus, the forming process of the first barrier layer 180, the second barrier layer 190, and the third barrier layer is simple and has good CMOS process compatibility; for example, it is compatible with self-aligned silicide processes without the need for additional masks.
[0061] In some embodiments, the ion implantation dose of the drain 130 is 1.5 to 3 times the standard dose, and the ion implantation dose of the source 140 is 1.5 to 3 times the standard dose, wherein the standard dose is 3 × 10⁻⁶. 13 cm -2 Up to 5×10 13 cm -2 .
[0062] Unit "cm" -2 "For every square centimeter."
[0063] In this embodiment, the ion implantation dose of the drain 130 is 1.5 to 3 times the standard dose, and the ion implantation dose of the source 140 is 1.5 to 3 times the standard dose. Both the drain 130 and the source 140 are implanted by ESD to form heavily doped regions in order to reduce the turn-on resistance of the discharge path.
[0064] For example, the ion implantation dose of the drain 130 can be 4 × 10⁻⁶. 15 cm -2 Up to 1×10 18 cm -2 .
[0065] For example, the ion implantation dose of source 140 can be 4 × 10⁻⁶. 15 cm -2 Up to 1×10 18 cm -2 .
[0066] In some embodiments, the injection energy of source 140 is higher than the standard energy, which can be 20 keV to 30 keV. For example, the injection energy of source 140 can be 40 keV to 80 keV. Thus, the junction depth of source 140 can be increased by 20% to 50%.
[0067] In some embodiments, the injection energy of the drain 130 is higher than the standard energy. For example, the injection energy of the drain 130 can be from 40 keV to 80 keV. Thus, the junction depth of the drain 130 can be increased by 20% to 50%.
[0068] The unit "keV" stands for kiloelectron volt.
[0069] In some embodiments, please refer to Figure 4 The thickness H of the oxide layer 120a of the gate 120 is 5 nm to 10 nm. By reducing the thickness of the oxide layer 120a, the resistance to total dose effect is enhanced.
[0070] The gate 120 includes an insulating layer and a gate dielectric 120b, with the insulating layer disposed between the substrate 110 and the gate dielectric 120b. The insulating layer can be an oxide or other insulating material. Exemplarily, the insulating layer can be an oxide layer 120a formed of oxide.
[0071] For example, the insulating layer may be silicon dioxide or silicon oxynitride, etc. The gate dielectric 120b may be polysilicon.
[0072] For example, the thickness of oxide layer 120a is 5nm, 6nm, 7nm, 8nm, 9nm and 10nm, etc.
[0073] The unit "nm" stands for nanometer.
[0074] In some embodiments, the gate 120 may be made of a radiation-hardened gate oxide material.
[0075] In some embodiments, please refer to Figure 2 and Figure 3 The gate 120 includes a finger-shaped portion 122, one end of which is connected to the annular portion 121, and the other end of which extends away from the annular portion 121.
[0076] For example, the finger-shaped portion 122 may be provided with a gate contact 150.
[0077] In this embodiment, the finger-shaped portion 122 is generally straight, and the finger-shaped portion 122 can increase the effective cross-sectional area of the parasitic transistor and improve the electrostatic current discharge capability.
[0078] In some embodiments, the annular portion 121 is a polygonal ring. Exemplarily, the annular portion 121 may be a quadrilateral ring, a pentagonal ring, a hexagonal ring, or an octagonal ring, etc.
[0079] Please see Figure 2 and Figure 3 The annular portion 121 is in the form of a square or rectangular ring. This makes it easy to manufacture and to arrange the source contact 170 and the drain contact 160.
[0080] In some embodiments, please refer to Figure 2 The number of finger-shaped parts 122 is one.
[0081] In some embodiments, please refer to Figure 3 The number of finger-shaped portions 122 is multiple, and the multiple finger-shaped portions 122 are arranged at intervals along the circumference of the annular portion 121. The multiple finger-shaped portions 122 can increase the contact area of the gate 120.
[0082] It is understood that the annular portion 121 includes an insulating layer and a gate dielectric 120b. The finger-shaped portion 122 includes an insulating layer and a gate dielectric 120b.
[0083] In the description of this specification, the references to "some embodiments" and "exemplary" indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the embodiments of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.
[0084] The various embodiments / implementations provided in this application can be combined with each other without creating contradictions. The above descriptions are merely preferred embodiments of this application and are not intended to limit this application. For those skilled in the art, this application can have various modifications and variations. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.
Claims
1. An NMOS transistor for use in an electrostatic discharge protection circuit, characterized in that, The NMOS transistor includes: Substrate; A gate is disposed on the substrate, the gate including an annular portion, the annular portion having a closed annular structure; A drain electrode is disposed on the substrate, and the annular portion surrounds the drain electrode. A source electrode is disposed on the substrate, and the source electrode is located on the outer periphery of the annular portion.
2. The NMOS transistor according to claim 1, characterized in that, The NMOS transistor includes: A gate contact is disposed on the gate, and the gate contact is used for electrical connection to the ground wire; A drain contact is disposed at the drain electrode, and the distance between the drain contact and the annular portion is a first spacing. A source contact is disposed at the source electrode, and the distance between the source contact and the annular portion is a second spacing, wherein the first spacing is greater than the second spacing.
3. The NMOS transistor according to claim 2, characterized in that, The drain contact is used to electrically connect the input terminal, and the source contact is used to electrically connect the ground wire.
4. The NMOS transistor according to claim 1, characterized in that, The NMOS transistor is a gate-coupled NMOS transistor, and the NMOS transistor includes: A gate contact is disposed on the gate; A drain contact is disposed at the drain electrode, and the distance between the drain contact and the annular portion is a first spacing. A source contact is disposed at the source electrode, and the distance between the source contact and the annular portion is a second spacing, wherein the first spacing is equal to the second spacing.
5. The NMOS transistor according to claim 4, characterized in that, The drain contact is used to electrically connect to the input terminal, the gate contact is used to electrically connect to the input terminal through an RC coupling network, and the source contact is used to electrically connect to the ground wire.
6. The NMOS transistor according to claim 1, characterized in that, The NMOS transistor includes a first barrier layer and a second barrier layer. The first barrier layer is disposed above the drain, and the annular portion surrounds the first barrier layer. The second barrier layer is disposed above the source, and the second barrier layer is located outside the annular portion.
7. The NMOS transistor according to claim 1, characterized in that, The ion implantation dose at the drain is 1.5 to 3 times the standard dose, and the ion implantation dose at the source is 1.5 to 3 times the standard dose, wherein the standard dose is 3 × 10⁻⁶. 13 cm -2 Up to 5×10 13 cm -2 .
8. The NMOS transistor according to claim 1, characterized in that, The thickness of the oxide layer of the gate is 5 nm to 10 nm.
9. The NMOS transistor according to claim 1, characterized in that, The gate includes a finger-shaped portion, one end of which is connected to the annular portion, and the other end of which extends in a direction away from the annular portion.
10. The NMOS transistor according to claim 9, characterized in that, The annular portion is a polygonal ring.
11. The NMOS transistor according to claim 9, characterized in that, The number of the finger-shaped portions is multiple, and the multiple finger-shaped portions are arranged at intervals along the circumference of the annular portion.