Bipolar transistor, preparation method thereof and electronic equipment

Abstract

The invention relates to a bipolar transistor and a preparation method thereof, and electronic equipment, and the method comprises the steps: providing a substrate, and enabling the top surface of the substrate to comprise a drift layer, a base layer and an emitter layer which are sequentially arranged in a direction away from the substrate; forming a mask layer covering the top surfaces of the emitter layer and the base layer; forming an initial groove surrounding the emitter layer and arranged along the radial direction of the emitter layer and a photoresist layer in the mask layer; the distance between the photoresist layer and the emitter layer is greater than the width of the initial groove; forming an annular terminal region in the drift layer based on the photoresist layer; after the photoresist layer is removed, forming a side wall structure on the side wall of the initial groove; based on the side wall structure, removing part of the base layer and the drift layer on the bottom surface of the initial groove to obtain a target groove; the annular termination region at least surrounds a corner of the target trench near the emitter layer. The method has a self-alignment characteristic, can control P-type injection in a terminal area, and can wrap a terminal etching corner.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to a bipolar transistor, its fabrication method, and a semiconductor device. Background Technology

[0002] Silicon carbide (SiC) materials, as wide-bandgap semiconductors, have broad prospects for high-power, high-temperature, and radiation-resistant applications. Among them, silicon carbide bipolar junction transistors (BJTs) are ideal devices for high-voltage, high-temperature, and high-frequency applications due to their high breakdown electric field, high thermal conductivity, and high electron saturation drift velocity. However, when SiC BJTs operate at high voltages, the electric field concentration effect at the PN junction edge can lead to premature breakdown. Therefore, a junction termination structure needs to be added at the device edge to optimize the electric field distribution and improve the breakdown voltage and reliability.

[0003] However, the fabrication of bipolar transistors is limited by the methods for implementing the terminal structure, making it difficult to ensure both structural integrity and positioning accuracy, which in turn restricts the core performance of the device. Summary of the Invention

[0004] Therefore, it is necessary to provide a bipolar transistor and its fabrication method, as well as an electronic device, to address the technical problems in the prior art, which can at least reduce the damage of ion implantation to the stepped structure and avoid the displacement of the terminal structure.

[0005] In a first aspect, this application provides a method for fabricating a bipolar transistor, comprising:

[0006] A substrate is provided, the top surface of which includes a drift layer, a base layer and an emitter layer arranged sequentially in a direction away from the substrate;

[0007] A mask layer is formed covering the top surface of the emitter layer and the base layer;

[0008] An initial trench and a photoresist layer are formed within the mask layer, surrounding the emitter layer and arranged radially along the emitter layer; the spacing between the photoresist layer and the emitter layer is greater than the width of the initial trench.

[0009] A ring-shaped terminal region is formed within the drift layer based on the photoresist layer;

[0010] After removing the photoresist layer, a sidewall structure is formed on the sidewall of the initial trench;

[0011] Based on the sidewall structure, part of the base layer and drift layer at the bottom of the initial trench are removed to obtain the target trench; the annular terminal region at least surrounds the corner of the target trench near the emitter layer; where the width represents the radial dimension.

[0012] In the bipolar transistor fabrication method described in the above embodiments, a photoresist layer is formed on the outer wall of the annular initial trench surrounding the emitter layer. Then, using a self-aligned process, an annular terminal region is formed via ion implantation, effectively preventing misalignment of the annular terminal region due to overlay errors. Furthermore, a sidewall structure is formed on this basis, and a target trench is etched based on the sidewall structure to form a stepped bipolar transistor. This embodiment, by adjusting the process sequence, avoids direct contact between ion implantation and the stepped structure, significantly reducing the probability of lattice defects.

[0013] In some embodiments, forming a photoresist layer includes:

[0014] Remove part of the mask layer to form the initial trench surrounding the emitter layer;

[0015] An initial photoresist layer is formed to fill the initial trenches;

[0016] The initial photoresist layer is patterned to expose part of the top surface of the base layer, and the remaining initial photoresist layer is used to form the photoresist layer.

[0017] In some embodiments, forming an annular terminal region includes:

[0018] An ion implantation process is performed on the exposed top surface of the base layer to form an annular terminal region; the top surface of the annular terminal region is lower than the top surface of the drift layer, and the bottom surface is higher than the bottom surface of the drift layer.

[0019] In some embodiments, a sidewall structure is formed, including:

[0020] A deposition process is used to form a sacrificial oxide layer in the initial trench and on the outer surface of the mask layer;

[0021] Partial removal of the sacrificial oxide layer forms a sidewall structure covering the sidewalls of the initial trench; the radial dimension of the target trench is positively correlated with the thickness of the sidewall structure.

[0022] In some embodiments, the annular termination region at least surrounds the corner of the target trench near the emitter layer, including:

[0023] The bottom surface of the target trench is not higher than the top surface of the annular terminal area, and not lower than the bottom surface of the annular terminal area.

[0024] In some embodiments, after forming the target trench, the process includes:

[0025] Remove the sidewall structure and mask layer;

[0026] A doped region is formed in the base layer; the doped region is located between the emitter layer and the annular terminal region, and extends inward from the top surface of the base layer;

[0027] Metal electrodes are formed on the top surface of the emitter layer, the bottom surface of the substrate, and the top surface of the doped region.

[0028] In some embodiments, the emitter layer includes a plurality of sub-emitter layers, which are radially spaced on the top surface of the base layer in the annular terminal region.

[0029] In some embodiments, the conductivity type of the annular terminal region is opposite to that of the drift layer, but the same as that of the doped region.

[0030] Secondly, this application also provides a bipolar transistor, fabricated using the method described in any of the above embodiments. In the above embodiments, through process design and self-alignment, the annular terminal region achieves wrapping coverage of the stepped corners, thereby improving the device's compressive strength.

[0031] Thirdly, this application also provides an electronic device including the bipolar transistor described in any of the above embodiments. The annular termination region is stable and suffers less damage, making the bipolar transistor less prone to performance degradation due to structural defects during long-term operation, thus reducing the failure risk of the electronic device and providing a foundation for its efficient operation.

[0032] The bipolar transistor, its fabrication method, and the electronic device provided in this application have the following unexpected technical effects:

[0033] Compared to the method of first etching trenches to form steps and then ion implanting them nearby, this application improves the process sequence to actively avoid damage to the step structure caused by ion implantation. At the same time, it utilizes a self-aligned process to achieve full coverage of the step corners, improve the electric field optimization effect of the annular terminal area, avoid the risk of breakdown caused by excessively high electric field strength in local areas, and thus improve the device's withstand voltage and operational reliability. Attached Figure Description

[0034] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0035] Figure 1 This is a cross-sectional schematic diagram of a substrate structure provided in related technologies;

[0036] Figure 2 for Figure 1 A cross-sectional schematic diagram of the resulting structure after the required device pattern is formed.

[0037] Figure 3 yes Figure 2A cross-sectional schematic diagram of the resulting structure after the terminal structure is formed;

[0038] Figure 4 This is a flowchart of a method for fabricating a bipolar transistor according to an embodiment of this application;

[0039] Figure 5 This is a cross-sectional schematic diagram of the structure obtained after forming the drift layer, base layer and emitter layer in step S1022 of the bipolar transistor fabrication method provided in one embodiment of this application.

[0040] Figure 6 This is a cross-sectional schematic diagram of the structure obtained after forming the sub-emitter layer in step S1024 of the bipolar transistor fabrication method provided in one embodiment of this application.

[0041] Figure 7 This is a cross-sectional schematic diagram of the structure obtained after forming a mask layer in step S104 of the bipolar transistor fabrication method provided in one embodiment of this application.

[0042] Figure 8 This is a cross-sectional schematic diagram of the structure obtained after forming the initial trench in step S1062 of the bipolar transistor fabrication method provided in one embodiment of this application.

[0043] Figure 9 This is a cross-sectional schematic diagram of the structure obtained after forming the initial photoresist layer in step S1064 of the bipolar transistor fabrication method provided in one embodiment of this application.

[0044] Figure 10 This is a cross-sectional schematic diagram of the structure obtained after forming a photoresist layer in step S1066 of the bipolar transistor fabrication method provided in one embodiment of this application.

[0045] Figure 11 This is a cross-sectional schematic diagram of the structure obtained after forming an annular terminal region in step S108 of the bipolar transistor fabrication method provided in one embodiment of this application.

[0046] Figure 12 This is a cross-sectional schematic diagram of the structure obtained after forming a sacrificial oxide layer in step S1102 of the method for fabricating a bipolar transistor provided in one embodiment of this application.

[0047] Figure 13 This is a schematic cross-sectional view of the structure obtained after forming the sidewall structure in step S1104 of the bipolar transistor fabrication method provided in one embodiment of this application.

[0048] Figure 14 This is a cross-sectional schematic diagram of the structure obtained after forming the target trench in step S1104 of the bipolar transistor fabrication method provided in one embodiment of this application.

[0049] Figure 15 for Figure 14 A cross-sectional schematic diagram of the resulting structure is shown in the diagram, in which a metal electrode is formed.

[0050] Explanation of reference numerals in the attached figures:

[0051] 1. Initial substrate; 2. Buffer layer; 10. Substrate; 11. Drift layer; 12. Base layer; 13. Emitter layer; 131. Sub-emitter layer; 14. Mask layer; 21. Initial trench; 22. Initial photoresist layer; 23. Photoresist layer; 24. Sacrificial oxide layer; 30. Annular terminal region; 40. Sidewall structure; 50. Target trench; 60. Doped region; 71. Metal emitter; 72. Collector; 73. Metal base. Detailed Implementation

[0052] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate preferred embodiments of the application. However, this application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0053] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0054] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, parts, regions, layers, doping types, and / or portions, these elements, parts, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, part, region, layer, doping type, or portion from another element, part, region, layer, doping type, or portion. Therefore, without departing from the teachings of this application, the first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0055] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “below,” “under,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.

[0056] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that when the terms “comprise” and / or “comprising” are used in this specification, the presence of the stated feature, integer, step, operation, element, and / or part is established, but the presence or addition of one or more other features, integers, steps, operations, elements, parts, and / or groups is not excluded. Meanwhile, when used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0057] Embodiments of the invention are described herein with reference to cross-sectional views illustrating ideal embodiments (and intermediate structures) of this application, thus allowing for variations in the illustrated shapes due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of this application should not be limited to the specific shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing techniques. For instance, implantation regions shown as rectangular typically have rounded or curved features at their edges and / or implantation concentration gradients, rather than a binary change from implantation regions to non-implantation regions. Similarly, the buried regions formed by implantation can result in some implantation in the region between the buried region and the surface traversed during implantation. Therefore, the regions shown in the figures are substantially schematic, and their shapes do not represent the actual shapes of regions of the device and do not limit the scope of this application.

[0058] Please see Figures 1-3 This is a cross-sectional structural diagram of each step in a terminal structure fabrication method in a related technology.

[0059] Please see Figure 1 A substrate 10 is provided, on which a drift layer 11, a base layer 12, and an emitter layer 13 are formed; a portion of the emitter layer 13, the base layer 12, and the drift layer 11 are etched away to form the desired device pattern, resulting in a structure as shown. Figure 2 As shown; using a patterned photoresist layer 23 as a mask, ion implantation is performed on the drift layer 11 to obtain the result shown. Figure 3 The terminal structure shown.

[0060] However, the junction termination structure formed by directly using photoresist as a barrier mask for ion implantation may suffer from implantation damage at the step angle after ion implantation, and insufficient alignment accuracy may lead to the offset of the junction termination structure, thereby affecting the device's compressive strength.

[0061] Based on this, please refer to Figure 4 This application provides a method for fabricating a bipolar transistor, comprising: steps S102-S112.

[0062] Step S102: Provide a substrate, the top surface of which includes a drift layer, a base layer and an emitter layer arranged sequentially in a direction away from the substrate.

[0063] Step S104: Form a mask layer covering the top surface of the emitter layer and the base layer.

[0064] Step S106: An initial trench and a photoresist layer are formed within the mask layer, surrounding the emitter layer and arranged radially along the emitter layer; the distance between the photoresist layer and the emitter layer is greater than the width of the initial trench.

[0065] Step S108: Based on the photoresist layer, form an annular terminal region within the drift layer.

[0066] Step S110: After removing the photoresist layer, a sidewall structure is formed on the sidewall of the initial trench.

[0067] Step S112: Based on the sidewall structure, remove part of the base layer and drift layer from the bottom of the initial trench to obtain the target trench; the annular terminal region at least surrounds the corner of the target trench near the emitter layer; where the width represents the radial dimension.

[0068] It should be understood that, although Figure 4 The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order in which these steps are executed, and they can be performed in other orders. Figure 4 At least some of the steps in the process may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but may be executed at different times. The execution order of these steps or stages is not necessarily sequential, but may be executed in turn or alternately with other steps or at least some of the steps or stages in other steps.

[0069] The following is combined Figures 5 to 14 The preparation methods provided in the embodiments of this application will be described in detail.

[0070] In the embodiments of this application, for ease of understanding, the radial direction of the emitter layer mentioned in this application is defined as R, and the direction away from the substrate is defined as the axial direction Z. Furthermore, the width is used to represent the dimension along the radial direction R, and the thickness is used to represent the dimension along the axial direction Z.

[0071] Please see Figures 5-6 The extended steps of step S102 include:

[0072] Step S1022: A buffer layer 2, a drift layer 11, a base layer 12, and an emitter layer 13 are sequentially formed on the top surface of the initial substrate 1 using an epitaxial process. At this point, the initial substrate 1 and the buffer layer 2 constitute the substrate 10, as shown in the specific structure below. Figure 5 As shown.

[0073] For example, the conductivity type of the initial substrate 1 is the same as that of the buffer layer 2, drift layer 11, and emitter layer 13, and opposite to that of the base layer 12. That is, in the embodiment where the substrate 10 includes an N-type initial substrate 1, the buffer layer 2, drift layer 11, and emitter layer 13 are N-type, and the base layer 12 is P-type; correspondingly, in the embodiment where the substrate includes a P-type substrate, the method described above can be used, simply by interchangeping "P" and "N" in each step of the above method. In the embodiments mentioned in this application, the conductivity type of the initial substrate 1 is N-type.

[0074] For example, the thickness of the drift layer 11 ranges from 13 to 16 μm, such as 13 μm, 14 μm, 15 μm, or 16 μm; the doping concentration ranges from 2E15m. -3 ~6E15m -3 For example, 2E15m -3 4E15m -3 Or 6E15m -3 wait.

[0075] For example, the thickness of the base layer 12 ranges from 500 nm to 900 nm, such as 500 nm, 600 nm, 700 nm, 800 nm, or 900 nm; its doping concentration ranges from 2E17m. -3 ~6E17m -3 For example, 2E17m -3 4E17m -3 Or 6E17m -3 wait.

[0076] For example, the thickness of the emitter layer 13 is 0.9 μm to 1.1 μm, such as 0.9 μm, 1 μm, or 1.1 μm; its doping concentration ranges from 2E19m. -3 ~5E19m -3 For example, 2E19m -3 3E19m -3 4E19m -3 or 5E17m -3 wait.

[0077] Step S1024: Etch away part of the emitter layer 13 to form multiple sub-emitter layers 131 arranged radially at intervals R, resulting in... Figure 6 The structure described above. It should be understood that the number of sub-emitter layers 131 in the bipolar transistor can be adjusted as needed (at least one). Figure 6 (Two examples are given).

[0078] Please see Figure 7 In step S104, a mask layer 14 is formed by using any one of the following processes, including but not limited to chemical vapor deposition (CVD), atomic layer deposition (ALD), or high density plasma deposition (HDP).

[0079] For example, the material of the mask layer 14 includes, but is not limited to, silicon dioxide (SiO2), silicon nitride (Si3N4), or silicon oxynitride (SiON).

[0080] Please see Figures 8-10 Step S106 further includes:

[0081] Step S1062: Photoresist is coated on the mask layer 14, and after a series of steps such as exposure and development, a portion of the mask layer 14 is removed using an etching process to form the initial trench 21 surrounding the emitter layer 13, as shown in the specific structure. Figure 8 As shown.

[0082] For example, the initial trench 21 is 18 μm to 22 μm away from the emitter layer 13 along the radial direction R, such as 18 μm, 19 μm, 20 μm, 21 μm or 22 μm.

[0083] Step S1064: Form an initial photoresist layer 22 that fills the initial trench 21, resulting in... Figure 9 The structure shown.

[0084] Step S1066: Pattern the initial photoresist layer 22, exposing part of the top surface of the base layer 12. The remaining initial photoresist layer 22 covers the sidewalls of the initial trench 21 away from the emitter layer 13, forming the photoresist layer 23. The initial trench 21 and the photoresist layer 23 surround the emitter layer 13 and are arranged radially R along the emitter layer 13, as shown in the specific structure. Figure 10 As shown.

[0085] Please see Figure 11 In step S108, an ion implantation process (channeling implantation) is performed on the exposed top surface of the base layer 12 to form an annular terminal region 30.

[0086] For example, the annular termination region 30 has the same conductivity type as the base layer 12 (i.e., P-type), its top surface is lower than the top surface of the drift layer 11, and its bottom surface is higher than the bottom surface of the drift layer 11, and its width is inversely proportional to the width of the photoresist layer. In this embodiment, the specific implantation depth (along the ZO direction) ranges from 1.5 μm to 3 μm, for example, 1.5 μm, 2 μm, 2.5 μm, or 3 μm.

[0087] In the above embodiments, compared with related technologies, the annular terminal region is formed by a separate photolithographic alignment sleeve, with the mask layer 14 and photoresist layer 23 blocking the emitter layer 13. The position determines the position of the subsequent terminal region. The annular terminal region formed by the self-alignment process can effectively avoid offset due to overlay error.

[0088] Please see Figures 12-13 The extended steps of step S110 include:

[0089] Step S1102: Remove the photoresist layer 23, and use a deposition process to form a sacrificial oxide layer 24 in the initial trench 21 and on the outer surface of the mask layer 14, to obtain the desired result. Figure 12The structure shown.

[0090] Step S1104: The sacrificial oxide layer 24 on the bottom surface of the initial trench 21 and the top surface of the mask layer 14 is removed by etching, while the sacrificial oxide layer 24 on the sidewalls of the initial trench 21 is retained to form the sidewall structure 40, resulting in the structure shown below. Figure 13 As shown.

[0091] Please see Figure 14 In step S112, an etching process is used to remove part of the base layer 12 and drift layer 11 on the bottom surface of the initial trench 21 based on the sidewall structure 40, to obtain the target trench 50.

[0092] In the above embodiment, a stepped structure with a height difference is formed between the base layer 12 and the drift layer 11. The height difference between the two mesa results in a right angle at the edge of the device, which can easily lead to a large electric field spike. Since the width of the target trench 50 is positively correlated with the thickness of the sidewall structure 40, the sidewall structure 40 can effectively narrow the trench, thereby ensuring that the annular terminal region 30 can accurately surround the corner of the target trench 50, preventing local avalanche breakdown and achieving the effect of optimizing the withstand voltage.

[0093] In some embodiments, after step S112, the method further includes: removing the sidewall structure 40 and the mask layer 14, and forming a doped region 60 extending inward from the top surface of the base layer 12 between the emitter layer 13 and the annular terminal region 30 by an ion implantation process. Subsequently, a metal emitter 71 is formed on the top surface of the emitter layer 13, a collector 72 is formed on the bottom surface of the substrate 10, and a metal base 73 is formed on the top surface of the doped region 60, resulting in a structure as shown below. Figure 15 As shown.

[0094] For example, the materials of the metal electrodes include, but are not limited to, nickel (Ni), gold (Au), or aluminum (Al). In this embodiment, the materials of the metal emitter 71 and the metal base 73 are any of the above materials, and the material of the collector 72 is nickel (Ni).

[0095] The bipolar transistors obtained through the above process steps can be found in [reference needed]. Figure 15 The overall bipolar transistor is centrally symmetrical. Figure 15 This application provides an example of a bipolar transistor fabricated using the method described herein. Other suitable examples of bipolar transistors fabricated using this application are also possible, and no limitations are imposed herein.

[0096] In some embodiments, this application provides a bipolar transistor fabricated using the fabrication method described in any of the above embodiments.

[0097] In some embodiments, this application also provides an electronic device employing the bipolar transistor as described in the above embodiments. Since the bipolar transistor and electronic device of the above embodiments are based on the same inventive concept as the fabrication method provided by this invention, the bipolar transistor and electronic device possess all the advantages of the bipolar transistor fabrication method provided by this invention, which will not be elaborated upon here.

[0098] In the above embodiments, the unexpected technical effect of this application is:

[0099] In the fabrication method provided in this application, an annular initial trench surrounding the emitter layer is first etched in the mask layer, and then a photoresist layer partially covering the initial trench is formed. Based on the above structure, an annular terminal region is formed in the drift layer by ion implantation. Then, a sidewall structure is formed and the target trench is etched accordingly to form a bipolar transistor with a stepped structure.

[0100] Compared to the method of first etching trenches to form steps and then implanting ions nearby, this application, by adjusting the steps for forming steps and annular terminal regions, isolates the implantation damage from direct contact with the step structure in terms of process sequence. This can significantly reduce the probability of lattice defects, while using the sidewall structure to achieve self-alignment between the target trench and the annular terminal region, effectively improving the consistency and reliability of bipolar transistors.

[0101] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0102] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A method for fabricating a bipolar transistor, characterized in that, include: A substrate is provided, the top surface of which includes a drift layer, a base layer and an emitter layer arranged sequentially in a direction away from the substrate; A mask layer is formed covering the top surface of the emitter layer and the base layer; An initial trench and a photoresist layer are formed within the mask layer, surrounding the emitter layer and arranged radially along the emitter layer; the distance between the photoresist layer and the emitter layer is greater than the width of the initial trench; Based on the photoresist layer, an annular terminal region is formed within the drift layer; After removing the photoresist layer, a sidewall structure is formed on the sidewall of the initial trench; Based on the sidewall structure, a portion of the base layer and the drift layer at the bottom of the initial trench are removed to obtain the target trench. The annular terminal region at least surrounds the corner of the target trench near the emitter layer; Wherein, the width represents the dimension along the radial direction.

2. The preparation method according to claim 1, characterized in that, Forming the photoresist layer includes: Remove a portion of the mask layer to form the initial trench surrounding the emitter layer; An initial photoresist layer is formed to fill the initial trench; The initial photoresist layer is patterned to expose a portion of the top surface of the base layer, and the remaining initial photoresist layer is used to form the photoresist layer.

3. The preparation method according to claim 2, characterized in that, Forming the annular terminal region includes: An ion implantation process is performed on the exposed top surface of the base layer to form the annular terminal region; the top surface of the annular terminal region is lower than the top surface of the drift layer, and the bottom surface is higher than the bottom surface of the drift layer.

4. The preparation method according to claim 1, characterized in that, The sidewall structure includes: A sacrificial oxide layer is formed in the initial trench and on the outer surface of the mask layer using a deposition process. A portion of the sacrificial oxide layer is removed to form a sidewall structure covering the sidewalls of the initial trench; the radial dimension of the target trench is positively correlated with the thickness of the sidewall structure.

5. The preparation method according to claim 1, characterized in that, The annular terminal region at least surrounds the corner of the target trench near the emitter layer, including: The bottom surface of the target trench is not higher than the top surface of the annular terminal area, and not lower than the bottom surface of the annular terminal area.

6. The preparation method according to any one of claims 1-5, characterized in that, After forming the target trench, the process includes: Remove the sidewall structure and mask layer; A doped region is formed in the base layer; the doped region is located between the emitter layer and the annular terminal region, and extends inward from the top surface of the base layer; Metal electrodes are formed on the top surface of the emitter layer, the bottom surface of the substrate, and the top surface of the doped region.

7. The preparation method according to any one of claims 1-5, characterized in that, The emitter layer includes a plurality of sub-emitter layers, which are distributed radially at intervals on the top surface of the base layer in the annular terminal region.

8. The preparation method according to claim 6, characterized in that, The conductivity type of the annular terminal region is opposite to that of the drift layer, but the same as that of the doped region.

9. A bipolar transistor, characterized in that, It is prepared by the preparation method according to any one of claims 1-8.

10. An electronic device, characterized in that, include: The bipolar transistor as described in claim 9.

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