Self-aligned patterning preparation method, groove silicon carbide device and chip

Abstract

The invention belongs to the technical field of power devices, and provides a self-aligned patterning preparation method, a trench silicon carbide device and a chip, a trench region is defined through a trench etching mask, and a gate trench penetrating into an N-type drift region is formed through etching under the coverage of the trench etching mask. A P-type shielding region is formed at the bottom of the groove by using a first self-aligned dielectric layer and a first isolation dielectric layer and a second isolation dielectric layer are respectively formed at the two sides of the bottom of the gate groove by using a second self-aligned dielectric layer by adopting a self-aligned patterning process, so that the self-aligned dielectric layers are simultaneously used as an injection mask and an isolation layer; according to the method, the multi-layer photoetching step is saved, the alignment precision of the P-type shielding region is improved, the electric field of the central oxide layer at the bottom of the groove type grid is reduced, the leakage current phenomenon of the grid of the device is reduced, the reliability of the device is improved, and meanwhile the two core problems of high-precision doping and high-temperature process compatibility in the silicon carbide power device are solved.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of power devices, and particularly relates to a self-aligned patterning preparation method, a trench silicon carbide device and a chip. BACKGROUND

[0002] Based on the excellent material properties of silicon carbide, including a wide band gap, a high critical electric field and good thermal conductivity, a silicon carbide (SiC) trench gate metal oxide semiconductor field effect transistor (TG-MOSFET) has a very high gate density without being limited by the parasitic junction field effect transistor (JFET) channel in a planar silicon carbide MOSFET, thereby reducing the contribution of channel resistance to the total on-resistance. Compared with a traditional planar MOSFET, the TG-MOSFET can significantly reduce the specific on-resistance by accommodating more channels on a given chip area and completely eliminating the JFET effect.

[0003] However, in the preparation process of the silicon carbide trench MOSFET, multiple photoresists need to be used for photolithography and etching, which is not only high in cost but also long in process time. SUMMARY

[0004] To solve the above technical problems, the application provides a self-aligned patterning preparation method, a trench silicon carbide device and a chip, a self-aligned patterning process is used to form a P-type shielding region, a first isolation dielectric layer and a second isolation dielectric layer at the bottom of a gate trench, so as to reduce the electric field of the central oxide layer at the bottom of the trench gate, reduce the gate leakage current phenomenon of the device and improve the reliability of the device.

[0005] The first aspect of the application provides a self-aligned patterning preparation method applied to a silicon carbide power device, and the self-aligned patterning preparation method comprises the following steps. A silicon carbide substrate is provided, and a buffer layer, an N-type drift region, a current spreading material layer and a P-type doped layer are sequentially formed on the front surface of the silicon carbide substrate; N-type doped ions are injected into a preset region of the P-type doped layer to form an N-type doped layer, and a gate trench deep into the N-type drift region is formed by etching part of the N-type doped layer; A first self-aligned dielectric material is deposited in the gate trench to form a first self-aligned dielectric layer, and the first self-aligned dielectric layer is selectively etched to expose a first region requiring P-type doped ion injection at the bottom of the gate trench; P-type doped ions are injected into the first region, and annealing treatment is performed after the first self-aligned dielectric layer is removed, so as to form a P-type shielding region; depositing a second self-aligned dielectric material to form a second self-aligned dielectric layer, and selectively etching the second self-aligned dielectric layer to form a first isolation dielectric layer and a second isolation dielectric layer on both sides of the bottom of the gate trench, respectively; forming a gate material layer in the recess of the gate dielectric layer after forming the gate dielectric layer on the bottom and inner wall of the gate trench, and forming a field oxide layer on the gate material layer; wherein the gate dielectric layer and the field oxide layer form a closed structure wrapping the gate material layer.

[0006] In some embodiments, the preparation method further comprises: depositing a source electrode material to form a source layer in contact with the first P-type well region, the second P-type well region, the first N-type doped region, the second N-type doped region, both sides of the gate dielectric layer, and the field oxide layer; depositing a drain electrode material to form a drain layer on the back surface of the silicon carbide substrate.

[0007] In some embodiments, the injecting P-type doped ions into the first region and annealing after removing the first self-aligned dielectric layer to form a P-type shielding region on the bottom of the gate trench comprises: injecting P-type doped ions into the first region; removing the first self-aligned dielectric layer and annealing at an environment of 1650-1800℃.

[0008] In some embodiments, the forming a field oxide layer on the gate material layer comprises: depositing a field oxide material to form the field oxide layer, and coating photoresist on the field oxide layer, etching the field oxide layer until the regions of the first P-type well region, the second P-type well region, the first N-type doped region, the second N-type doped region, and both sides of the gate dielectric layer are exposed; wherein the width of the field oxide layer is greater than the width of the gate material layer.

[0009] In some embodiments, the depositing a first self-aligned dielectric material to form a first self-aligned dielectric layer in the gate trench and selectively etching the first self-aligned dielectric layer to expose a first region requiring injection of P-type doped ions on the bottom of the gate trench comprises: depositing a silicon nitride material to form an etching stop layer in the gate trench; continuing to deposit a silicon oxide material to form an interlayer dielectric layer covering the entire gate trench; etching the bottom of the gate trench with an etchant to expose the first region requiring injection of P-type doped ions; wherein the position of the first region is defined by the initial gate structure of the device.

[0010] In some embodiments, the depositing the second self-aligned medium material forms a second self-aligned medium layer, and the second self-aligned medium layer is selectively etched to form a first isolation medium layer and a second isolation medium layer on two sides of the bottom of the gate trench, comprising: Depositing a silicon nitride material in the gate trench to form an etching stop layer; Continuing to deposit a silicon oxide material to form an interlayer dielectric layer covering the entire gate trench; Etching the bottom of the gate trench with an etchant to retain the silicon nitride material on two sides of the P-type shielding region to form the first isolation medium layer and the second isolation medium layer; wherein the position of the P-type shielding region is defined by the initial gate structure of the device.

[0011] In some embodiments, the depositing the second self-aligned medium material forms a second self-aligned medium layer, and the second self-aligned medium layer is selectively etched to form a first isolation medium layer and a second isolation medium layer on two sides of the bottom of the gate trench, further comprising: Adjusting the etching selectivity ratio of the silicon oxide material and the silicon nitride material to adjust the topography of the gate trench.

[0012] In some embodiments, the interface between the gate material and the field oxide layer is arc-shaped or stepped.

[0013] The second aspect of the embodiments of the present application further provides a trench silicon carbide device prepared by any of the above preparation methods.

[0014] The third aspect of the embodiments of the present application further provides a chip comprising a trench silicon carbide device prepared by any of the above preparation methods.

[0015] The beneficial effects of the embodiments of the present application are: by defining a trench region through a trench etching mask, etching to form a gate trench deep into the N-type drift region under the coverage of the trench etching mask, and using a self-aligned patterning process to form a P-type shielding region at the bottom of the trench using a first self-aligned medium layer, and using a second self-aligned medium layer to form a first isolation medium layer and a second isolation medium layer on two sides of the bottom of the gate trench, thereby using a self-aligned medium layer as an implantation mask and an isolation layer at the same time, saving multiple photolithography steps, not only improving the alignment accuracy of the P-type shielding region, but also reducing the electric field of the central oxide layer at the bottom of the trench gate, reducing the device gate leakage current phenomenon, improving the reliability of the device, and at the same time solving the two core problems of high-precision doping and high-temperature process compatibility in silicon carbide power devices. BRIEF DESCRIPTION OF DRAWINGS

[0016] Figure 1is a flowchart of a preparation method of self-alignment patterning provided by an embodiment of the present application; Figure 2 is a schematic diagram of part of a preparation process of self-alignment patterning provided by an embodiment of the present application; Figure 3 is a schematic diagram of part of a preparation process of self-alignment patterning provided by an embodiment of the present application; Figure 4 is a schematic diagram of part of a preparation process of self-alignment patterning provided by an embodiment of the present application; Figure 5 is a schematic diagram of part of a preparation process of self-alignment patterning provided by an embodiment of the present application; Figure 6 is a flowchart of a preparation method of self-alignment patterning provided by an embodiment of the present application; Figure 7 is a schematic diagram of part of a preparation process of self-alignment patterning provided by an embodiment of the present application; Figure 8 is a schematic diagram of a silicon carbide power device prepared by a preparation method of self-alignment patterning provided by an embodiment of the present application; Figure 9 is a schematic diagram of a silicon carbide power device prepared by a preparation method of self-alignment patterning provided by an embodiment of the present application; Figure 10 is a schematic diagram of a silicon carbide power device prepared by a preparation method of self-alignment patterning provided by an embodiment of the present application. DETAILED DESCRIPTION

[0017] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present application more clearly understood, the present application will be further described in detail below in combination with the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and not to limit the present application.

[0018] TG-MOSFET can significantly reduce the specific on-resistance by accommodating more channels on a given chip area and completely eliminating the JFET effect. However, for the conventional silicon carbide trench MOSFET in reverse blocking mode, the high electric field in the trench bottom gate oxide layer is the main problem, which makes the breakdown voltage (VBR) limited by the collapse of the gate oxide layer at a voltage much lower than the voltage at which the inherent ability of the drift region semiconductor junction to break down.

[0019] In order to solve the above technical problems, an embodiment of the present application provides a self-alignment patterning preparation method applied to a silicon carbide power device, as shown in Figure 1 The self-alignment patterning preparation method in the embodiment includes steps S100 to S600.

[0020] In step S100, a silicon carbide substrate 210 is provided, and a buffer layer 220, an N-type drift region 230, a current spreading material layer 240, and a P-type doped layer 250 are sequentially formed on the front surface of the silicon carbide substrate 210.

[0021] In this embodiment, the N-type doped layer and the P-type doped layer can be sequentially formed on the front surface of the silicon carbide substrate 210 by epitaxy or ion implantation doping, as shown in schematic structure (a) of FIG. 1. Figure 2

[0022] In step S200, N-type doped ions are implanted in a preset region of the P-type doped layer 250 to form an N-type doped layer 260, and a gate trench 311 is etched to the N-type drift region 230 under the coverage of a trench etching mask 301.

[0023] In this embodiment, in combination with the schematic structure (a) shown in FIG. 1, the preset region of the P-type doped layer 250 can be the central region. By implanting N-type doped ions in the central region of the P-type doped layer 250, the implantation depth of the N-type doped ions is less than the thickness of the P-type doped layer 250, so that the thickness of the formed N-type doped layer 260 is less than the thickness of the P-type doped layer 250. Figure 2 In combination with the schematic structure (b) shown in FIG. 1, the trench etching mask 301 is used to define the trench region, the trench etching mask 301 covers the P-type doped layer 250 and the N-type doped layer 260, and exposes the trench region to be etched.

[0024] Figure 2 In combination with the schematic structure (c) shown in FIG. 1, the gate trench 311 is etched to the N-type drift region 230 under the coverage of the trench etching mask 301, the depth of the gate trench 311 is greater than the sum of the thicknesses of the P-type doped layer 250 and the current spreading material layer 240, and the trench etching mask 301 is removed after etching is completed, as shown in schematic structure (d) of FIG. 1. Figure 2 Figure 2 The formed gate trench 311 divides the current spreading material layer 240 into a first current spreading layer 241 and a second current spreading layer 242, divides the P-type doped layer 250 into a first P-type well region 251 and a second P-type well region 252, and divides the N-type doped layer 260 into a first N-type doped region 261 and a second N-type doped region 262.

[0025] ​​​In some embodiments, the N-type doped layer 260 is formed by implanting N-type doped ions into the central region of the P-type doped layer 250, and the first P-type well region 251 and the second P-type well region 252 are in L-shaped structure; the first N-type doped region 261 is formed on the horizontal part of the first P-type well region 251, and the second N-type doped region 262 is formed on the horizontal part of the second P-type well region 252.

[0026] In some embodiments, the gate trench 311 reaches the N-type drift region 230, the lower surface of the gate trench 311 is the groove bottom of the N-type drift region 230, and the distance between the groove bottom of the N-type drift region 230 and the lower surface of the current spreading material layer 240 is greater than the thickness of the current spreading material layer 240. The N-type drift region 230 is in a concave structure, the first current spreading layer 241 and the first P-type well region 251 are formed on the first side of the N-type drift region 230, and the second current spreading layer 242 and the second P-type well region 252 are formed on the second side of the N-type drift region 230.

[0027] In step S300, a first self-aligned dielectric material is deposited in the gate trench 311 to form a first self-aligned dielectric layer 401, and the first self-aligned dielectric layer 401 is selectively etched to expose the first region requiring implantation of P-type doped ions at the bottom of the gate trench 312.

[0028] In the present embodiment, as shown in Figure 3 , the first self-aligned dielectric material is deposited on the bottom and inner wall of the gate trench 311, and on the P-type doped layer 250 and the N-type doped layer 260 to form the first self-aligned dielectric layer 401, as shown in schematic structure (a) in Figure 3 . After selective etching of the first self-aligned dielectric layer 401, a new gate trench 312 is formed, the bottom of the new gate trench 312 reaches the N-type drift region 230, and the first region requiring implantation of P-type doped ions is exposed, the first region being located at the bottom region of the gate trench 312, as shown in schematic structure (b) in Figure 3 .

[0029] In step S400, P-type doped ions are implanted into the first region, and annealing treatment is performed after removing the first self-aligned dielectric layer 401 to form the P-type shielding region 310.

[0030] In the present embodiment, as shown in Figure 3 , P-type doped ions are implanted into the first region at the bottom of the gate trench 312, and a new gate trench 313 is obtained after removing the first self-aligned dielectric layer 401, and the P-type shielding region 310 is formed after annealing treatment, obtaining the schematic structure (d) in Figure 3 , in which the P-type shielding region 310 is formed at the groove bottom of the N-type drift region 230.

[0031] In some embodiments, the doping concentration of the P-type shielding region 310 is distributed in a gradient manner.

[0032] In step S500, a second self-aligned dielectric material is deposited to form a second self-aligned dielectric layer 402, and the second self-aligned dielectric layer 402 is selectively etched to form a first isolation dielectric layer 321 and a second isolation dielectric layer 322 on both sides of the bottom of the gate trench 313, respectively.

[0033] In the present embodiment, the second self-aligned dielectric layer 402 is formed by combining the self-aligned multi-patterning process and the photolithography process. Figure 4 As shown in FIG. 4B, a second self-aligned dielectric material is deposited to form a second self-aligned dielectric layer 402 on the bottom and inner wall of the gate trench 313, and on the P-type doped layer 250 and the N-type doped layer 260, as shown in schematic structure (a) of FIG. 4C. Figure 4 After the second self-aligned dielectric layer 402 is selectively etched, a new gate trench 314 is formed, and a first isolation dielectric layer 321 and a second isolation dielectric layer 322 are formed on both sides of the bottom of the gate trench 314, respectively, as shown in schematic structure (b) of FIG. 4D. Figure 4

[0034] In the present embodiment, since the photolithography process is performed by using a mask, the alignment needs to be performed once for each mask, which not only increases the process time, but also causes the problem of alignment error. In the present embodiment, the self-aligned multi-patterning process is used to form the initial linear pattern in the initial stage of the photolithography process, and the self-aligned dielectric material (such as silicon oxide material or silicon nitride material) is deposited by ALD or CVD in the deposition stage. Then, the spacer is selectively etched and reserved, and the lower layer material is selectively etched to form a new gate trench by using the spacer as a mask. The material characteristics (such as etching selectivity, surface energy difference) or the physical characteristics of the deposition / etching process are used to automatically align the pattern without the need for multiple photolithography alignment. In this way, the cost of three masks can be reduced, the process time and the alignment error can be shortened, the etching precision can be improved, and the yield can be improved and the complexity of the photolithography process can be reduced.

[0035] In some embodiments, the second self-aligned dielectric material can include silicon oxide material and silicon nitride material, so that the second self-aligned dielectric layer 402 of the composite dielectric material is formed. After the second self-aligned dielectric layer 402 is selectively etched, a new gate trench 314 is formed, and a first isolation dielectric layer 321 and a second isolation dielectric layer 322 with higher dielectric constant are formed on both sides of the bottom of the gate trench 314, respectively.

[0036] In some embodiments, the first isolation dielectric layer 321 is in contact with the first current spreading layer 241 and the first side step bottom of the gate dielectric layer 410; and the second isolation dielectric layer 322 is in contact with the second current spreading layer 242 and the second side step bottom of the gate dielectric layer 410.

[0037] ​In the embodiment, the P-type shielding region 310 and the first and second isolation dielectric layers 321 and 322 on both sides of the trench bottom gate oxide can further reduce the electric field concentration effect of the gate bottom corner region, avoid high electric field breakdown, reduce the device gate leakage current phenomenon, and improve the reliability of the device.

[0038] In step S600, after forming the gate dielectric layer 410 at the bottom and inner wall of the gate trench 314, the gate material layer 500 is formed in the recess of the gate dielectric layer 410, and the field oxide layer 420 is formed on the gate material layer 500.

[0039] In the embodiment, the P-type shielding region 310 and the first and second isolation dielectric layers 321 and 322 on both sides of the trench bottom gate oxide can further reduce the electric field concentration effect of the gate bottom corner region, avoid high electric field breakdown, reduce the device gate leakage current phenomenon, and improve the reliability of the device. Figure 4 and Figure 5 As shown in FIG. 13B, the gate dielectric layer 410 is deposited at the bottom and inner wall of the gate trench 313 to obtain the schematic structure (c) in FIG. 13C. The gate material 403 is filled in the recess of the gate dielectric layer 410 to obtain the schematic structure (a) in FIG. 13D. The gate material is etched to form the gate material layer 500, as shown in the schematic structure (b) in FIG. 13E. In combination with the schematic structure (c) in FIG. 13C, the field oxide material is deposited on the gate material layer 500 to form the field oxide layer 420. Figure 4 Figure 5 As shown in FIG. 13B, the gate dielectric layer 410 is deposited at the bottom and inner wall of the gate trench 313 to obtain the schematic structure (c) in FIG. 13C. The gate material 403 is filled in the recess of the gate dielectric layer 410 to obtain the schematic structure (a) in FIG. 13D. The gate material is etched to form the gate material layer 500, as shown in the schematic structure (b) in FIG. 13E. In combination with the schematic structure (c) in FIG. 13C, the field oxide material is deposited on the gate material layer 500 to form the field oxide layer 420. Figure 5 Figure 5 As shown in FIG. 13B, the gate dielectric layer 410 is deposited at the bottom and inner wall of the gate trench 313 to obtain the schematic structure (c) in FIG. 13C. The gate material 403 is filled in the recess of the gate dielectric layer 410 to obtain the schematic structure (a) in FIG. 13D. The gate material is etched to form the gate material layer 500, as shown in the schematic structure (b) in FIG. 13E. In combination with the schematic structure (c) in FIG. 13C, the field oxide material is deposited on the gate material layer 500 to form the field oxide layer 420.

[0040] In some embodiments, the first N-type doped region 261 is formed between the first side of the gate dielectric layer 410 and the first P-type well region 251, and the second N-type doped region 262 is formed between the second side of the gate dielectric layer 410 and the second P-type well region 252. The distance between the two sides of the gate dielectric layer 410 gradually increases from the bottom to the opening. The height of the gate dielectric layer 410 is greater than the sum of the heights of the first current spreading layer 241 and the first P-type well region 251. The first and second isolation dielectric layers 321 and 322 are located on both sides of the gate dielectric layer 410, and the bottoms of the first and second isolation dielectric layers 321 and 322 are flush with the bottom of the gate dielectric layer 410. The source layer 120 is in contact with the first P-type well region 251, the second P-type well region 252, the first N-type doped region 261, the second N-type doped region 262, the two sides of the gate dielectric layer 410, and the field oxide layer 420.

[0041] In some embodiments, the gate dielectric layer 410 is a concave structure, the bottom of the gate dielectric layer 410 is arc-shaped, and the first and second isolation dielectric layers 321 and 322 are respectively attached to both sides of the bottom of the gate dielectric layer 410, and the first and second isolation dielectric layers 321 and 322 are arc-shaped.

[0042] ​​In some embodiments, the gate material layer 500 can be a metal material. By setting a metal gate, the threshold voltage instability phenomenon of the device during the reliability operation process can be improved.

[0043] In some embodiments, the first isolation medium layer 321 and the second isolation medium layer 322 can be a silicon oxide and silicon nitride composite medium layer, which can be formed by alternately setting multiple layers of silicon oxide layers and silicon nitride layers.

[0044] In the present embodiment, the first isolation medium layer 321 and the second isolation medium layer 322 can be formed by chemically depositing a second self-aligned medium material and then etching. In the same reaction chamber, by adjusting the reaction gas in an alternating time period, for example, gradually increasing the nitrogen and reducing the oxygen, the stage gradually deposits silicon nitride, and if the oxygen is gradually increased and the nitrogen is gradually reduced, the stage gradually deposits silicon oxide. At the same time, the silicon-containing gas needs to be introduced, and the content of various gases in the mixed gas is controlled to control the content of oxygen and nitrogen in the thin film, so as to achieve the purpose of alternately depositing the silicon oxide layer and the silicon nitride layer in the same reaction chamber.

[0045] In some embodiments, the gate medium layer 410 is a symmetrical structure.

[0046] In some embodiments, the inner wall of the groove of the gate medium layer 410 is a stepped structure.

[0047] In the present embodiment, the inner diameter of the groove of the gate medium layer 410 gradually decreases from the source layer 120 to the drain layer 110, and the inner wall of the groove of the gate medium layer 410 is a stepped structure.

[0048] In some embodiments, the two side portions of the gate medium layer 410 are a stepped structure.

[0049] In the present embodiment, the inner wall of the groove of the gate medium layer 410 is a stepped structure, and the outer surface of the two side portions of the gate medium layer 410 is also a stepped structure.

[0050] In some embodiments, referring to Figure 6 As shown in the figure, the preparation method in the present embodiment further includes steps S710 to S720.

[0051] In step S710, a source electrode material is deposited to form a source layer 120 in contact with the first P-type well region 251, the second P-type well region 252, the first N-type doped region 261, the second N-type doped region 262, the two side portions of the gate medium layer 410, and the field oxide layer 420.

[0052] In combination with Figure 7As shown in schematic structure (a) in FIG. 4, photoresist 302 is formed on field oxide layer 420 to define source electrode region, and then part of first P-type well region 251, second P-type well region 252, first N-type doped region 261 and second N-type doped region 262 are exposed by etching field oxide layer 420 under the cover of photoresist 302, as shown in schematic structure (b) in FIG. 4. Figure 7 As shown in schematic structure (a) in FIG. 4, photoresist 302 is formed on field oxide layer 420 to define source electrode region, and then part of first P-type well region 251, second P-type well region 252, first N-type doped region 261 and second N-type doped region 262 are exposed by etching field oxide layer 420 under the cover of photoresist 302, as shown in schematic structure (b) in FIG. 4. Figure 7 As shown in schematic structure (a) in FIG. 4, photoresist 302 is formed on field oxide layer 420 to define source electrode region, and then part of first P-type well region 251, second P-type well region 252, first N-type doped region 261 and second N-type doped region 262 are exposed by etching field oxide layer 420 under the cover of photoresist 302, as shown in schematic structure (b) in FIG. 4.

[0053] In step S720, drain electrode material is deposited to form drain layer 110 on the back surface of silicon carbide substrate 210.

[0054] In this embodiment, the trench silicon carbide device formed by source layer 120 and drain layer 110 is as shown in schematic structure (c) and schematic structure (d) in FIG. 4. Figure 8As shown, the trench silicon carbide device comprises a drain layer 110, a silicon carbide substrate 210, a buffer layer 220, an N-type drift region 230, a first current spreading layer 241, a second current spreading layer 242, a first P-type well region 251, a second P-type well region 252, a gate dielectric layer 410, a first isolation dielectric layer 321, a second isolation dielectric layer 322, a gate material layer 500, a P-type shielding region 310, a first N-type doped region 261, a second N-type doped region 262, a field oxide layer 420, and a source layer 120. The drain layer 110, the silicon carbide substrate 210, the buffer layer 220, and the N-type drift region 230 are stacked; the N-type drift region 230 is a concave structure, the first current spreading layer 241 and the first P-type well region 251 are formed on a first side of the N-type drift region 230, and the second current spreading layer 242 and the second P-type well region 252 are formed on a second side of the N-type drift region 230; the P-type shielding region 310 is formed at the bottom of the recess of the N-type drift region 230, the gate dielectric layer 410 is formed on the P-type shielding region 310, and the gate dielectric layer 410 is a concave structure, and the gate dielectric layer 410 and the field oxide layer 420 form a closed structure wrapping the gate material layer 500. The first N-type doped region 261 is formed between the first side of the gate dielectric layer 410 and the first P-type well region 251, and the second N-type doped region 262 is formed between the second side of the gate dielectric layer 410 and the second P-type well region 252. The distance between the two sides of the gate dielectric layer 410 gradually increases from the bottom to the opening, and the height of the gate dielectric layer 410 is greater than the sum of the heights of the first current spreading layer 241 and the first P-type well region 251. The first isolation dielectric layer 321 and the second isolation dielectric layer 322 are located on both sides of the gate dielectric layer 410, and the bottoms of the first isolation dielectric layer 321 and the second isolation dielectric layer 322 are flush with the bottom of the gate dielectric layer 410. The source layer 120 contacts the first P-type well region 251, the second P-type well region 252, the first N-type doped region 261, the second N-type doped region 262, the two sides of the gate dielectric layer 410, and the field oxide layer 420.

[0055] In the embodiment, the first self-aligned medium layer 401 and the second self-aligned medium layer 402 are used as the self-aligned medium layer, and the self-aligned medium layer is used as the implantation mask and the isolation layer at the same time, thereby saving the multiple photolithography steps, improving the alignment accuracy of the P-type shielding region, reducing the electric field of the central oxide layer at the bottom of the trench gate, reducing the gate leakage current of the device, improving the reliability of the device, and solving the two core problems of high-precision doping and high-temperature process compatibility in the silicon carbide power device. In the TG-MOS device, when the device is operated in reverse and the drain is operated at a high voltage, there is an electric field concentration effect at the corner of the gate oxide at the bottom of the trench gate, which causes the gate oxide to collapse and the leakage current, and the device may not pass the reliability test. In the present application, the P-type shielding region 310 is formed at the bottom of the groove of the N-type drift region 230, the gate medium layer 410 with a concave structure is formed on the P-type shielding region 310, and the gate medium layer 410 and the field oxide layer 420 form a closed structure of the gate material layer 500, thereby reducing the electric field of the central oxide layer at the bottom of the trench gate, and the P-type shielding region 310 and the first isolation medium layer 321 and the second isolation medium layer 322 on both sides of the trench bottom gate oxide can further reduce the electric field concentration effect of the corner region at the bottom of the gate, avoid the high electric field collapse, reduce the gate leakage current of the device, and improve the reliability of the device.

[0056] In some embodiments, in step S400, P-type doping ions are implanted into the first region, and annealing treatment is performed after the first self-aligned medium layer 401 is removed to form a P-type shielding region at the bottom of the gate trench, including: implanting P-type doping ions into the first region; removing the first self-aligned medium layer 401 and performing annealing treatment in an environment of 1650-1800°C.

[0057] In the embodiment, the first self-aligned medium layer 401 is used as a mask, P-type doping ions can be implanted into the N-type drift region 230 through the first region at the bottom of the gate trench 312 to form the P-type shielding region 310. In the case that the first self-aligned medium layer 401 is used as a mask, the implantation process of the P-type doping ions can be performed multiple times, so that the doping concentration of the P-type shielding region 310 presents a trapezoidal gradient.

[0058] In some embodiments, the P-type doping ions can include aluminum ions.

[0059] In some embodiments, in step S600, the field oxide layer 420 is formed on the gate material layer 500, including: using photoresist to define the coverage range of the field oxide layer 420, and etching the silicon oxide material under the coverage of the photoresist until the first P-type well region 251 and the second P-type well region 252, to form the field oxide layer 420 on the gate medium layer 410 and the gate material layer 500.

[0060] In the embodiment, the width of the field oxide layer 420 is greater than the width of the gate material layer 500 by etching the field oxide layer 420, so that the subsequent electrode deposition material can be in contact with the first P-type well region 251, the second P-type well region 252, the first N-type doped region 261, the second N-type doped region 262, and the two side portions of the gate dielectric layer 410.

[0061] In some embodiments, in step S300, the first self-aligned dielectric layer 401 is deposited, and the first self-aligned dielectric layer 401 is selectively etched to expose the first region requiring implantation of P-type doped ions at the bottom of the gate trench 311, including: depositing silicon nitride material in the gate trench 311 to form an etching stop layer; continuing to deposit silicon oxide material to form an interlayer dielectric layer covering the entire gate trench 311; and etching the bottom of the gate trench 311 with an etchant to expose the first region requiring implantation of P-type doped ions.

[0062] In the embodiment, the position of the first region is defined by the initial gate structure of the device, and the deposition of the silicon nitride material as the etching stop layer can ensure high-precision pattern transfer, control the critical dimension, and reduce process defects. Specifically, in the self-alignment process, the etching stop layer utilizes the difference in etching rate with adjacent materials (such as silicon oxide and polysilicon) to accurately stop etching during pattern transfer, avoiding over-etching of the underlying structure, and the etching stop layer can also prevent the loss of inner and outer stop layer height of the side wall, ensuring the uniformity of subsequent pattern transfer.

[0063] In some embodiments, the etching selectivity ratio of the etching stop layer to the adjacent material is greater than or equal to 10:1.

[0064] In some embodiments, by adjusting the nitrogen content in the silicon nitride material, the etching stop layer can include a multi-layer structure, and adjusting the etching speed of the etching stop layer can also facilitate the adjustment of the shape and size of the first region.

[0065] In some embodiments, in step S500, the second self-aligned dielectric material is deposited to form the second self-aligned dielectric layer 402, and the second self-aligned dielectric layer 402 is selectively etched to form the first isolation dielectric layer 321 and the second isolation dielectric layer 322 on both sides of the bottom of the gate trench, including: depositing silicon nitride material in the gate trench to form an etching stop layer; continuing to deposit silicon oxide material to form an interlayer dielectric layer covering the entire gate trench; and etching the bottom of the gate trench with an etchant to retain the silicon nitride material on both sides of the P-type shielding region 310 to form the first isolation dielectric layer 321 and the second isolation dielectric layer 322.

[0066] In the embodiment, the position of the P-type shielding region 310 is defined by the initial gate structure of the device. In the second self-alignment process, the mandrel is first determined, the initial linear pattern is established, the silicon nitride material is deposited as the etching stop layer, the mandrel provides the geometric reference for the subsequent deposition of the side wall, the thickness of the etching stop layer is determined, which can ensure the high-precision transfer of the pattern, control the critical dimension, and reduce the process defects. Then, the interlayer dielectric layer is deposited, and the etchant is used to etch the bottom of the gate trench to reserve the silicon nitride material on both sides of the P-type shielding region 310 as the first isolation medium layer 321 and the second isolation medium layer 322.

[0067] In the self-alignment process, the etching stop layer utilizes the difference in etching rate with the adjacent material (such as silicon oxide and polysilicon) to accurately stop etching during pattern transfer, avoiding over-etching of the underlying structure, and the etching stop layer can also prevent the loss of the height of the inner and outer side wall stop layers, ensuring the uniformity of the subsequent pattern transfer.

[0068] In some embodiments, in step S500, the second self-alignment medium material is deposited to form a second self-alignment medium layer, and the second self-alignment medium layer is selectively etched to form a first isolation medium layer and a second isolation medium layer on both sides of the bottom of the gate trench, and the method further comprises: adjusting the etching selectivity ratio of the silicon oxide material and the silicon nitride material to adjust the topography of the gate trench.

[0069] In the embodiment, the selective removal is achieved by the difference in etching rate of different materials (such as silicon oxynitride and silicon), and the pattern is automatically aligned without the need for multiple photolithography alignments by using the material characteristics (such as etching selectivity ratio and surface energy difference) or the physical characteristics of the deposition / etching process.

[0070] In some embodiments, the interface between the gate material layer 500 and the field oxide layer 420 is arc-shaped or stepped.

[0071] In some embodiments, the first side step top of the gate medium layer 410 is formed on the upper surface of the first N-type doped region 261, and the second side step top of the gate medium layer 410 is formed on the upper surface of the second N-type doped region 262.

[0072] In some embodiments, the interface between the gate material layer 500 and the field oxide layer 420 is arc-shaped, and the top of the arc is close to the P-type shielding region 310.

[0073] In some embodiments, the contact interface between the P-type shielding region 310 and the gate medium layer 410 is located between the first isolation medium layer 321 and the second isolation medium layer 322.

[0074] In the embodiment, relative to the double-trench MOSFET structure, the self-aligned patterning photolithography technology is used to complete the back corner barrier oxide layer at the bottom corner of the trench of the silicon carbide trench gate MOSFET to reduce the electric field concentration effect at the corner, avoid the high electric field collapse and reduce the gate leakage current phenomenon, and improve the device operation reliability. The process and structure can significantly reduce the high electric field of the bottom central oxide layer of the trench gate, also can reduce the cell size and the JFET area impedance in the device, and improve the specific on-resistance R on，sp .

[0075] The embodiment of the present application also provides a trench silicon carbide device prepared by the preparation method in any one of the above embodiments.

[0076] The silicon carbide power device (DT_MOS) prepared by the self-aligned patterning preparation method provided in the embodiment of the present application can significantly reduce the electric field concentration effect at the corner, avoid the high electric field collapse and reduce the gate leakage current phenomenon, and improve the device operation reliability, compared with the example silicon carbide power device. Moreover, the breakdown voltage BV of the silicon carbide power device (DT_MOS) is obviously improved compared with the breakdown voltage BV of the example silicon carbide power device, and the on-resistance R on of the silicon carbide power device (DT_MOS) is also obviously reduced compared with the on-resistance R on of the example silicon carbide power device.

[0077] The static FOM measures the "area-resistance" benchmark of the on-efficiency of the device, determines the upper limit of the chip cost and the heat dissipation design, and the dynamic FOM is usually used to evaluate the performance of the device in the switching process, especially the charge-related characteristics, can quantify the topology-sensitive index of the switching-on loss balance, and drive the high frequency and energy efficiency optimization. In order to reduce the switching loss and improve the high frequency application performance, the device performance needs to be improved by reducing the gate charge or the on-resistance, and the smaller the value is, the better. By comparing the simulation parameters of the silicon carbide power device prepared by the self-aligned patterning preparation method provided in the embodiment of the present application and the example silicon carbide power device, it can be known that the static FOM of the silicon carbide power device (DT_MOS) is obviously improved compared with the static FOM of the example silicon carbide power device, and the dynamic FOM of the silicon carbide power device (DT_MOS) is also obviously reduced compared with the dynamic FOM of the example silicon carbide power device. The silicon carbide power device (DT_MOS) prepared by the self-aligned patterning preparation method provided in the embodiment of the present application can obviously obtain the optimization of the dynamic FOM and the static FOM, compared with the example silicon carbide power device.

[0078] The embodiment of the present application also provides a chip comprising the trench silicon carbide device prepared by the self-aligned patterning preparation method in any one of the above embodiments.

[0079] In the embodiment, the chip comprises a chip substrate, and one or more trench silicon carbide devices prepared by the self-aligned patterning preparation method are arranged on the substrate.

[0080] In a specific application embodiment, other related semiconductor devices can also be integrated on the chip substrate to form an integrated circuit together with the self-aligned patterning preparation method.

[0081] In a specific application embodiment, the chip can be a switching chip or a driving chip.

[0082] The beneficial effects of the embodiments of the present application are as follows: the P-type shielding region is formed at the bottom of the recess in the N-type drift region, the gate dielectric layer is formed on the P-type shielding region, and the gate dielectric layer has a concave structure; the gate dielectric layer and the field oxide layer form a closed structure of the gate material layer; the P-type shielding region is formed at the bottom of the trench in the self-aligned patterning preparation method, so as to reduce the electric field of the central oxide layer at the bottom of the trench gate, reduce the gate leakage current phenomenon of the trench silicon carbide device, and improve the reliability of the device.

[0083] Those skilled in the art can clearly understand that, for the convenience and brevity of description, only the above-mentioned various doped regions and device divisions are exemplified, and in actual application, the above-mentioned functions can be completed by different doped regions and devices according to needs, that is, the internal structure of the device is divided into different doped regions to complete all or part of the functions described above. The doped regions and devices in the embodiments can be integrated in one unit, or each unit can exist physically alone, or two or more units can be integrated in one unit.

[0084] In addition, the specific names of the doped regions and devices are only for the convenience of mutual differentiation, and are not used to limit the protection scope of the present application.

[0085] In the above embodiments, the description of each embodiment has its own emphasis, and the parts not described or recorded in detail in a certain embodiment can be referred to the related description of other embodiments.

[0086] In addition, the doped regions in each embodiment of the present application can be integrated in one unit, or each unit can exist physically alone, or two or more units can be integrated in one unit.

[0087] The above-described embodiments are only used to illustrate the technical solutions of the present application, but not limit them; although the present application is described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: it can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement to part of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application, and should be included in the protection scope of the present application.

Claims

1. A method for preparing self-aligned patterned patterns, characterized in that, The self-aligned patterning fabrication method, applied to silicon carbide power devices, includes: A silicon carbide substrate is provided, and a buffer layer, an N-type drift region, a current spreading material layer, and a P-type doped layer are sequentially formed on the front side of the silicon carbide substrate. N-type dopant ions are implanted in a predetermined region of the P-type doped layer to form an N-type doped layer, and a gate trench extending into the N-type drift region is formed by etching along a portion of the N-type doped layer. This divides the current spreading material layer into a first current spreading layer and a second current spreading layer, the P-type doped layer into a first P-type well region and a second P-type well region, and the N-type doped layer into a first N-type doped region and a second N-type doped region. A first self-aligned dielectric material is deposited in the gate trench to form a first self-aligned dielectric layer, and the first self-aligned dielectric layer is selectively etched to expose a first region at the bottom of the gate trench that needs to be implanted with P-type doped ions. P-type doped ions are implanted into the first region, and after removing the first self-aligned dielectric layer, the region is annealed to form a P-type shielding region. A second self-aligned dielectric material is deposited to form a second self-aligned dielectric layer, and the second self-aligned dielectric layer is selectively etched to form a first isolation dielectric layer and a second isolation dielectric layer on both sides of the bottom of the gate trench, respectively. After forming a gate dielectric layer at the bottom and on the inner wall of the gate trench, a gate material layer is formed in the groove of the gate dielectric layer, and a field oxide layer is formed on the gate material layer; wherein, the gate dielectric layer and the field oxide layer form a closed structure that encloses the gate material layer.

2. The self-aligned patterning preparation method as described in claim 1, characterized in that, The preparation method further includes: Deposit source electrode material to form a source layer that contacts the first P-type well region, the second P-type well region, the first N-type doped region, the second N-type doped region, both sides of the gate dielectric layer, and the field oxide layer; Deposit drain electrode material to form a drain layer on the back side of the silicon carbide substrate.

3. The self-aligned patterning preparation method as described in claim 1 or 2, characterized in that, The step of implanting P-type doped ions into the first region and annealing after removing the first self-aligned dielectric layer to form a P-type shielding region at the bottom of the gate trench includes: P-type doped ions are injected into the first region; Remove the first self-aligned dielectric layer and anneal it at 1650-1800°C.

4. The self-aligned patterning preparation method as described in claim 2, characterized in that, The formation of a field oxide layer on the gate material layer includes: A field oxide layer is formed by depositing a field oxide material, and photoresist is coated on the field oxide layer. The field oxide layer is then etched until the first P-type well region, the second P-type well region, the first N-type doped region, the second N-type doped region, and the regions on both sides of the gate dielectric layer are exposed; wherein the width of the field oxide layer is greater than the width of the gate material layer.

5. The self-aligned patterning preparation method as described in claim 1 or 2, characterized in that, The step of depositing a first self-aligned dielectric material in the gate trench to form a first self-aligned dielectric layer, and selectively etching the first self-aligned dielectric layer to expose a first region at the bottom of the gate trench that requires implantation of P-type doped ions, includes: Silicon nitride material is deposited in the gate trench to form an etch stop layer; Continue depositing silicon oxide material to form an interlayer dielectric layer covering the entire gate trench; The bottom of the gate trench is etched using an etchant to expose a first region to be implanted with P-type doped ions; wherein the location of the first region is defined by the initial gate structure of the device.

6. The self-aligned patterning preparation method as described in claim 1 or 2, characterized in that, The deposition of the second self-aligned dielectric material forms a second self-aligned dielectric layer, and the second self-aligned dielectric layer is selectively etched to form a first isolation dielectric layer and a second isolation dielectric layer on both sides of the bottom of the gate trench, respectively, including: Silicon nitride material is deposited in the gate trench to form an etch stop layer; Continue depositing silicon oxide material to form an interlayer dielectric layer covering the entire gate trench; The bottom of the gate trench is etched using an etchant to retain the silicon nitride material on both sides of the P-type shielding region, thereby forming the first isolation dielectric layer and the second isolation dielectric layer; wherein, the position of the P-type shielding region is defined by the initial gate structure of the device.

7. The self-aligned patterning preparation method as described in claim 6, characterized in that, The method of depositing a second self-aligned dielectric material to form a second self-aligned dielectric layer, and selectively etching the second self-aligned dielectric layer to form a first isolation dielectric layer and a second isolation dielectric layer on both sides of the bottom of the gate trench, further includes: The etching selectivity ratio of the silicon oxide material and the silicon nitride material is adjusted to regulate the morphology of the gate trench.

8. The self-aligned patterning preparation method as described in claim 7, characterized in that, The interface between the gate material and the field oxide layer is arc-shaped or stepped.

9. A trench silicon carbide device, characterized in that, The trench silicon carbide device is prepared by the preparation method according to any one of claims 1-8.

10. A chip, characterized in that, Including trench silicon carbide devices prepared by the preparation method according to any one of claims 1-8.

Images