Method of manufacturing self-aligned pattern, trench silicon carbide device, and chip

Abstract

The application belongs to the technical field of power devices, and provides a self-alignment patterning preparation method, a trench silicon carbide device and a chip. A trench etching mask is used to define a trench region. A gate trench is etched to reach the N-type drift region under the coverage of the trench etching mask. A first self-alignment medium layer is used to form a P-type shielding region at the bottom of the trench by using a self-alignment patterning process. A second self-alignment medium layer is used to form a first isolation medium layer and a second isolation medium layer on both sides of the bottom of the gate trench. The self-alignment medium layer is used as an implantation mask and an isolation layer at the same time, thereby saving multiple photolithography steps. The alignment accuracy of the P-type shielding region is improved, the electric field of the central oxide layer at the bottom of the trench gate is reduced, the device gate leakage current phenomenon is reduced, the reliability of the device is improved, and the two core problems of high-precision doping and high-temperature process compatibility in the silicon carbide power device are solved.

Description

Technical Field

[0001] This application belongs to the field of power device technology, and particularly relates to a self-aligned patterning fabrication method, trench silicon carbide devices, and chips. Background Technology

[0002] Due to their excellent material properties, including wide bandgap, high critical electric field, and good thermal conductivity, silicon carbide (SiC) trench-gate metal-oxide-semiconductor field-effect transistors (TG-MOSFETs) exhibit very high gate density without being limited by the parasitic junction field-effect transistor (JFET) channels found in planar SiC MOSFETs. This reduces the contribution of channel resistance to the total on-resistance. Compared to traditional planar MOSFETs, TG-MOSFETs can significantly reduce specific on-resistance by accommodating more channels within a given chip area and completely eliminating the JFET effect.

[0003] However, the current fabrication process for silicon carbide trench MOSFETs requires multiple layers of photoresist for photolithography and etching, which is not only costly but also time-consuming. Summary of the Invention

[0004] To address the aforementioned technical problems, embodiments of this application provide a self-aligned patterning fabrication method, a trench silicon carbide device, and a chip. The self-aligned patterning process forms a P-type shielding region, a first isolation dielectric layer, and a second isolation dielectric layer at the bottom of the gate trench, thereby reducing the electric field of the central oxide layer at the bottom of the trench gate, reducing gate leakage current, and improving device reliability.

[0005] The first aspect of this application provides a method for fabricating self-aligned patterning, applied to silicon carbide power devices, the method comprising:

[0006] A silicon carbide substrate is provided, and a buffer layer, an N-type drift region, a current spreading material layer, and a P-type doped layer are sequentially formed on the front side of the silicon carbide substrate.

[0007] N-type dopant ions are implanted in a predetermined region of the P-type doped layer to form an N-type doped layer, and a gate trench extending into the N-type drift region is formed by etching along a portion of the N-type doped layer.

[0008] A first self-aligned dielectric material is deposited in the gate trench to form a first self-aligned dielectric layer, and the first self-aligned dielectric layer is selectively etched to expose a first region at the bottom of the gate trench that needs to be implanted with P-type doped ions.

[0009] P-type doped ions are implanted into the first region, and after removing the first self-aligned dielectric layer, the region is annealed to form a P-type shielding region.

[0010] A second self-aligned dielectric material is deposited to form a second self-aligned dielectric layer, and the second self-aligned dielectric layer is selectively etched to form a first isolation dielectric layer and a second isolation dielectric layer on both sides of the bottom of the gate trench, respectively.

[0011] After forming a gate dielectric layer at the bottom and on the inner wall of the gate trench, a gate material layer is formed in the groove of the gate dielectric layer, and a field oxide layer is formed on the gate material layer; wherein, the gate dielectric layer and the field oxide layer form a closed structure that encloses the gate material layer.

[0012] In some embodiments, the preparation method further includes:

[0013] Deposit source electrode material to form a source layer that contacts the first P-type well region, the second P-type well region, the first N-type doped region, the second N-type doped region, both sides of the gate dielectric layer, and the field oxide layer;

[0014] Deposit drain electrode material to form a drain layer on the back side of the silicon carbide substrate.

[0015] In some embodiments, implanting P-type dopant ions into the first region and annealing after removing the first self-aligned dielectric layer to form a P-type shielding region at the bottom of the gate trench includes:

[0016] P-type doped ions are injected into the first region;

[0017] Remove the first self-aligned dielectric layer and anneal it at 1650-1800°C.

[0018] In some embodiments, forming a field oxide layer on the gate material layer includes:

[0019] A field oxide layer is formed by depositing a field oxide material, and photoresist is coated on the field oxide layer. The field oxide layer is then etched until the first P-type well region, the second P-type well region, the first N-type doped region, the second N-type doped region, and the regions on both sides of the gate dielectric layer are exposed; wherein the width of the field oxide layer is greater than the width of the gate material layer.

[0020] In some embodiments, the step of depositing a first self-aligned dielectric material in the gate trench to form a first self-aligned dielectric layer, and selectively etching the first self-aligned dielectric layer to expose a first region at the bottom of the gate trench that requires implantation of P-type doped ions, includes:

[0021] Silicon nitride material is deposited in the gate trench to form an etch stop layer;

[0022] Continue depositing silicon oxide material to form an interlayer dielectric layer covering the entire gate trench;

[0023] The bottom of the gate trench is etched using an etchant to expose a first region to be implanted with P-type doped ions; wherein the location of the first region is defined by the initial gate structure of the device.

[0024] In some embodiments, the deposition of the second self-aligned dielectric material to form a second self-aligned dielectric layer, and the selective etching of the second self-aligned dielectric layer to form a first isolation dielectric layer and a second isolation dielectric layer on both sides of the bottom of the gate trench, respectively, includes:

[0025] Silicon nitride material is deposited in the gate trench to form an etch stop layer;

[0026] Continue depositing silicon oxide material to form an interlayer dielectric layer covering the entire gate trench;

[0027] The bottom of the gate trench is etched using an etchant to retain the silicon nitride material on both sides of the P-type shielding region, thereby forming the first isolation dielectric layer and the second isolation dielectric layer; wherein, the position of the P-type shielding region is defined by the initial gate structure of the device.

[0028] In some embodiments, the deposition of the second self-aligned dielectric material to form a second self-aligned dielectric layer, and the selective etching of the second self-aligned dielectric layer to form a first isolation dielectric layer and a second isolation dielectric layer on both sides of the bottom of the gate trench, further includes:

[0029] The etching selectivity ratio of the silicon oxide material and the silicon nitride material is adjusted to regulate the morphology of the gate trench.

[0030] In some embodiments, the interface between the gate material and the field oxide layer is arc-shaped or stepped.

[0031] A second aspect of this application also provides a trench silicon carbide device, which is prepared by any of the preparation methods described above.

[0032] A third aspect of this application also provides a chip, including a trench silicon carbide device prepared by the preparation method described in any of the preceding claims.

[0033] The beneficial effects of this application's embodiments are as follows: a trench region is defined by a trench etching mask, and a gate trench extending into the N-type drift region is etched under the coverage of the trench etching mask. A self-aligned patterning process is used to form a P-type shielding region at the bottom of the trench using a first self-aligned dielectric layer, and a first isolation dielectric layer and a second isolation dielectric layer are formed on both sides of the bottom of the gate trench using a second self-aligned dielectric layer. Thus, the self-aligned dielectric layer is used as both an injection mask and an isolation layer, saving multiple photolithography steps. This not only improves the alignment accuracy of the P-type shielding region, but also reduces the electric field of the central oxide layer at the bottom of the trench gate, reduces gate leakage current, and improves device reliability. At the same time, it solves the two core problems of high-precision doping and high-temperature process compatibility in silicon carbide power devices. Attached Figure Description

[0034] Figure 1 This is a schematic flowchart of a self-aligned patterning preparation method provided in an embodiment of this application;

[0035] Figure 2 This is a schematic diagram of a portion of the fabrication process for self-aligned patterning provided in the embodiments of this application;

[0036] Figure 3 This is a schematic diagram of a portion of the fabrication process for self-aligned patterning provided in the embodiments of this application;

[0037] Figure 4 This is a schematic diagram of a portion of the fabrication process for self-aligned patterning provided in the embodiments of this application;

[0038] Figure 5 This is a schematic diagram of a portion of the fabrication process for self-aligned patterning provided in the embodiments of this application;

[0039] Figure 6 This is a schematic flowchart of a self-aligned patterning preparation method provided in an embodiment of this application;

[0040] Figure 7 This is a schematic diagram of a portion of the fabrication process for self-aligned patterning provided in the embodiments of this application;

[0041] Figure 8 This is a schematic diagram of the structure of a silicon carbide power device prepared by the self-aligned patterning method provided in the embodiments of this application;

[0042] Figure 9 This is a schematic diagram of the structure of a silicon carbide power device prepared by the self-aligned patterning method provided in the embodiments of this application;

[0043] Figure 10 This is a schematic diagram of the structure of a silicon carbide power device prepared by the self-aligned patterning method provided in the embodiments of this application. Detailed Implementation

[0044] To make the technical problems, technical solutions, and beneficial effects to be solved by this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and are not intended to limit the scope of this application.

[0045] TG-MOSFETs can significantly reduce specific on-resistance by accommodating more channels on a given chip area and completely eliminating the JFET effect. However, for conventional silicon carbide trench MOSFETs in reverse blocking mode, the high electric field in the gate oxide layer at the bottom of the trench is a major problem, which limits the breakdown voltage (VBR) to gate oxide collapse at voltages far below the inherent breakdown capability of the drift region semiconductor junction.

[0046] To address the aforementioned technical problems, this application provides a self-aligned patterning fabrication method for silicon carbide power devices. (See also...) Figure 1 As shown, the self-aligned patterning preparation method in this embodiment includes steps S100 to S600.

[0047] In step S100, a silicon carbide substrate 210 is provided, and a buffer layer 220, an N-type drift region 230, a current spreading material layer 240, and a P-type doped layer 250 are sequentially formed on the front side of the silicon carbide substrate 210.

[0048] In this embodiment, a buffer layer 220, an N-type drift region 230, a current spreading material layer 240, and a P-type doped layer 250 can be formed sequentially on the front side of the silicon carbide substrate 210 by epitaxy or ion implantation doping. Figure 2 The schematic structure (a) is shown in the figure.

[0049] In step S200, N-type dopant ions are implanted in a preset region of the P-type doped layer 250 to form an N-type doped layer 260, and a gate trench 311 extending into the N-type drift region 230 is formed under the cover of the trench etching mask 301.

[0050] In this embodiment, combined with Figure 2 As shown in the schematic structure (a), the preset region of the P-type doped layer 250 can be its central region. By injecting N-type dopant ions into the central region of the P-type doped layer 250, the injection depth of the N-type dopant ions is less than the thickness of the P-type doped layer 250, so that the thickness of the formed N-type doped layer 260 is less than the thickness of the P-type doped layer 250.

[0051] Combination Figure 2As shown in the schematic structure (b), a trench etching mask 301 is used to define the trench region. The trench etching mask 301 covers the P-type doped layer 250 and the N-type doped layer 260, exposing the trench region to be etched. Combined with... Figure 2 As shown in the schematic structure (c), a gate trench 311 extending into the N-type drift region 230 is formed under the cover of the trench etching mask 301. The depth of the gate trench 311 is greater than the sum of the thicknesses of the P-type doped layer 250 and the current spreading material layer 240. After etching, the trench etching mask 301 is removed. Figure 2 The schematic structure (d) is shown in the diagram. The formed gate trench 311 divides the current spreading material layer 240 into a first current spreading layer 241 and a second current spreading layer 242, divides the P-type doped layer 250 into a first P-type well region 251 and a second P-type well region 252, and divides the N-type doped layer 260 into a first N-type doped region 261 and a second N-type doped region 262.

[0052] In some embodiments, an N-type doped layer 260 is formed by implanting N-type dopant ions into the central region of the P-type doped layer 250, and the first P-type well region 251 and the second P-type well region 252 are L-shaped structures; the first N-type doped region 261 is formed on the horizontal portion of the first P-type well region 251, and the second N-type doped region 262 is formed on the horizontal portion of the second P-type well region 252.

[0053] In some embodiments, the gate trench 311 extends into the N-type drift region 230, and the lower surface of the gate trench 311 forms the bottom of the recess in the N-type drift region 230. The distance between the bottom of the recess in the N-type drift region 230 and the lower surface of the current spreading material layer 240 is greater than the thickness of the current spreading material layer 240. The N-type drift region 230 has a concave structure. The first current spreading layer 241 and the first P-type well region 251 are formed on the first side of the N-type drift region 230, and the second current spreading layer 242 and the second P-type well region 252 are formed on the second side of the N-type drift region 230.

[0054] In step S300, a first self-aligned dielectric material is deposited in the gate trench 311 to form a first self-aligned dielectric layer 401, and the first self-aligned dielectric layer 401 is selectively etched to expose a first region at the bottom of the gate trench 312 that needs to be implanted with P-type doped ions.

[0055] In this embodiment, combined with Figure 3 As shown, depositing a first self-aligned dielectric material on the bottom and inner wall of the gate trench 311, as well as on the P-type doped layer 250 and the N-type doped layer 260, can form a first self-aligned dielectric layer 401, such as... Figure 3The schematic structure is shown in (a). After selective etching of the first self-aligned dielectric layer 401, a new gate trench 312 is formed. The bottom of the new gate trench 312 extends into the N-type drift region 230 and exposes a first region requiring P-type doped ions to be implanted. This first region is located at the bottom of the gate trench 312, as shown in the diagram. Figure 3 The schematic structure (b) is shown in the figure.

[0056] In step S400, P-type doped ions are implanted into the first region, and after removing the first self-aligned dielectric layer 401, an annealing process is performed to form a P-type shielding region 310.

[0057] In this embodiment, combined with Figure 3 As shown, P-type doped ions are implanted into the first region at the bottom of the gate trench 312, and a new gate trench 313 is obtained after removing the first self-aligned dielectric layer 401. After annealing, a P-type shielding region 310 is formed, resulting in... Figure 3 The schematic structure (d) shows that the P-type shielding area 310 is formed at the bottom of the groove of the N-type drift area 230.

[0058] In some embodiments, the doping concentration of the P-type shielding region 310 exhibits a gradient distribution.

[0059] In step S500, a second self-aligned dielectric material is deposited to form a second self-aligned dielectric layer 402, and the second self-aligned dielectric layer 402 is selectively etched to form a first isolation dielectric layer 321 and a second isolation dielectric layer 322 on both sides of the bottom of the gate trench 313, respectively.

[0060] In this embodiment, combined with Figure 4 As shown, a second self-aligned dielectric layer 402 is formed by depositing a second self-aligned dielectric material on the bottom and inner wall of the gate trench 313, as well as on the P-type doped layer 250 and the N-type doped layer 260. Figure 4 The schematic structure is shown in (a). After selective etching of the second self-aligned dielectric layer 402, a new gate trench 314 is formed. A first isolation dielectric layer 321 and a second isolation dielectric layer 322 are formed on both sides of the bottom of the gate trench 314, as shown in the diagram. Figure 4 The schematic structure (b) is shown in the figure.

[0061] In this embodiment, since each photomask requires alignment during photolithography, it not only increases process time but also introduces alignment errors. By employing a self-aligned multi-patterning process, an initial linear pattern is established at the beginning of the photolithography process. During the deposition stage, a self-aligned dielectric material (such as silicon oxide or silicon nitride) can be deposited via ALD or CVD. Then, spacers are selectively etched. Using the spacers as a mask, the underlying material is selectively etched to form new gate trenches. By utilizing material properties (such as etching selectivity and surface energy differences) or the physical properties of the deposition / etching process, the pattern can be automatically aligned without multiple photolithography alignments. This reduces the cost of three photomasks, shortens process time and alignment errors, improves etching accuracy, and helps improve yield and reduce the complexity of the photolithography process.

[0062] In some embodiments, the second self-aligned dielectric material may include silicon oxide and silicon nitride, thereby forming a second self-aligned dielectric layer 402 of composite dielectric material. After selective etching of the second self-aligned dielectric layer 402, a new gate trench 314 is formed. A first isolation dielectric layer 321 and a second isolation dielectric layer 322 with higher dielectric constant are formed on both sides of the bottom of the gate trench 314, respectively.

[0063] In some embodiments, the first isolation dielectric layer 321 is in contact with the bottom of the first side step of the first current spreading layer 241 and the gate dielectric layer 410; the second isolation dielectric layer 322 is in contact with the bottom of the second side step of the second current spreading layer 242 and the gate dielectric layer 410.

[0064] In this embodiment, the P-type shielding region 310 and the first isolation dielectric layer 321 and the second isolation dielectric layer 322 on both sides of the gate oxide at the bottom of the trench can further reduce the electric field concentration effect in the bottom corner region of the gate, avoid high electric field collapse, reduce the gate leakage current phenomenon of the device, and improve the reliability of the device.

[0065] In step S600, after forming a gate dielectric layer 410 at the bottom and inner wall of the gate trench 314, a gate material layer 500 is formed in the groove of the gate dielectric layer 410, and a field oxide layer 420 is formed on the gate material layer 500.

[0066] In this embodiment, combined with Figure 4 and Figure 5 As shown, a gate dielectric layer 410 is deposited at the bottom and inner wall of the gate trench 313 to obtain Figure 4 The schematic structure (c) shows that the gate material 403 is filled into the groove of the gate dielectric layer 410. Figure 5 In the schematic structure (a), the gate material is etched to form a gate material layer 500, as shown. Figure 5 The schematic structure (b) is shown in the diagram. Combined with... Figure 5 As shown in the schematic structure (c), a field oxide material is deposited on the gate material layer 500 to form a field oxide layer 420, and a gate dielectric layer 410 is formed on the P-type shielding region 310. The gate dielectric layer 410 has a concave structure, and the gate dielectric layer 410 and the field oxide layer 420 form a closed structure that encloses the gate material layer 500.

[0067] In some embodiments, a first N-type doped region 261 is formed between a first side of the gate dielectric layer 410 and a first P-type well region 251, and a second N-type doped region 262 is formed between a second side of the gate dielectric layer 410 and a second P-type well region 252. The spacing between the two sides of the gate dielectric layer 410 gradually increases from the bottom to the opening. The height of the gate dielectric layer 410 is greater than the sum of the heights of the first current extension layer 241 and the first P-type well region 251. A first isolation dielectric layer 321 and a second isolation dielectric layer 322 are located on both sides of the gate dielectric layer 410, and the bottoms of the first isolation dielectric layer 321 and the second isolation dielectric layer 322 are flush with the bottom of the gate dielectric layer 410. The source layer 120 is in contact with the first P-type well region 251, the second P-type well region 252, the first N-type doped region 261, the second N-type doped region 262, the two sides of the gate dielectric layer 410, and the field oxide layer 420.

[0068] In some embodiments, the gate dielectric layer 410 has a concave structure, the bottom of the gate dielectric layer 410 is arc-shaped, the first isolation dielectric layer 321 and the second isolation dielectric layer 322 are respectively attached to the bottom sides of the gate dielectric layer 410, and the first isolation dielectric layer 321 and the second isolation dielectric layer 322 are arc-shaped.

[0069] In some embodiments, the gate material layer 500 can be a metal material. By providing a metal gate, the phenomenon of unstable threshold voltage during reliable operation of the device can be improved.

[0070] In some embodiments, the first isolation dielectric layer 321 and the second isolation dielectric layer 322 may be a composite dielectric layer of silicon oxide and silicon nitride, which may be formed by alternating layers of silicon oxide and silicon nitride.

[0071] In this embodiment, a first isolation dielectric layer 321 and a second isolation dielectric layer 322 can be formed by chemically depositing a second self-aligned dielectric material and then etching. In the same reaction chamber, by adjusting the reaction gas in alternating time periods, for example, by gradually increasing nitrogen and decreasing oxygen, silicon nitride is gradually deposited in that stage; if oxygen is gradually increased and nitrogen is decreased, silicon oxide is gradually deposited in that stage. At the same time, silicon-containing gas needs to be introduced. By adjusting the content of various gases in the mixed gas, the oxygen and nitrogen content in the film can be controlled, thereby achieving the purpose of alternating deposition of silicon oxide and silicon nitride layers in the same reaction chamber.

[0072] In some embodiments, the gate dielectric layer 410 has a symmetrical structure.

[0073] In some embodiments, the inner wall of the groove in the gate dielectric layer 410 has a stepped structure.

[0074] In this embodiment, the inner diameter of the groove in the gate dielectric layer 410 gradually decreases from the source layer 120 to the drain layer 110, and the inner wall of the groove in the gate dielectric layer 410 has a stepped structure.

[0075] In some embodiments, the two sides of the gate dielectric layer 410 have a stepped structure.

[0076] In this embodiment, the inner wall of the groove of the gate dielectric layer 410 is a stepped structure, and the outer surfaces of both sides of the gate dielectric layer 410 are also stepped structures.

[0077] In some embodiments, see Figure 6 As shown, the preparation method in this embodiment further includes steps S710 to S720.

[0078] In step S710, source electrode material is deposited to form a source layer 120 that contacts the first P-type well region 251, the second P-type well region 252, the first N-type doped region 261, the second N-type doped region 262, both sides of the gate dielectric layer 410, and the field oxide layer 420.

[0079] Combination Figure 7 As shown in the schematic structure (a), photoresist 302 is formed on the field oxide layer 420 to define the source electrode region. Then, under the coverage of the photoresist 302, the field oxide layer 420 is etched to expose parts of the first P-type well region 251, the second P-type well region 252, the first N-type doped region 261, and the second N-type doped region 262, as shown in the schematic structure (a). Figure 7 The schematic structure (b) is shown in the diagram. After removing the photoresist 302, source electrode material is deposited to form the source layer 120, as shown in the diagram. Figure 7 The schematic structures (c) and (d) are shown in the figure.

[0080] In step S720, drain electrode material is deposited to form a drain layer 110 on the back side of the silicon carbide substrate 210.

[0081] In this embodiment, the trench silicon carbide device formed by the source layer 120 and drain layer 110 is as follows: Figure 8As shown, the trench silicon carbide device includes: a drain layer 110, a silicon carbide substrate 210, a buffer layer 220, an N-type drift region 230, a first current spreading layer 241, a second current spreading layer 242, a first P-type well region 251, a second P-type well region 252, a gate dielectric layer 410, a first isolation dielectric layer 321, a second isolation dielectric layer 322, a gate material layer 500, a P-type shielding region 310, a first N-type doped region 261, a second N-type doped region 262, a field oxide layer 420, and a source layer 120. A drain layer 110, a silicon carbide substrate 210, a buffer layer 220, and an N-type drift region 230 are stacked together. The N-type drift region 230 has a concave structure. A first current spreading layer 241 and a first P-type well region 251 are formed on the first side of the N-type drift region 230, and a second current spreading layer 242 and a second P-type well region 252 are formed on the second side of the N-type drift region 230. A P-type shielding region 310 is formed at the bottom of the groove of the N-type drift region 230, and a gate dielectric layer 410 is formed on the P-type shielding region 310. The gate dielectric layer 410 has a concave structure, and the gate dielectric layer 410 and the field oxide layer 420 form a closed structure that encloses the gate material layer 500. A first N-type doped region 261 is formed between the first side of the gate dielectric layer 410 and the first P-type well region 251, and a second N-type doped region 262 is formed between the second side of the gate dielectric layer 410 and the second P-type well region 252. The spacing between the two sides of the gate dielectric layer 410 gradually increases from the bottom to the opening. The height of the gate dielectric layer 410 is greater than the sum of the heights of the first current extension layer 241 and the first P-type well region 251. The first isolation dielectric layer 321 and the second isolation dielectric layer 322 are located on both sides of the gate dielectric layer 410, and the bottoms of the first isolation dielectric layer 321 and the second isolation dielectric layer 322 are flush with the bottom of the gate dielectric layer 410. The source layer 120 is in contact with the first P-type well region 251, the second P-type well region 252, the first N-type doped region 261, the second N-type doped region 262, the two sides of the gate dielectric layer 410, and the field oxide layer 420.

[0082] In this embodiment, the first self-aligned dielectric layer 401 and the second self-aligned dielectric layer 402 serve as self-aligned dielectric layers, acting as both an injection mask and an isolation layer. This saves multiple photolithography steps, improves the alignment accuracy of the P-type shielding region, reduces the electric field of the central oxide layer at the bottom of the trench gate, reduces gate leakage current, and improves device reliability. It also solves two core challenges in silicon carbide power devices: high-precision doping and high-temperature process compatibility. In TG-MOS devices, during reverse operation and high drain voltage operation, an electric field concentration effect exists at the gate oxide corners at the bottom of the trench gate, causing gate oxide collapse and leakage current, potentially preventing the device from passing reliability tests. In this application, a P-type shielding region 310 can be formed at the bottom of the trench in the N-type drift region 230, and a gate dielectric layer 410 with a concave structure can be formed on the P-type shielding region 310. The gate dielectric layer 410 and the field oxide layer 420 form a closed structure that encloses the gate material layer 500, thereby reducing the electric field of the central oxide layer at the bottom of the trench gate. Furthermore, the P-type shielding region 310 and the first isolation dielectric layer 321 and the second isolation dielectric layer 322 on both sides of the gate oxide at the bottom of the trench can further reduce the electric field concentration effect in the corner region at the bottom of the gate, avoid high electric field collapse, reduce the gate leakage current phenomenon of the device, and improve the reliability of the device.

[0083] In some embodiments, step S400 involves implanting P-type dopant ions into the first region and annealing after removing the first self-aligned dielectric layer 401 to form a P-type shielding region at the bottom of the gate trench. This includes: implanting P-type dopant ions into the first region; removing the first self-aligned dielectric layer 401; and annealing at an environment of 1650-1800°C.

[0084] In this embodiment, using the first self-aligned dielectric layer 401 as a mask, P-type dopant ions can be injected into the N-type drift region 230 through the first region at the bottom of the gate trench 312 to form a P-type shielding region 310. With the first self-aligned dielectric layer 401 as a mask, the P-type dopant ion injection process can be performed multiple times, so that the doping concentration of the P-type shielding region 310 gradually changes in a trapezoidal shape.

[0085] In some embodiments, the p-type doped ion may include aluminum ions.

[0086] In some embodiments, step S600, forming a field oxide layer 420 on the gate material layer 500, includes: defining the coverage area of ​​the field oxide layer 420 with photoresist, and etching silicon oxide material under the coverage of photoresist up to the first P-type well region 251 and the second P-type well region 252, so as to form a field oxide layer 420 on the gate dielectric layer 410 and the gate material layer 500.

[0087] In this embodiment, by etching the field oxide layer 420, the width of the field oxide layer 420 is set to be greater than the width of the gate material layer 500, so that the subsequent electrode deposition material can contact the first P-type well region 251, the second P-type well region 252, the first N-type doped region 261, the second N-type doped region 262, and both sides of the gate dielectric layer 410.

[0088] In some embodiments, in step S300, depositing a first self-aligned dielectric layer 401 and selectively etching the first self-aligned dielectric layer 401 to expose a first region at the bottom of the gate trench 311 that requires the implantation of P-type doped ions includes: depositing silicon nitride material in the gate trench 311 to form an etch stop layer; continuing to deposit silicon oxide material to form an interlayer dielectric layer covering the entire gate trench 311; and using an etchant to etch the bottom of the gate trench 311 to expose the first region that requires the implantation of P-type doped ions.

[0089] In this embodiment, the location of the first region is defined by the initial gate structure of the device. Depositing silicon nitride as an etch stop layer ensures high-precision pattern transfer, controls critical dimensions, and reduces process defects. Specifically, in the self-aligned process, the etch stop layer utilizes the difference in etching rate with adjacent materials (such as silicon oxide or polysilicon) to precisely stop etching during pattern transfer, preventing over-etching of the underlying structure. Furthermore, the etch stop layer also prevents height loss of the stop layer inside and outside the sidewalls, ensuring uniformity of subsequent pattern transfer.

[0090] In some embodiments, the etching selectivity ratio between the etch stop layer and the adjacent material is greater than or equal to 10:1.

[0091] In some embodiments, by adjusting the nitrogen content in the silicon nitride material, the etch stop layer can include a multi-layer structure. Adjusting the etching rate of the etch stop layer can also facilitate the adjustment of the shape and size of the first region.

[0092] In some embodiments, in step S500, depositing a second self-aligned dielectric material to form a second self-aligned dielectric layer 402, and selectively etching the second self-aligned dielectric layer 402 to form a first isolation dielectric layer 321 and a second isolation dielectric layer 322 on both sides of the bottom of the gate trench, includes: depositing silicon nitride material in the gate trench to form an etch stop layer; continuing to deposit silicon oxide material to form an interlayer dielectric layer covering the entire gate trench; and using an etchant to etch the bottom of the gate trench to retain the silicon nitride material on both sides of the P-type shielding region 310 to form the first isolation dielectric layer 321 and the second isolation dielectric layer 322.

[0093] In this embodiment, the position of the P-type shielding region 310 is defined by the initial gate structure of the device. In the second self-alignment process, the mandrel is first determined, an initial linear pattern is established, and silicon nitride material is deposited as an etch stop layer. The mandrel provides a geometric reference for subsequent sidewall deposition, and the sidewall thickness of the etch stop layer is determined, which can ensure high-precision pattern transfer, control critical dimensions, and reduce process defects. Then, an interlayer dielectric layer is deposited, and an etchant is used to etch the bottom of the gate trench to retain the silicon nitride material on both sides of the P-type shielding region 310 as the first isolation dielectric layer 321 and the second isolation dielectric layer 322.

[0094] In self-aligned processes, the etch stop layer utilizes the difference in etch rate with adjacent materials (such as silicon oxide and polysilicon) to precisely stop etching during pattern transfer, avoiding over-etching of the underlying structure. Furthermore, the etch stop layer can also prevent the loss of stop layer height inside and outside the sidewalls, ensuring the uniformity of subsequent pattern transfer.

[0095] In some embodiments, step S500 involves depositing a second self-aligned dielectric material to form a second self-aligned dielectric layer, and selectively etching the second self-aligned dielectric layer to form a first isolation dielectric layer and a second isolation dielectric layer on both sides of the bottom of the gate trench, and further includes adjusting the etching selectivity ratio of silicon oxide material and silicon nitride material to adjust the morphology of the gate trench.

[0096] In this embodiment, selective removal is achieved by utilizing the difference in etching rates of different materials (such as silicon oxynitride and silicon). By utilizing material properties (such as etching selectivity and surface energy differences) or the physical properties of the deposition / etching process, the pattern can be automatically aligned without the need for multiple photolithographic alignments.

[0097] In some embodiments, the interface between the gate material layer 500 and the field oxide layer 420 is arc-shaped or stepped.

[0098] In some embodiments, the top of the first side step of the gate dielectric layer 410 is formed on the upper surface of the first N-type doped region 261; the top of the second side step of the gate dielectric layer 410 is formed on the upper surface of the second N-type doped region 262.

[0099] In some embodiments, the interface between the gate material layer 500 and the field oxide layer 420 is arc-shaped, with the apex of the arc close to the P-type shielding region 310.

[0100] In some embodiments, the contact interface between the P-type shielding region 310 and the gate dielectric layer 410 is located between the first isolation dielectric layer 321 and the second isolation dielectric layer 322.

[0101] In this embodiment, compared to the dual-trench MOSFET structure, this application uses self-aligned patterned photolithography to apply a bottom corner barrier oxide layer at the bottom corners of both sides of the trench in the silicon carbide trench gate MOSFET. This reduces the electric field concentration effect at the corners, avoids high-field collapse, reduces gate leakage current, and improves device operational reliability. This process and structure can significantly reduce the high electric field of the central oxide layer at the bottom of the trench gate, and also reduce the cell size and the impedance of the JFET region within the device, improving the specific on-resistance R of the device. on，sp .

[0102] This application also provides a trench silicon carbide device, which is prepared by the preparation method described in any of the above embodiments.

[0103] The silicon carbide power device (DT_MOS) fabricated by the self-aligned patterning method provided in this application significantly reduces the electric field concentration effect at the corners compared to the example silicon carbide power device, avoiding high electric field collapse and reducing gate leakage current, thus improving device operational reliability. Furthermore, the breakdown voltage BV of the silicon carbide power device (DT_MOS) is significantly improved compared to the example silicon carbide power device, and the on-resistance R of the silicon carbide power device (DT_MOS) is also significantly improved. on Compared to the on-resistance R of the example silicon carbide power device on It also shows a significant reduction.

[0104] Static FOM (Field-of-Meaning) measures the "area-resistance" benchmark of device conduction efficiency, determining the upper limit of chip cost and thermal design. Dynamic FOM is typically used to evaluate device performance during switching processes, especially charge-related characteristics. It can quantify the topology-sensitive index of switching-conduction loss balance, driving high-frequency and energy efficiency optimization. To reduce switching losses and improve high-frequency application performance, it is necessary to improve device performance by reducing gate charge or on-resistance; the smaller the value, the better. Comparison of simulation parameters between the silicon carbide power device (DT_MOS) fabricated by the self-aligned patterning method provided in this application and the example silicon carbide power device shows that the static FOM of the silicon carbide power device (DT_MOS) is significantly improved compared to the example silicon carbide power device, and the dynamic FOM of the silicon carbide power device (DT_MOS) is also significantly reduced compared to the example silicon carbide power device. The silicon carbide power device (DT_MOS) fabricated by the self-aligned patterning method provided in this application can significantly achieve optimization of both dynamic and static FOM compared to the example silicon carbide power device.

[0105] This application also provides a chip, including a trench silicon carbide device fabricated by the self-aligned patterning method of any of the above embodiments.

[0106] In this embodiment, the chip includes a chip substrate, on which one or more trench silicon carbide devices prepared by a self-aligned patterning method are disposed.

[0107] In one specific application embodiment, other related semiconductor devices can also be integrated on the chip substrate to form an integrated circuit with the self-aligned patterning fabrication method.

[0108] In one specific application embodiment, the chip can be a switch chip or a driver chip.

[0109] The beneficial effects of the embodiments of this application are as follows: A P-type shielding region is formed at the bottom of the trench in the N-type drift region, and a gate dielectric layer is formed on the P-type shielding region. The gate dielectric layer has a concave structure, and the gate dielectric layer and the field oxide layer form a closed structure that encloses the gate material layer. By forming a P-type shielding region at the bottom of the trench in the self-aligned patterning fabrication method, the electric field of the central oxide layer at the bottom of the trench gate is reduced, the gate leakage current phenomenon of the trench silicon carbide device is reduced, and the reliability of the device is improved.

[0110] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of doped regions and devices is used as an example. In practical applications, the above functions can be assigned to different doped regions and devices as needed, that is, the internal structure of the device can be divided into different doped regions to complete all or part of the functions described above. In the embodiments, the doped regions and devices can be integrated into one unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0111] Furthermore, the specific names of each doped region and device are only for the purpose of distinguishing them from each other and are not intended to limit the scope of protection of this application.

[0112] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0113] In addition, in the various embodiments of this application, each doped region can be integrated into one unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0114] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A method for preparing self-aligned patterned patterns, characterized in that, The self-aligned patterning fabrication method, applied to silicon carbide power devices, includes: A silicon carbide substrate is provided, and a buffer layer, an N-type drift region, a current spreading material layer, and a P-type doped layer are sequentially formed on the front side of the silicon carbide substrate. N-type dopant ions are implanted in a predetermined region of the P-type doped layer to form an N-type doped layer, and a gate trench extending into the N-type drift region is formed by etching along a portion of the N-type doped layer. This divides the current spreading material layer into a first current spreading layer and a second current spreading layer, the P-type doped layer into a first P-type well region and a second P-type well region, and the N-type doped layer into a first N-type doped region and a second N-type doped region. A first self-aligned dielectric material is deposited in the gate trench to form a first self-aligned dielectric layer, and the first self-aligned dielectric layer is selectively etched to expose a first region at the bottom of the gate trench that needs to be implanted with P-type doped ions. P-type doped ions are implanted into the first region, and after removing the first self-aligned dielectric layer, the region is annealed to form a P-type shielding region. A second self-aligned dielectric material is deposited to form a second self-aligned dielectric layer, and the second self-aligned dielectric layer is selectively etched to form a first isolation dielectric layer and a second isolation dielectric layer on both sides of the bottom of the gate trench, respectively. After forming a gate dielectric layer at the bottom and on the inner wall of the gate trench, a gate material layer is formed in the groove of the gate dielectric layer, and a field oxide layer is formed on the gate material layer; wherein, the gate dielectric layer and the field oxide layer form a closed structure that encloses the gate material layer.

2. The self-aligned patterning preparation method as described in claim 1, characterized in that, The preparation method further includes: Deposit source electrode material to form a source layer that contacts the first P-type well region, the second P-type well region, the first N-type doped region, the second N-type doped region, both sides of the gate dielectric layer, and the field oxide layer; Deposit drain electrode material to form a drain layer on the back side of the silicon carbide substrate.

3. The self-aligned patterning preparation method as described in claim 1 or 2, characterized in that, The step of implanting P-type doped ions into the first region and annealing after removing the first self-aligned dielectric layer to form a P-type shielding region at the bottom of the gate trench includes: P-type doped ions are injected into the first region; Remove the first self-aligned dielectric layer and anneal it at 1650-1800°C.

4. The self-aligned patterning preparation method as described in claim 2, characterized in that, The formation of a field oxide layer on the gate material layer includes: A field oxide layer is formed by depositing a field oxide material, and photoresist is coated on the field oxide layer. The field oxide layer is then etched until the first P-type well region, the second P-type well region, the first N-type doped region, the second N-type doped region, and the regions on both sides of the gate dielectric layer are exposed; wherein the width of the field oxide layer is greater than the width of the gate material layer.

5. The self-aligned patterning preparation method as described in claim 1 or 2, characterized in that, The step of depositing a first self-aligned dielectric material in the gate trench to form a first self-aligned dielectric layer, and selectively etching the first self-aligned dielectric layer to expose a first region at the bottom of the gate trench that requires implantation of P-type doped ions, includes: Silicon nitride material is deposited in the gate trench to form an etch stop layer; Continue depositing silicon oxide material to form an interlayer dielectric layer covering the entire gate trench; The bottom of the gate trench is etched using an etchant to expose a first region to be implanted with P-type doped ions; wherein the location of the first region is defined by the initial gate structure of the device.

6. The self-aligned patterning preparation method as described in claim 1 or 2, characterized in that, The deposition of the second self-aligned dielectric material forms a second self-aligned dielectric layer, and the second self-aligned dielectric layer is selectively etched to form a first isolation dielectric layer and a second isolation dielectric layer on both sides of the bottom of the gate trench, respectively, including: Silicon nitride material is deposited in the gate trench to form an etch stop layer; Continue depositing silicon oxide material to form an interlayer dielectric layer covering the entire gate trench; The bottom of the gate trench is etched using an etchant to retain the silicon nitride material on both sides of the P-type shielding region, thereby forming the first isolation dielectric layer and the second isolation dielectric layer; wherein, the position of the P-type shielding region is defined by the initial gate structure of the device.

7. The self-aligned patterning preparation method as described in claim 6, characterized in that, The method of depositing a second self-aligned dielectric material to form a second self-aligned dielectric layer, and selectively etching the second self-aligned dielectric layer to form a first isolation dielectric layer and a second isolation dielectric layer on both sides of the bottom of the gate trench, further includes: The etching selectivity ratio of the silicon oxide material and the silicon nitride material is adjusted to regulate the morphology of the gate trench.

8. The self-aligned patterning preparation method as described in claim 7, characterized in that, The interface between the gate material and the field oxide layer is arc-shaped or stepped.

9. A trench silicon carbide device, characterized in that, The trench silicon carbide device is prepared by the preparation method according to any one of claims 1-8.

10. A chip, characterized in that, Including trench silicon carbide devices prepared by the preparation method according to any one of claims 1-8.

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