A trench silicon carbide MOSFET and a preparation method and a chip thereof

Abstract

This application belongs to the field of power device technology and provides a trench silicon carbide MOSFET and its fabrication method and chip. By discretizing the P-type well region inside the device into a first P-type well region, a second P-type well region, and a third P-type well region with different doping concentrations, the third P-type well region is located below the gate oxide layer, and the first P-type well region and the second P-type well region are located outside the gate oxide layer. The first P-type well region and the second P-type well region are isolated by the horizontal portion of the second current spread layer. The first P-type well region and the third P-type well region act as a breakdown junction and deplete the second current spread layer near the channel of the second P-type well region. The third P-type well region can terminate the drain electric field line to realize the transfer of the electric field peak in the gate oxide layer, improve the gate reliability of the device, and extend the service life. At the same time, it plays a certain role in shielding the drain voltage, reducing the parasitic capacitance at the bottom of the gate trench, optimizing the gate drain charge, and optimizing the dynamic characteristics of the device.

Description

Technical Field

[0001] This application belongs to the field of power device technology, and in particular relates to a trench silicon carbide MOSFET and its fabrication method and chip. Background Technology

[0002] Due to their excellent material properties, including wide bandgap, high critical electric field, and good thermal conductivity, silicon carbide-based devices, such as the SiC Trench-Gate Metal Oxide Semiconductor Field Effect Transistor (SiC TG-MOSFET), have very high gate density without being limited by the parasitic JFET channels in planar SiC MOSFETs, thus reducing the contribution of channel resistance to the total on-resistance.

[0003] Compared to traditional planar MOSFETs, TG-MOSFETs can significantly reduce specific on-resistance by accommodating more channels within a given chip area and completely eliminating the JFET effect. However, during device operation, high electric field peaks tend to form in the gate oxide layer of the trench, especially at the bottom corner, affecting the reliability of long-term operation; the gate-drain capacitance is generally large, resulting in higher switching time and switching losses. To alleviate these problems, continuous optimization of the trench SiC MOSFET structure is necessary. Summary of the Invention

[0004] To address the aforementioned technical problems, this application provides a trench silicon carbide MOSFET and its fabrication method and chip, aiming to reduce the gate oxide electric field strength and parasitic capacitance of the device without sacrificing the device's on-resistance, thereby optimizing the device's dynamic characteristics.

[0005] The first aspect of this application provides a trench silicon carbide MOSFET, which includes: a drain layer, a silicon carbide substrate, an N-type drift region, a first P-type well region, a second P-type well region, a third P-type well region, a first current spreading layer, a second current spreading layer, a gate oxide layer, an N-type heavily doped region, an insulating dielectric layer, a source layer, and a plurality of P-type heavily doped regions.

[0006] The drain layer, the silicon carbide substrate, and the N-type drift region are stacked in a first direction. The N-type drift region has a concave structure. The third P-type well region is formed at the bottom of the groove of the N-type drift region. The gate oxide layer is formed on the third P-type well region and has a concave structure. A gate layer is formed in the groove of the gate oxide layer.

[0007] The first P-type well region and the first current spreading layer are formed on the horizontal portion of the N-type drift region, and the first P-type well region is located on the side periphery of the gate oxide layer; the second current spreading layer is formed on the first P-type well region and the first current spreading layer, the second P-type well region is formed on the horizontal portion of the second current spreading layer, and the heavily doped N-type region is formed on the horizontal portion of the second P-type well region. The first P-type well region, the second current spreading layer, the second P-type well region, and the heavily doped N-type region are located on both sides of the gate oxide layer within a first predetermined cross section in the second direction.

[0008] Multiple P-type heavily doped regions are spaced apart on the second P-type well region in a third direction, and are located between the vertical portion of the second P-type well region and the second current spreading layer within a second predetermined cross section in the second direction; the first direction, the second direction, and the third direction are perpendicular to each other;

[0009] The source layer and the second current spread layer are connected by a Schottky contact, and the source layer is connected by an ohmic contact with the N-type heavily doped region, the P-type heavily doped region and the second P-type well region. The insulating dielectric layer is disposed between the source layer and the gate layer.

[0010] In some embodiments, the third P-type well region is located below the gate oxide layer, and the distance between the lower surface of the first P-type well region and the upper surface of the third P-type well region is greater than the thickness of the bottom of the gate oxide layer.

[0011] In some embodiments, the doping concentration of the third P-type well region is greater than the doping concentration of the first P-type well region, and the doping concentration of the first P-type well region is greater than the doping concentration of the second P-type well region.

[0012] In some embodiments, the doping concentration of the first current spreading layer is greater than the doping concentration of the second current spreading layer;

[0013] The doping concentrations of the first current spreading layer and the second current spreading layer are greater than the doping concentration of the N-type drift region.

[0014] In some embodiments, the heavily doped P-type region extends into the vertical portion of the first P-type well region, and divides the second current extension layer into isolated horizontal and vertical portions within the second preset cross section; the second preset cross section is horizontally aligned with the third portion.

[0015] In some embodiments, the depth of the P-type heavily doped region in the first direction is greater than the depth of the second current spreading layer, and in the third direction it is located between the vertical portion of the N-type heavily doped region and the second current spreading layer.

[0016] In some embodiments, the contact interface between the P-type heavily doped region and the source layer within the second preset cross-section is smaller than the width of the P-type heavily doped region within the second preset cross-section, so that the N-type heavily doped region does not contact the source layer within the second preset cross-section.

[0017] A second aspect of this application also provides a method for fabricating a trench silicon carbide MOSFET, the method comprising:

[0018] A silicon carbide substrate is provided, and an N-type drift region is formed on the front side of the silicon carbide substrate;

[0019] A first P-type well region and a first current spreading layer are formed on the N-type drift region;

[0020] A second current spreading layer is formed on the first P-type well region and the first current spreading layer along the first direction, and a second P-type well region and an N-type heavily doped region are formed on the second current spreading layer through multiple ion implantation processes; the second current spreading layer and the second P-type well region are concave in shape in the cross section of the second direction;

[0021] Multiple P-type impurities are injected into multiple preset regions spaced upwards from the third side to form multiple heavily doped P-type regions; wherein, the cross-section of the portion between adjacent preset regions in the second direction is defined as a first preset cross-section, and the cross-section of the portion within the preset regions in the second direction is defined as a second preset cross-section.

[0022] The pre-defined trench region on the N-type heavily doped region is etched to form a gate trench that extends into the N-type drift region. P-type impurities are injected into the N-type drift region along the gate trench to form a third P-type well region. A gate oxide layer and a gate layer are formed in the gate trench. The gate layer is located in the groove of the gate oxide layer.

[0023] An insulating dielectric layer is deposited and etched so that the insulating dielectric layer covers the gate layer, and covers a portion of the heavily doped N-type region within the first preset cross section, and covers the entire region of the heavily doped N-type region within the second preset cross section.

[0024] A source layer and a drain layer are formed, wherein the source layer and the second current extension layer are connected by a Schottky contact, and the source layer and the N-type heavily doped region, the P-type heavily doped region and the second P-type well region are connected by an ohmic contact.

[0025] In some embodiments, etching a predetermined trench region on the heavily doped N-type region to form a gate trench extending into the N-type drift region, implanting P-type impurities into the N-type drift region along the gate trench to form a third P-type well region, and forming a gate oxide layer and a gate layer within the gate trench includes:

[0026] P-type doped ion implantation is performed using the same mask as that used to etch the gate trench to form a third P-type well region below the gate trench; wherein the upper surface of the third P-type well region is lower than the lower surface of the first P-type well region.

[0027] A third aspect of this application also provides a chip, including a trench silicon carbide MOSFET as described in any of the preceding claims; or, including a trench silicon carbide MOSFET prepared by the preparation method described in any of the preceding claims.

[0028] The beneficial effects of this application's embodiments are as follows: By discretizing the P-type well region inside the device into a first P-type well region, a second P-type well region, and a third P-type well region with different doping concentrations, the third P-type well region is located below the gate oxide layer, while the first and second P-type well regions are located outside the gate oxide layer. The first and second P-type well regions are isolated by the horizontal portion of the second current spread layer. The first and third P-type well regions act as a breakdown junction and deplete the second current spread layer near the channel of the second P-type well region. The third P-type well region can terminate the drain electric field line to realize the transfer of the electric field peak in the gate oxide layer, thereby improving the gate reliability of the device and extending its service life. At the same time, it plays a certain shielding role for the drain voltage, reduces the parasitic capacitance at the bottom of the gate trench, optimizes the gate drain charge, and optimizes the dynamic characteristics of the device. Attached Figure Description

[0029] Figure 1 This is a schematic diagram of a horizontal cross-section of a trench silicon carbide MOSFET provided in an embodiment of this application;

[0030] Figure 2 This is a schematic diagram of cross-section A of the trench silicon carbide MOSFET provided in an embodiment of this application;

[0031] Figure 3 This is a schematic diagram of cross-section B of the trench silicon carbide MOSFET provided in an embodiment of this application;

[0032] Figure 4 This is a schematic flowchart of a method for fabricating a trench silicon carbide MOSFET provided in an embodiment of this application;

[0033] Figure 5 This is a schematic diagram of one of the structural methods for fabricating a trench silicon carbide MOSFET provided in an embodiment of this application;

[0034] Figure 6 This is a schematic diagram of one of the structures of the trench silicon carbide MOSFET fabrication method provided in the embodiments of this application;

[0035] Figure 7This is a schematic diagram of one of the structures of the trench silicon carbide MOSFET fabrication method provided in the embodiments of this application;

[0036] Figure 8 This is a schematic diagram of one of the structures of the trench silicon carbide MOSFET fabrication method provided in the embodiments of this application;

[0037] Figure 9 This is a schematic diagram of one of the structures of the trench silicon carbide MOSFET fabrication method provided in the embodiments of this application;

[0038] Figure 10 This is a schematic diagram of one of the structures of the trench silicon carbide MOSFET fabrication method provided in the embodiments of this application;

[0039] Figure 11 This is a schematic diagram of one of the structures of the trench silicon carbide MOSFET fabrication method provided in the embodiments of this application;

[0040] Figure 12 This is a schematic diagram of one of the structures of the trench silicon carbide MOSFET fabrication method provided in the embodiments of this application;

[0041] Figure 13 This is a schematic diagram of one of the structures of the trench silicon carbide MOSFET fabrication method provided in the embodiments of this application;

[0042] Figure 14 This is a schematic diagram of one of the structures of the trench silicon carbide MOSFET fabrication method provided in the embodiments of this application;

[0043] Figure 15 This is a schematic diagram of one of the structural methods for fabricating a trench silicon carbide MOSFET provided in the embodiments of this application. Detailed Implementation

[0044] To make the technical problems, technical solutions, and beneficial effects to be solved by this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and are not intended to limit the scope of this application.

[0045] In current SiC MOSFET device development, trench structures are a highly promising design because they can optimize the device's conduction capability (specific on-resistance) by creating channels in crystal orientations with higher mobility, eliminating JFET region resistance, and increasing channel density through cell size compression. Most manufacturers are currently focusing their research on trench structures, which are considered the mainstream structure for future SiC MOSFET devices. Compared to traditional planar MOSFETs, TG-MOSFETs can significantly reduce specific on-resistance by accommodating more channels within a given chip area and completely eliminating the JFET effect. However, during device operation, high electric field peaks easily form in the gate oxide layer of the trench, especially at the bottom corner, affecting long-term reliability; the gate-drain capacitance is generally large, leading to higher switching time and switching losses. To alleviate these problems, continuous optimization of the trench SiC MOSFET structure is necessary.

[0046] To address the aforementioned technical problems, this application provides a trench silicon carbide MOSFET, see [link to relevant documentation]. Figure 1 , Figure 2 as well as Figure 3 As shown, the trench silicon carbide MOSFET in this embodiment includes: a drain layer 110, a silicon carbide substrate 210, an N-type drift region 220, a first P-type well region 310, a second P-type well region 320, a third P-type well region 330, a first current spreading layer 410, a second current spreading layer 420, a gate oxide layer 610, an N-type heavily doped region 510, a gate layer 620, an insulating dielectric layer 630, a source layer 120, and a plurality of P-type heavily doped regions 710; the drain layer 110, the silicon carbide substrate 210, and the N-type drift region 220 are stacked in a first direction, the N-type drift region 220 has a concave structure, the third P-type well region 330 is formed at the bottom of the trench of the N-type drift region 220, the gate oxide layer 610 is formed on the third P-type well region 330, and the gate oxide layer 610 has a concave structure, and the gate layer 620 is formed in the trench of the gate oxide layer 610. A first P-type well region 310 and a first current spreading layer 410 are formed on the horizontal portion of the N-type drift region 220, and the first P-type well region 310 is located on the side periphery of the gate oxide layer 610; a second current spreading layer 420 is formed on the first P-type well region 310 and the first current spreading layer 410, the second P-type well region 320 is formed on the horizontal portion of the second current spreading layer 420, and an N-type heavily doped region 510 is formed on the horizontal portion of the second P-type well region 320. The first P-type well region 310, the second current spreading layer 420, the second P-type well region 320, and the N-type heavily doped region 510 are located on both sides of the gate oxide layer 610 within a first predetermined cross-section (cross-section A) in the second direction. Figure 1As shown, multiple P-type heavily doped regions 710 are spaced apart on the second P-type well region 320 in the third direction, and are located between the vertical portion of the second P-type well region 320 and the second current extension layer 420 in the second predetermined cross section (cross section B) in the second direction; the first direction, the second direction and the third direction are perpendicular to each other; the source layer 120 and the second current extension layer 420 are in Schottky contact, and the source layer 120 and the N-type heavily doped region 510, the P-type heavily doped region 710 and the second P-type well region 320 are in ohmic contact; the insulating dielectric layer 630 is disposed between the source layer 120 and the gate layer 620.

[0047] In this embodiment, the P-type well region inside the device is discretized into a first P-type well region 310, a second P-type well region 320, and a third P-type well region 330 with different doping concentrations. The third P-type well region 330 is located below the gate oxide layer 610, while the first P-type well region 310 and the second P-type well region 320 are located outside the gate oxide layer 610. The first P-type well region 310 and the second P-type well region 320 are isolated by the horizontal portion of the second current spread layer 420. The first P-type well region 310 acts as a breakdown junction and depletes the second current spread layer 420 near the channel of the second P-type well region 320. The third P-type well region 330 can terminate the drain electric field line to realize the transfer of the electric field peak in the gate oxide layer 610, improve the gate reliability of the device, and extend its service life. At the same time, it plays a certain role in shielding the drain voltage, reducing the parasitic capacitance at the bottom of the gate trench, optimizing the gate drain charge, and optimizing the dynamic characteristics of the device.

[0048] In some embodiments, the third P-type well region 330 is located below the gate oxide layer 610, and the distance between the lower surface of the first P-type well region 310 and the upper surface of the third P-type well region 330 is greater than the thickness of the bottom of the gate oxide layer 610.

[0049] In this embodiment, the first P-type well region 310, the second P-type well region 320, and the third P-type well region 330 have different doping concentrations. By forming the first P-type well region 310, the second P-type well region 320, and the third P-type well region 330 with different doping concentrations, the P-type well region is discretely divided into three parts. The first P-type well region 310 is located below the second P-type well region 320, and the third P-type well region 330 is located at the bottom of the trench and below the gate oxide layer 610. The active region of the device is... Figure 2The cross-section A shown presents a repeating arrangement of multiple cells. Since the doping concentration of the first P-type well region 310 is greater than that of the second P-type well region 320, the high doping of the first P-type well region 310 can deplete the second current extension layer 420 near the channel of the second P-type well region 320, preventing the second P-type well region 320 from breaking down prematurely. Furthermore, the third well region shields the drain voltage, improving the gate reliability of the device and extending its lifespan. At the same time, it also provides some shielding for the drain voltage, reducing the parasitic capacitance at the bottom of the gate trench, optimizing the gate-drain charge, and improving the dynamic characteristics of the device.

[0050] In some embodiments, the doping concentrations of the third P-type well region 330, the first P-type well region 310, and the second P-type well region 320 decrease sequentially, with the doping concentration of the third P-type well region 330 being greater than that of the first P-type well region 310, and the doping concentration of the first P-type well region 310 being greater than that of the second P-type well region 320.

[0051] In this embodiment, the third P-type well region 330 can terminate the drain electric field line and realize the transfer of the electric field peak in the gate oxide layer 610 when the device is in the blocking state, thereby improving the gate reliability and extending the service life of the device. At the same time, it plays a certain role in shielding the drain voltage, reducing the parasitic capacitance at the bottom of the gate trench, optimizing the gate drain charge, and optimizing the dynamic characteristics of the device. By setting the doping concentration of the first P-type well region 310 to be greater than that of the second P-type well region 320, the high doping of the first P-type well region 310 can deplete the second current extension layer 420 near the channel of the second P-type well region 320, thus preventing the second P-type well region 320 from breaking down prematurely.

[0052] In some embodiments, the area between the first P-type well region 310 and the second P-type well region 320 is the horizontal portion of the second current spreading layer 420.

[0053] In some embodiments, the thickness of the horizontal portion of the second current extension layer 420 is equal to or greater than 0.2 μm to ensure the formation of a low-resistance current path under low current. The spacing between the first P-type well region 310 and the second P-type well region 320 (e.g., the thickness of the second current extension layer 420) is not less than 0.2 μm, the spacing between the P-type well regions of adjacent cells (e.g., the width of the first current extension layer 410) is not less than 0.5 μm, and the peak doping concentration in the channel of the second P-type well region 320 is not higher than 4e17cm-3.

[0054] In some embodiments, the peak doping concentration of the first P-type well region 310 is not less than 1e18cm-3, which is beneficial for reducing short-circuit current and optimizing breakdown voltage.

[0055] In some embodiments, the width of the third P-type well region 330 is equal to the width of the gate trench. The third P-type well region 330 can use the same mask as the gate trench, reducing the manufacturing cost of the device.

[0056] In some embodiments, the doping concentration of the first current spreading layer 410 is greater than the doping concentration of the second current spreading layer 420; the doping concentration of the first current spreading layer 410 and the second current spreading layer 420 is greater than the doping concentration of the N-type drift region 220.

[0057] In this embodiment, both the first current spreading layer 410 and the second current spreading layer 420 are N-type doped, and the doping concentration of the first current spreading layer 410 and the second current spreading layer 420 is higher than that of the N-type drift region 220. This can provide a low-resistance transport path for electrons, thereby reducing the specific on-resistance of the device. At the same time, the interface between the second current spreading layer 420 and the source layer 120 is a Schottky contact, which can act as the body diode inside the device. Furthermore, the high doping concentration of the first current spreading layer 410 and the second current spreading layer 420 reduces the voltage drop of the body diode.

[0058] In this embodiment, when the trench silicon carbide MOSFET is turned on, at low voltage, the second P-type well region 320 has a low doping concentration, which can achieve a low channel resistance. Conductive electrons mainly flow through the path of the low-resistance second P-type well region 320 → second current extension layer 420 → first current extension layer 410 → drain layer 110, away from the heavily doped first P-type well region 310 and third P-type well region 330, reducing their impact on the current path and lowering the device on-resistance within the rated current range. At high voltage, the space between adjacent cells in the region of the first P-type well region 310 and the heavily doped P-type region 710 is reduced. The charge region expansion pinches off the paths of the first current extension layer 410 and the second current extension layer 420. Conductive electrons pass through the channels of the second P-type well region 320 and the first P-type well region 310 simultaneously. The opening of the conductive channel in the first P-type well region 310 can ensure that the device has a certain pulse voltage capability. At the same time, because the channel length of the first P-type well region 310 is large (the channel of the first P-type well region 310 includes vertical and horizontal parts) and the doping concentration is high, it has a high channel resistance. Combined with the compression of the current path by the space charge region of the third P-type well region 330, the saturation current of the device under short-circuit conditions can be reduced, avoiding high instantaneous power burnout of the device.

[0059] In some embodiments, both the first P-type well region 310 and the second P-type well region 320 have an L-shaped structure within cross-section A, and the doping concentration of the first P-type well region 310 is at least 10 times that of the second P-type well region 320. In this embodiment, by discretizing the P-type well region of the device into three parts, the first P-type well region 310 and the third P-type well region 330 play a major role in blocking mode and short-circuit mode, optimizing the reliability and robustness of the device; the second P-type well region 320 plays a major role in conducting mode and can be used to design the resistance and threshold voltage of the device. By designing them separately, the complexity of the device is reduced, the overall performance of the device is improved, and the product development iteration speed is accelerated.

[0060] In some embodiments, the P-type heavily doped region 710 extends into the vertical portion of the first P-type well region 310, and divides the second current extension layer 420 into isolated horizontal and vertical portions within a second preset cross section; the second preset cross section is horizontally disposed in the third direction.

[0061] In this embodiment, by setting spaced P-type heavily doped regions 710 and increasing the implantation junction depth of the P-type heavily doped regions 710, it is ensured that the P-type heavily doped regions 710 on cross-section B extend into the first P-type well region 310. This eliminates the need for increased area cost and additional grounding structures, enabling both discrete P-type well regions (first P-type well region 310 and second P-type well region 320) to be grounded. Simultaneously, because the P-type heavily doped regions 710 employ a discontinuous island-like design in the third direction, only the N-type heavily doped region 510 exists on cross-section A. This facilitates cell size compression and avoids blocking current paths on cross-section A, thus preventing the device from turning on normally.

[0062] In some embodiments, in order to ensure the grounding effect of the first P-type well region 310, the heavily doped P-type region 710 extends into the first P-type well region 310 by at least 0.2 μm in the first direction of the cross section B.

[0063] In some embodiments, to ensure optimization of conduction characteristics, the doping concentration of the first current spreading layer 410 and the second current spreading layer 420 is equal to or greater than three times the doping concentration of the N-type drift region 220.

[0064] In some embodiments, the depth of the P-type heavily doped region 710 in the first direction is greater than the depth of the second current extension layer 420, and in the third direction it is located between the vertical portion of the N-type heavily doped region 510 and the second current extension layer 420.

[0065] In this embodiment, within section B, the cell width is increased by leaving a current path composed of a first current extension layer 410 and a second current extension layer 420 between the P-type well regions of adjacent cells. This is compensated for by the island-shaped design of the heavily doped P-type region 710 and the grounding design of the heavily doped P-type region 710. Furthermore, compared to traditional trench SiC MOSFET structures, this region incorporates a built-in Schottky diode, which reduces the body diode voltage drop of the MOSFET device and optimizes the reverse recovery characteristics of the body diode. This allows the trench silicon carbide MOSFET in this embodiment to be used in practical applications without requiring anti-parallel connection with an external diode, thus saving overall system area cost. In blocking mode, the space charge region of the P-type well region and the heavily doped P-type region 710 also protects the Schottky contact, preventing excessive leakage current.

[0066] In some embodiments, the contact interface between the P-type heavily doped region 710 and the source layer 120 within the second preset cross section is smaller than the width of the P-type heavily doped region 710 within the second preset cross section, so that the N-type heavily doped region 510 does not contact the source layer 120 within the second preset cross section.

[0067] In some embodiments, the spacing between adjacent heavily doped P-type regions 710 is greater than the width of the heavily doped P-type regions 710 in the second direction.

[0068] This application also provides a method for fabricating a trench silicon carbide MOSFET, see [link to relevant documentation]. Figure 4 As shown, the preparation method in this embodiment includes steps S100 to S700.

[0069] In step S100, a silicon carbide substrate 210 is provided, and an N-type drift region 220 is formed on the front side of the silicon carbide substrate 210.

[0070] In this embodiment, combined with Figure 5 As shown, a silicon carbide epitaxial wafer that meets the requirements is provided, or an N-type drift region 220 is epitaxially formed on the front side of the corresponding silicon carbide substrate 210, such as... Figure 5 As shown, the structures of section A and section B are identical.

[0071] In step S200, a first P-type well region 310 and a first current extension layer 410 are formed on the N-type drift region 220.

[0072] In this embodiment, combined with Figure 6As shown, the regions of the first current extension layer 410 and the first P-type well region 310 are defined by a preset mask. Under the cover of the mask, local P-type impurities (e.g., aluminum ions) and N-type impurities (e.g., nitrogen ions) are implanted in sequence to form the first P-type well region 310 and the first current extension layer 410, respectively. The first current extension layer 410 is located on both sides of the first P-type well region 310.

[0073] In some embodiments, the thickness of the first current spreading layer 410 is greater than the thickness of the first P-type well region 310, so that the N-type drift region 220 has a convex structure.

[0074] In some embodiments, the peak doping concentration of the first P-type well region 310 is not less than 1e18cm-3, which is beneficial for reducing short-circuit current and optimizing breakdown voltage.

[0075] In step S300, a second current extension layer 420 is formed on the first P-type well region 310 and the first current extension layer 410 along the first direction, and a second P-type well region 320 and an N-type heavily doped region 510 are formed on the second current extension layer 420 by multiple ion implantation processes.

[0076] In this embodiment, combined with Figure 7 As shown, in Figure 6 An epitaxial layer with the same doping type as the N-type drift region 220 is grown on the entire wafer using an epitaxial process. A nitrogen ion implantation process is then performed on the new epitaxial layer to form a second current spreading layer 420 on the first P-type well region 310, the first current spreading layer 410, and the N-type drift region 220. Alternatively,... Figure 6 A second current-extending layer 420 with a predetermined N-type doping concentration is directly grown on the entire wafer. Combined with... Figure 8 As shown, by sequentially implanting P-type impurities (e.g., aluminum ions) and N-type impurities (e.g., nitrogen ions) into a portion of the second current extension layer 420, a second P-type well region 320 and an N-type heavily doped region 510 can be formed, such that the second current extension layer 420 and the second P-type well region 320 have concave shapes in the cross-section of the second direction.

[0077] In some embodiments, such as Figure 8 As shown, the width of the first P-type well region 310 is the same as the width of the horizontal portion of the second P-type well region 320. The horizontal portion of the second current extension layer 420 is located between the first P-type well region 310 and the second P-type well region 320. To ensure the formation of a low-resistance current path under low current, the spacing between the first P-type well region 310 and the second P-type well region 320 is not less than 0.2 μm, the spacing between the P-type well regions of adjacent cells is not less than 0.5 μm, and the peak doping concentration in the channel of the second P-type well region 320 is not higher than 4e17 cm-3.

[0078] In step S400, P-type impurities are injected into multiple preset regions spaced upwards to form multiple heavily doped P-type regions 710.

[0079] In this embodiment, the cross-section of the portion between adjacent preset regions in the second direction is defined as the first preset cross-section, and the cross-section of the portion within the preset region in the second direction is defined as the second preset cross-section. Multiple preset regions spaced upwards are implanted with P-type impurities (e.g., aluminum ions) to form multiple heavily doped P-type regions 710, such as... Figure 9 Section A is shown in the figure.

[0080] In step S500, a pre-defined trench region on the N-type heavily doped region 510 is etched to form a gate trench extending into the N-type drift region 220. P-type impurities are injected into the N-type drift region 220 along the gate trench to form a third P-type well region 330. A gate oxide layer 610 and a gate layer 620 are formed in the gate trench.

[0081] Combination Figure 10 As shown, etching is performed on a predetermined region of the heavily doped N-type region 510, with the etching depth extending to the N-type drift region 220 to form a gate trench, resulting in a concave structure for the N-type drift region 220. Combined with... Figure 11 As shown, P-type impurities are implanted into the N-type drift region 220 along the gate trench to form a third P-type well region 330, and thermal oxidation is performed within the gate trench to form a gate oxide layer 610 along the inner wall of the gate trench. Polysilicon material is then deposited to form a gate layer 620, which is located within the recess of the gate oxide layer 610. Figure 12 As shown.

[0082] In step S600, an insulating dielectric layer 630 is deposited and etched so that the insulating dielectric layer 630 covers the gate layer 620, covers a portion of the N-type heavily doped region 510 within a first preset cross section, and covers the entire region of the N-type heavily doped region 510 within a second preset cross section.

[0083] In this embodiment, Figure 13 The wafer surface shown is deposited with insulating dielectric material to form an insulating dielectric layer 630, such as Figure 14 As shown. Then, the insulating dielectric layer 630 is etched to create openings, forming an ohmic contact metal layer and a Schottky contact metal layer.

[0084] In step S700, a source layer 120 and a drain layer 110 are formed.

[0085] Combination Figure 15As shown, a thickened source layer 120 is formed on the front side of the wafer, and a drain layer 110 is formed on the back side of the silicon carbide substrate 210. The source layer 120 and the second current extension layer 420 are connected by a Schottky contact, and the source layer 120 is connected by an ohmic contact with the N-type heavily doped region 510, the P-type heavily doped region 710 and the second P-type well region 320.

[0086] In some embodiments, in step S500, etching a predetermined trench region on the N-type heavily doped region 510 to form a gate trench extending into the N-type drift region 220, implanting P-type impurities into the N-type drift region 220 along the gate trench to form a third P-type well region 330, and forming a gate oxide layer 610 and a gate layer 620 in the gate trench, includes: using the same mask as the one used for etching the gate trench to perform P-type doped ion implantation to form a third P-type well region 330 below the gate trench; wherein, the upper surface of the third P-type well region 330 is lower than the lower surface of the first P-type well region 310.

[0087] In some embodiments, in order to avoid surface breakdown and improve the effect of ohmic contact, it is necessary to appropriately increase the doping concentration of the surface of the second P-type well region 320 so that it is significantly higher than the doping concentration of the channel region of the second P-type well region 320, which is beneficial to reduce the leakage current of the Schottky contact.

[0088] In some embodiments, in order to ensure the grounding effect of the first P-type well region 310, the heavily doped P-type region 710 extends into the first P-type well region 310 by at least 0.2 μm in the first direction of the cross section B.

[0089] This application also provides a chip, including a trench silicon carbide MOSFET as described in any of the above embodiments; or, including a trench silicon carbide MOSFET prepared by the preparation method described in any of the above embodiments.

[0090] In this embodiment, the chip includes a chip substrate, on which one or more trench silicon carbide MOSFETs are disposed. The trench silicon carbide MOSFETs can be disposed on the chip substrate as described in any of the above embodiments.

[0091] In one specific application embodiment, other related semiconductor devices can also be integrated on the chip substrate to form an integrated circuit with the trench silicon carbide MOSFET.

[0092] In one specific application embodiment, the chip can be a switch chip or a driver chip.

[0093] In this embodiment, the P-type well region inside the device is discretized into a first P-type well region and a second P-type well region with different doping concentrations. In the device blocking state, the first P-type well region and the third P-type well region mainly function as the breakdown junction. The high doping of the first P-type well region can ensure that the breakdown voltage of the device meets the requirements. Moreover, the high doping of the first P-type well region can deplete the second current extension layer near the channel of the second P-type well region. The drain voltage is shielded by the third P-type well region, which improves the gate reliability of the device and extends its service life. At the same time, it plays a certain role in shielding the drain voltage, reducing the parasitic capacitance at the bottom of the gate trench, optimizing the gate drain charge, and optimizing the dynamic characteristics of the device.

[0094] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of doped regions and devices is merely an example. In practical applications, the above functions can be assigned to different doped regions and devices as needed, that is, the internal structure of the device can be divided into different doped regions to complete all or part of the functions described above. In the embodiments, each doped region and device can be integrated into one unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0095] Furthermore, the specific names of each doped region and device are only for the purpose of distinguishing them from each other and are not intended to limit the scope of protection of this application.

[0096] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0097] In addition, in the various embodiments of this application, each doped region can be integrated into one unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0098] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A trench silicon carbide MOSFET, characterized in that, The trench silicon carbide MOSFET includes: a drain layer, a silicon carbide substrate, an N-type drift region, a first P-type well region, a second P-type well region, a third P-type well region, a first current spreading layer, a second current spreading layer, a gate oxide layer, an N-type heavily doped region, an insulating dielectric layer, a source layer, and multiple P-type heavily doped regions. The drain layer, the silicon carbide substrate, and the N-type drift region are stacked in a first direction. The N-type drift region has a concave structure. The third P-type well region is formed at the bottom of the groove of the N-type drift region. The gate oxide layer is formed on the third P-type well region and has a concave structure. A gate layer is formed in the groove of the gate oxide layer. The first P-type well region and the first current spreading layer are formed on the horizontal portion of the N-type drift region, and the first P-type well region is located on the side periphery of the gate oxide layer; the second current spreading layer is formed on the first P-type well region and the first current spreading layer, the second P-type well region is formed on the horizontal portion of the second current spreading layer, and the heavily doped N-type region is formed on the horizontal portion of the second P-type well region. The first P-type well region, the second current spreading layer, the second P-type well region, and the heavily doped N-type region are located on both sides of the gate oxide layer within a first predetermined cross section in the second direction. Multiple P-type heavily doped regions are spaced apart on the second P-type well region in a third direction, and are located between the vertical portion of the second P-type well region and the second current extension layer in a second predetermined cross section in the second direction; the first direction, the second direction and the third direction are perpendicular to each other; the doping concentration of the third P-type well region is greater than the doping concentration of the first P-type well region, and the doping concentration of the first P-type well region is greater than the doping concentration of the second P-type well region. The source layer and the second current spread layer are connected by a Schottky contact, and the source layer is connected by an ohmic contact with the N-type heavily doped region, the P-type heavily doped region and the second P-type well region. The insulating dielectric layer is disposed between the source layer and the gate layer.

2. The trench silicon carbide MOSFET as described in claim 1, characterized in that, The third P-type well region is located below the gate oxide layer, and the distance between the lower surface of the first P-type well region and the upper surface of the third P-type well region is greater than the thickness of the bottom of the gate oxide layer.

3. The trench silicon carbide MOSFET as described in claim 1, characterized in that, The doping concentration of the first current spreading layer is greater than the doping concentration of the second current spreading layer; The doping concentrations of the first current spreading layer and the second current spreading layer are greater than the doping concentration of the N-type drift region.

4. The trench silicon carbide MOSFET as described in claim 1, characterized in that, The heavily doped P-type region extends into the vertical portion of the first P-type well region, and within the second preset cross section, the second current extension layer is divided into isolated horizontal and vertical portions; the second preset cross section is horizontally aligned with the third portion.

5. The trench silicon carbide MOSFET as described in claim 1, characterized in that, The depth of the P-type heavily doped region in the first direction is greater than the depth of the second current spreading layer, and in the third direction it is located between the vertical portion of the N-type heavily doped region and the second current spreading layer.

6. The trench silicon carbide MOSFET as described in claim 1, characterized in that, The contact interface between the P-type heavily doped region and the source layer within the second preset cross-section is smaller than the width of the P-type heavily doped region within the second preset cross-section, so that the N-type heavily doped region does not contact the source layer within the second preset cross-section.

7. A method for fabricating a trench silicon carbide MOSFET, characterized in that, The preparation method includes: A silicon carbide substrate is provided, and an N-type drift region is formed on the front side of the silicon carbide substrate; A first P-type well region and a first current spreading layer are formed on the N-type drift region; A second current spreading layer is formed on the first P-type well region and the first current spreading layer along the first direction, and a second P-type well region and an N-type heavily doped region are formed on the second current spreading layer through multiple ion implantation processes; the second current spreading layer and the second P-type well region are concave in shape in the cross section of the second direction; Multiple P-type impurities are injected into multiple preset regions spaced upwards from the third side to form multiple heavily doped P-type regions; wherein, the cross-section of the portion between adjacent preset regions in the second direction is defined as a first preset cross-section, and the cross-section of the portion within the preset regions in the second direction is defined as a second preset cross-section. A pre-defined trench region on the heavily doped N-type region is etched to form a gate trench extending into the N-type drift region. P-type impurities are then implanted into the N-type drift region along the gate trench to form a third P-type well region. A gate oxide layer and a gate layer are formed within the gate trench. The gate layer is located within a recess in the gate oxide layer. The doping concentration of the third P-type well region is greater than that of the first P-type well region, and the doping concentration of the first P-type well region is greater than that of the second P-type well region. An insulating dielectric layer is deposited and etched so that the insulating dielectric layer covers the gate layer, and covers a portion of the heavily doped N-type region within the first preset cross section, and covers the entire region of the heavily doped N-type region within the second preset cross section. A source layer and a drain layer are formed, wherein the source layer and the second current extension layer are connected by a Schottky contact, and the source layer and the N-type heavily doped region, the P-type heavily doped region and the second P-type well region are connected by an ohmic contact.

8. The preparation method according to claim 7, characterized in that, The process includes etching a pre-defined trench region on the heavily doped N-type region to form a gate trench extending into the N-type drift region, implanting P-type impurities into the N-type drift region along the gate trench to form a third P-type well region, and forming a gate oxide layer and a gate layer within the gate trench. P-type doped ion implantation is performed using the same mask as that used to etch the gate trench to form a third P-type well region below the gate trench; wherein the upper surface of the third P-type well region is lower than the lower surface of the first P-type well region.

9. A chip, characterized in that, Includes the trench silicon carbide MOSFET as described in any one of claims 1-6; or includes the trench silicon carbide MOSFET prepared by the preparation method as described in claim 7 or 8.

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