High-reliability flip LED chip and preparation method thereof

Abstract

The invention provides a high-reliability flip LED chip and a preparation method thereof, the flip LED chip comprises a substrate, a semiconductor layer, a metal reflection layer, a first passivation layer, a metal contact layer and a second passivation layer which are stacked in sequence, and the semiconductor layer comprises an N-type semiconductor layer, an active layer and a P-type semiconductor layer; the metal reflecting layer is electrically connected with the P-type semiconductor layer; the first passivation layer comprises a first through hole and a second through hole; a first metal contact part in the metal contact layer is electrically connected with the N-type semiconductor layer through a first through hole, and a second metal contact part in the metal contact layer is electrically connected with the metal reflecting layer through a second through hole; wherein the first passivation layer comprises a first entity part which is in contact with the second passivation layer and a second entity part which is arranged at an interval with the second passivation layer, and the thickness of the first entity part is greater than that of the second entity part. The flip LED chip provided by the embodiment of the invention has the advantages of high yield and high reliability.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor technology, in particular to a high-reliability flip LED chip and a preparation method thereof. BACKGROUND

[0002] A light emitting diode (Light Emitting Diode, LED for short) device is a kind of electroluminescent semiconductor light emitting device. At present, it has been widely used in lighting, display, medical treatment, optical communication and other fields due to its advantages of low energy consumption, small size, long service life, good stability, fast response and stable light emitting wavelength. LED chip is the core light emitting component of LED device. LED chips can be divided into vertical LED chips, flip LED chips and vertical LED chips according to different architectures. Among them, flip LED chip has the advantages of low voltage, high brightness, high reliability, high saturation current density and excellent development prospect.

[0003] In the flip LED chip in the related art, a metal reflection layer is usually arranged on one side of the semiconductor layer (epitaxial layer) for realizing the light emitting function, so as to utilize the high reflectivity of the metal reflection layer to improve the light emitting efficiency and increase the brightness of the flip LED chip. Silver (Ag) becomes the preferred material of the metal reflection layer due to its high reflectivity (visible light band reflectivity > 95%) and good electrical conductivity. However, Ag is prone to electrochemical migration in the preparation process of the LED chip, which further increases the risk of short circuit and reduces the product yield.

[0004] Therefore, how to improve the electrochemical migration problem of the metal reflection layer to reduce the risk of short circuit and improve the product yield and reliability is a technical problem that needs to be solved by those skilled in the art. SUMMARY

[0005] The present application provides a high-reliability flip LED chip and a preparation method thereof, which can effectively solve the electrochemical migration problem of the metal reflection layer in the flip LED chip in the related art.

[0006] In a first aspect, the application provides a flip LED chip with high reliability, comprising: a substrate; a semiconductor layer arranged on one side of the substrate, the semiconductor layer comprising an N-type semiconductor layer, an active layer, and a P-type semiconductor layer arranged in sequence; a metal reflection layer arranged on a side of the semiconductor layer away from the substrate and electrically connected with the P-type semiconductor layer; a first passivation layer arranged on a side of the metal protection layer away from the substrate, the first passivation layer comprising at least one first through hole and at least one second through hole; a metal contact layer arranged on a side of the first passivation layer away from the substrate, the metal contact layer comprising a first metal contact part and a second metal contact part, the first metal contact part being electrically connected with the N-type semiconductor layer through the first through hole, and the second metal contact part being electrically connected with the metal reflection layer through the second through hole; and a second passivation layer arranged on a side of the metal contact layer away from the substrate; wherein the first passivation layer comprises a first solid part and a second solid part, the first solid part being in contact with the second passivation layer, and the second solid part being arranged apart from the second passivation layer, and the thickness of the first solid part being greater than the thickness of the second solid part.

[0007] Optionally, the thickness of the first solid part is the same as the thickness of the second passivation layer, and the thickness of the second solid part is less than the thickness of the second passivation layer.

[0008] Optionally, the first solid part has a first area of a normal projection on the substrate, and the second solid part has a second area of a normal projection on the substrate, wherein the second area is more than five times the first area.

[0009] Optionally, the thickness of the second solid part is 0.8 to 0.9 times the thickness of the first solid part.

[0010] Optionally, the flip LED chip further comprises a metal protection layer arranged on a side of the metal reflection layer away from the substrate, and the second metal contact part is in contact with the metal protection layer through the second through hole, wherein the metal protection layer does not cover the sidewall of the metal reflection layer.

[0011] Optionally, the metal reflection layer has a first area of a normal projection on the substrate, and the metal protection layer has a second area of a normal projection on the substrate, wherein the first area is equal to the second area.

[0012] Optionally, the semiconductor layer comprises an edge step structure, a step surface of the edge step structure is the N-type semiconductor layer, and a sidewall of the edge step structure is a P-type semiconductor layer and an active layer, wherein the first passivation layer further comprises a first slot, the first slot exposes at least part of the step surface of the edge step structure, the first metal contact is electrically connected to the N-type semiconductor layer through the first slot, and the first passivation layer covering the sidewall of the edge step structure is covered by the metal contact layer.

[0013] In a second aspect, the present application provides a preparation method of a high-reliability flip LED chip, the preparation method of the flip LED chip comprising: forming a patterned semiconductor layer on a substrate, the semiconductor layer comprising an N-type semiconductor layer, an active layer, and a P-type semiconductor layer arranged in sequence; forming a patterned metal reflective layer on the semiconductor layer, wherein the metal reflective layer is electrically connected to the P-type semiconductor layer; forming a first passivation layer on the metal reflective layer, wherein the first passivation layer has a first region, a second region, and a third region; forming a patterned first photoresist layer on the first passivation layer in the first region and the second region; performing etching treatment on the first passivation layer in the third region by using the first photoresist layer to thin the first passivation layer in the third region to a state greater than 0; removing the first photoresist layer by using a cleaning solution; forming a patterned second photoresist layer on the first passivation layer in the first region; performing etching treatment on the first passivation layer in the second region and the third region by using the second photoresist layer to thin the first passivation layer in the second region to a state greater than 0 and to make the thickness of the first passivation layer in the third region be 0, so as to form at least one first through hole and at least one second through hole on the first passivation layer, wherein the first through hole is arranged to overlap the N-type semiconductor layer in a direction perpendicular to the substrate, and the second through hole is arranged to overlap the metal reflective layer; forming a metal contact layer on the second photoresist layer, the metal contact layer covering the first passivation layer, the second photoresist layer, the first through hole, and the second through hole; removing the metal contact layer on the second photoresist layer and the second photoresist layer to make the thickness of the metal contact layer in the first region be 0 and form a hollow part in the metal contact layer; forming a patterned second passivation layer on the second photoresist layer, the second passivation layer being in contact with the first passivation layer through the hollow part; The first passivation layer comprises a first entity and a second entity, the first entity is in contact with the second passivation layer, the second entity is spaced apart from the second passivation layer, and the thickness of the first entity is greater than the thickness of the second entity.

[0014] Optionally, the step of forming the patterned metal reflective layer on the semiconductor layer comprises: forming a patterned third photoresist layer on the semiconductor layer; forming a metal reflective layer on the semiconductor layer and the third photoresist layer; forming a metal protective layer on the metal reflective layer; cleaning to remove the third photoresist layer; The area of the orthographic projection of the metal protective layer on the substrate is a first area, the area of the orthographic projection of the metal protective layer on the substrate is a second area, and the first area is equal to the second area.

[0015] Optionally, in the step of etching the first passivation layer of the third region by using the first photoresist layer, the thickness of the first passivation layer of the third region is a first thickness; in the step of etching the first passivation layer of the second region and the third region by using the second photoresist layer, the thickness of the first passivation layer of the second region is a second thickness, wherein the first thickness is 4 to 9 times the second thickness.

[0016] The application provides a flip LED chip with high reliability and a preparation method thereof. The flip LED chip comprises a substrate, a semiconductor layer, a metal reflection layer, a first passivation layer, a metal contact layer and a second passivation layer. The semiconductor layer is arranged on one side of the substrate, and comprises an N-type semiconductor layer, an active layer and a P-type semiconductor layer arranged in sequence. The metal reflection layer is arranged on the side of the semiconductor layer away from the substrate and is electrically connected with the P-type semiconductor layer. The first passivation layer is arranged on the side of the metal protection layer away from the substrate, and comprises at least one first through hole and at least one second through hole. The metal contact layer is arranged on the side of the first passivation layer away from the substrate, and comprises a first metal contact part and a second metal contact part. The first metal contact part is electrically connected with the N-type semiconductor layer through the first through hole, and the second metal contact part is electrically connected with the metal reflection layer through the second through hole. The second passivation layer is arranged on the side of the metal contact layer away from the substrate. The first passivation layer comprises a first entity part and a second entity part. The first entity part is in contact with the second passivation layer, and the second entity part is arranged in a spaced manner with the second passivation layer. The thickness of the first entity part is greater than that of the second entity part. The flip LED chip and the preparation method thereof can effectively improve the problem of electrochemical migration of the metal reflection layer, thereby reducing the short circuit risk of the flip LED chip, improving the product yield and reliability. BRIEF DESCRIPTION OF DRAWINGS

[0017] The technical scheme and other beneficial effects of the application will be apparent from the following detailed description of the specific embodiments of the application with reference to the accompanying drawings.

[0018] Figure 1 A cross-sectional schematic view of the flip LED chip provided by some embodiments of the application is shown.

[0019] Figure 2 A top view schematic view of the first passivation layer and the underlying film layer thereof provided by some embodiments of the application is shown.

[0020] Figure 3 A top view schematic view of the first passivation layer provided by some embodiments of the application is shown.

[0021] Figure 4 A cross-sectional schematic view corresponding to step S11 in step S10 provided by some embodiments of the application is shown.

[0022] Figure 5 A cross-sectional schematic view corresponding to step S12 in step S10 provided by some embodiments of the application is shown.

[0023] Figure 6This is a cross-sectional schematic diagram corresponding to step S13 in step S10 provided in some embodiments of this application.

[0024] Figure 7 This is a cross-sectional schematic diagram corresponding to step S21 in step S20 provided in some embodiments of this application.

[0025] Figure 8 This is a cross-sectional schematic diagram corresponding to step S22 in step S20 provided in some embodiments of this application.

[0026] Figure 9 This is a cross-sectional schematic diagram corresponding to step S26 in step S20 provided in some embodiments of this application.

[0027] Figure 10 This is a cross-sectional schematic diagram corresponding to step S30 provided in some embodiments of this application.

[0028] Figure 11 These are cross-sectional schematic diagrams corresponding to step S40 provided in some embodiments of this application.

[0029] Figure 12 for Figure 11 A magnified view of region M1 in the image.

[0030] Figure 13 These are cross-sectional schematic diagrams corresponding to step S51 in step S50 provided in some embodiments of this application.

[0031] Figure 14 for Figure 13 A magnified view of the M2 region in the image.

[0032] Figure 15 These are cross-sectional schematic diagrams corresponding to step S52 in step S50 provided in some embodiments of this application.

[0033] Figure 16 for Figure 15 A magnified view of region M1 in the image.

[0034] Figure 17 for Figure 15 A magnified view of the M2 region in the image.

[0035] Figure 18 This is a cross-sectional schematic diagram corresponding to step S60 provided in some embodiments of this application.

[0036] Figure 19 This is a cross-sectional schematic diagram corresponding to step S70 provided in some embodiments of this application.

[0037] Figure 20 This is a cross-sectional schematic diagram corresponding to step S80 provided in some embodiments of this application.

[0038] Figure 21 The cross-sectional schematic view corresponding to step S90 provided by some embodiments of the present application is shown in FIG. 9.

[0039] Labeling of the drawings: Substrate 100; semiconductor layer 110; buffer layer 111; N-type semiconductor layer 112; active layer 113; P-type semiconductor layer 114; edge step structure 115; transparent conductive layer 120; current barrier layer 130; metal reflective layer 140; metal protective layer 150; first passivation layer 160; first solid part 161; second solid part 162; metal contact layer 170; first metal contact part 171; second metal contact part 172; second passivation layer 180; electrode layer 190; first electrode 191; second electrode 192; second photoresist layer 200; first region A1; second region A2; third region A3; first via T1; second via T2; third via T3; fourth via T4; fifth via T5; sixth via T6; seventh via T7; eighth via T8; ninth via T9; current spreading hole T10; first slot C1; hollow part L1. DETAILED DESCRIPTION

[0040] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the scope of protection of the present application.

[0041] The terms “first”, “second” in the specification are only for the purpose of description, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined with “first”, “second” can explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of “multiple” is two or more, unless otherwise specifically limited.

[0042] In the description of the present application, it should be noted that, unless otherwise specifically defined and limited, the terms “mounting”, “connection”, “connecting” should be understood in a broad sense, for example, it can be fixed connection, or detachable connection, or integrally connected; it can be mechanical connection, or electrical connection or can communicate with each other; it can be directly connected, or indirectly connected through intermediate medium, or the communication between two elements or the interaction relationship between two elements. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0043] The following disclosure provides many different embodiments, or examples, for implementing different structures of the present application. For purposes of simplicity of the present disclosure, the descriptions of the certain examples below refer to components and settings that are relative to the present application. Of course, they are merely examples, and are not intended to limit the present application. Furthermore, the present application can repeat reference numerals and / or reference letters in various examples, and such repetition is for the purpose of simplicity and clarity, and does not in itself dictate a relationship between the various embodiments and / or settings discussed.

[0044] Figure 1 A cross-sectional schematic view of the flip LED chip provided for some embodiments of the present application; Figure 2 A top view schematic view of the first passivation layer and its underlying film layer provided for some embodiments of the present application; Figure 3 A top view schematic view of the first passivation layer provided for some embodiments of the present application. As shown in Figure 1 、 Figure 2 、 Figure 3 In the first aspect, some embodiments of the present application provide a flip LED chip with high reliability, which comprises a substrate 100, a semiconductor layer 110, a metal reflection layer 140, a first passivation layer 160, a metal contact layer 170 and a second passivation layer 180, the semiconductor layer 110 is arranged on one side of the substrate 100, and the semiconductor layer 110 comprises an N-type semiconductor layer 112, an active layer 113 and a P-type semiconductor layer 114 arranged in sequence; the metal reflection layer 140 is arranged on the side of the semiconductor layer 110 away from the substrate 100, and is electrically connected with the P-type semiconductor layer 114; the first passivation layer 160 is arranged on the side of the metal protection layer 150 away from the substrate 100, and the first passivation layer 160 comprises at least one first through hole T1 and at least one second through hole T2; the metal contact layer 170 is arranged on the side of the first passivation layer 160 away from the substrate 100, and the metal contact layer 170 comprises a first metal contact part 171 and a second metal contact part 172, the first metal contact part 171 is electrically connected with the N-type semiconductor layer 112 through the first through hole T1, and the second metal contact part 172 is electrically connected with the metal reflection layer 140 through the second through hole T2; the second passivation layer 180 is arranged on the side of the metal contact layer 170 away from the substrate 100; wherein the first passivation layer 160 comprises a first entity part 161 and a second entity part 162, the first entity part 161 is in contact with the second passivation layer 180, the second entity part 162 is arranged apart from the second passivation layer 180, and the thickness of the first entity part 161 is greater than the thickness of the second entity part 162.

[0045] In the related art, after the metal reflective layer 140 is prepared, other patterned film layers, such as the patterned first passivation layer 160 and the patterned metal contact layer 170, need to be prepared on the metal reflective layer 140. The patterning process of the first passivation layer 160 and the patterning process of the metal contact layer 170 both need to use a photoresist mask, and accordingly, the cleaning process of the photoresist mask used in the patterning process of the first passivation layer 160 and the patterning process of the metal contact layer 170. The cleaning process of the photoresist mask needs to use a cleaning solution, for example, the semi-finished product of the flip-chip LED chip needs to be soaked in the cleaning solution to clean and remove the photoresist mask on the first passivation layer 160. However, the applicant found that the cleaning solution inevitably contains conductive ions, which makes the cleaning solution form an electrical connection path between the N-type semiconductor layer 112 and the P-type semiconductor layer 114 when the cleaning solution contacts the N-type semiconductor layer 112 and the metal protective layer 150, thereby causing an electric field between the N-type semiconductor layer 112 and the P-type semiconductor layer 114 that facilitates the electrochemical migration of the metal reflective layer 140. This means that in the related art, the patterning process of the first passivation layer 160 and the patterning process of the metal contact layer 170 will both generate an electric field that facilitates the electrochemical migration of the metal reflective layer 140, thereby greatly increasing the short-circuit risk of the flip-chip LED chip, reducing product yield, and having poor reliability.

[0046] To solve the above problems, the applicant found that the purpose of the patterning process of the first passivation layer 160 includes forming the first through hole T1 and the second through hole T2, and the photoresist mask used can be arranged on the surface of the first passivation layer 160, and the photoresist mask can be arranged at a position other than the first through hole T1 and the second through hole T2. The purpose of the patterning process of the metal contact layer 170 includes forming the first metal contact part 171 and the second metal contact part 172 arranged at intervals, and the photoresist mask used can be arranged on the surface of the first passivation layer 160, and the photoresist mask can be arranged at a position corresponding to the hollow part L1 between the first metal contact part 171 and the second metal contact part 172.

[0047] Based on the above analysis, the applicant found that, since the first metal contact part 171 is electrically connected with the N-type semiconductor layer 112 through the first through hole T1, and the second metal contact part 172 is electrically connected with the metal reflection layer 140 through the second through hole T2, it means that the position of the hollow part L1 does not overlap with the positions of the first through hole T1 and the second through hole T2, so that the two patterning purposes can be achieved by the photoresist mask (the second photoresist layer 200) corresponding to the position of the hollow part L1 and arranged on the surface of the first passivation layer 160, one of which can be thinning processing (defined as the second thinning processing) on the area of the first passivation layer 160 including the positions of the first through hole T1 and the second through hole T2, and the other can be forming the metal contact layer 170 including the first metal contact part 171, the second metal contact part 172 and the hollow part L1.

[0048] Based on the above analysis, the applicant can perform a pre-thinning processing (defined as the first thinning processing) on the positions of the first through hole T1 and the second through hole T2 by using the photoresist mask (the first photoresist layer) arranged on the first passivation layer 160 before forming the second photoresist layer 200, so that the thickness of the first passivation layer 160 at the positions of the first through hole T1 and the second through hole T2 is thinner than that of other areas, but the thickness is still greater than 0. Then, the cleaning step of the first photoresist layer is performed, and then the second thinning processing is performed on the area of the first passivation layer 160 including the positions of the first through hole T1 and the second through hole T2 by using the second photoresist layer 200, so that the first passivation layer 160 at the positions of the first through hole T1 and the second through hole T2 can be thinned to a thickness of 0 faster than the first passivation layer 160 at other areas, thereby ensuring that other areas still retain the first passivation layer 160 on the basis of successfully forming the first through hole T1 and the second through hole T2, without increasing the number of photoresist mask processes, which can effectively control the process cost. And since the thickness of the first passivation layer 160 at the positions of the first through hole T1 and the second through hole T2 is still greater than 0 when the cleaning step of the first photoresist layer is performed, the electric field conducive to the electrochemical migration of the metal reflection layer 140 can be avoided, thereby reducing the risk of short circuit and improving product yield and reliability.

[0049] Correspondingly, due to the protection of the second photoresist layer 200 of the hollow part L1, the thickness of the first passivation layer 160 under the hollow part L1 is not thinned, and the second passivation layer 180 passes through the hollow part L1 and contacts the first passivation layer 160 under the hollow part L1, so that the thickness of the first solid part 161 in contact with the second passivation layer 180 is the largest; and the second solid part 162 spaced from the second passivation layer 180 will be subjected to the second thinning process, so that the thickness of the second solid part 162 is smaller than the thickness of the first solid part 161.

[0050] In some embodiments of the present application, the metal reflection layer 140 includes silver.

[0051] In the flip LED chip provided by the embodiments of the present application, when the metal reflection layer 140 includes silver, for example, a silver reflection layer, the high reflectivity and excellent conductivity of the metal reflection layer 140 can be further improved. However, the metal reflection layer 140 of the present application can not include silver, that is, the flip LED chip of the present application is applicable to the solution of the electrochemical migration problem of other metal elements except silver.

[0052] In some embodiments of the present application, the thickness of the first solid part 161 is the same as the thickness of the second passivation layer 180, and the thickness of the second solid part 162 is smaller than the thickness of the second passivation layer 180.

[0053] In the flip LED chip provided by the embodiments of the present application, in order to simplify the film forming process, the parameters of the whole surface deposition process of the first passivation layer 160 and the whole surface deposition process of the second passivation layer 180 can be set to be the same, and correspondingly, the thickness of the first solid part 161 of the first passivation layer 160 which is not thinned and the thickness of the second passivation layer 180 are the same, and the thickness of the second solid part 162 subjected to the second thinning process is smaller than the thickness of the second passivation layer 180.

[0054] In some embodiments of the present application, the material of the second passivation layer 180 is the same as the material of the first passivation layer 160. For example, the material of the second passivation layer 180 includes at least one of aluminum oxide and silicon dioxide.

[0055] In some embodiments of the present application, the orthographic projection area of the first solid part 161 on the substrate 100 is a first area, and the orthographic projection area of the second solid part 162 on the substrate 100 is a second area, wherein the second area is more than five times the first area.

[0056] In the flip LED chip provided by the embodiment of the application, when the cleaning solution can electrically connect the N-type semiconductor layer 112 and the P-type semiconductor layer 114 through the first through hole T1 and the second through hole T2 in the cleaning process of the photoresist mask pattern, an electric field is generated in the cleaning solution, thereby promoting the electrochemical migration of the metal reflection layer 140, and the larger the area of the photoresist mask pattern is and the longer the cleaning time is. The first solid part 161 corresponds to the position of the hollow part L1 in the metal contact layer 170, and the hollow part L1 in the metal contact layer 170 corresponds to the position of the photoresist mask (the second photoresist layer 200) in the patterning process of the metal contact layer 170, that is, the larger the area of the first solid part 161 is, the more obvious the electrochemical migration problem of the metal reflection layer 140 is. The second area is more than five times the first area, thereby making the area of the second photoresist layer 200 smaller, thereby accelerating the cleaning speed of the second photoresist layer 200, and further improving the electrochemical migration problem of the metal reflection layer 140, reducing the short circuit risk, and improving the product yield.

[0057] In some embodiments of the application, the thickness of the second solid part 162 is 0.8 to 0.9 times the thickness of the first solid part 161.

[0058] The flip LED chip provided by the embodiment of the application can control the thickness of the second thinning process, without affecting the normal formation of the first through hole T1 and the second through hole T2, so that the thickness of the second solid part 162 is 0.8 to 0.9 times the thickness of the first solid part 161, so that the thickness of the first solid part 161 and the second solid part 162 of the first passivation layer 160 can be kept at a high level, which is beneficial to effectively guarantee the protection and sealing functions of the first passivation layer 160.

[0059] In some embodiments of the application, the flip LED chip further comprises a metal protection layer 150, the metal protection layer 150 is arranged on the side of the metal reflection layer 140 away from the substrate 100, and the second metal contact part 172 is in contact with the metal protection layer 150 through the second through hole T2, wherein the metal protection layer 150 does not cover the side wall of the metal reflection layer 140.

[0060] In the flip LED chip provided by the embodiment of the present application, in order to avoid performance deterioration of the flip LED chip due to the problem of electrochemical migration of the metal reflection layer 140 in the subsequent use process, the metal protection layer 150 is arranged at least at the position of the second through hole T2 prone to the problem of electrochemical migration, so as to improve the reliability of the flip LED chip. In addition, since the thickness of the first solid part 161 is greater than the thickness of the second solid part 162, the cleaning process of the first photoresist layer does not generate an electric field that promotes the electrochemical migration of the metal reflection layer 140, thereby greatly reducing the short circuit risk in the production process of the flip LED chip and improving the product yield. Accordingly, this enables the flip LED chip of the present application to no longer be provided with the metal protection layer 150 that needs to completely cover the sidewall of the metal reflection layer 140, which can save the material cost of the metal protection layer 150 on the one hand, and more importantly, can expand the setting area of the metal reflection layer 140, thereby improving the reflection efficiency of the metal reflection layer 140 and improving the brightness and luminous efficiency of the flip LED chip.

[0061] In some embodiments of the present application, the area of the orthographic projection of the metal reflection layer 140 on the substrate 100 is a first area, and the area of the orthographic projection of the metal protection layer 150 on the substrate 100 is a second area, wherein the first area is equal to the second area.

[0062] In the flip LED chip provided by the embodiment of the present application, the applicant further found that although the metal protection layer 150 can be arranged only in the region of the second through hole T2 to reduce the amount of metal protection layer 150 material as much as possible, this means that the photoresist mask of the metal protection layer 150 and the photoresist mask of the metal reflection layer 140 cannot be shared, that is, an additional mask process will be newly added, and more importantly, the newly added mask process will lead to an increase in the number of photoresist mask cleaning processes, which may in turn cause the deterioration of the problem of electrochemical migration of the metal reflection layer 140. Therefore, by making the area of the orthographic projection of the metal reflection layer 140 on the substrate 100 the same as the area of the orthographic projection of the metal protection layer 150 on the substrate 100, the mask process and the mask cleaning process can be reduced without affecting the reflection area of the metal reflection layer 140, thereby reducing the process cost, improving the product yield and reliability.

[0063] In some embodiments of the present application, the semiconductor layer 110 comprises an edge step structure 115, a step surface of the edge step structure 115 is the N-type semiconductor layer 112, and a sidewall of the edge step structure 115 is the P-type semiconductor layer 114 and the active layer 113. The first passivation layer 160 further comprises a first slot C1, the first slot C1 exposes at least part of the step surface of the edge step structure 115, and the first metal contact 171 is electrically connected with the N-type semiconductor layer 112 through the first slot C1. The first passivation layer 160 covering the sidewall of the edge step structure 115 is covered by the metal contact layer 170.

[0064] In the flip LED chip provided by the embodiments of the present application, the first slot C1 is arranged on the first passivation layer 160, thereby exposing the step surface of the edge step structure 115, so as to increase the exposed area of the N-type semiconductor layer 112, so that more metal contact layers 170 can be in contact with and electrically connected with the N-type semiconductor layer 112, thereby facilitating the improvement of the electrical performance of the flip LED chip. In addition, since the sidewall of the edge step structure 115 is covered by the first passivation layer 160, the short circuit problem caused by the direct contact between the metal contact layer 170 and the sidewall of the edge step structure 115 can be avoided. Moreover, the first passivation layer 160 covering the sidewall of the edge step structure 115 is covered by the metal contact layer 170, so that the light emitted from the sidewall of the edge step structure 115 can be reflected by the metal contact layer 170, thereby further improving the light extraction efficiency of the flip LED chip.

[0065] In some embodiments of the present application, the second passivation layer 180 comprises a third through hole T3 and a fourth through hole T4, the third through hole T3 exposes the first metal contact 171, and the fourth through hole T4 exposes the second metal contact 172. The flip LED chip further comprises an electrode layer 190, the electrode layer 190 comprises a first electrode 191 and a second electrode 192, the first electrode 191 is in contact with the first metal contact 171 through the third through hole T3, and then is electrically connected with the N-type semiconductor layer 112 through the first metal contact 171, the second electrode 192 is in contact with the second metal contact 172 through the fourth through hole T4, and then is electrically connected with the P-type semiconductor layer 114 through the second metal contact 172.

[0066] In some embodiments of the present application, the material of the electrode layer 190 is different from the material of the metal contact layer 170. For example, the material of the electrode layer 190 is gold-tin alloy.

[0067] In some embodiments of the present application, the substrate 100 can be a sapphire substrate 100.

[0068] In some embodiments of the present application, the surface of the side of the substrate 100 facing away from the semiconductor layer 110 is a roughened surface.

[0069] In some embodiments of the present application, the semiconductor layer 110 further comprises a buffer layer 111 disposed between the substrate 100 and the N-type semiconductor layer 112.

[0070] In some embodiments of the present application, the surface of the side of the buffer layer 111 facing toward the substrate 100 is a roughened surface.

[0071] In some embodiments of the present application, the semiconductor layer 110 comprises a plurality of fifth through holes T5 penetrating the P-type semiconductor layer 114 and the active layer 113 and exposing the N-type semiconductor layer 112, wherein the first through holes T1 are disposed in correspondence with the fifth through holes T5.

[0072] In some embodiments of the present application, the flip LED chip further comprises a transparent conductive layer 120 disposed on the side of the P-type semiconductor layer 114 facing away from the substrate 100. Specifically, the transparent conductive layer 120 is disposed on the surface of the side of the P-type semiconductor layer 114 facing away from the substrate 100 to be in direct contact with the P-type semiconductor layer 114, and the material of the transparent conductive layer 120 can be ITO. The transparent conductive layer 120 is used to achieve a current spreading function to improve device performance and light extraction efficiency.

[0073] In some embodiments of the present application, the transparent conductive layer 120 comprises a plurality of sixth through holes T6 penetrating the transparent conductive layer 120 and disposed in correspondence with the fifth through holes T5 to expose the N-type semiconductor layer 112.

[0074] In some embodiments of the present application, the flip LED chip further comprises a current barrier layer 130 disposed on the side of the transparent conductive layer 120 facing away from the substrate 100, and the current barrier layer 130 comprises a plurality of seventh through holes T7 penetrating the current barrier layer 130 and disposed in correspondence with the fifth through holes T5 to expose the N-type semiconductor layer 112.

[0075] In some embodiments of the present application, the current barrier layer 130 further comprises a plurality of current expansion holes T10 arranged in an array and exposing the transparent conductive layer 120, so that the metal reflective layer 140 arranged on the side of the current barrier layer 130 away from the substrate 100 can be in contact with the transparent conductive layer 120 through the current expansion holes T10, and then be electrically connected with the P-type semiconductor layer 114 through the transparent conductive layer 120.

[0076] In some embodiments of the present application, the metal reflective layer 140 comprises a plurality of eighth through holes T8 arranged correspondingly with the fifth through holes T5 to expose the N-type semiconductor layer 112.

[0077] In some embodiments of the present application, the metal protective layer 150 comprises a plurality of ninth through holes T9 arranged correspondingly with the fifth through holes T5 to expose the N-type semiconductor layer 112.

[0078] In some embodiments of the present application, the first passivation layer 160 is arranged on the side of the metal protective layer 150 away from the substrate 100, and the first passivation layer 160 comprises a plurality of the first through holes T1 arranged correspondingly with the fifth through holes T5 to expose the N-type semiconductor layer 112 and a plurality of the second through holes T2 exposing the metal protective layer 150. It should be noted that in other embodiments of the present application, the metal protective layer 150 can be omitted, and the second through holes T2 expose the metal reflective layer 140.

[0079] In a second aspect, the embodiments of the present application provide a preparation method of a high-reliability flip LED chip, and the preparation method of the flip LED chip comprises steps S10, S20, S30, S40, S50, S60, S70 and S80.

[0080] Referring to Figure 4 , Figure 5 , Figure 6 , the step S10 comprises forming a patterned semiconductor layer 110 on a substrate 100, the semiconductor layer 110 comprising an N-type semiconductor layer 112, an active layer 113 and a P-type semiconductor layer 114 arranged in sequence, and a local region of the N-type semiconductor layer 112 being exposed.

[0081] Referring to Figure 7 , Figure 8 , Figure 9As shown, step S20 includes forming a patterned metal reflective layer 140 on the semiconductor layer 110, wherein the metal reflective layer 140 is electrically connected with the P-type semiconductor layer 114 and does not cover the exposed local region of the N-type semiconductor layer 112.

[0082] Referring to Figure 10 , step S30 includes forming a first passivation layer 160 on the metal reflective layer 140, wherein the first passivation layer 160 is in contact with the sidewall of the metal reflective layer 140, and the first passivation layer 160 has a first region A1, a second region A2 and a third region A3, and the thickness of the first passivation layer 160 in the first region A1, the second region A2 and the third region A3 is the same.

[0083] Referring to Figure 11 , step S40 includes forming a patterned first photoresist layer on the first passivation layer 160 in the first region A1 and the second region A2, i.e., the first photoresist layer does not expose the first passivation layer 160 in the third region A3; using the first photoresist layer, etching the first passivation layer 160 in the third region A3 to thin the first passivation layer 160 in the third region A3 to a thickness greater than 0; and removing the first photoresist layer using a cleaning solution. Figure 12 For Figure 11 , a partial enlarged view of the M1 region in FIG. 4B, referring to Figure 12 , after step S40, the thickness of the first passivation layer 160 in the third region A3 is greatly thinned, and the thickness of the first passivation layer 160 in the first region A1 and the second region A2 remains unchanged.

[0084] Referring to Figure 13 , step S50 includes forming a patterned second photoresist layer 200 on the first passivation layer 160 in the first region A1. Figure 14 For Figure 13 , a partial enlarged view of the M2 region in FIG. 4C, referring to Figure 14 , before the second photoresist layer 200 is formed and the first passivation layer 160 in the second region A2 and the third region A3 is not etched, the thickness of the first passivation layer 160 in the first region A1 and the second region A2 is the same.

[0085] Referring to Figure 15, step S50 further comprises: etching the first passivation layer 160 of the second region A2 and the third region A3, so as to thin the first passivation layer 160 of the second region A2 to a state greater than 0, and make the thickness of the first passivation layer 160 of the third region A3 to be 0, to form at least one first via hole T1, at least one second via hole T2, and a first slot C1 on the first passivation layer 160, wherein, in the direction perpendicular to the substrate 100, the first via hole T1, the first slot C1 and the N-type semiconductor layer 112 are arranged in an overlapping manner, and the second via hole T2 and the metal reflection layer 140 are arranged in an overlapping manner.

[0086] Referring to Figure 18 , step S60 comprises: forming a metal contact layer 170 on the second photoresist layer 200, and the metal contact layer 170 covers the first passivation layer 160, the second photoresist layer 200, the first via hole T1 and the second via hole T2.

[0087] Referring to Figure 19 , step S70 comprises: removing the metal contact layer 170 on the second photoresist layer 200 and the second photoresist layer 200, so as to make the thickness of the metal contact layer 170 of the first region A1 to be 0, and form a hollow portion L1 in the metal contact layer 170, so that the remaining metal contact layer 170 comprises a first metal contact portion 171 and a second metal contact portion 172 arranged in a spaced manner, the first metal contact portion 171 fills the first via hole T1 to electrically connect the N-type semiconductor layer 112, and the second metal contact portion 172 fills the second via hole T2 to electrically connect the P-type semiconductor layer 114, and the orthographic projection of the hollow portion L1 on the substrate 100 is located in the first region A1, in addition, the first metal contact portion 171 is also electrically connected to the N-type semiconductor layer 112 through the first slot C1.

[0088] Referring to Figure 20 , step S80 comprises: forming a patterned second passivation layer 180 on the metal contact layer 170, and the second passivation layer 180 is in contact with the first passivation layer 160 through the hollow portion L1. In step S80, the second passivation layer 180 fills the hollow portion L1, so as to electrically isolate the first metal contact portion 171 and the second metal contact portion 172 through the second passivation layer 180.

[0089] The preparation method of the flip LED chip provided by the embodiment of the application comprises steps S10, S20, S30, S40, S50, S60, S70, S80. After the step S40 ends, the thickness of the first passivation layer 160 of the third region A3 is greatly reduced, while the thickness of the first passivation layer 160 of the first region A1 and the second region A2 remains unchanged, so that the thickness of the first passivation layer 160 of the third region A3 is thinner than that of other regions, and then in the second thinning process of the first passivation layer 160 included in the subsequent step S50, the thickness of the first passivation layer 160 of the third region A3 is first changed to 0, while the thickness of other regions is still greater than 0, so that the through-hole structure is formed for facilitating the conduction of the N-type semiconductor layer 112 and the P-type semiconductor layer 114 by the external electrical signal while the sealing and protection functions of the first passivation layer 160 are taken into account.

[0090] On this basis, in the steps S40 to S70, the cleaning process of the photoresist mask has multiple processes, such as the cleaning process of the first photoresist layer and the cleaning process of the second photoresist layer 200, but when the cleaning process of the first photoresist layer is performed, the thickness of the first passivation layer 160 of the first region A1, the second region A2 and the third region A3 is greater than 0, so the cleaning solution cannot be electrically connected with the semiconductor layer 110, and thus an electric field cannot be generated between the P-type semiconductor layer 114 and the N-type semiconductor layer 112, thereby improving the problem of electrochemical migration of the metal reflection layer 140, and improving the yield and reliability.

[0091] In addition, although the first passivation layer 160 forms the through-hole structure by the previous one patterning process, which is changed to two patterning processes, the application reuses the photoresist mask (second photoresist layer 200) of the metal contact layer 170, so that the photoresist mask required by the process is not increased, and the cleaning process of the photoresist mask is not increased, that is, the electrochemical migration problem of the metal reflection layer 140 in one photoresist cleaning process is solved without changing the number of photoresist cleaning processes.

[0092] In the preparation method of the flip LED chip provided in the embodiments of the present application, the thickness of the first passivation layer 160 of the first region A1 and the second region A2 is still greater than 0 after the step S80 is completed, that is, the first passivation layer 160 of the first region A1 and the second region A2 is the entity part of the first passivation layer 160, but since the first passivation layer 160 of the first region A1 (defined as the first entity part 161) is not thinned, and the first passivation layer 160 of the second region A2 (defined as the second entity part 162) is thinned once, therefore, the thickness of the first entity part 161 is greater than the thickness of the second entity part 162. Since the position of the hollow part L1 of the metal contact layer 170 corresponds to the first region A1, correspondingly, the first passivation layer 160 (the first entity part 161) in contact with the second passivation layer 180, and the first passivation layer 160 (the second entity part 162) spaced apart from the second passivation layer 180.

[0093] Secondly, in the preparation method of the flip LED chip provided in the embodiments of the present application, the metal contact layer 170 is additionally provided, and then the first metal contact part 171 is used to fill the first through hole T1 to electrically connect the N-type semiconductor layer 112, and the second metal contact part 172 is used to fill the second through hole T2 to electrically connect the P-type semiconductor layer 114, so as to facilitate the electrical connection between the electrode and the N-type semiconductor layer 112 and the P-type semiconductor layer 114 by using the metal contact layer 170 as a medium.

[0094] Continuing to refer to FIGS. 1 to 6, Figure 7 , Figure 8 , Figure 9 In some embodiments of the present application, the step S20 of forming the patterned metal reflection layer 140 on the semiconductor layer 110 includes: forming a patterned third photoresist layer on the semiconductor layer 110; forming a metal reflection layer 140 on the semiconductor layer 110 and the third photoresist layer; forming a metal protection layer 150 on the metal reflection layer 140; and cleaning and removing the third photoresist layer; wherein the area of the orthographic projection of the metal protection layer 150 on the substrate 100 is a first area, the area of the orthographic projection of the metal protection layer 150 on the substrate 100 is a second area, and the first area is equal to the second area.

[0095] The preparation method of the flip LED chip provided by the embodiments of the present application can simplify the process, reduce the production cost, and further improve the electrochemical migration of the metal reflective layer 140 and the reliability of the flip LED chip.

[0096] In addition, since the first area and the second area are the same, the metal reflective layer 140 and the metal protective layer 150 completely overlap, so that the metal protective layer 150 cannot compress the lateral space of the metal reflective layer 140, and the area of the metal reflective layer 140 can be maximized, thereby improving the reflection efficiency and luminous brightness of the flip LED chip.

[0097] In some embodiments of the present application, in the step of etching the first passivation layer 160 of the third region A3 by using the first photoresist layer, the thickness of the first passivation layer 160 of the third region A3 is the first thickness; in the step of etching the first passivation layer 160 of the second region A2 and the third region A3 by using the second photoresist layer 200, the thickness of the first passivation layer 160 of the second region A2 is the second thickness, and the first thickness is 4 to 9 times of the second thickness.

[0098] In the preparation method of the flip LED chip provided by the embodiments of the present application, the first thickness is 4 to 9 times of the second thickness, so that the thickness of the first passivation layer 160 remaining in the second region A2 is as large as possible under the condition of normally forming the via structure penetrating through the first passivation layer 160, thereby improving the sealing and protection functions of the first passivation layer 160 and the reliability of the flip LED chip.

[0099] The preparation method of the flip LED chip provided by some embodiments of the present application will be further described below.

[0100] In some embodiments of the present application, the step S10 includes the step S11, the step S12, and the step S13.

[0101] Referring to Figure 4 The step S11 includes forming a semiconductor layer 110 on a substrate 100, and the semiconductor layer 110 includes a buffer layer 111, an N-type semiconductor layer 112, an active layer 113, and a P-type semiconductor layer 114 which are sequentially stacked.

[0102] Referring to Figure 5, step S12 includes: performing first patterning process on the semiconductor layer 110 to form a plurality of fifth through holes T5 and an edge step structure 115 on the semiconductor layer 110, wherein the fifth through holes T5 penetrate the P-type semiconductor layer 114 and the active layer 113, the edge step structure 115 exposes the step surface of the N-type semiconductor layer 112, and the sidewall of the edge step structure 115 is the P-type semiconductor layer 114 and the active layer 113.

[0103] Referring to Figure 6 , step S13 includes: performing second patterning process on the semiconductor layer 110 to make at least part of the substrate 100 not covered by the edge step structure 115.

[0104] In some embodiments of the present application, step S20 includes step S21, step S22, step S23, and step S24.

[0105] Referring to Figure 7 , step S21 includes: forming a patterned transparent conductive layer 120 on the semiconductor layer 110, wherein the transparent conductive layer 120 includes a plurality of sixth through holes T6, the sixth through holes T6 penetrate the transparent conductive layer 120 and are arranged corresponding to the fifth through holes T5 to expose the N-type semiconductor layer 112, and the material of the transparent conductive layer 120 can be ITO or other transparent conductive oxide.

[0106] Referring to Figure 8 , step S22 includes: forming a patterned current barrier layer 130 on the transparent conductive layer 120, wherein the current barrier layer 130 includes a plurality of seventh through holes T7 and a plurality of current expansion holes T10, the seventh through holes T7 penetrate the current barrier layer 130 and are arranged corresponding to the fifth through holes T5 to expose the N-type semiconductor layer 112; and the current expansion holes T10 are arranged in an array and expose the transparent conductive layer 120.

[0107] Step S23 includes: forming a patterned third photoresist layer on the current barrier layer 130.

[0108] Step S24 includes: forming a metal reflective layer 140 on the semiconductor layer 110 and the third photoresist layer.

[0109] Step S25 includes: forming a metal protective layer 150 on the metal reflective layer 140.

[0110] Referring to Figure 9S26 includes removing the metal reflective layer 140 and the metal protective layer 150 on the third photoresist layer, and cleaning to remove the third photoresist layer, wherein the metal protective layer 150 has the same area of the orthographic projection on the substrate 100 as the metal reflective layer 140, the metal reflective layer 140 includes a plurality of eighth through holes T8, the metal protective layer 150 includes a plurality of ninth through holes T9, the ninth through holes T9, the eighth through holes T8 and the fifth through holes T5 are arranged correspondingly to expose the N-type semiconductor layer 112; the metal reflective layer 140 fills the current spreading hole T10 to be in contact with the transparent conductive layer 120 through the current spreading hole T10, and then to be electrically connected with the P-type semiconductor layer 114 through the transparent conductive layer 120.

[0111] In some embodiments of the present application, the metal reflective layer 140 includes Ag, and the metal protective layer 150 includes at least one of Ni, TiW and Pt.

[0112] Referring to Figure 10 In some embodiments of the present application, step S30 includes forming a first passivation layer 160 on the metal protective layer 150 of the metal reflective layer 140, the first passivation layer 160 is formed by atomic layer deposition or plasma enhanced chemical vapor deposition, and the first passivation layer 160 can include at least one of silicon dioxide and aluminum trioxide, wherein the first passivation layer 160 is in contact with the sidewall of the metal reflective layer 140, and the first passivation layer 160 has a first area A1, a second area A2 and a third area A3.

[0113] In some embodiments of the present application, step S40 includes step S41, step S42 and step S43.

[0114] Step S41 includes forming a patterned first photoresist layer on the first passivation layer 160, the first photoresist layer covers the first area A1 and the second area A2 of the first passivation layer 160, and exposes the third area A3 of the first passivation layer 160.

[0115] Step S42 includes performing a first thinning process on the first passivation layer 160 of the third area A3 by using the first photoresist layer to remove part of the thickness of the first passivation layer 160 of the third area A3 by etching. For example, the first thinning process can remove 80% to 90% of the thickness of the first passivation layer 160 of the third area A3.

[0116] Referring to Figure 11 , Figure 12S43 includes removing the first photoresist layer by using a cleaning solution, so that the thickness of the first passivation layer 160 in the first region A1 and the second region A2 is greater than the thickness of the first passivation layer 160 in the third region A3, and the thickness of the first passivation layer 160 in the third region A3 is greater than 0.

[0117] In some embodiments of the present application, in step S43, since the thickness of the first passivation layer 160 in any region is greater than 0 at this time, the metal protection layer 150 (which can be replaced by the metal reflection layer 140 in other embodiments, i.e., the metal protection layer 150 is directly omitted) and the N-type semiconductor layer 112 below the first passivation layer 160 are both protected from directly contacting the cleaning solution, thereby avoiding the problem that the cleaning solution electrically connects the N-type semiconductor layer 112 and the P-type semiconductor layer 114 during the cleaning and photoresist removal process, and generates an electric field that promotes the electrochemical migration of the metal reflection layer 140.

[0118] In some embodiments of the present application, step S50 includes step S51 and step S52.

[0119] Referring to Figure 13 and Figure 14 , step S51 includes forming a second photoresist layer 200 on the first passivation layer 160 in the first region A1.

[0120] Referring to Figure 15 , Figure 16 and Figure 17 , step S52 includes performing a second thinning process on the second region A2 and the third region A3 of the first passivation layer 160.

[0121] In some embodiments of the present application, in step S51, the selection of the first region A1 directly determines the position of the hollow portion L1 of the metal contact layer 170, but the shape and position of the hollow portion L1 are not specifically limited in the present application, as long as the hollow portion L1 can effectively electrically isolate the first metal contact portion 171 and the second metal contact portion 172 of the metal contact layer 170 and does not overlap with the third region A3, that is, the shape and position of the first region A1 do not necessarily have to be the same as the shape and position shown in the figure, and can also be adjusted according to the actual process.

[0122] In some embodiments of the present application, in step S52, the purpose of the second thinning is to make the thickness of the first passivation layer 160 in the third region A3 be 0, and to make the thickness of the first passivation layer 160 in the second region A2 be as large as possible. That is, assuming that the thickness of the first passivation layer 160 in step S30 is d, the thickness of the first passivation layer 160 after the first thinning is e, the thickness of the first passivation layer 160 after the second thinning is f, the thickness of the first passivation layer 160 in the first region A1 after step S70 is a, the thickness of the first passivation layer 160 in the second region A2 is b, and the thickness of the first passivation layer 160 in the third region A3 is c, then a = d, b = d - f, and c = d - e - f. In a theoretical case, to make the thickness of the first passivation layer 160 in the second region A2 be as large as possible, d - e - f = 0. However, in an actual process, to make the thickness of the first passivation layer 160 in the third region A3 be 0, the value of the thickness f of the first passivation layer 160 after the second thinning needs to be appropriately increased, so that d - e - f < 0, that is, in an actual process, the thickness b of the first passivation layer 160 in the second region A2 is d - f < e.

[0123] In some embodiments of the present application, after step S50 is completed, the first passivation layer 160 includes at least one first via T1 and at least one second via T2, the first via T1 exposes the N-type semiconductor layer 112, and the second via T2 exposes the metal protection layer 150.

[0124] Continuing to refer to Figure 16 After the second thinning is completed, the thickness of the first passivation layer 160 in the third region A3 is 0, to form a first via T1 and a second via T2 on the first passivation layer 160, the first via T1 exposes the N-type semiconductor layer 112, and the second via T2 exposes the metal protection layer 150.

[0125] Continuing to refer to Figure 17 After the second thinning is completed, the thickness of the first passivation layer 160 in the first region A1 is greater than the thickness of the first passivation layer 160 in the second region A2, the first passivation layer 160 in the first region A1 is a first solid part 161, and the first passivation layer 160 in the second region A2 is a second solid part 162.

[0126] Referring to Figure 18In some embodiments of the present application, step S60 comprises forming a metal contact layer 170 on the second photoresist layer 200, wherein the metal contact layer 170 covers the first via T1, the second via T2, the step surface of the edge step structure 115, part of the first passivation layer 160 and part of the second photoresist layer 200. Since the second photoresist layer 200 has a certain thickness, the metal contact layer 170 on the first passivation layer 160 and the metal contact layer 170 on the second photoresist layer 200 are disconnected at the boundary area.

[0127] Referring to Figure 19 In some embodiments of the present application, step S70 comprises removing the second photoresist layer 200 and the metal contact layer 170 on the second photoresist layer 200, and the remaining metal contact layer 170 comprises a first metal contact 171, a second metal contact 172 and a hollow portion L1 arranged between the first metal contact 171 and the second metal contact 172. The first metal contact 171 fills the first via T1 to electrically connect the N-type semiconductor layer 112, the second metal contact 172 fills the second via T2 to electrically connect the P-type semiconductor layer 114, and the hollow portion L1 has a normal projection on the substrate 100 located in the first region A1.

[0128] Referring to Figure 20 In some embodiments of the present application, the method for manufacturing the flip LED chip further comprises step S80, which comprises forming a patterned second passivation layer 180 on the metal contact layer 170. In step S80, the second passivation layer 180 fills the hollow portion L1 to electrically isolate the first metal contact 171 and the second metal contact 172 through the second passivation layer 180. The second passivation layer 180 further comprises a third via T3 and a fourth via T4. The third via T3 exposes the first metal contact 171, and the fourth via T4 exposes the second metal contact 172.

[0129] Referring to Figure 21 In some embodiments of the present application, the method for manufacturing the flip LED chip further comprises step S90, which comprises forming an electrode layer 190 on the second passivation layer 180. The electrode layer 190 comprises a first electrode 191 and a second electrode 192. The first electrode 191 is in contact with and electrically connected to the first metal contact 171, and the second electrode 192 is in contact with and electrically connected to the second metal contact 172.

[0130] In summary, the application provides a flip LED chip with high reliability and a preparation method thereof. The flip LED chip comprises a substrate, a semiconductor layer, a metal reflection layer, a first passivation layer, a metal contact layer and a second passivation layer. The semiconductor layer is arranged on one side of the substrate. The semiconductor layer comprises an N-type semiconductor layer, an active layer and a P-type semiconductor layer arranged in sequence. The metal reflection layer is arranged on the side of the semiconductor layer away from the substrate and is electrically connected with the P-type semiconductor layer. The first passivation layer is arranged on the side of the metal protection layer away from the substrate. The first passivation layer comprises at least one first through hole and at least one second through hole. The metal contact layer is arranged on the side of the first passivation layer away from the substrate. The metal contact layer comprises a first metal contact part and a second metal contact part. The first metal contact part is electrically connected with the N-type semiconductor layer through the first through hole. The second metal contact part is electrically connected with the metal reflection layer through the second through hole. The second passivation layer is arranged on the side of the metal contact layer away from the substrate. The first passivation layer comprises a first solid part and a second solid part. The first solid part is in contact with the second passivation layer. The second solid part is arranged apart from the second passivation layer. The thickness of the first solid part is greater than the thickness of the second solid part. The application can improve the problem of electrochemical migration of the metal reflection layer and improve the yield and reliability of the product.

[0131] The above describes in detail a flip LED chip with high reliability and a preparation method thereof provided by the embodiments of the application. The principles and implementation manners of the application are described by using specific examples. The above description of the embodiments is only used to help understand the method of the application and its core idea. Meanwhile, for those skilled in the art, according to the idea of the application, the specific implementation manner and application range can be changed. In summary, the content of the specification should not be understood as a limitation of the application.

Claims

1. An inverted LED chip, characterized by, The flip LED chip comprises: a substrate; a semiconductor layer arranged on one side of the substrate, the semiconductor layer comprising an N-type semiconductor layer, an active layer, and a P-type semiconductor layer arranged in sequence; a metal reflection layer arranged on a side of the semiconductor layer away from the substrate and electrically connected with the P-type semiconductor layer; a first passivation layer arranged on a side of the metal protection layer away from the substrate, the first passivation layer comprising at least one first through hole and at least one second through hole; a metal contact layer arranged on a side of the first passivation layer away from the substrate, the metal contact layer comprising a first metal contact part and a second metal contact part, the first metal contact part being electrically connected with the N-type semiconductor layer through the first through hole, and the second metal contact part being electrically connected with the metal reflection layer through the second through hole; a second passivation layer arranged on a side of the metal contact layer away from the substrate; wherein the first passivation layer comprises a first entity part and a second entity part, the first entity part being in contact with the second passivation layer, the second entity part being arranged apart from the second passivation layer, and the thickness of the first entity part being greater than the thickness of the second entity part.

2. The flip-chip LED chip of claim 1, wherein, The thickness of the first entity part is the same as that of the second passivation layer, and the thickness of the second entity part is less than that of the second passivation layer.

3. The flip-chip LED chip of claim 1, wherein, The first entity part has a first area of a normal projection on the substrate, and the second entity part has a second area of a normal projection on the substrate, wherein the second area is more than five times of the first area.

4. The flip-chip LED chip of claim 1, wherein, The thickness of the second entity part is 0.8 to 0.9 times of the thickness of the first entity part.

5. The flip-chip LED chip of claim 1, wherein, The flip LED chip further comprises a metal protection layer arranged on a side of the metal reflection layer away from the substrate, the second metal contact part being in contact with the metal protection layer through the second through hole, wherein the metal protection layer does not cover the sidewall of the metal reflection layer.

6. The flip-chip LED chip of claim 5, wherein, The metal reflection layer has a first area of a normal projection on the substrate, and the metal protection layer has a second area of a normal projection on the substrate, wherein the first area is equal to the second area.

7. The flip-chip LED chip of claim 1, wherein, The semiconductor layer comprises an edge step structure, a step surface of the edge step structure being the N-type semiconductor layer, and a sidewall of the edge step structure being the P-type semiconductor layer and the active layer, wherein the first passivation layer further comprises a first slot, the first slot exposing at least part of the step surface of the edge step structure, the first metal contact part being electrically connected with the N-type semiconductor layer through the first slot, and the first passivation layer covering the sidewall of the edge step structure being covered by the metal contact layer.

8. A method for fabricating a flip-chip LED, characterized in that, The preparation method of the flip LED chip comprises: forming a patterned semiconductor layer on a substrate, the semiconductor layer comprising an N-type semiconductor layer, an active layer, and a P-type semiconductor layer arranged in sequence; forming a patterned metal reflection layer on the semiconductor layer, wherein the metal reflection layer is electrically connected with the P-type semiconductor layer; forming a first passivation layer on the metal reflective layer, wherein the first passivation layer has a first region, a second region and a third region; forming a patterned first photoresist layer on the first passivation layer of the first region and the second region; performing etching treatment on the first passivation layer of the third region by using the first photoresist layer, so as to thin the first passivation layer of the third region to a state greater than 0; removing the first photoresist layer by using a cleaning solution; forming a patterned second photoresist layer on the first passivation layer of the first region; performing etching treatment on the first passivation layer of the second region and the third region by using the second photoresist layer, so as to thin the first passivation layer of the second region to a state greater than 0, and make the thickness of the first passivation layer of the third region be 0, so as to form at least one first via hole and at least one second via hole on the first passivation layer, wherein the first via hole is arranged in an overlapping manner with the N-type semiconductor layer in a direction perpendicular to the substrate, and the second via hole is arranged in an overlapping manner with the metal reflective layer; forming a metal contact layer on the second photoresist layer, the metal contact layer covering the first passivation layer, the second photoresist layer, the first via hole and the second via hole; removing the metal contact layer on the second photoresist layer and the second photoresist layer, so as to make the thickness of the metal contact layer of the first region be 0, and form a hollow part in the metal contact layer; forming a patterned second passivation layer on the second photoresist layer, the second passivation layer being in contact with the first passivation layer through the hollow part; wherein the first passivation layer comprises a first entity and a second entity, the first entity is in contact with the second passivation layer, the second entity is arranged in a spaced manner with the second passivation layer, and the thickness of the first entity is greater than the thickness of the second entity.

9. The method of claim 8, wherein the method further comprises: The step of forming a patterned metal reflective layer on the semiconductor layer comprises: forming a patterned third photoresist layer on the semiconductor layer; forming a metal reflective layer on the semiconductor layer and the third photoresist layer; forming a metal protective layer on the metal reflective layer; cleaning to remove the third photoresist layer; wherein the area of the orthographic projection of the metal protective layer on the substrate is a first area, the area of the orthographic projection of the metal protective layer on the substrate is a second area, and the first area is equal to the second area.

10. The method of claim 9, wherein the method further comprises: In the step of performing etching treatment on the first passivation layer of the third region by using the first photoresist layer, the thinning thickness of the first passivation layer of the third region is a first thickness; in the step of performing etching treatment on the first passivation layer of the second region and the third region by using the second photoresist layer, the thinning thickness of the first passivation layer of the second region is a second thickness, wherein the first thickness is 4 to 9 times of the second thickness.

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