Dynamic dual-threshold laser echo pulse noise suppression method and embedded system

Abstract

The invention discloses a laser echo pulse noise suppression method based on dynamic double thresholds and an embedded system, belongs to the technical field of laser signal processing, and aims to solve the problem that strong pulse noise suppression and effective signal protection are difficult to balance in the prior art. The method comprises the following steps: acquiring a frame of digital signal sample; calculating a median value M and an absolute deviation mean value MADM of the sample; determining a dynamic high threshold TH and a low threshold TL based on M and MADM; and traversing each sampling point, and performing grading processing according to the relationship between the amplitude and the double thresholds: applying first noise suppression processing to the sampling point with the amplitude higher than TH, applying second noise suppression processing to the sampling point with the amplitude between TL and TH, and keeping the original value of the sampling point with the amplitude not higher than TL. The invention also discloses an embedded system for realizing the method. According to the invention, the pulse noise can be adaptively and accurately suppressed, the signal integrity is effectively protected, and the signal-to-noise ratio and the system robustness are improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of laser signal processing, and in particular to a laser echo pulse noise suppression method based on dynamic double thresholds and an embedded system. BACKGROUND

[0002] In pulsed laser ranging, laser radar and other applications, in addition to containing effective signals of target objects, the echo signals received by laser detectors often also contain various noises. The sources of these noises are diverse, including environmental background light, thermal noise generated by detectors and subsequent processing circuits, and electromagnetic interference inside and outside the system. Some of the noises appear in the form of pulses with amplitudes much higher than the effective signals, i.e., pulse-type noises. These strong pulse noises can seriously contaminate the effective signals, significantly reducing the signal-to-noise ratio of the signals, and thus causing the subsequent signal processing unit to make false judgments, affecting the accurate measurement rate and maximum effective distance of the ranging.

[0003] To solve the above problems, some noise suppression methods have been proposed in the prior art. One common method is to use a fixed threshold method, i.e., to pre-set a fixed amplitude threshold, and to regard all signal points exceeding the threshold as noise and to be rejected or suppressed. However, this method has the disadvantage that the threshold cannot be changed once it is set, and cannot adapt to the real-time changes in noise intensity in the environment. In a scenario with strong noise, a fixed low threshold can result in a large number of noises being missed; while in a scenario with weak noise, a fixed high threshold can cause some weak effective signals to be misjudged as noise, causing signal damage. Another type of method is the adaptive threshold method, such as some algorithms based on signal statistical characteristics (such as median absolute deviation), which can dynamically adjust the threshold according to the statistical characteristics of the current signal. Although this type of method has certain adaptive ability, it usually uses a single threshold for judgment, i.e., a binary division of the signal points as "noise" or "not noise". When there are pulse noises with greatly different intensities in the echo signals, the setting of a single threshold often results in a trade-off: if the threshold is set high to filter out extremely strong noises, it cannot effectively suppress medium-intensity noises; on the contrary, if the threshold is set low, it can damage effective signals with high amplitudes. Therefore, the prior art still has difficulty in achieving an ideal balance between effectively suppressing strong pulse noises and protecting effective signals when dealing with echo signals with complex pulse characteristics and large dynamic range of signal intensity, and the noise suppression effect needs to be further improved. SUMMARY

[0004] The purpose of the present application is to provide a noise suppression scheme that can be finely and hierarchically processed according to real-time noise characteristics, so as to effectively suppress strong impulse noise while avoiding damage to effective signals, thereby comprehensively improving the signal-to-noise ratio and the accuracy of the laser ranging system, in view of the technical problem in the prior art that it is difficult to balance the effective suppression of strong impulse noise and the protection of effective signals when processing laser echo signals.

[0005] In a first aspect, the embodiments of the present application provide a laser echo pulse noise suppression method based on dynamic double thresholds, comprising the following steps:

[0006] Obtaining a frame of digital signal samples corresponding to a laser echo signal;

[0007] Based on the digital signal samples, calculating the median M of the digital signal samples, and calculating the absolute deviation mean MADM of the digital signal samples relative to the median M;

[0008] Based on the median M and the absolute deviation mean MADM, determining a dynamic high threshold TH and a dynamic low threshold TL;

[0009] Traversing each sampling point in the digital signal samples, and classifying the sampling point according to the relationship between the amplitude of the sampling point and the dynamic high threshold TH and the dynamic low threshold TL, the classification processing comprising:

[0010] If the amplitude of the sampling point is greater than the high threshold TH, a first noise suppression processing is applied to the sampling point;

[0011] If the amplitude of the sampling point is between the low threshold TL and the high threshold TH, a second noise suppression processing is applied to the sampling point, wherein the second noise suppression processing is different from the first noise suppression processing;

[0012] If the amplitude of the sampling point is less than or equal to the low threshold TL, the original amplitude of the sampling point is retained.

[0013] Based on the above method, optionally, the dynamic high threshold TH and the dynamic low threshold TL are determined by the following formulas:

[0014] TH=M+K1*MADM;

[0015] TL=M+K2*MADM;

[0016] Wherein, K1 is a high threshold coefficient, K2 is a low threshold coefficient, and K1>K2.

[0017] Based on the above method, optionally, the value range of the high threshold coefficient K1 is 2.5-3.5, and the value range of the low threshold coefficient K2 is 1.2-1.8.

[0018] Based on the above method, optionally, the method further comprises:

[0019] After a frame of signal processing is completed, the number of sampling points determined as having an amplitude greater than the high threshold value TH is counted;

[0020] If the number is greater than a preset first number threshold value, the value of the high threshold value coefficient K1 is increased, but the value does not exceed a preset upper limit value;

[0021] If the number is less than a preset second number threshold value, the value of the high threshold value coefficient K1 is decreased, but the value does not fall below a preset lower limit value.

[0022] Based on the above method, optionally, the first noise suppression processing comprises: replacing the amplitude of the sampling point with the amplitude of a sampling point at the same position in the previous frame of data, or with the median value M calculated for the current frame;

[0023] The second noise suppression processing comprises: performing median filtering or local weighted mean filtering on the sampling point and its time-adjacent sampling points, and taking the filtering result as the new amplitude of the point.

[0024] Based on the above method, optionally, the method further comprises:

[0025] Point-by-point accumulation is performed on one or more frames of digital signal samples after the classification processing.

[0026] In a second aspect, the embodiments of the present application also provide a laser echo pulse noise suppression embedded system based on dynamic double thresholds, comprising:

[0027] A sample acquisition module is configured to acquire a frame of digital signal samples corresponding to a laser echo signal;

[0028] A parameter calculation module is configured to calculate a median value M of the digital signal samples and calculate an absolute deviation mean value MADM of the digital signal samples relative to the median value M based on the digital signal samples;

[0029] A threshold value determination module is configured to determine a dynamic high threshold value TH and a dynamic low threshold value TL based on the median value M and the absolute deviation mean value MADM;

[0030] A classification processing module is configured to traverse each sampling point in the digital signal samples and perform classification processing according to the relationship between the amplitude of the sampling point and the dynamic high threshold value TH and the dynamic low threshold value TL, wherein:

[0031] When the amplitude of the sampling point is greater than the high threshold value TH, the classification processing module applies first noise suppression processing to the sampling point;

[0032] when the amplitude of the sampling point is between the low threshold TL and the high threshold TH, the classification processing module applies a second noise suppression processing to the sampling point, wherein the second noise suppression processing is different from the first noise suppression processing;

[0033] when the amplitude of the sampling point is less than or equal to the low threshold TL, the classification processing module retains the original amplitude of the sampling point.

[0034] Based on the above system, optionally, the sample acquisition module comprises an ADC sampling circuit module; and,

[0035] The parameter calculation module, the threshold determination module and the classification processing module are realized by an FPGA main control circuit module.

[0036] Compared with the prior art, the present application has the following beneficial effects:

[0037] 1. Precise noise suppression and high signal fidelity. The present application calculates the absolute deviation mean which can stably represent the noise dispersion degree, and sets a dynamic double threshold combining with the median, which can more accurately reflect the real-time noise level of the signal. Further, a three-level classification processing strategy is adopted to apply different intensity processing to strong noise, suspected noise and effective signal, which realizes precise suppression of impulse noise, while maximizes the integrity of the effective signal, significantly improves the signal-to-noise ratio and signal fidelity compared with the prior art.

[0038] 2. Strong self-adaptability. The double threshold in the present application can dynamically change with the statistical characteristics of each frame of signal, and by introducing a feedback adjustment mechanism, the high threshold coefficient can be adaptively adjusted according to the noise density, so that the method can automatically adapt to various complex environments from low noise to strong impulse noise, ensuring the stability and robustness of the system in different working scenarios.

[0039] 3. Efficient hardware implementation and low cost. The method proposed in the present application has clear logic, and the calculation process is suitable for parallel processing, which can be realized based on an FPGA and an ADC chip, and the hardware structure is simple. Using the parallel processing characteristics of FPGA, the algorithm flow can be solidified into hardware logic to realize high-speed real-time processing synchronized with data acquisition, which meets the stringent requirements of laser ranging and other applications for real-time performance, while effectively reducing the hardware cost and power consumption of the system. BRIEF DESCRIPTION OF DRAWINGS

[0040] The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate embodiments consistent with the present application and, together with the description, further serve to explain the principles of the application. In addition, the drawings and the description are not intended to limit the application in any way.

[0041] Figure 1 A functional block diagram of an embedded system provided for an embodiment of the present application;

[0042] Figure 2 A flowchart of a noise suppression method provided for an embodiment of the present application;

[0043] Figure 3 A circuit schematic diagram of an ADC sampling circuit module and an FPGA master control circuit module in an embodiment of the present application;

[0044] Figure 4 A schematic diagram of a dynamic double-threshold noise suppression principle provided for an embodiment of the present application. DETAILED DESCRIPTION

[0045] To make the objects, technical solutions, and advantages of the present application clearer, the following will combine the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are some but not all of the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by a person of ordinary skill in the art without creative work fall within the protection scope of the present application. The following embodiments and features in the embodiments can be combined with each other without conflict.

[0046] Embodiment 1

[0047] The present embodiment provides a laser echo pulse noise suppression method based on a dynamic double threshold and a specific implementation scheme of an embedded system thereof. The scheme aims to effectively suppress pulse noise and maximize the preservation of valid signals by performing fine hierarchical processing on laser echo signals, thereby improving the performance of laser ranging and other applications.

[0048] Reference Figure 1 FIG. 1 shows a whole functional block diagram of an embedded system provided by an embodiment of the present application. The system can be integrated in a laser radar or laser ranging module at a physical level. The system mainly includes a signal conditioning circuit module 10, an analog-to-digital converter sampling circuit module 20, a field programmable gate array master control circuit module 30, a power module 40 for providing stable working voltage for the whole system, and a communication module 50 for data communication with an external master control unit or host computer.

[0049] Specifically, the raw laser echo analog signal received by the laser detector (not shown in the figure) is first sent to the signal conditioning circuit module 10. This module usually contains multiple stages of amplifiers and bandpass filters, which function to amplify the weak analog signal and filter out noise outside the operating frequency band, thereby laying the foundation for subsequent digital processing. The conditioned analog signal is then transmitted to the analog-to-digital converter sampling circuit module 20. Under the precise control of the sampling clock signal emitted by the field programmable gate array master circuit module 30, the analog-to-digital converter sampling circuit module 20 performs high-speed sampling and quantization on the analog signal at a pre-set sampling rate, converting it into a series of digital signal samples arranged in time sequence, which is a frame of digital signal. As the core of the system, the field programmable gate array master circuit module 30 receives the digital signal samples from the analog-to-digital converter sampling circuit module 20 and is used to perform all the core steps of the noise suppression algorithm proposed in this application. The processed data or the calculated target information can be sent out through the communication module 50 (e.g., universal asynchronous receiver-transmitter interface).

[0050] Please refer to Figure 3 for a more detailed illustration of the circuit principles of the analog-to-digital converter sampling circuit module 20 and the field programmable gate array master circuit module 30 in this embodiment. In this embodiment, the core of the analog-to-digital converter sampling circuit module 20 can be a high-speed analog-to-digital converter chip D1, such as an 8-bit parallel analog-to-digital converter of model BS10108 from Boson Micro. Correspondingly, the core of the field programmable gate array master circuit module 30 can be a GW1N-9 series field programmable gate array chip U1 from Gwinstek Semiconductor. The analog signal VIN from the signal conditioning circuit module 10 is input to the analog input terminal of the analog-to-digital converter chip D1. The field programmable gate array chip U1 generates and provides a stable sampling clock CLK_ADC to the analog-to-digital converter chip D1 through its general-purpose input / output pins, and the clock frequency can be set to 100 megahertz. The analog-to-digital converter chip D1 samples and quantizes the input analog signal VIN once at each rising edge of CLK_ADC, and transmits the resulting 8-bit digital quantity to the field programmable gate array chip U1 in real time through the parallel data bus D0-D7. The internal logic of the field programmable gate array chip U1 is responsible for receiving and caching these data, and at the same time, the chip U1 can also communicate with the external system through its serial communication pins UART_TX / RX.

[0051] Please refer to Figure 2 the flowchart for a detailed description of the specific process of the noise suppression method performed by the field programmable gate array master circuit module 30 in this embodiment.

[0052] Step S10: Signal Acquisition. The field-programmable gate array (FPGA) main control circuit module 30 controls the analog-to-digital converter (ADC) sampling circuit module 20 to continuously sample to acquire a frame of digital signal samples corresponding to the laser echo signal. In a specific setting of this embodiment, the sampling depth of each frame is 1024 points. Since the quantization bit of the ADC chip D1 is 8 bits, a frame of digital signal samples is a sequence of 1024 8-bit unsigned integers, denoted as {X1, X2, ..., X...}. 1024 The field-programmable gate array (FPGA) chip U1 has an internal dual-port random access memory (RAM) to buffer the frame data for subsequent processing.

[0053] Step S20: Calculate the noise baseline parameters, namely the median M and the mean absolute deviation (MADM). After a complete frame of 1024 sample points is acquired and stored in the internal memory of the field-programmable gate array (FPGA), the parameter calculation logic unit (corresponding to the parameter calculation module in the claims) inside the FPGA is activated. This unit first calculates the median M of the amplitude of these 1024 sample points. It is understood that the median, as a statistic that can resist the influence of extreme values ​​(i.e., strong impulse noise), can effectively characterize the overall baseline level of the signal. Calculating the median requires sorting the 1024 data points and selecting the value at the middle position. In the FPGA, this process can be implemented by an efficient parallel sorting algorithm, the specific implementation of which will be detailed in Example 4. After obtaining the median M, the unit then calculates the mean absolute deviation (MADM) of all sample points relative to the median M. The mean absolute deviation (MADM) is a parameter proposed in this application for robustly characterizing the noise dispersion in a signal, and its calculation formula is as follows:

[0054]

[0055] Where N is the total number of sampling points in a frame, in this example N = 1024; X i Let X be the amplitude at the i-th sampling point; M is the calculated median. The computational logic inside the field-programmable gate array (FPGA) can efficiently complete this calculation using a pipelined structure: for each sampling point X... i A subtractor calculates the difference between it and M, and an absolute value module obtains |X|. i -M|, then an accumulator accumulates all absolute deviation values, and finally a division operation is performed (which can be efficiently achieved in hardware by right shifting 10 bits, i.e., dividing by 1024) to obtain MADM.

[0056] Step S30: determining dynamic double thresholds TH and TL. Based on the median M and the mean of absolute deviation MADM calculated in the previous step, the threshold determination logic unit (corresponding to the threshold determination module in the claims) inside the FPGA calculates the dynamic high threshold TH and the dynamic low threshold TL for the noise determination of the current frame. The reason why these two thresholds are dynamic is that their values will be adaptively adjusted with the changes of M and MADM of each frame signal. In this embodiment, the high threshold TH and the low threshold TL are determined by the following linear formulas:

[0057] TH = M + K1 MADM

[0058] TL = M + K2 MADM

[0059] where K1 is the high threshold coefficient, K2 is the low threshold coefficient, and is the effective division interval, K1 must be greater than K2. The values of these two coefficients directly affect the strength of noise suppression and the fidelity of the signal. Experimental data show that when the value range of the high threshold coefficient K1 is preferably between 2.5 and 3.5, and the value range of the low threshold coefficient K2 is preferably between 1.2 and 1.8, the system can achieve a good balance between noise suppression and signal fidelity. In this embodiment, a set of fixed coefficient values can be set as an example: K1 = 3.0, K2 = 1.5. The hardware multiplier and adder inside the FPGA can quickly complete the calculation of these two thresholds.

[0060] Step S40: hierarchical noise suppression processing. After the dynamic double thresholds TH and TL are determined, the hierarchical processing logic unit (corresponding to the classification processing module in the claims) inside the FPGA starts to traverse the 1024 sample points in the memory, judges the amplitude of each sample point X i , and applies different processing according to the interval it belongs to. Referring to Figure 4 , this figure directly shows the principle of such hierarchical processing. The sample points in the signal waveform 100 are divided into different categories according to their amplitudes relative to the high threshold TH, the low threshold TL, and the median M. The specific processing logic is as follows:

[0061] 1. If the amplitude of the sample point X i is greater than the high threshold TH (X i > TH), the point is determined to be a strong noise point 101. For such points, the first noise suppression processing is performed. In this embodiment, the specific way of the first noise suppression processing is to replace the strong noise point X ithe amplitude of the same position in the previous frame of data stored in the FPGA. For this purpose, the FPGA needs to additionally open a storage area to save the results of the previous frame processing. This processing method is based on the assumption that the occurrence of noise is random, and the probability of strong noise occurring at the same position in two adjacent frames is extremely low. In the case of the initial frame of the processing system, since there is no previous frame data for reference, the amplitude of this point can be directly set to a preset background value, for example, 0.

[0062] 2. If the amplitude of the sampling point X i is between the low threshold TL and the high threshold TH (TL < X i ≤ TH), the point is determined to be a suspected noise point 102. Such points can be either weak noise or edges or high-intensity parts of the valid signal. In order to suppress potential noise while preserving signal details as much as possible, a second noise suppression processing with moderate intensity is applied. In this embodiment, the specific way of the second noise suppression processing is to perform three-point median filtering on the suspected noise point X i and its two adjacent sampling points X i-1 and X i+1 in time. That is, the amplitudes of the three points X i-1 , X i , and X i+1 are sorted, and the middle value is taken as the new amplitude of X i . It can be understood that, as a kind of nonlinear filtering, median filtering can effectively remove impulse noise, and the protection effect on signal edges is better than that of mean filtering.

[0063] 3. If the amplitude of the sampling point X i is less than or equal to the low threshold TL (X i ≤ TL), the point is determined to be located in the valid signal area. For such points, it is considered that they are valid signals or acceptable background noise, so no suppression processing is performed, that is, the original amplitude of the sampling point is preserved.

[0064] To make the working process clearer, the following example is given: assuming that in the processing of a certain frame signal, the field programmable gate array calculates the median M = 70 and the absolute deviation mean MADM = 36.67. According to the set coefficients K1 = 3.0 and K2 = 1.5, the high threshold TH ≈ 180 and the low threshold TL ≈ 125 are calculated. When the field programmable gate array processes a sample point with an amplitude of 200, since 200 > 180, the point is determined to be a strong noise point, and its amplitude will be replaced by the amplitude of the corresponding position in the previous frame. When processing a sample point with an amplitude of 150, since 125 < 150 ≤ 180, the point is determined to be a suspected noise point, and the field programmable gate array will read the values of the adjacent points before and after it, and use the median of the three points to update the value of the point. When processing a sample point with an amplitude of 75, since 75 ≤ 125, the point is determined to be a valid signal point, and its amplitude 75 will be completely retained.

[0065] As an optional implementation, after step S40, step S60, i.e. signal superposition, can also be performed. In order to further improve the signal-to-noise ratio, especially for weak echo signals at a long distance, the field programmable gate array can perform point-by-point accumulation on the digital signal samples of continuous multiple frames (for example, 16 frames or 32 frames) after the above hierarchical noise suppression processing. That is, the values of the first sample points of each frame are accumulated, the values of the second sample points are accumulated, and so on. The amplitude of the accumulated signal is higher, and the signal-to-noise ratio is also significantly improved.

[0066] Finally, in step S70, the final signal waveform after the noise suppression processing (and the optional signal superposition) is subjected to target calculation. This process is usually completed by the peak detection logic inside the field programmable gate array, and the time of flight of the laser pulse is determined by finding the peak position in the waveform, and then the distance of the target is calculated.

[0067] The embodiment realizes accurate and adaptive suppression of noise by introducing a dynamic double threshold based on the absolute deviation mean and a hierarchical processing strategy. Compared with the traditional fixed threshold or single threshold method, the present scheme can effectively filter out strong impulse noise while better protecting the shape of the valid echo signal, thereby significantly improving the detection success rate and accurate measurement rate of the laser ranging system.

[0068] Embodiment 2

[0069] The present embodiment is a variant implementation based on embodiment 1. The core idea, i.e. the framework of determining dynamic double thresholds based on the median M and the absolute deviation mean MADM and performing three-level classification processing, remains consistent with embodiment 1. The main difference of the present embodiment is that different specific implementation algorithms are provided for the first noise suppression processing and the second noise suppression processing in step S40. These variant schemes can provide different advantages in specific application scenarios or simplify hardware implementation.

[0070] In this embodiment, the hardware configuration, signal acquisition (step S10), parameter calculation (step S20), and double threshold determination (step S30) of the system are the same as those in Embodiment 1. The difference lies in the specific operation of the hierarchical noise suppression processing (step S40):

[0071] For the sampling point determined as a strong noise point (i.e., the amplitude is greater than the high threshold TH), the first noise suppression processing applied can be changed to directly replace the amplitude of the strong noise point with the median M calculated for the current frame. Compared with Embodiment 1, the advantage of this processing method is that it does not need to rely on the data of the previous frame, which means that the field programmable gate array does not need to allocate additional storage space to save the signal of the previous frame, thereby saving hardware resources. In addition, this method is completely based on the statistical characteristics of the current frame for processing and is not affected by historical data, so it is more robust to situations such as cold start of the system or sudden change of the scene (e.g., the laser radar suddenly turns from an open space to a near wall). The median M represents the overall level of the signal of the current frame, and replacing the extreme abnormal value with it is a reasonable and effective suppression means.

[0072] For the sampling point determined as a suspected noise point (i.e., the amplitude is between the low threshold TL and the high threshold TH), the second noise suppression processing applied can be changed to apply local weighted mean filtering to the suspected noise point.

[0073] Unlike the three-point median filtering in Embodiment 1, local weighted mean filtering is a linear filtering. For example, the following weighting formula can be used to calculate the new amplitude Y i of the sampling point X i :

[0074] Y i = w -1 X i-1 + w0X i + w1X i+1

[0075] where w -1 , w0, and w1 are weighting coefficients, and their sum is 1. To highlight the effect of the center point, the weight of the center point is usually greater than that of the adjacent points. A specific example is:

[0076] Y i = 0.2X i-1 + 0.6 X i + 0.2X i+1

[0077] Implementing such a weighted average operation in a field programmable gate array requires the use of hardware multipliers and adders. Compared with the sorting logic required for median filtering, the hardware implementation structure of weighted mean filtering is more direct. Under certain signal models, especially when the effective signal itself is relatively smooth, weighted mean filtering can produce smoother and less distorted results because it preserves the linear combination of the original signal components.

[0078] Following the working process example in Embodiment 1, when a sample point with an amplitude of 200 is determined to be strong noise, according to the rules of this embodiment, its new amplitude will be set to 70 (i.e. the median M of the current frame). When a sample point with an amplitude of 150 is determined to be suspected noise, assuming its previous point X i-1 has an amplitude of 140 and its next point X i+1 has an amplitude of 160, its new amplitude will be calculated by weighted average: Y i = 0.2 * 140 + 0.6 * 150 + 0.2 * 160 = 28 + 90 + 32 = 150.

[0079] This embodiment shows that without departing from the core inventive concept of the present application, the specific algorithms of the first and second noise suppression processes can be flexibly selected and replaced, thereby providing diversified implementation approaches for different application requirements and hardware resource limitations.

[0080] Embodiment 3

[0081] This embodiment improves the technical solution of Embodiment 1 and proposes a dynamic feedback adjustment mechanism for the high threshold coefficient K1. This mechanism aims to give the noise suppression system stronger adaptive ability, enabling it to automatically optimize the suppression strategy according to the severity of environmental noise, thereby maintaining optimal performance in various complex and dynamic scenarios.

[0082] In this embodiment, the hardware composition and basic processing flow (S10, S20, S30, S40, S60, S70) of the system are basically the same as those of Embodiment 1. The core difference lies in that in the flow shown in Figure 2 , a step S50, i.e. the step of dynamically adjusting the high threshold coefficient K1, is added.

[0083] The specific implementation of this step is as follows:

[0084] In the field programmable gate array main control circuit module 30, in addition to implementing each logic unit described in Embodiment 1, an additional strong noise point statistics and K1 adjustment unit is integrated. The working flow of this unit includes:

[0085] 1. Strong noise point statistics: After all 1024 sample points of a frame are processed in step S40 (hierarchical noise suppression processing), the counter inside FPGA counts the total number of sample points in the current frame that are determined as strong noise points because their amplitudes are greater than the high threshold TH, and the number is recorded as N_strong.

[0086] 2. Coefficient adjustment logic: After the statistics are completed, FPGA compares the value of N_strong with two preset quantity thresholds, i.e., the first quantity threshold (upper threshold) and the second quantity threshold (lower threshold). In the present embodiment, the first quantity threshold can be set as 50, and the second quantity threshold can be set as 10. FPGA adjusts the high threshold coefficient K1 used for the calculation of the high threshold TH of the next frame according to the comparison result:

[0087] If N_strong > 50, it indicates that a large number of strong impulse noises appear in the current frame signal, which means that the current working environment is noisy. At this time, the original high threshold TH can be too low. In order to more effectively suppress the extremely strong noises and avoid misjudging the high-amplitude valid signals, it is necessary to increase the high threshold TH. Accordingly, FPGA increases the currently stored K1 value by a fixed step (for example, 0.1). In order to prevent the K1 value from increasing unlimitedly, a preset upper limit value (for example, 3.5) is set, and the adjusted K1 value cannot exceed the upper limit.

[0088] If N_strong < 10, it indicates that the current frame signal is very clean, and strong impulse noises are rare. At this time, the original high threshold TH can be set too high, or it is too conservative to protect the weaker valid signals. In order to make the threshold more sensitive, FPGA decreases the currently stored K1 value by a fixed step (for example, 0.1). Similarly, in order to prevent the K1 value from being too low to cause damage to normal signals, a preset lower limit value (for example, 2.5) is set, and the adjusted K1 value cannot be lower than the lower limit.

[0089] If 10 ≤ N_strong ≤ 50, it indicates that the current noise level is in a normal and acceptable range, and the current K1 value is considered to be appropriate, so the K1 value is kept unchanged.

[0090] 3. Coefficient update: The adjusted K1 value will be written into a special register inside FPGA and used for the calculation of the high threshold TH of the next frame signal. The low threshold coefficient K2 can be kept fixed in the present embodiment, for example, 1.5.

[0091] Working process example: suppose the initial value of K1 is 3.0 when the system starts. When the system works in a noisy environment, if the number of strong noise points N_strong in each frame detected by the field programmable gate array exceeds 50 for several consecutive frames, the value of K1 will gradually increase from 3.0 to 3.1, 3.2, and so on, until N_strong falls below 50 or K1 reaches the upper limit of 3.5. The increase of K1 causes the high threshold TH to increase accordingly, so that it can more accurately capture and suppress extremely strong noise. Subsequently, if the system (for example, an unmanned vehicle equipped with a laser radar) enters a clean signal tunnel, N_strong will drop sharply to below 10. At this time, K1 will gradually decrease from the current value (for example, 3.2) to 2.5. The decrease of K1 causes the high threshold TH to decrease, making the system more sensitive to moderate intensity noise, while also better protecting possible valid signals with low amplitude.

[0092] By introducing such a feedback adjustment mechanism based on the number of strong noise points, the noise suppression system in this embodiment has self-adaptive adjustment capability. Instead of relying on a fixed set of parameters, it can continuously evaluate the environmental noise level and dynamically optimize itself, thereby achieving robust and efficient noise suppression performance in various unknown and changing scenarios.

[0093] Embodiment 4

[0094] This embodiment focuses on efficiently implementing the noise suppression method proposed in this application in the field programmable gate array, and in particular proposes an optimized implementation scheme based on the parallel computing advantage of the field programmable gate array for the most computationally intensive step S20 (calculating the median M). The scheme aims to ensure high real-time performance of the entire processing flow, so that it can match data acquisition rates as high as 100 megahertz or even higher to meet the stringent requirements of laser ranging and other applications for low latency.

[0095] In conventional software implementation, sorting 1024 data points to obtain the median usually requires a large number of instructions and takes a long time, making it difficult to complete within a sampling interval as short as 10 nanoseconds (corresponding to a 100 megahertz sampling rate). However, the parallel hardware architecture of the field programmable gate array provides a solution to this problem.

[0096] In this embodiment, the logic design inside the field programmable gate array master circuit module 30 (with the field programmable gate array chip U1 as the core) fully utilizes its parallel processing capability. The specific implementation is as follows:

[0097] 1. Data parallelization for storage and access: When a frame of 1024 8-bit sample data is sent into the FPGA chip U1 through the parallel data bus D0-D7, they are written into a 1024x8-bit dual-port random access memory. Such a memory allows simultaneous read and write operations in one clock cycle, providing the data basis for parallel processing.

[0098] 2. Parallel optimization of median calculation - odd-even parallel sorting network: To find the median of 1024 data in a very short time, this embodiment does not use the traditional serial sorting algorithm (such as quicksort), but implements a highly efficient hardware sorting structure in the FPGA, such as a parallel sorter based on an odd-even sorting network. The specific process is as follows:

[0099] Data separation: The control logic of the FPGA first reads out the 1024 data stored in the random access memory into two independent 512-point data streams in parallel according to the parity of their storage addresses, one for the odd address sequence and the other for the even address sequence.

[0100] Parallel sorting: Inside the FPGA, two identical and parallel 512-point sorting network modules are instantiated through hardware description languages (such as Verilog or VHDL). The sorting network is a fixed hardware structure composed of basic compare-swap units, which can sort the input data in a fixed number of clock cycles. The two sorting network modules simultaneously sort the odd and even sequences from small to large. Due to parallel execution, the sorting time depends on the depth of the single 512-point sorting network.

[0101] Merge and take median: When the two 512-point sub-sequences are sorted, the median of the entire 1024-point sequence (i.e. the average of the 512th and 513th values after sorting) can be determined in an efficient way. One precise method is to use a small merging network to merge the middle part of the two ordered sub-sequences to find the 512th and 513th elements globally. As an optional simplified implementation, an approximate method can be used: directly take the average of the 256th value of the sorted odd sequence (i.e. the median of the odd sequence) and the 257th value of the sorted even sequence (approximately the median of the even sequence) as the estimate of the entire sequence median M. This average operation is implemented in hardware as an adder and a right shift by one bit (>>1) operation, requiring very few clock cycles.

[0102] 3. Pipeline processing architecture: Each step (S20, S30, S40) of the entire noise suppression algorithm is designed as a deep pipeline structure in the field programmable gate array. Among them, the calculation of the median M and the absolute deviation mean MADM constitutes the first few levels of the pipeline, the calculation of the double threshold TH and TL constitutes the middle level, and the traversal judgment and processing of each sampling point constitute the back level of the pipeline. Data flows between levels, and each level completes its specific calculation task in one clock cycle. Once the pipeline is filled, the field programmable gate array can output a processed sampling point in each clock cycle (or a fixed number of clock cycles).

[0103] Through the above parallelization and pipelining design, the entire noise suppression algorithm containing complex calculations is solidified into high-speed hardware logic. Its processing speed can completely match the data acquisition speed, ensuring that the processed results can be output within a very short time (usually in the order of microseconds) after a frame of data is collected, realizing high real-time processing. This fully utilizes the advantages of field programmable gate arrays in signal processing applications, ensuring that the laser ranging system can output accurate distance information without delay, which is crucial for high-speed motion target tracking and other application scenarios.

[0104] In summary, compared with the prior art, the present application has the following beneficial effects:

[0105] 1. Accurate noise suppression and high signal fidelity. The absolute deviation mean, which can stably represent the dispersion degree of noise, is calculated, and the dynamic double threshold is set in combination with the median, which can more accurately reflect the real-time noise level of the signal. Further, a three-level classification processing strategy is adopted to apply different intensities of processing to strong noise, suspected noise and effective signal, realizing accurate suppression of impulse noise while maximizing the integrity of the effective signal, significantly improving the signal-to-noise ratio and signal fidelity compared with the prior art.

[0106] 2. Strong adaptability. The double threshold in the present application can dynamically change with the statistical characteristics of each frame of signal, and by introducing a feedback adjustment mechanism, the high threshold coefficient can be adaptively adjusted according to the noise density, so that the method can automatically adapt to various complex environments from low noise to strong impulse noise, ensuring the stability and robustness of the system in different working scenarios.

[0107] 3. Efficient hardware implementation and low cost. The method proposed in the present application has clear logic and calculation process suitable for parallel processing, and can be implemented based on an FPGA and an ADC chip, with a simple hardware structure. Using the parallel processing characteristics of the FPGA, the algorithm flow can be solidified into hardware logic, realizing high-speed real-time processing synchronized with data acquisition, meeting the stringent real-time requirements of laser ranging and other applications, while effectively reducing the hardware cost and power consumption of the system.

[0108] It can be understood that the same or similar parts in the above-mentioned embodiments can be mutually referred to, and the content not described in detail in some embodiments can refer to the same or similar content in other embodiments.

[0109] It should be noted that, in the description of the present application, the terms "first", "second", etc. are only for the purpose of description, and cannot be understood as indicating or implying relative importance. In addition, in the description of the present application, unless otherwise specified, the meaning of "a plurality of" is at least two.

[0110] It should be understood that parts of the present application can be realized by hardware, software, firmware or their combination. In the above-mentioned embodiments, a plurality of steps or methods can be realized by software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if realized by hardware, and as in another embodiment, it can be realized by any one or their combination of the following technologies known in the art: discrete logic circuit with logic gate circuit for implementing logic function on data signal, application specific integrated circuit with suitable combination logic gate circuit, programmable gate array (PGA), field programmable gate array (FPGA) and the like.

[0111] Those skilled in the art of the present technology can understand that all or part of the steps carried out by the above-mentioned embodiments can be instructed by a program related to hardware, which can be stored in a computer readable storage medium, and the program includes one or a combination of steps of the method embodiments when executed.

[0112] In addition, each functional unit in each embodiment of the present application can be integrated in one processing module, or each unit can be physically present separately, or two or more units can be integrated in one module. The above-mentioned integrated module can be realized in the form of hardware or in the form of software functional module. The integrated module, if realized in the form of software functional module and sold or used as an independent product, can also be stored in a computer readable storage medium. The above-mentioned storage medium can be read only memory, disk or optical disk, etc.

[0113] In the description of the present specification, the description of the terms "one embodiment", "some embodiments", "example", "specific example" or "some examples" means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In the present specification, the illustrative description of the above-mentioned terms does not necessarily mean the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.

[0114] Although the embodiments of the present application have been shown and described above, it is understood that the above-described embodiments are exemplary and are not to be construed as limiting the present application, and that changes, modifications, substitutions and variations can be made by those skilled in the art without departing from the scope of the present application.

Claims

1. A dynamic dual threshold based laser return pulse noise suppression method, characterized in that, The method comprises the following steps: obtaining a frame of digital signal samples corresponding to a laser echo signal; based on the digital signal samples, calculating a median value M of the digital signal samples, and calculating an absolute deviation mean value MADM of the digital signal samples relative to the median value M; based on the median value M and the absolute deviation mean value MADM, determining a dynamic high threshold value TH and a dynamic low threshold value TL; traversing each sampling point in the digital signal samples, and performing classification processing according to the relationship between the amplitude of the sampling point and the dynamic high threshold value TH and the dynamic low threshold value TL, the classification processing comprising: if the amplitude of the sampling point is greater than the high threshold value TH, applying first noise suppression processing to the sampling point; if the amplitude of the sampling point is between the low threshold value TL and the high threshold value TH, applying second noise suppression processing to the sampling point, wherein the second noise suppression processing is different from the first noise suppression processing; if the amplitude of the sampling point is less than or equal to the low threshold value TL, retaining the original amplitude of the sampling point.

2. The method of claim 1, wherein, The dynamic high threshold value TH and the dynamic low threshold value TL are determined by the following formulas: TH = M + K1*MADM; TL = M + K2*MADM; wherein K1 is a high threshold coefficient, K2 is a low threshold coefficient, and K1 > K2.

3. The method of claim 2, wherein, The value range of the high threshold coefficient K1 is 2.5-3.5, and the value range of the low threshold coefficient K2 is 1.2-1.

8.

4. The method of claim 2, wherein, The method further comprises: after a frame of signal processing is completed, counting the number of sampling points determined to have an amplitude greater than the high threshold value TH; if the number is greater than a preset first number threshold, increasing the value of the high threshold coefficient K1, but the value does not exceed a preset upper limit value; if the number is less than a preset second number threshold, decreasing the value of the high threshold coefficient K1, but the value does not fall below a preset lower limit value.

5. The method according to claim 1, wherein the first noise suppression processing comprises replacing the amplitude of the sampling point with the amplitude of a sampling point at the same position in a previous frame of data, or with the median value M calculated for the current frame; the second noise suppression processing comprises performing median filtering or local weighted mean filtering on the sampling point and its adjacent sampling points in time, and taking the filtering result as the new amplitude of the point.

6. The method of claim 1, wherein, The method further comprises: point-by-point accumulation of a frame or multiple frames of digital signal samples after the classification processing.

7. A dynamic dual threshold based laser return pulse noise suppression embedded system, characterized in that, comprises: a sample acquisition module configured to obtain a frame of digital signal samples corresponding to a laser echo signal; a parameter calculation module configured to calculate a median value M of the digital signal samples based on the digital signal samples, and calculate an absolute deviation mean value MADM of the digital signal samples relative to the median value M; a threshold determination module configured to determine a dynamic high threshold value TH and a dynamic low threshold value TL based on the median value M and the absolute deviation mean value MADM; a classification processing module configured to traverse each sampling point in the digital signal samples, and perform classification processing according to the relationship between the amplitude of the sampling point and the dynamic high threshold value TH and the dynamic low threshold value TL, wherein: When the amplitude of the sampling point is greater than the high threshold TH, the classification processing module applies a first noise suppression processing to the sampling point; When the amplitude of the sampling point is between the low threshold TL and the high threshold TH, the classification processing module applies a second noise suppression processing to the sampling point, wherein the second noise suppression processing is different from the first noise suppression processing; When the amplitude of the sampling point is less than or equal to the low threshold TL, the classification processing module retains the original amplitude of the sampling point.

8. The embedded system of claim 7, wherein the sample acquisition module comprises an ADC sampling circuit module; and the parameter calculation module, the threshold determination module, and the classification processing module are implemented by an FPGA master circuit module.

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