Storage module detection circuit, method, apparatus, and medium

Abstract

The application discloses a kind of storage module detection circuit, method, device and medium, it is related to storage module detection technical field.The circuit includes: data communication module;Data analysis and verification module are electrically connected with data communication module;Interface control module is electrically connected with data communication module and data analysis and verification module respectively;Data communication module is used to receive the data packet sent by host, and the data packet meeting protocol is sent to data analysis and verification module;Data analysis and verification module are used to analyze data packet, obtain analysis result;Interface control module is used to carry out read operation or write operation to storage module according to analysis result, receive the response result of storage module;Data analysis and verification module are used to check response result, obtain verification result, and send verification result to data communication module;Data communication module is also used to send verification result to host.The circuit can realize detection and result feedback to storage module by simple command.

Description

Technical Field

[0001] This invention relates to the field of computer manufacturing technology, and in particular to a storage module detection circuit, method, apparatus and medium. Background Technology

[0002] During operation, storage modules may experience data corruption or bit errors. To ensure system data integrity and stable operation, a detection module is needed to inspect the storage modules and determine if there are anomalies such as data bit flipping or read interference. Currently, when inspecting storage modules, the detection module needs to perform complex control on the storage modules according to the timing requirements and complex instructions, which is a rather cumbersome process. Summary of the Invention

[0003] This invention aims to at least solve one of the technical problems existing in the prior art. To this end, this invention proposes a storage module detection circuit, method, apparatus, and medium, which can simplify the detection process of storage modules.

[0004] In a first aspect, a storage module detection circuit according to an embodiment of the present invention includes:

[0005] Data communication module;

[0006] The data parsing and verification module is electrically connected to the data communication module.

[0007] The interface control module is electrically connected to both the data communication module and the data parsing and verification module.

[0008] The data communication module is used to receive data packets sent by the host and send the data packets conforming to the protocol to the data parsing and verification module; the data parsing and verification module is used to parse the data packets and obtain the parsing result; the interface control module is used to perform read or write operations on the storage module according to the parsing result and receive the response result from the storage module; the data parsing and verification module is also used to verify the response result, obtain the verification result, and send the verification result to the data communication module; the data communication module is also used to send the verification result to the host.

[0009] According to some embodiments of the present invention, the data communication module includes:

[0010] A receiving response unit is used to respond to the trigger command of the host, receive the data packet, parse the frame header in the data packet, send the storage unit selection information contained in the frame header to the interface control module, and convert the serial data in the data packet into parallel data and send it to the data parsing and verification module.

[0011] The result caching unit is electrically connected to the receiving response unit, and the result caching unit is used to cache the verification result; the receiving response unit is also used to send the verification result cached by the result caching unit to the host.

[0012] According to some embodiments of the present invention, the data parsing and verification module includes:

[0013] The data generation unit is used to parse the data packet, obtain the parsing result, and send the parsing result to the interface control module;

[0014] A data verification unit is used to verify the response result, obtain the verification result, and send the verification result to the data communication module.

[0015] A counter is electrically connected to both the data generation unit and the data verification unit, and the counter is used to control the working state of the data generation unit and the data verification unit.

[0016] According to some embodiments of the present invention, the data generation unit includes a sending module and a multi-channel parallel data selection module. Each data selection module includes a first inverter and a first selector. The input terminal of the first inverter is connected to the input data of the data packet. The output terminal of the first inverter is electrically connected to the first input terminal of the first selector. The second input terminal of the first selector is connected to the input data of the data packet. The output terminal of the first selector is electrically connected to the input terminal of the sending module. The output terminal of the sending module is electrically connected to the interface control module. The controlled terminal of the first selector is also electrically connected to the counter.

[0017] According to some embodiments of the present invention, the data verification unit includes:

[0018] A data caching unit is used to receive the response result;

[0019] A cache register, electrically connected to the data cache unit, is used to cache the response result;

[0020] The second inverter, electrically connected to the buffer register, is used to invert the response result;

[0021] The second selector is electrically connected to the counter, the cache register, and the second inverter, respectively, and is used to select between the response result and the inverted response result according to the instruction of the counter;

[0022] The comparison module is used to compare the output data of the second selector with the output data of the first selector and send the comparison result to the data communication module.

[0023] According to some embodiments of the present invention, the interface control module includes:

[0024] The third selector is used to obtain storage unit selection information in the data packet, generate a chip select signal according to the storage unit selection information, and send the chip select signal to the storage module.

[0025] An interface timing control unit is used to perform read or write operations on the storage module based on the parsing result.

[0026] The data receiving unit is used to acquire the response result and send the response result to the data parsing and verification module.

[0027] Secondly, according to an embodiment of the present invention, a storage module detection method is applied to the storage module detection circuit described in the first aspect embodiment, the method comprising:

[0028] The data communication module receives data packets sent by the host and sends data packets that conform to the protocol to the data parsing and verification module.

[0029] The data packet is parsed by the data parsing and verification module to obtain the parsing result;

[0030] The interface control module performs read or write operations on the storage module based on the parsing results and receives the response results from the storage module.

[0031] The response result is verified by the data parsing and verification module to obtain the verification result, and the verification result is sent to the data communication module.

[0032] The verification result is sent to the host via the data communication module.

[0033] According to some embodiments of the present invention, the step of receiving data packets sent by the host through the data communication module and sending the data packets conforming to the protocol to the data parsing and verification module includes:

[0034] In response to the trigger command from the host, the data communication module is instructed to receive and parse the frame header of the data packet;

[0035] When the data packet conforms to the protocol, the storage unit selection information contained in the frame header is sent to the interface control module through the data communication module, and the serial data in the data packet is converted into parallel data and sent to the data parsing and verification module.

[0036] Thirdly, according to an embodiment of the present invention, a storage module detection device includes a storage module detection circuit as described in the first aspect embodiment.

[0037] Fourthly, according to an embodiment of the present invention, the storage medium stores computer-executable instructions for causing a computer to execute the storage module detection method described in the second aspect embodiment.

[0038] The storage module detection circuit, method, apparatus, and medium according to embodiments of the present invention have at least the following beneficial effects: They can receive data packets sent by the host through a data communication module, determine whether the data packets conform to the protocol, parse the data packets through a data parsing and verification module, and then perform read and write operations on the storage module through an interface control module based on the parsing result. The data parsing and verification module also verifies the response result of the storage module, thereby realizing the detection of the storage module and outputting the verification result and error count result to the host. This circuit can realize the detection of the storage module and result feedback through simple commands, and has error count output, possessing a certain degree of versatility.

[0039] Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0040] The above and / or additional aspects and advantages of the present invention will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which:

[0041] Figure 1 This is a schematic diagram of the storage module detection circuit according to an embodiment of the present invention;

[0042] Figure 2 This is a schematic diagram of the working process of the storage module detection circuit according to an embodiment of the present invention;

[0043] Figure 3 This is a schematic diagram of the communication timing between the data communication module and the host in an embodiment of the present invention;

[0044] Figure 4 This is a circuit schematic diagram of the data generation unit according to an embodiment of the present invention;

[0045] Figure 5 This is a circuit schematic diagram of the data verification unit according to an embodiment of the present invention;

[0046] Figure 6 This is a schematic diagram illustrating the working process of the interface control module in an embodiment of the present invention.

[0047] Figure 7 This is a flowchart illustrating the steps of the storage module detection method according to an embodiment of the present invention. Detailed Implementation

[0048] The embodiments of the present invention are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application. The step numbers in the following embodiments are set only for ease of explanation, and there is no limitation on the order between the steps. The execution order of each step in the embodiments can be adaptively adjusted according to the understanding of those skilled in the art.

[0049] In the description of this invention, it should be understood that the orientation descriptions, such as up, down, front, back, left, right, etc., are based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limiting this invention.

[0050] The terms "first," "second," "third," and "fourth," etc., used in the specification, claims, and accompanying drawings of this invention are used to distinguish different objects, not to describe a specific order. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or apparatuses.

[0051] In this invention, the reference to "embodiment" means that a specific feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of the invention. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a mutually exclusive, independent, or alternative embodiment. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0052] During operation, storage modules may experience data corruption or bit errors. To ensure system data integrity and stable operation, a detection module is needed to inspect the storage modules and determine if there are anomalies such as data bit flipping or read interference. Currently, when inspecting storage modules, the detection module needs to perform complex control on the storage modules according to the timing requirements and complex instructions, which is a rather cumbersome process.

[0053] To address this, embodiments of the present invention provide a storage module detection circuit, method, apparatus, and medium. This system receives data packets sent by a host via a data communication module, determines whether the data packets conform to a protocol, parses the data packets via a data parsing and verification module, and then performs read / write operations on the storage module via an interface control module based on the parsing results. The data parsing and verification module also verifies the response results of the storage module, thereby achieving storage module detection and outputting verification results and error counts to the host. This circuit can achieve storage module detection and result feedback through simple commands, and includes error count output, demonstrating a degree of versatility.

[0054] The storage module detection circuit, method, apparatus, and medium of embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0055] On one hand, embodiments of the present invention propose a storage module detection circuit, such as... Figure 1 As shown, the circuit includes:

[0056] Data communication module 100;

[0057] The data parsing and verification module 200 is electrically connected to the data communication module 100;

[0058] The interface control module 300 is electrically connected to the data communication module 100 and the data parsing and verification module 200, respectively.

[0059] The data communication module 100 receives data packets sent by the host and sends data packets conforming to the protocol to the data parsing and verification module 200. The data parsing and verification module 200 parses the data packets to obtain the parsing results. The interface control module 300 performs read or write operations on the storage module based on the parsing results and receives the response results from the storage module. The data parsing and verification module 200 also verifies the response results, obtains the verification results, and sends the verification results to the data communication module 100. The data communication module 100 also sends the verification results to the host.

[0060] Specifically, in this application, it can be implemented using FPGA (Field Programmable Gate Array) or similar methods. Figure 1The storage module detection circuit is shown. The data communication module 100 is responsible for communicating with the host. The data communication module 100 can connect to the host via common wired or wireless communication methods. In this example, the data communication module 100 receives data sent by the host through a single-wire full-duplex interface. It should be noted that the FPGA has an internal state machine. Initially, the state machine is in an idle state. When the host sends a control command to the data communication module 100, the data communication module 100 detects the falling edge start bit and enters the data receiving state, thus receiving the data packets sent by the host. The data communication module 100 determines whether the data packet conforms to a preset protocol. If it does, it sends the data packet to the data parsing and verification module 200. After parsing the data packet, the data parsing and verification module enters a write operation state or a read operation state, generating data and addresses, and sending them to the interface control module 300. The interface control module 300 then controls the reading and writing of the storage module. Subsequently, the data parsing and verification module 200 receives the data returned by the storage module through the interface control module 300, completes the verification, and outputs the result to the data communication module 100. The data communication module 100 then returns the verification result to the host and determines whether the read or write operation has ended based on the generated address. When the operation ends, the state machine transitions to the idle state. A schematic diagram of the working state transition of the storage module detection circuit is shown below. Figure 2 As shown.

[0061] Furthermore, such as Figure 1As shown, in some embodiments of this application, the data communication module 100 includes a receiving response unit 110 and a result caching unit 120. The receiving response unit 110 is used to receive data packets in response to a trigger command from the host, parse the frame header in the data packets, send the storage unit selection information contained in the frame header to the interface control module 300, and convert the serial data in the data packets into parallel data and send it to the data parsing and verification module 200. The result caching unit 120 is electrically connected to the receiving response unit 110. The result caching unit 120 is used to cache the verification results. The receiving response unit 110 is also used to send the verification results cached by the result caching unit 120 to the host. Specifically, in the initial state, the state machine is in an idle state. When the host sends a control command to the receiving response unit 110, and the receiving response unit 110 detects the falling edge start bit, the state machine switches to the frame header receiving state and begins to receive and judge the frame header bit by bit. When a frame header conforming to the protocol is received, the storage unit selection information contained in the frame header is parsed and forwarded to the interface control module 300. The module continues to receive commands and data sent by the host according to the UART protocol, converts the serial data into 8-bit parallel data, and forwards it to the data parsing and verification circuit. After the data parsing and verification circuit obtains the verification result, it sends it to the result buffer unit 120 for buffering. The receiving response unit 110 then retrieves the verification result from the result buffer unit 120 and sends it to the host.

[0062] Furthermore, such as Figure 1 As shown, in some embodiments of this application, the data parsing and verification module 200 includes: a data generation unit 210, a data verification unit 230, and a counter 220. The data generation unit 210 is used to parse data packets, obtain parsing results, and send the parsing results to the interface control module 300. The data verification unit 230 is used to verify the response results of the storage module, obtain verification results, and send the verification results to the data communication module 100. The counter 220 is electrically connected to the data generation unit 210 and the data verification unit 230, respectively, and the counter 220 is used to control the working state of the data generation unit 210 and the data verification unit 230. Specifically, when the data communication module 100 sends commands and data, the data generation unit 210 parses the command, address, and write data, and sends them to the interface control module 300, enabling the interface control module 300 to perform write operations on the storage module. When the host sends a read command, the interface control module 300 performs a read operation on the storage module and sends the read data to the data verification unit 230, which performs verification, obtains the verification result, and sends the result back to the data communication module 100. It should be noted that when the host communicates with the data communication module 100, it must follow a predetermined single-wire communication protocol. The communication protocol timing diagram is shown below. Figure 3As shown, the data sent by the host is composed of a data frame in the order of start bit, frame header, control command, write data, and end bit. The frame header contains the chip select information of the memory unit. When the control command is a read operation, no write data content needs to be sent. The response data returned by the memory module detection circuit is composed of a data frame in the order of start bit, block address, number of error bits, and end bit. The host can further decode the data frame according to actual needs.

[0063] Furthermore, such as Figure 4 As shown, in some embodiments of this application, the data generation unit 210 includes a sending module 212 and a multi-channel parallel data selection module 211. Each data selection module 211 includes a first inverter and a first selector. The input of the first inverter is connected to the input data of the data packet, the output of the first inverter is electrically connected to the first input of the first selector, the second input of the first selector is connected to the input data of the data packet, the output of the first selector is electrically connected to the input of the sending module 212, the output of the sending module 212 is electrically connected to the interface control module 300, and the controlled end of the first selector is also electrically connected to the counter 220. Specifically, the data generation unit 210 implements data generation as follows: Figure 4 As shown, when the host sends a write command, the original data contained in the data packet is converted into 8-bit parallel data. Each bit is input to the corresponding first inverter for inversion, resulting in data that is completely opposite to the original data. The original data and the inverted data are simultaneously input to the first selector. The least significant bit of counter 220 is connected to the controlled terminal of the first selector. When the least significant bit is high, the first selector outputs the original data; when the least significant bit is low, it outputs the inverted data. This ensures that counter 220 outputs the original data when it is even and the inverted data when it is odd, guaranteeing that the generated data is continuously inverted. Thus, the data generation unit 210 can generate continuously inverted write data for testing the storage module.

[0064] Furthermore, such as Figure 4 As shown, in some embodiments of this application, the data verification unit includes:

[0065] Data buffer unit 231 is used to receive response results;

[0066] The buffer register 232 is electrically connected to the data buffer unit 231 and is used to buffer the response result;

[0067] The second inverter 233 is electrically connected to the buffer register 232 and is used to invert the response result;

[0068] The second selector 234 is electrically connected to the counter 220, the buffer register 232, and the second inverter 233, respectively, and is used to select the response result and the inverted response result according to the instruction of the counter 220.

[0069] The comparison module 235 is used to compare the output data of the second selector 234 with the output data of the first selector and send the comparison result to the data communication module 100.

[0070] Specifically, after the host sends a read command, the interface control module 300 retrieves the read data from the storage module and sends it to the data cache unit 231. The data cache unit 231 then sends the read data to the cache register 232. Next, the second inverter 233 inverts the read data, and the second selector 234 determines whether to output the original read data or the inverted read data according to the instruction from the counter 220. Finally, the comparison module 235 compares the data written to the storage module with the read data to verify the data and sends the verification result to the data communication module 100. The verification result includes the number of error bits. It should be noted that when the value of the counter 220 is all 0, the cache register 232 is enabled, and the read data is retrieved from the cache register 232.

[0071] Furthermore, such as Figure 1 As shown, in some embodiments of this application, the interface control module 300 includes:

[0072] The third selector 310 is used to obtain the storage unit selection information in the data packet, generate a chip select signal according to the storage unit selection information, and send the chip select signal to the storage module.

[0073] The interface timing control unit 320 is used to perform read or write operations on the storage module based on the parsing results.

[0074] The data receiving unit 330 is used to obtain the response result and send the response result to the data parsing and verification module 200.

[0075] Specifically, when the data communication module 100 receives a data packet and parses the frame header in the data packet, it sends the storage unit selection information contained in the frame header to the third selector 310, enabling the third selector 310 to send a chip select signal to the storage module, allowing the storage module to determine the storage unit to be operated on. Simultaneously, the data communication module 100 converts the serial data in the data packet into parallel data and sends it to the data parsing and verification module 200 to parse out the command, address, and write data, and sends this data to the interface timing control unit 320, enabling the interface timing control unit 320 to perform a write operation on the storage module. When the host sends a read command, the interface timing control unit 320 performs a read operation on the storage module and sends the read data to the data receiving unit 330. The data receiving unit 330 then sends the read data to the data verification unit 230 for verification, obtains the verification result, and sends the verification result back to the data communication module 100.

[0076] It should be noted that the interface control module 300 is connected to the storage module through a storage interface, and the interface control module 300 implements the interface timing control state flow, such as... Figure 6 As shown, through 4-line and 16-line decoding logic, the system receives storage unit selection information and busy signal sent by the data communication module 100 according to the host's command. When the address transmitted by the data parsing and verification module 200 is valid, the state machine jumps from the idle state to the command sending state. The interface control module 300 sends instructions to the storage module through the storage interface. After completing the instruction sending, it enters the address sending state and sends the valid address to the storage module. After completing the address sending, it enters the read or write data state. In the write data state, the interface control module 300 receives valid data from the data parsing and verification module 200 and sends it. After sending a block of data, it waits for the busy signal to end before jumping out of this state. After entering the read data state, it waits for the busy signal to end before receiving the data read from the storage module through the interface control module 300 and storing it in the data cache. After the read and write states are completed, if the address is not the last block address of a single storage unit, it re-enters the write command state; otherwise, it enters the idle state to wait for the next trigger.

[0077] The storage module detection circuit according to the embodiments of this application can receive and respond to host commands, realize the detection of abnormal data conditions in the storage module, realize the reading and writing of data in the storage module, and simultaneously avoid insufficient data port inversion during the test by writing data with data reversal interval. The circuit provides a data communication module 100, which receives data sent by the host through a single-wire full-duplex interface. Its internal state machine first determines the falling edge start bit and enters the frame header receiving state from the idle state. After receiving the correct frame header, it forwards the host command to the data parsing and verification module 200. Based on the data written to the buffer by the data parsing and verification module 200, it returns response data to the host in a serial transmission manner until the buffer is empty. The circuit also provides a data parsing and verification module 200, which enters a write or read operation through the host command forwarded by the data communication module 100. In the write operation, it receives 8 bits of data written to the storage module through the data communication module 100 and uses a counter to monitor the storage module. The circuit generates write addresses and continuous write data. During read operations, a counter controls the generation of read addresses for the storage module and buffers read data received from the storage module interface control circuit. The low-order bits of the counter control the generation of comparison data to verify the received data and output the verification result. Based on host commands, the corresponding return data is written to the buffer. The circuit also provides an interface control module 300, which uses a state machine to control the address and data generated by the data parsing and verification module 200 to be sent according to the storage module's interface protocol. It receives read data according to the storage module's interface protocol and receives the chip select signal and busy signal from the data communication module 100 through a 4-line / 16-line decoding logic. This circuit can detect and provide feedback on the storage module through simple commands and includes an error count output, demonstrating a degree of versatility.

[0078] On the other hand, based on the aforementioned storage module detection circuit, this application also provides a storage module detection method, such as... Figure 7 As shown, the method includes, but is not limited to, steps S100-S500:

[0079] Step S100: Receive data packets sent by the host through the data communication module 100, and send data packets that conform to the protocol to the data parsing and verification module 200;

[0080] Step S200: The data packet is parsed by the data parsing and verification module 200 to obtain the parsing result;

[0081] Step S300: The interface control module 300 performs read or write operations on the storage module according to the parsing result, and receives the response result from the storage module;

[0082] Step S400: The response result is verified by the data parsing and verification module 200 to obtain the verification result, and the verification result is sent to the data communication module 100.

[0083] Step S500: Send the verification result to the host via the data communication module 100.

[0084] Specifically, the data communication module 100 is responsible for communicating with the host. The data communication module 100 can connect to the host via common wired or wireless communication methods. In this example, the data communication module 100 receives data sent by the host through a single-wire full-duplex interface. It should be noted that the FPGA has an internal state machine. Initially, the state machine is in an idle state. When the host sends a control command to the data communication module 100, the data communication module 100 detects the falling edge start bit and enters the data receiving state, thus receiving the data packets sent by the host. The data communication module 100 determines whether the data packet conforms to a preset protocol. If it does, it sends the data packet to the data parsing and verification module 200. After parsing the data packet, the data parsing and verification module enters a write operation state or a read operation state, generating data and addresses, and sending them to the interface control module 300. The interface control module 300 then controls the reading and writing of the storage module. Subsequently, the data parsing and verification module 200 receives the data returned by the storage module through the interface control module 300, completes the verification, and outputs the result to the data communication module 100. The data communication module 100 then returns the verification result to the host and determines whether the read or write operation has ended based on the generated address. When the operation ends, the state machine transitions to the idle state. A schematic diagram of the working state transition of the storage module detection circuit is shown below. Figure 2 As shown.

[0085] Furthermore, such as Figure 1 As shown, in some embodiments of this application, the data communication module 100 includes a receiving response unit 110 and a result caching unit 120. The receiving response unit 110 is used to receive data packets in response to a trigger command from the host, parse the frame header in the data packets, send the storage unit selection information contained in the frame header to the interface control module 300, and convert the serial data in the data packets into parallel data, sending it to the data parsing and verification module 200. The result caching unit 120 is electrically connected to the receiving response unit 110. The result caching unit 120 is used to cache the verification results, and the receiving response unit 110 is also used to send the verification results cached by the result caching unit 120 to the host. That is, the above step S100 specifically includes the following two steps:

[0086] In response to the host's trigger command, the data communication module 100 receives and parses the frame header of the data packet;

[0087] When the data packet conforms to the protocol, the storage unit selection information contained in the frame header is sent to the interface control module 300 through the data communication module 100, and the serial data in the data packet is converted into parallel data and sent to the data parsing and verification module 200.

[0088] Specifically, in the initial state, the state machine is in an idle state. When the host sends a control command to the receiving response unit 110, and the receiving response unit 110 detects the falling edge start bit, the state machine switches to the frame header receiving state and begins to receive and judge the frame header bit by bit. When a frame header conforming to the protocol is received, the storage unit selection information contained in the frame header is parsed and forwarded to the interface control module 300. The module continues to receive commands and data sent by the host according to the UART protocol, converts the serial data into 8-bit parallel data, and forwards it to the data parsing and verification circuit. After the data parsing and verification circuit obtains the verification result, it sends it to the result buffer unit 120 for buffering. The receiving response unit 110 then retrieves the verification result from the result buffer unit 120 and sends it to the host.

[0089] Furthermore, such as Figure 1 As shown, in some embodiments of this application, the data parsing and verification module 200 includes: a data generation unit 210, a data verification unit 230, and a counter 220. The data generation unit 210 is used to parse data packets, obtain parsing results, and send the parsing results to the interface control module 300. The data verification unit 230 is used to verify the response results of the storage module, obtain verification results, and send the verification results to the data communication module 100. The counter 220 is electrically connected to the data generation unit 210 and the data verification unit 230, respectively, and the counter 220 is used to control the working state of the data generation unit 210 and the data verification unit 230. Specifically, when the data communication module 100 sends commands and data, the data generation unit 210 parses the command, address, and write data, and sends them to the interface control module 300, enabling the interface control module 300 to perform write operations on the storage module. When the host sends a read command, the interface control module 300 performs a read operation on the storage module and sends the read data to the data verification unit 230, which performs verification, obtains the verification result, and sends the result back to the data communication module 100. It should be noted that when the host communicates with the data communication module 100, it must follow a predetermined single-wire communication protocol. The communication protocol timing diagram is shown below. Figure 3As shown, the data sent by the host is composed of a data frame in the order of start bit, frame header, control command, write data, and end bit. The frame header contains the chip select information of the memory unit. When the control command is a read operation, no write data content needs to be sent. The response data returned by the memory module detection circuit is composed of a data frame in the order of start bit, block address, number of error bits, and end bit. The host can further decode the data frame according to actual needs.

[0090] Furthermore, such as Figure 4 As shown, in some embodiments of this application, the data generation unit 210 includes a sending module 212 and a multi-channel parallel data selection module 211. Each data selection module 211 includes a first inverter and a first selector. The input of the first inverter is connected to the input data of the data packet, the output of the first inverter is electrically connected to the first input of the first selector, the second input of the first selector is connected to the input data of the data packet, the output of the first selector is electrically connected to the input of the sending module 212, the output of the sending module 212 is electrically connected to the interface control module 300, and the controlled end of the first selector is also electrically connected to the counter 220. Specifically, the data generation unit 210 implements data generation as follows: Figure 4 As shown, when the host sends a write command, the original data contained in the data packet is converted into 8-bit parallel data. Each bit is input to the corresponding first inverter for inversion, resulting in data that is completely opposite to the original data. The original data and the inverted data are simultaneously input to the first selector. The least significant bit of counter 220 is connected to the controlled terminal of the first selector. When the least significant bit is high, the first selector outputs the original data; when the least significant bit is low, it outputs the inverted data. This ensures that counter 220 outputs the original data when it is even and the inverted data when it is odd, guaranteeing that the generated data is continuously inverted. Thus, the data generation unit 210 can generate continuously inverted write data for testing the storage module.

[0091] Furthermore, such as Figure 4 As shown, in some embodiments of this application, the data verification unit includes:

[0092] Data buffer unit 231 is used to receive response results;

[0093] The buffer register 232 is electrically connected to the data buffer unit 231 and is used to buffer the response result;

[0094] The second inverter 233 is electrically connected to the buffer register 232 and is used to invert the response result;

[0095] The second selector 234 is electrically connected to the counter 220, the buffer register 232, and the second inverter 233, respectively, and is used to select the response result and the inverted response result according to the instruction of the counter 220.

[0096] The comparison module 235 is used to compare the output data of the second selector 234 with the output data of the first selector and send the comparison result to the data communication module 100.

[0097] Specifically, after the host sends a read command, the interface control module 300 retrieves the read data from the storage module and sends it to the data cache unit 231. The data cache unit 231 then sends the read data to the cache register 232. Next, the second inverter 233 inverts the read data, and the second selector 234 determines whether to output the original read data or the inverted read data according to the instruction from the counter 220. Finally, the comparison module 235 compares the data written to the storage module with the read data to verify the data and sends the verification result to the data communication module 100. The verification result includes the number of error bits. It should be noted that when the value of the counter 220 is all 0, the cache register 232 is enabled, and the read data is retrieved from the cache register 232.

[0098] Furthermore, such as Figure 1 As shown, in some embodiments of this application, the interface control module 300 includes:

[0099] The third selector 310 is used to obtain the storage unit selection information in the data packet, generate a chip select signal according to the storage unit selection information, and send the chip select signal to the storage module.

[0100] The interface timing control unit 320 is used to perform read or write operations on the storage module based on the parsing results.

[0101] The data receiving unit 330 is used to obtain the response result and send the response result to the data parsing and verification module 200.

[0102] Specifically, when the data communication module 100 receives a data packet and parses the frame header in the data packet, it sends the storage unit selection information contained in the frame header to the third selector 310, enabling the third selector 310 to send a chip select signal to the storage module, allowing the storage module to determine the storage unit to be operated on. Simultaneously, the data communication module 100 converts the serial data in the data packet into parallel data and sends it to the data parsing and verification module 200 to parse out the command, address, and write data, and sends this data to the interface timing control unit 320, enabling the interface timing control unit 320 to perform a write operation on the storage module. When the host sends a read command, the interface timing control unit 320 performs a read operation on the storage module and sends the read data to the data receiving unit 330. The data receiving unit 330 then sends the read data to the data verification unit 230 for verification, obtains the verification result, and sends the verification result back to the data communication module 100.

[0103] It should be noted that the interface control module 300 is connected to the storage module through a storage interface, and the interface control module 300 implements the interface timing control state flow, such as... Figure 6 As shown, through 4-line and 16-line decoding logic, the system receives storage unit selection information and busy signal sent by the data communication module 100 according to the host's command. When the address transmitted by the data parsing and verification module 200 is valid, the state machine jumps from the idle state to the command sending state. The interface control module 300 sends instructions to the storage module through the storage interface. After completing the instruction sending, it enters the address sending state and sends the valid address to the storage module. After completing the address sending, it enters the read or write data state. In the write data state, the interface control module 300 receives valid data from the data parsing and verification module 200 and sends it. After sending a block of data, it waits for the busy signal to end before jumping out of this state. After entering the read data state, it waits for the busy signal to end before receiving the data read from the storage module through the interface control module 300 and storing it in the data cache. After the read and write states are completed, if the address is not the last block address of a single storage unit, it re-enters the write command state; otherwise, it enters the idle state to wait for the next trigger.

[0104] The storage module detection method according to the embodiments of this application can receive and respond to host commands, realize the detection of abnormal data conditions in the storage module, realize the reading and writing of data in the storage module, and simultaneously avoid insufficient data port inversion during the test by writing data with data reversal interval. The circuit provides a data communication module 100, which receives data sent by the host through a single-wire full-duplex interface. Its internal state machine first determines the falling edge start bit and enters the frame header receiving state from the idle state. After receiving the correct frame header, it forwards the host command to the data parsing and verification module 200. Based on the data written to the buffer by the data parsing and verification module 200, it returns response data to the host in a serial transmission manner until the buffer is empty. The circuit also provides a data parsing and verification module 200, which enters a write or read operation through the host command forwarded by the data communication module 100. In the write operation, it receives 8 bits of data written to the storage module through the data communication module 100 and uses a counter to monitor the storage module. The circuit generates write addresses and continuous write data. During read operations, a counter controls the generation of read addresses for the storage module and buffers read data received from the storage module interface control circuit. The low-order bits of the counter control the generation of comparison data to verify the received data and output the verification result. Based on host commands, the corresponding return data is written to the buffer. The circuit also provides an interface control module 300, which uses a state machine to control the address and data generated by the data parsing and verification module 200 to be sent according to the storage module's interface protocol. It receives read data according to the storage module's interface protocol and receives the chip select signal and busy signal from the data communication module 100 through a 4-line / 16-line decoding logic. This circuit can detect and provide feedback on the storage module through simple commands and includes an error count output, demonstrating a degree of versatility.

[0105] Thirdly, this application also proposes a storage module detection device, which includes the storage module detection circuit described above.

[0106] Fourthly, embodiments of the present invention also provide a storage medium, which is a computer-readable storage medium storing a computer program that, when executed by a processor, implements the aforementioned storage module detection circuit.

[0107] Memory, as a non-transitory computer-readable storage medium, can be used to store non-transitory software programs and non-transitory computer-executable programs. Furthermore, memory may include high-speed random access memory, and may also include non-transitory memory, such as at least one disk storage device, flash memory device, or other non-transitory solid-state storage device. In some embodiments, memory may optionally include memory remotely located relative to the processor, and these remote memories can be connected to the processor via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof. The device embodiments described above are merely illustrative, and the units described as separate components may or may not be physically separate, and may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0108] Although specific embodiments are described herein, those skilled in the art will recognize that many other modifications or alternative embodiments are also within the scope of this disclosure. For example, any of the functions and / or processing capabilities described in connection with a particular device or component can be performed by any other device or component. Furthermore, while various exemplary embodiments and architectures have been described according to embodiments of this disclosure, those skilled in the art will recognize that many other modifications to the exemplary embodiments and architectures described herein are also within the scope of this disclosure.

[0109] The foregoing description, with reference to block diagrams and flowcharts of systems, methods, systems, and / or computer program products according to exemplary embodiments, has described certain aspects of this disclosure. It should be understood that one or more blocks in the block diagrams and flowcharts, as well as combinations of blocks in the block diagrams and flowcharts, can be implemented by executing computer-executable program instructions, respectively. Similarly, according to some embodiments, some blocks in the block diagrams and flowcharts may not need to be executed in the order shown, or may not all need to be executed. Furthermore, additional components and / or operations beyond those shown in the blocks in the block diagrams and flowcharts may exist in some embodiments.

[0110] Therefore, blocks in block diagrams and flowcharts support combinations of means for performing a specified function, combinations of elements or steps for performing a specified function, and program instruction means for performing a specified function. It should also be understood that each block in a block diagram and flowchart, and combinations of blocks in block diagrams and flowcharts, can be implemented by a dedicated hardware computer system or a combination of dedicated hardware and computer instructions that performs a specific function, element, or step.

[0111] The program modules, applications, etc., described herein may include one or more software components, including, for example, software objects, methods, data structures, etc. Each such software component may include computer-executable instructions that, in response to execution, cause at least a portion of the functionality described herein (e.g., one or more operations of the exemplary methods described herein) to be performed.

[0112] Software components can be coded using any of a variety of programming languages. An exemplary programming language could be a low-level programming language, such as assembly language associated with a specific hardware architecture and / or operating system platform. Software components including assembly language instructions may need to be converted into executable machine code by an assembler before being executed by the hardware architecture and / or platform. Another exemplary programming language could be a higher-level programming language that is portable across multiple architectures. Software components including higher-level programming languages ​​may need to be converted into an intermediate representation by an interpreter or compiler before execution. Other examples of programming languages ​​include, but are not limited to, macro languages, shell or command languages, job control languages, scripting languages, database query or search languages, or report writing languages. In one or more exemplary embodiments, a software component containing instructions from one of the above-described programming language examples can be executed directly by the operating system or other software components without first being converted into another form.

[0113] Software components can be stored as files or other data storage structures. Software components of similar type or related function can be stored together in a specific directory, folder, or library. Software components can be static (e.g., pre-defined or fixed) or dynamic (e.g., created or modified at runtime).

[0114] The embodiments of the present invention have been described in detail above with reference to the accompanying drawings. However, the present invention is not limited to the above embodiments. Within the scope of knowledge possessed by those skilled in the art, various changes can be made without departing from the spirit of the present invention.

Claims

1. A storage module detection circuit, characterized in that, include: Data communication module; The data parsing and verification module is electrically connected to the data communication module. The interface control module is electrically connected to both the data communication module and the data parsing and verification module. The data communication module receives data packets sent by the host and sends the data packets conforming to the protocol to the data parsing and verification module. The data parsing and verification module parses the data packets to obtain a parsing result. The interface control module performs read or write operations on the storage module based on the parsing result and receives the response result from the storage module. The data parsing and verification module also verifies the response result, obtains a verification result, and sends the verification result to the data communication module. The data communication module also sends the verification result to the host. The data communication module includes: A receiving response unit is used to respond to the trigger command of the host, receive the data packet, parse the frame header in the data packet, send the storage unit selection information contained in the frame header to the interface control module, and convert the serial data in the data packet into parallel data and send it to the data parsing and verification module. The result caching unit is electrically connected to the receiving response unit, and the result caching unit is used to cache the verification result; the receiving response unit is also used to send the verification result cached by the result caching unit to the host. The data parsing and verification module includes: The data generation unit is used to parse the data packet, obtain the parsing result, and send the parsing result to the interface control module; A data verification unit is used to verify the response result, obtain the verification result, and send the verification result to the data communication module. A counter is electrically connected to the data generation unit and the data verification unit respectively, and the counter is used to control the working state of the data generation unit and the data verification unit; The data generation unit includes a sending module and a multi-channel parallel data selection module. Each data selection module includes a first inverter and a first selector. The input terminal of the first inverter is connected to the input data of the data packet. The output terminal of the first inverter is electrically connected to the first input terminal of the first selector. The second input terminal of the first selector is connected to the input data of the data packet. The output terminal of the first selector is electrically connected to the input terminal of the sending module. The output terminal of the sending module is electrically connected to the interface control module. The controlled terminal of the first selector is also electrically connected to the counter.

2. The storage module detection circuit according to claim 1, characterized in that, The data verification unit includes: A data caching unit is used to receive the response result; A cache register, electrically connected to the data cache unit, is used to cache the response result; The second inverter, electrically connected to the buffer register, is used to invert the response result; The second selector is electrically connected to the counter, the cache register, and the second inverter, respectively, and is used to select between the response result and the inverted response result according to the instruction of the counter; The comparison module is used to compare the output data of the second selector with the output data of the first selector and send the comparison result to the data communication module.

3. The storage module detection circuit according to claim 1, characterized in that, The interface control module includes: The third selector is used to obtain storage unit selection information in the data packet, generate a chip select signal according to the storage unit selection information, and send the chip select signal to the storage module. An interface timing control unit is used to perform read or write operations on the storage module based on the parsing result. The data receiving unit is used to acquire the response result and send the response result to the data parsing and verification module.

4. A method for detecting a storage module, characterized in that, The method, applied to the storage module detection circuit as described in any one of claims 1-3, comprises: The data communication module receives data packets sent by the host and sends data packets that conform to the protocol to the data parsing and verification module. The data packet is parsed by the data parsing and verification module to obtain the parsing result; The interface control module performs read or write operations on the storage module based on the parsing results and receives the response results from the storage module. The response result is verified by the data parsing and verification module to obtain the verification result, and the verification result is sent to the data communication module. The verification result is sent to the host via the data communication module.

5. The storage module detection method according to claim 4, characterized in that, The step of receiving data packets sent by the host through the data communication module and sending data packets conforming to the protocol to the data parsing and verification module includes: In response to the trigger command from the host, the data communication module is instructed to receive and parse the frame header of the data packet; When the data packet conforms to the protocol, the storage unit selection information contained in the frame header is sent to the interface control module through the data communication module, and the serial data in the data packet is converted into parallel data and sent to the data parsing and verification module.

6. A storage module detection device, characterized in that, Includes the storage module detection circuit as described in any one of claims 1-3.

7. A storage medium, characterized in that, The storage medium stores computer-executable instructions, which are used to cause a computer to execute the storage module detection method according to any one of claims 4-5.

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