Chip prototype verification method, system and device and medium

Abstract

The invention discloses a chip prototype verification method, system and device and a medium, relates to the technical field of chip prototype verification, and provides a chip prototype verification method for solving the problem that a fixed value is adopted due to the fact that the phase difference between data and a clock is difficult to adjust in the prototype verification process of a BMC (Baseboard Management Controller) chip at present. A serial port configuration register is used for realizing cross-clock domain delay configuration, an edge detection mechanism is established to ensure that the change can be stably captured by an input delay module under an MMCM / PLL clock domain even if the clock domain for receiving a clock signal is switched, and the changed delay configuration takes effect. Furthermore, delay processing is carried out on signals, which cannot meet the delay requirement, of the FPGA through anti-phase delay. Based on the above, even for a special SoC chip, namely a BMC chip, the method can also ensure flexible phase control of the signal of the special SoC chip, so that more complete function verification can be realized.

Description

Technical Field

[0001] This invention relates to the field of chip prototype verification technology, and in particular to a chip prototype verification method, system, device and medium. Background Technology

[0002] Chip prototyping has become a mainstream and mature verification method in current chip design. For Baseboard Management Controller (BMC) chips used in server systems, chip prototyping is also necessary during the design phase. Currently, this is primarily achieved through Field-Programmable Gate Arrays (FPGAs). Furthermore, since BMC chips are mainly used to implement out-of-band management functions for server host networks, the network functionality of the BMC chip must be verified as completely as possible during prototyping. In particular, the prototyping of the Ethernet controller within the BMC chip needs to be thorough and comprehensive, adaptable to different server hardware platforms.

[0003] Currently, because the receiving side has three different receiving clock frequencies—125Mbps, 25Mbps, and 2.5Mbps—and these correspond to the Ethernet controller interfaces (such as the RGMII interface) of the BMC chip operating at speeds of 10M / 100M / 1000Mbps respectively, they cannot be simultaneously adjusted via the Mixed-mode Clock Manager (MMCM) / Phase-locked Loop (PLL). Furthermore, the 2.5M clock frequency does not meet the minimum input clock frequency requirements of the MMCM / PLL and cannot be adjusted via the MMCM / PLL. Therefore, the phase difference between the clock and data is currently mostly set to a fixed value and cannot be adjusted.

[0004] However, due to differences in FPGA device performance and printed circuit board (PCB) trace delay, if the transmit (TX) / receive (RX) clock and data are set to fixed values ​​in the FPGA project, then the debugging work of this interface needs to be repeated during actual debugging. Running different versions of FPGA projects and debugging the hardware interface functions will consume manpower and time, and the functional verification will be incomplete.

[0005] Therefore, those skilled in the art urgently need a chip prototype verification method to solve the problem that it is difficult to adjust the phase difference between data and clock during the prototype verification process of BMC chips, which leads to the need to repeatedly perform multiple versions of functional debugging, which consumes manpower and resources and results in incomplete functional verification. Summary of the Invention

[0006] The purpose of the present application is to provide a chip prototype verification method, system, device and medium to solve the problem that it is difficult to adjust the phase difference between data and clock in the current BMC chip prototype verification process, resulting in the need to repeatedly perform multiple versions of functional debugging, consuming manpower and resources, and incomplete functional verification.

[0007] To solve the above technical problems, the present application provides a chip prototype verification method, comprising: The test chip and the test machine are tested for network connectivity through a network connectivity test tool command in a serial port debugging assistant; When the network connectivity test fails, the first delay parameter of the received clock signal is configured in the register through the serial port debugging assistant; The received clock signal is processed by the input delay module based on the first delay parameter; If the network connectivity test still fails after the delay processing, the first delay parameter is adjusted again, and the step of configuring the first delay parameter of the received clock signal in the register through the serial port debugging assistant is returned to; The first delay parameter includes an enable state bit, an inversion state bit and a delay value configuration bit. The delay value configuration bit takes effect when the enable state bit changes from the initial state to the effective state; the enable state bit is reset and then configured to take effect again each time the first delay parameter is configured; the inversion state bit is configured to take effect when the input delay module cannot meet the minimum delay requirement of the received clock signal; and the received clock signal is processed by the inverter when the inversion state bit takes effect.

[0008] In an optional embodiment, before the step of configuring the first delay parameter of the received clock signal in the register through the serial port debugging assistant, the method further comprises: Determining whether the sending action performed by the test chip during the network connectivity test is successful; If not, the phase difference between the sending clock signal and the sending control signal is measured, and the phase of the sending clock signal is adjusted through an engineering change instruction, and the step of determining whether the sending action performed by the test chip during the network connectivity test is successful is returned to.

[0009] In an optional embodiment, after the step of determining whether the sending action performed by the test chip during the network connectivity test is successful, the method further comprises: if successful, obtaining an engineering backend layout routing timing report, and viewing a trace delay between a received control signal and each bit of data signal in the engineering backend layout routing timing report; if the trace delay between the received control signal and any bit of the data signal is greater than a trace delay threshold, adjusting a phase difference between the received control signal and the data signal.

[0010] In an alternative embodiment, the adjusting the phase difference between the received control signal and the data signal comprises: configuring a second delay parameter of the received control signal and / or the data signal in the register through the serial port debugging assistant; wherein the second delay parameter comprises the enable state bit and the delay value configuration bit; delay processing the received control signal and / or the data signal through the input delay module based on the second delay parameter.

[0011] In an alternative embodiment, the data signal has N bits; wherein N is any positive integer; The input delay module has N+2, corresponding to the received clock signal, the received control signal and N bits of the data signal; the delay action performed by each input delay module is controlled by the corresponding delay parameter stored in the register.

[0012] In an alternative embodiment, N=4; The register comprises a first register, a second register and a third register; wherein the first register is used to store the first delay parameter corresponding to the received clock signal, and the second delay parameter corresponding to the received control signal; the second register is used to store the second delay parameter corresponding to the first and second bits of the data signal; the third register is used to store the second delay parameter corresponding to the third and fourth bits of the data signal; configuring the first delay parameter / the second delay parameter in the register through the serial port debugging assistant comprises: writing the first delay parameter / the second delay parameter into the corresponding register through the address of the register corresponding to the first delay parameter / the second delay parameter to be configured.

[0013] In an alternative embodiment, the writing the first delay parameter / the second delay parameter into the corresponding register comprises: In the universal bootloader stage, modifying the value in the corresponding register through a memory write command; After entering the kernel system, the corresponding register is accessed through a device memory access tool, and the value in the register is modified.

[0014] In an alternative embodiment, the input delay module has 2 M minimum delay units; wherein M is any positive integer; The delay value configuration bit is M bits, and the enable state bit and the inverse state bit are each 1 bit; The first register, the second register, and the third register are 2 K bit registers; wherein K is any positive integer, and 2 K is greater than or equal to 2M+3.

[0015] In an alternative embodiment, adjusting the first delay parameter / the second delay parameter includes: Adjusting the delay value configuration bit by a preset step; wherein the preset step is greater than the minimum delay unit and is an integer multiple of the minimum delay unit.

[0016] In an alternative embodiment, after adjusting the first delay parameter / the second delay parameter, further comprising: Determining whether the network connectivity test is successful; if the network connectivity test fails, returning to the step of adjusting the first delay parameter / the second delay parameter; When the network connectivity test is successful for the first time, recording the value of the delay value configuration bit in the current first delay parameter / the second delay parameter as a first delay value; and returning to the step of adjusting the first delay parameter / the second delay parameter; When the network connectivity test fails for the first time after being successful, recording the value of the delay value configuration bit in the current first delay parameter / the second delay parameter as a second delay value; Determining an optimal delay value according to the average of the first delay value and the second delay value.

[0017] In an alternative embodiment, adjusting the first delay parameter includes: The inverse state bit is in a non-effective state by default; When the delay value configuration bit of the first delay parameter is configured as a maximum value, if the network connectivity test still fails, the inverse state bit is configured as an effective state.

[0018] In an alternative embodiment, the network connectivity test between the chip under test and the test machine through the network connectivity test tool command in the serial port debugging assistant includes: configure a network for the chip under test through the serial port debugging assistant, and configure a network segment of the test machine as the same network segment of the chip under test; command the chip under test to send a request to the test machine through the serial port debugging assistant, and check whether the chip under test receives a response returned by the test machine through the serial port debugging assistant; If yes, it is determined that the network connectivity test is successful; otherwise, it is determined that the network connectivity test fails.

[0019] In an optional embodiment, determining whether the sending action performed by the chip under test when performing the network connectivity test is successful comprises: checking whether the request sent by the chip under test is received through network packet analysis software deployed on the test machine; if yes, it is determined that the sending action is successful, otherwise, it is determined that the sending action fails.

[0020] To solve the above technical problems, the application further provides a chip prototype verification system, comprising a test machine and a hardware platform; Wherein, serial port communication and network communication are established between the test machine and the hardware platform. The hardware platform comprises a field programmable logic gate array and a non-volatile storage medium. The field programmable logic gate array is used to perform code synthesis and layout routing on the code of the chip under test transplanted through a software tool to generate a data stream file. The non-volatile storage medium is used to store the data stream file.

[0021] In an optional embodiment, the field programmable logic gate array comprises a minimum system, an Ethernet controller, a mixed mode clock management unit / phase-locked loop module, an input delay module, a bus interface module and a register. The bus interface module is used to convert data sent by the minimum system through an advanced high-performance bus into a read operation or a write operation on the register.

[0022] In an optional embodiment, the field programmable logic gate array comprises a cross-clock domain processing module. The cross-clock domain processing module is used to: realize synchronous processing of a reset signal; cross-clock domain the value of a register in an advanced high-performance bus clock domain to the clock domain of the mixed mode clock management unit / phase-locked loop module; and generate a delay valid signal, which is a signal for resetting and regenerating a corresponding enable state bit.

[0023] To solve the above technical problems, the application further provides a chip prototype verification device, comprising: The network test module is configured to test the network connectivity of the chip under test and the test machine through a network connectivity test tool command in the serial port debugging assistant. The parameter configuration module is configured to configure a first delay parameter of a receiving clock signal in a register through the serial port debugging assistant when the network connectivity test fails. The delay processing module is configured to perform delay processing on the receiving clock signal through an input delay module based on the first delay parameter. The parameter adjustment module is configured to re-adjust the first delay parameter and trigger the parameter configuration module if the network connectivity test still fails after the delay processing.

[0024] To solve the above technical problems, the application further provides a computer program product, comprising computer programs / instructions, which, when executed by a processor, implement the steps of the chip prototype verification method.

[0025] To solve the above technical problems, the application further provides a chip prototype verification device, comprising: A memory is configured to store computer programs. A processor is configured to implement the steps of the chip prototype verification method when executing the computer programs.

[0026] To solve the above technical problems, the application further provides a non-volatile storage medium, which stores computer programs, and the computer programs, when executed by a processor, implement the steps of the chip prototype verification method.

[0027] The chip prototype verification method provided by the application provides a scheme for flexibly controlling the phase of a received clock signal by configuring the delay of the received clock signal through a serial port. The phase of the received clock signal is controlled based on a register, so that the clock domains can be isolated. Even if the input delay module clock (for example, 300 Mbps) is provided by the MMCM / PLL module in the FPGA currently used for chip prototype verification, the delay configuration across the clock domains can be guaranteed to take effect on the input delay module. Further, the method establishes an edge detection mechanism to ensure that the input delay module under the MMCM / PLL clock domain can capture the change even when the clock domain of the received clock signal is switched, and the changed delay configuration is taken effect. Based on this, even for the special object of the BMC chip, the received clock has three different clock frequencies of 125M / 25M / 2.5Mbps at the 10M / 100M / 1000Mbps rates at the RGMII interface. The method can also guarantee that the received clock can be effectively delayed (i.e., phase controlled) when the clock frequency is switched. In addition, when the input delay module uses the clock (for example, 300 Mbps) provided by the MMCM / PLL module, if the clock frequency of the received clock signal is 2.5Mbps, the delay capability of the input delay module may not meet the delay needs of the received clock signal. At this time, the method also realizes the delay processing of the received clock signal through an inverter, solving the problem of insufficient delay of the input delay module. Moreover, the enable control of the inverter is also realized by the configuration of the register, solving the problems of cross-clock domain control and possible problems caused by the switching of the received clock frequency when the inverter is applied to the FPGA project to delay the received clock signal.

[0028] Based on the above, the method can solve the problem that the phase of the received clock can only be configured as a fixed value during the prototype verification of a chip with multiple clock frequencies, such as the BMC chip, resulting in insufficient flexibility of the prototype verification and incomplete functional verification. The adaptability of chip prototype verification to different hardware platforms is improved, and more complete functional verification can be achieved.

[0029] The chip prototype verification system, device, and non-volatile storage medium provided by the application correspond to the above method and have the same effect. BRIEF DESCRIPTION OF DRAWINGS

[0030] To more clearly illustrate the embodiments of the application, the drawings needed in the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the application, and other drawings can be obtained by those skilled in the art without creative labor.

[0031] Figure 1A flow chart of a chip prototype verification method provided by an embodiment of the present application.

[0032] Figure 2 A structural diagram of a chip prototype verification hardware architecture provided by an embodiment of the present application.

[0033] Figure 3 A flow chart of another chip prototype verification method provided by an embodiment of the present application.

[0034] Figure 4 A structural diagram of an Ethernet engineering provided by an embodiment of the present application.

[0035] Figure 5 A structural diagram of a chip prototype verification device provided by an embodiment of the present application.

[0036] Figure 6 A structural diagram of another chip prototype verification device provided by an embodiment of the present application. DETAILED DESCRIPTION

[0037] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the protection scope of the present application.

[0038] The core of the present application is to provide a chip prototype verification method, system, device and medium.

[0039] In order for those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the drawings and specific embodiments.

[0040] In the related art, the baseboard management controller (BMC) chip is a key device for realizing the out-of-band management function in a server system, and its network function is particularly important. Therefore, when the BMC chip is verified, one of the verification focuses is to verify the network function of the BMC chip, and the network function of the BMC chip needs to be verified as completely as possible.

[0041] However, the Ethernet controller interfaces supported by the BMC chip mainly have two types of Reduced Media Independent Interface (RMII) and Reduced Gigabit Media Independent Interface (RGMII). The RGMII interface is a dedicated network interface of the BMC and supports 10M / 100M / 1000Mbps rate communication. The RGMII interface is a clock-synchronous parallel data interface. When the RGMII interface operates at a 1000Mbps rate, the corresponding clock frequency is 125MHz, the data bit width is 4 bits, and the data is sampled at both rising and falling edges; when the RGMII interface operates at a 100Mbps rate, the clock frequency is 25MHz; and when the RGMII interface operates at a 10Mbps rate, the clock frequency is 2.5MHz.

[0042] In addition, when data is transmitted and received, a certain phase difference needs to be maintained between the clock signal and the data signal to meet the clock sampling / holding time. Due to differences in FPGA device performance and hardware platform Printed Circuit Board (PCB) wiring delay, the phase difference needs to be adjusted according to different FPGAs and hardware platforms.

[0043] However, the receiving clock signal on the receiving side has three different clock frequencies of 125M / 25M / 2.5Mbps, which changes with the rate of the RGMII and cannot be adjusted by the MMCM / PLL. Therefore, in the current FPGA engineering, the phase of the clock signal and the data signal of the transmitting (TX) / receiving (RX) is usually set to a fixed value and cannot be adjusted. In addition, the 2.5Mbps clock frequency does not meet the minimum input clock frequency of the Mixed-mode clock manager (MMCM) / Phase-locked loop (PLL) that provides a clock signal in a general FPGA device. Therefore, the hardware structure of the current FPGA device does not support adjusting the phase of the 2.5Mbps clock frequency receiving clock signal.

[0044] Based on the above, due to large differences in PCB wiring delay and other factors in different server hardware platforms, repeated debugging of the RGMII interface is required during actual debugging, and running different versions of FPGA engineering and hardware interface function debugging requires a lot of manpower and time, and the function verification is incomplete.

[0045] To solve the above problems, the present application provides a chip prototype verification method, which comprises the steps of Figure 1As shown, comprising: S11: The chip under test and the tester perform network connectivity test through the network connectivity test tool command in the serial port debugging assistant.

[0046] S12: When the network connectivity test fails, the first delay parameter of the received clock signal is configured in the register through the serial port debugging assistant.

[0047] S13: The received clock signal is processed through the input delay module based on the first delay parameter.

[0048] S14: If the network connectivity test still fails after the delay processing, the first delay parameter is adjusted again, and the step S12 is returned.

[0049] The first delay parameter includes an enable state bit, an inversion state bit, and a delay value configuration bit; the delay value configuration bit takes effect when the enable state bit changes from an initial state to an effective state; the enable state bit is reset and then configured to take effect again each time the first delay parameter is configured; the inversion state bit is configured to take effect when the input delay module cannot meet the minimum delay requirement of the received clock signal; and the received clock signal is processed through an inverter when the inversion state bit takes effect.

[0050] For step S11, first, the test hardware architecture based on which the chip prototype verification is implemented is described. The test hardware architecture is as shown in Figure 2 It mainly includes a tester and a hardware platform. The hardware platform is FPGA, the code of the BMC chip is transplanted into the FPGA, the code is synthesized, laid out and wired through the software tool of the FPGA, and finally a data stream file is generated. The generated data stream file is burned into an external non-volatile storage medium (such as a flash chip in Figure 2 ) through the downloader of the FPGA to ensure that the power failure does not result in loss, thereby realizing the prototype verification project of the BMC chip.

[0051] There is network communication and serial communication between the hardware platform and the tester. Among them, Figure 2 The RJ45 in is a network port used for network function test. However, it is only an optional example of the network port, and does not mean that only the RJ45 network port can be used when the BMC chip is tested for network function. In addition, only the function of the Ethernet controller is implemented in the BMC chip, so a physical layer (PHY) chip needs to be externally connected to the connection seat of the RJ45 network port and communicate with the opposite network, that is, establish a network connection with the tester.

[0052] The above part is a common hardware architecture for implementing the network function of a BMC chip at present, and the embodiment will not be described again. However, it should be noted that a key point of the method is to adjust the phase of the received clock signal by configuring a serial port register. The BMC chip is a system on chip (SoC), and supports a serial port module internally, so the test machine can perform system debugging on the SoC chip based on serial communication through a serial port debugging assistant. For example, printing system startup information, peripheral information, and the like. The test machine can also send commands through the serial port, and read / write and configure the register. In addition, since the focus of the method is to test the network function of the BMC, the FPGA in Figure 2 only shows the part related to the network communication function of the BMC, that is, the Ethernet controller.

[0053] Based on the above hardware architecture, the user can command the FPGA to simulate the BMC to initiate a network communication request through the serial port debugging assistant at the test machine. For example, a network connectivity test tool based on the Internet Control Message Protocol (ICMP) can be used, that is, the PING command. The PING command is used to send an echo request to the target host (that is, the test machine), and waits for the test machine to return an echo reply, that is, the network function test of the BMC chip is implemented. However, it is not difficult to know that the embodiment is not limited to the PING command as the only network connectivity test tool for network function test, other tools can also be used as long as the test machine and the FPGA support.

[0054] For the above example, the embodiment also provides an optional embodiment for the specific implementation of step S11, which specifically includes: S111: configuring the network for the chip to be tested through the serial port debugging assistant, and configuring the network segment of the test machine to be the same network segment as the chip to be tested.

[0055] As can be known from the above description, the user can send commands to the FPGA through the serial port debugging assistant to achieve configuration. After the FPGA chip simulates the BMC to start the BMC system (such as Linux), the network of the BMC system can be configured based on the commands through the serial port debugging assistant, such as setting the Media Access Control Address (MAC) / Internet Protocol (IP) address / subnet mask, and the like. To realize the network communication connection between the FPGA and the test machine, the network configuration (such as the IP address) of the same network segment needs to be set on the test machine.

[0056] S112: The chip under test sends a request to the tester through the serial port debugging assistant command, and checks whether the chip under test receives the response returned by the tester through the serial port debugging assistant.

[0057] S113: If the response is received, it is determined that the network connectivity test is successful; otherwise, it is determined that the network connectivity test fails.

[0058] It should be noted that the specific scheme for implementing the BMC chip network function test based on the PING command provided in this embodiment utilizes the lightweight, standardization and cross-platform compatibility of the PING command. The PING command directly verifies the IP layer and network interface function of the chip through the ICMP echo request and response mechanism, without relying on a complex protocol stack. Moreover, the ICMP protocol is simple, so that the tool has low resource occupation on the BMC chip and is suitable for embedded environment, i.e., testing based on FPGA.

[0059] After that, for step S12. It should be noted that if the network connectivity test in step S11 succeeds once, the phases of the signals including the receive clock do not need to be adjusted. However, this is an ideal case, and does not involve the technical problem addressed by the present application, so this embodiment will not be described in detail, and it is only necessary to be clear that in any step of judging whether the network connectivity test function is successful, if the network connectivity test is successful, the method can be ended.

[0060] Further, one of the focuses of the method is to configure the register through the serial port, and control the phases of the signals including the receive clock signal (achieved through delay) by the register. It has been clearly explained in the above description that the reading and writing of the register can be achieved through the serial port debugging assistant of the tester, and this embodiment will not be described in detail.

[0061] But need to explain, the step S12 to the register configuration includes three kinds of enable state bit, inverse state bit and delay value configuration bit. Among them, the delay value configuration bit is also the specific delay value, when the received clock signal is delayed to adjust its phase, that is, the value of the delay value configuration bit is used as data guidance for delay. For how to determine the above delay value, the embodiment does not make any limitation here. For the enable state bit, as known from the above description, its function is to make the delay value configuration bit effective, that is, to control whether the delay is effective. It is particularly important to note that the enable state bit in this method only takes effect when it changes from the initial state to the effective state, that is, a kind of edge detection mechanism. Assuming that the initial state of the enable state bit is low (i.e. logic "0") and the effective state is high (i.e. logic "1"), the condition for the delay configuration to take effect is that the enable state bit changes from "0" to "1", that is, an upward edge of the signal at the enable state bit occurs. When the upward edge of the signal of the enable state bit is detected, the delay takes effect. Based on this setting, the input signal needs to meet the setup and hold time requirements to ensure that the signal is stable before the clock active edge, thereby realizing the effect of the configuration of the register across the clock domain. Even if there are many different time frequencies of the received clock signal of the BMC chip, the delay configuration across the clock domain can be realized by the register. Finally, for the reverse state bit, it is mainly aimed at the problem in the above related technical part that the existing common FPGA cannot meet the minimum delay requirement of the BMC chip when the clock frequency of the received clock signal is 2.5Mbps. That is, on the basis of the delay that can be realized by the existing FPGA, the delay of the received clock signal is realized by the inverter to meet the delay requirement of the 2.5Mbps received clock signal. It should be noted that if the clock frequency of the received clock of the BMC chip is 125M / 25M / 2.5Mbps, the inverting delay usually only acts on 2.5Mbps. But in some special cases and other scenarios, the inverting delay can be set based on the needs. For example, when the delay realized by the existing MMCM / PLL module of the FPGA cannot meet the requirements, the inverting delay can be used to meet the needs.

[0062] Finally, for the step S13 and the step S14. That is, after the delay adjustment in the step S12, it is judged whether the current phase adjustment is effective, or whether the delay value setting of the current phase adjustment is appropriate. If the network connectivity test still fails, the delay value needs to be adjusted again, that is, returned to the delay configuration step of the step S12.

[0063] It is worth noting that, whenever the first delay parameter is reconfigured, the enable state bit needs to be changed from the initial state to the effective state. Since the enable state bit is ultimately in the effective state after the last configuration, the enable state bit needs to be reset before being configured to the effective state this time to meet the edge detection requirement, so that the delay configuration is effective across the clock domain.

[0064] Further, if it can be determined that the clock frequency of the current received clock signal is 2.5 Mbps (or other clock frequencies that cannot meet the delay requirement by the original device of the FPGA device), the inversion state bit in the first delay parameter can be set to the effective state. In another possible implementation scenario, if the clock frequency of the received clock signal cannot be directly obtained, when the last delay configuration is already the maximum delay, if the network connectivity test still fails, the adjustment of the first delay parameter this time can include setting the inversion state bit to the effective state.

[0065] That is, the embodiment provides a first delay parameter adjustment scheme for the inversion state bit: The inversion state bit is in the ineffective state by default. When the delay value configuration bit of the first delay parameter is configured to the maximum value, if the network connectivity test still fails, the inversion state bit is configured to the effective state.

[0066] For example, assuming that the input delay module supports a maximum of 512 steps of delay adjustment, i.e., including 512 minimum delay units. At this time, the delay value configuration bit corresponds to a delay value range of 0-511. Assuming that in the adjustment process of the delay parameter, the delay is repeatedly adjusted in an incremental step manner. Before the delay value configuration bit reaches the maximum (i.e., step 511) for the first time, the inversion state bit is in the ineffective state (or the initial state, such as logic "0"). When the delay value configuration bit reaches the maximum for the first time, if the network connectivity test result is still a failure, the inversion state bit can be set to the effective state (such as logic "1") from the next delay adjustment. At the same time, the delay value configuration bit can be reset to the minimum value (i.e., step 0) to re-perform the step-by-step delay adjustment.

[0067] The implementation scheme provided by the embodiment does not need to know the current network rate or the clock frequency of the current received clock signal, and has lower requirements for implementation. At the same time, the method is not limited to inverting a specific frequency clock signal to meet its delay requirement, and is used for any signal frequency that cannot be implemented by the original device of the FPGA, which is a more flexible and convenient delay adjustment scheme.

[0068] In summary, the method can realize the cross-clock domain delay processing of the received clock signal by dynamically adjusting the register through the serial port. Even for the BMC chip, which is a special SoC chip with three different clock frequencies of 125M / 25M / 2.5Mbps, the flexible adjustment of the received clock phase can be realized across the clock domain. At the same time, even for the special clock frequency of 2.5Mbps, the delay requirement can be met through the inverting delay. Therefore, the method can solve all the problems of the received clock phase adjustment during the network function test of the BMC chip, so it is not necessary to set a fixed value. The clock phase can be flexibly adjusted according to the actual FPGA hardware condition and the wiring delay of the hardware platform PCB. The network function test of the BMC chip can be applied to various FPGA hardware platforms, and the prototype verification of the network interface with various rates is supported, the function verification is more complete, and it is not necessary to perform the FPGA engineering and hardware interface function debugging of different versions, thereby improving the chip prototype verification efficiency.

[0069] It should be noted that the method is not only applicable to the network function verification of the BMC chip, but also applicable to the prototype verification of other SoC chips. Only because the BMC chip has various different clock frequencies during the network function verification, and at least one clock frequency cannot meet the delay requirement of the FPGA device, the method has a significant advantage in solving this special problem. If other SoC chips also have the above problems, the method can also realize the above effects during the prototype verification of the chips.

[0070] On the other hand, as described above, the method is not only applicable to the network function verification of the BMC chip. Similarly, the method can also not only adjust the phase of the received clock signal during the network function verification of the BMC chip. Only because the received clock signal is special, the above embodiment focuses on the description. In the actual network function verification of the BMC chip, in addition to the received clock signal, the RX side also includes the received control signal and the data signal (as described in the related art part, generally 4 bits). Similarly, the TX side also includes the transmission clock signal, the transmission control signal, etc. For these signals, the application also provides a corresponding embodiment.

[0071] The embodiment provides an optional scheme for adjusting the phase difference between the transmission clock signal and the transmission control signal on the TX side. The above method further includes the following steps before step S12: S21: determining whether the transmission action performed by the to-be-tested chip during the network connectivity test is successful.

[0072] S22: If failed, measure the phase difference between the transmission clock signal and the transmission control signal, and adjust the phase of the transmission clock signal through an engineering change order, and return to step S21.

[0073] Wherein, for step S21, it can be known from the above embodiment description. The one-time network connectivity test includes the transmission of one request and the reception of one response for the FPGA side. For example, when the network connectivity test is implemented through a PING command, the one-time network connectivity test includes the transmission of an Echo Request from the FPGA to the tester, and the reception of an Echo Reply returned by the tester. Therefore, whether the transmission action performed in step S21 is successful, i.e., whether the request is successfully transmitted. By determining whether the request is successfully transmitted, the determination of whether the transmission action performed in step S21 is successful can be completed.

[0074] For this, in combination with the above optional example using the PING command, the embodiment also adaptively provides a specific implementation of step S21. The above step S21 specifically includes: viewing whether the request transmitted by the chip under test is received through the network packet analysis software deployed on the tester; if yes, it is determined that the transmission action is successful, otherwise it is determined that the transmission action is failed.

[0075] For example, the network packet analysis software described above in the embodiment can be wireshark, which can view whether the tester receives the Address Resolution Protocol (ARP) request sent by the FPGA corresponding to the network segment. That is, whether the tester receives the network request sent by the FPGA. It is not difficult to understand that the tester can be implemented through a personal computer (PC), so it is easy to implement the deployment of the network packet analysis software on the tester, and therefore the embodiment provides a simple and easy-to-implement judgment scheme for whether the transmission action is performed successfully.

[0076] Further, for the specific implementation of step S22, step S22 mainly includes two parts of the measurement of the phase difference and the adjustment of the phase difference. For the measurement of the phase difference, the simplest can be achieved through an oscilloscope, and the embodiment does not repeat it. For the adjustment of the phase difference, the embodiment also gives a possible example in combination with the actual scene, that is, a specific scheme of adjusting the phase through an Engineering Change Order (ECO): Open the hardware platform layout and routing design checkpoint file (DesignCheckpoint), that is, the ".dcp" file, through the FPGA software (such as vivado). Then, find the TX side MMCM unit from the.dcp file. Since the MMCM can output multiple clocks, the clock to be adjusted needs to be found to adjust its phase. Finally, the phase is set, and the phase is corresponding to a clock period according to 0°~360°. Assuming that the original phase of the clock is 0°, the time to be adjusted is 2ns, and the clock period is 8ns, the phase can be set to 90 to complete the adjustment.

[0077] From the above, the embodiment is aimed at the phase difference adjustment between the TX side transmission clock signal and the transmission control signal, and provides an alternative implementation scheme. And the scheme is simple and efficient, and is suitable for judging and adjusting before the load receiving side signal phase adjustment, so as to exclude the possibility of network connectivity test failure caused by the sending side, and improve the efficiency of the whole verification process.

[0078] Further, the embodiment also provides an adaptive adjustment scheme for the phase difference between the receiving control signal and the data signal of the receiving side. The above method further comprises the following steps after step S21: S23: If successful, obtain the engineering backend layout and routing timing report, and check the wiring delay between the receiving control signal and each bit of data signal in the engineering backend layout and routing timing report.

[0079] S24: If the wiring delay between the receiving control signal and any bit of data signal is greater than the wiring delay threshold, adjust the phase difference between the receiving control signal and the data signal.

[0080] From the above embodiment, if the sending is successful but the network connectivity test still fails, it means that the RX side is the problem. Before adjusting the receiving clock signal, the embodiment first adjusts the wiring delay between the receiving control signal and the data signal of the receiving side. The wiring delay is related to the wiring of the FPGA hardware and the hardware platform PCB, so the wiring delay between the receiving control signal and each bit of data signal, that is, the wiring delay on each data channel, can be checked according to the timing report after the FPGA engineering backend layout and routing, that is, the engineering backend layout and routing timing report in the above step S23. It should be noted that the embodiment does not limit the specific value of the wiring delay threshold, which should be determined according to actual needs. For example, in the actual scene, the maximum wiring delay between the data channels can be determined by board-level measurement to be 1ns, so the wiring delay threshold in the above embodiment can be determined to be 1ns, and the wiring delay is considered to be too large and needs to be adjusted when it exceeds 1ns.

[0081] As for the adjustment of the trace delay, the most direct way is to adjust the trace between the FPGA device and the hardware platform PCB, but this way of modifying hardware is difficult to realize in practical application. Then as a signal on the RX side with the receiving clock signal, the signal can also be processed by the input delay unit of the FPGA and the configuration control of the register to realize the delay, so as to adjust the trace delay. Specifically, the application provides an optional embodiment, and the step S24 of adjusting the phase difference between the receiving control signal and the data signal specifically includes: S241: configuring the second delay parameter of the receiving control signal and / or the data signal in the register through the serial port debugging assistant.

[0082] Among them, the second delay parameter includes an enable state bit and a delay value configuration bit.

[0083] S242: based on the second delay parameter, the receiving control signal and / or the data signal are processed by the input delay module.

[0084] It is not difficult to understand that the purpose of the scheme provided by the embodiment is to adjust the phase difference between the receiving control signal and the data signal. Therefore, separately delaying the receiving control signal, separately delaying the data signal, or simultaneously delaying the receiving control signal and the data signal can achieve the purpose, so the embodiment step S242 does not limit the delay of which signal or both signals.

[0085] In addition, the second delay parameter for controlling the delay of the receiving control signal and the data signal is mainly different from the first delay parameter in that there is no inversion state bit. This is because for the operation verification of SoC chips such as BMC chips, the delay realized by the FPGA based on the MMCM / PLL module can generally meet the delay of the control signal and the data signal, so there is no need to set the inversion state bit. However, it is not difficult to understand that if the FPGA cannot meet the delay requirement, the inversion delay can also be increased.

[0086] In addition, the enable state bit and the delay value configuration bit included in the second delay parameter are not different from the first delay parameter. The delay value configuration bit is also used to indicate a specific delay value, and the enable state bit is used to enable the delay configuration across clock domains. For example, for the prototype verification of the BMC chip, the clock provided by the MMCM / PLL module in the FPGA is generally 300Mbps. When the FPGA receives the configuration command sent by the test machine through the serial port debug helper to read / write the register, the interaction is implemented through the Advanced High Performance Bus (AHB), the AHB clock domain is different from the clock domain provided by the MMCM / PLL module, and there is a cross-clock domain problem, so the above-mentioned edge detection mechanism based on the enable state bit is needed to enable the configuration across clock domains.

[0087] Further, based on the delay processing procedures for different signals in the above-mentioned several embodiments, the embodiment provides a complete BMC chip network function verification procedure. As shown in Figure 3 , the procedure comprises the following steps. First, the network connectivity test is started through the PING command; then it is judged whether the test is successful; if yes, the network function verification procedure ends; if not, it is first judged whether the request is successfully sent on the TX side; if yes, it is indicated that the problem is on the RX side, and the delay between the received clock signal and the data signal or the delay between the received control signal and the data signal is adjusted based on the above-mentioned register configuration through the serial port; if not, it is indicated that the problem is on the TX side, and the phase of the sending clock at the current rate is adjusted through the ECO; and after the delay adjustment of any signal, the step of starting the network connectivity test is returned to, it is judged whether the network is connected after the adjustment, and the next cycle is performed until the network connectivity test is successful, and the procedure ends.

[0088] On the other hand, the adjustment of the received side signal delay is implemented through the register configuration control input delay module (IDELAY). For this purpose, the present application further provides a further embodiment: Suppose that the data signal has N bits; wherein N is any positive integer. Then the input delay module has N+2, which respectively correspond to the received clock signal, the received control signal and the N-bit data signal; the delay action performed by each input delay module is controlled by the corresponding delay parameter stored in the register.

[0089] That is, in the embodiment, the number of IDELAYs corresponds to the number of RX side signals one-to-one, and is respectively used for the delay adjustment of the corresponding signal. And the delay parameter corresponding to the IDELAY and the register establishes a corresponding relationship, and the enablement and the specific delay output of the IDELAY are controlled by the corresponding delay parameter, so as to avoid control confusion and also realize the simultaneous delay control of multiple signals.

[0090] Further, from the above description of the related art, it is known that in the network function verification of the BMC chip, the bit width of the data signal is usually 4 bits. That is, N = 4 in the N-bit data signal. At this time, the embodiment further provides a further implementation scheme: The register includes a first register, a second register, and a third register; wherein the first register is configured to store a first delay parameter corresponding to a received clock signal and a second delay parameter corresponding to a received control signal; the second register is configured to store a second delay parameter corresponding to a first bit and a second bit of a data signal; and the third register is configured to store a second delay parameter corresponding to a third bit and a fourth bit of the data signal.

[0091] Correspondingly, the method provided by the above embodiment includes the following steps when the first delay parameter / second delay parameter is configured in the register through the serial port debugging assistant: writing the first delay parameter / second delay parameter into the corresponding register through the address of the register corresponding to the first delay parameter / second delay parameter to be configured.

[0092] As known from the above, the embodiment takes two signals as a group, and stores the corresponding two delay parameters through one register. This can avoid the use of a too large register. In particular, in the case where the bit width of the register is usually a power of 2, the above setting can effectively avoid the waste of register resources.

[0093] Further, for the selection of the bit width of each register, the embodiment also provides a corresponding optional scheme: The input delay module has 2 M minimum delay units; wherein M is any positive integer. The delay value configuration bit is M bits, and the enable state bit and the inversion state bit are each 1 bit. The first register, the second register, and the third register are 2 K bit registers; wherein K is any positive integer, and 2 K is greater than or equal to 2M+3.

[0094] First, the bit width of the delay value configuration bit is not limited in the above embodiment. Therefore, the embodiment provides an example of the maximum bit width of the delay value configuration bit: the bit width of the delay value configuration bit meets the control needs of the finest granularity of the input delay module, that is, the number of different states included in the delay value configuration bit is consistent with the maximum number of different delays that can be supported by the input delay module, that is, 2 M. At this time, the register storing data in binary needs M-bit delay value configuration bits. Based on this, for the first delay parameter including the inverting state bit, the required register bit width = M+2, and for the second delay parameter not including the inverting state bit, the required register bit width = M+1. At this time, the first register corresponds to the received clock signal and the received control signal, i.e. corresponds to one first delay parameter and one second delay parameter, and the required bit width is maximum, 2M+3. The second register and the third register only correspond to two second delay parameters, and the required bit width is 2M+2. For convenience of implementation, the first, second and third registers adopt the same type and bit width of the register, and then the first register with the maximum required bit width is selected as the standard. Since the bit width of the register is usually a power of 2, i.e. 2 K , 2 K must be greater than or equal to 2M+3. For example, taking M=8, the register can select a 32-bit register.

[0095] For example, the meaning of each bit in the first register is as follows:

[32] : Inverting state bit: representing whether the received clock is inverted, 1 indicating that the received clock is inverted, and 0 indicating that the received clock is not inverted.

[0096]

[24] : Enable state bit of the received control signal: used to generate an edge signal of the received control signal enable.

[0097] [23:15]: Delay value configuration bit of the received control signal: representing the specific delay value of the received control signal.

[0098] [9]: Enable state bit of the received clock signal.

[0099] [8:0]: Delay value configuration bit of the received clock signal.

[0100] The meaning of each bit in the second register is as follows (4-bit data signals are represented by data 0~3):

[24] : Enable state bit of the received data 3.

[0101] [23:15]: Delay value configuration bit of the received data 3.

[0102] [9]: Enable state bit of the received data 2.

[0103] [8:0]: Delay value configuration bit of the received data 2.

[0104] The meaning of each bit in the third register is as follows:

[24] : Enable state bit of the received data 1.

[0105] [23:15]: Delay value configuration bit of data 1 on the receiving side.

[0106] [9]: Enable state bit of data 0 on the receiving side.

[0107] [8:0]: Delay value configuration bit of data 0 on the receiving side.

[0108] From the above, the embodiment provides a further register implementation scheme, which realizes the delay control of 6-way signals through 3 32-bit registers, guarantees the effective and independent delay control of various signals affecting the network connectivity test results when the BMC chip performs network function verification, and thus guarantees the reliability and integrity of the network function verification.

[0109] Further, when a plurality of registers are set as in the above embodiment, the user needs to further determine the address of the register to be configured when configuring the register through the serial port debugging assistant of the test machine, so as to write the delay parameter into the correct register.

[0110] In addition, the embodiment also provides an optional implementation scheme for how to realize the register configuration. The above steps of writing the first delay parameter / second delay parameter into the register specifically include: S31: In the universal bootloader stage, the value in the corresponding register is modified through a memory write command.

[0111] S32: After entering the kernel system, the corresponding register is accessed through a device memory access tool, and the value in the register is modified.

[0112] From the above, the embodiment provides a corresponding register configuration scheme for all stages possibly involved in the process of implementing the BMC chip network function verification through the FPGA device and the test set. It is guaranteed that the delay parameter can be configured in each stage of the BMC network function verification process, and the function verification is complete and flexible.

[0113] Specifically, in the universal bootloader (uboot) stage, the value in the corresponding register is modified through a memory write command (mw command). After the FPGA device loads the BMC system and starts, the test machine can access the kernel (kernel) system of the BMC chip through a serial port debugging assistant. At this time, the register configuration can be realized through a device memory access tool (such as a devmem command).

[0114] In another aspect, in the above embodiment, the value of the delay value configuration bit (i.e. the specific delay value) is not limited when adjusting the delay parameter each time. However, an alternative embodiment is provided, i.e. the adjustment is performed in a step-by-step (incremental) manner, so that the delay is constantly approaching the real requirement, and the network is connected. For this step-by-step incremental adjustment method, if the maximum granularity (i.e. the most precise control effect) is to be achieved, each step should be the smallest delay unit supported by the input delay module. For example, in the above example, IDELAY supports the adjustment of the smallest delay unit of 512 steps. However, the problem with this solution is that it may need to be repeated several times to find the delay value that can connect the network.

[0115] To solve the above problem, the present embodiment provides an alternative embodiment. The steps of the above embodiment for adjusting the first delay parameter / second delay parameter (mainly adjusting the delay value configuration bit, but in order to make the configuration effective, the enable state bit needs to be reset and then set, and the adjustment of the inverse state bit is discussed in the above embodiment, which is not discussed in the present embodiment) include: S41: adjusting the delay value configuration bit in a preset step; wherein the preset step is greater than the smallest delay unit and is an integer multiple of the smallest delay unit.

[0116] For example, still taking the delay processing of IDELAY supporting the smallest delay unit of 512 steps as an example, the preset step in the present embodiment can be set to 64 smallest delay units, i.e. 8-step delay adjustment, which can greatly reduce the number of step delay adjustment and improve the verification efficiency.

[0117] However, it is not difficult to know that the step adjustment scheme provided by the above embodiment is at the expense of accuracy, thereby improving the verification efficiency, so it is not essentially better than the 512-step scheme. Based on this, the present embodiment further provides an alternative embodiment based on the above scheme. After adjusting the first delay parameter / second delay parameter, the above method further includes: S42: determining whether the network connectivity test is successful; if the network connectivity test fails, returning to the step of adjusting the first delay parameter / second delay parameter.

[0118] S43: when the network connectivity test is successful for the first time, recording the value of the delay value configuration bit in the current first delay parameter / second delay parameter as the first delay value; and returning to the step of adjusting the first delay parameter / second delay parameter (such as step S41 above).

[0119] S44: when the network connectivity test fails for the first time after being successful, recording the value of the delay value configuration bit in the current first delay parameter / second delay parameter as the second delay value.

[0120] S45: determining the optimal delay value according to the average of the first delay value and the second delay value.

[0121] For example, the 512-step is supported by the IDelay, and the preset step is 64. After the embodiment, the possible step adjustment process is as follows: First, the first network connectivity test has no delay, that is, the step is 0. Assuming that the network connectivity test fails at this time, the step needs to be adjusted to 64 next time. After multiple step adjustments, assuming that the network connectivity test is found to be successful for the first time at the step of 128, the first delay value delay1=128 is recorded. Continue to adjust the delay value by step, until the network connectivity test is found to fail for the first time after being successful, assuming that the step is 448 (512-64), the second delay value delay2=448 is recorded. The optimal delay value delay0 can be determined based on (128+448) / 2=288.

[0122] As can be seen, the scheme provided by the embodiment on the one hand takes into account the advantage of fewer step adjustment times in the previous embodiment, and on the other hand can also realize more fine delay adjustment control. By recording the two delay values of the first successful network connectivity test and the first failure after being successful, the two endpoints of the network connected by different delays are determined, and then the midpoint (average value) is taken to obtain the optimal delay value, realizing more accurate delay control, taking into account efficiency and accuracy.

[0123] In the above embodiment, a chip prototype verification method is described in detail, and the present application also provides an embodiment of a corresponding chip prototype verification system. As shown in Figure 2 The chip prototype verification system provided by the embodiment includes a tester and a hardware platform, wherein serial communication and network communication are established between the tester and the hardware platform.

[0124] The hardware platform includes a field programmable logic gate array (FPGA) and a non-volatile storage medium (Flash chip). The field programmable logic gate array is used to perform code synthesis and layout routing on the code of the transplanted to-be-tested chip through a software tool to generate a data stream file. The non-volatile storage medium is used to store the data stream file.

[0125] Since the embodiments of the system part correspond to the embodiments of the method part, the embodiments of the system part are described in the description of the embodiments of the method part, and will not be described here.

[0126] The embodiment is directed to the specific structure of the Ethernet engineering module of the FPGA which can realize network function test of the BMC chip, and further description is made. As shown in Figure 4As shown in the figure, the FPGA-implemented Ethernet project includes a minimum system, an Ethernet controller, a mixed-mode clock management unit / phase-locked loop module, an input delay module, a bus interface module, and a register. The bus interface module is configured to convert data transmitted by the minimum system through the AHB bus into a read operation or a write operation on the register.

[0127] It should be noted that the minimum system is a common concept in the field of electronic circuits and has different connotations in different scenarios. In this embodiment, the minimum system refers to a framework for implementing the minimum system function in the FPGA. For example, as shown in the figure, Figure 4 As shown in the figure, the minimum system includes a central processing unit (CPU) in the SoC chip, a bus arbitration module, a firmware flash for storing the boot code of the CPU, a double-rate synchronous dynamic random access memory (DDR) memory, a serial port module, and the like, for loading the system of the SoC chip, simulating the functions to be verified of the SoC chip.

[0128] In addition, the main scenario targeted by the present application is to verify the network function of the BMC chip, and therefore the FPGA project also includes an Ethernet controller. In addition, there are some related modules for implementing signal delay processing, such as IDELAY, MMCM / PLL (providing clock), and a bus interface module (AHB bus interface data communication). Based on the bus interface module, the user can achieve delay control of the RX clock signal / control signal / data by configuring the register through the serial port. The user reads / writes the register on the serial port debugging assistant and sends it to the bus arbitration module in the system. The bus arbitration module is transmitted to the bus interface according to the address, and the bus interface module converts the data on the AHB bus into a read / write operation on the register.

[0129] It should be noted that the FPGA Ethernet project structure provided in this embodiment is only one optional implementation scheme, which is simple in structure and can meet the needs of verifying the network function of the BMC chip, and is a relatively optimal implementation scheme. In actual applications, the hardware in the above structure can be increased or reduced without affecting the verification of the network function of the BMC chip for other aspects, and this embodiment does not limit this.

[0130] For example, this embodiment provides a further implementation scheme on the basis of the above embodiment. As shown in the figure, Figure 4 As shown in the figure, the FPGA-implemented Ethernet project further includes a cross-clock domain processing module.

[0131] The cross-clock domain processing module is configured to: implement synchronization processing of the reset signal; transfer the value of the register in the high-level high-performance bus clock domain to the clock domain of the mixed mode clock management unit / phase-locked loop module; and generate a delay effective signal, which is a signal for resetting and regenerating the corresponding enable state bit.

[0132] That is, the cross-clock domain processing module is configured to implement the processing part for realizing the cross-clock domain in the above-mentioned method embodiment. Specifically, the cross-clock domain processing module is configured to: implement synchronization processing of the reset signal; transfer the value of the register in the AHB bus clock domain to 300 Mbps provided by the MMCM / PLL; and generate a signal for delaying configuration taking effect, that is, clear and reset the enable state bit to generate a specific edge (such as a rising edge) to trigger configuration taking effect.

[0133] Based on the setting of the cross-clock domain processing module, the function logic of the cross-clock domain processing part in the above-mentioned method is independently implemented, so as to avoid affecting other components for BMC network function testing in the FPGA and ensure the reliability of chip prototype verification.

[0134] In addition to the embodiment of the chip prototype verification method provided in the above-mentioned embodiment, the present application also provides an embodiment of a corresponding computer program product. The computer program product comprises computer programs / instructions, and when the computer programs / instructions are executed by a processor, the steps of the chip prototype verification method according to any one of the above-mentioned embodiments can be implemented.

[0135] Since the embodiment of the computer program product part corresponds to the embodiment of the method part, the embodiment of the computer program product part is described in the description of the embodiment of the method part, and will not be described here.

[0136] In the above-mentioned embodiment, a chip prototype verification method is described in detail, and the present application also provides an embodiment of a corresponding chip prototype verification device. It should be noted that the embodiment of the device part is described from two angles, one is based on the functional module, and the other is based on the hardware.

[0137] Based on the functional module, as shown in Figure 5 The embodiment of the present application provides a chip prototype verification device, which comprises: The network test module 11 is configured to perform network connectivity testing on the to-be-tested chip and the test machine through a network connectivity testing tool command in a serial port debugging assistant. The parameter configuration module 12 is configured to, when the network connectivity testing fails, configure a first delay parameter of a received clock signal in a register through the serial port debugging assistant. Delay processing module 13 is used to perform delay processing on the received clock signal based on the first delay parameter and through the input delay module; The parameter adjustment module 14 is used to readjust the first delay parameter and trigger the parameter configuration module if the network connectivity test still fails after the delay processing.

[0138] Since the embodiments of the apparatus and the embodiments of the method correspond to each other, please refer to the description of the embodiments of the method for the embodiments of the apparatus, which will not be repeated here.

[0139] Figure 6 A structural diagram of a chip prototype verification device provided in another embodiment of the present invention is shown below. Figure 6 As shown, a chip prototype verification device includes: a memory 20 for storing computer programs; The processor 21 is used to execute a computer program to implement the steps of a chip prototype verification method as described in the above embodiment.

[0140] The chip prototype verification device provided in this embodiment may include, but is not limited to, personal computers, FPGAs, etc.

[0141] The processor 21 may include one or more processing cores, such as a quad-core processor or an octa-core processor. The processor 21 may be implemented using at least one of the following hardware forms: Digital Signal Processor (DSP), Field-Programmable Gate Array (FPGA), or Programmable Logic Array. The processor 21 may also include a main processor and a coprocessor. The main processor, also known as the Central Processing Unit (CPU), is used to process data in the wake-up state; the coprocessor is a low-power processor used to process data in the standby state. In some embodiments, the processor 21 may integrate a Graphics Processing Unit (GPU), which is responsible for rendering and drawing the content to be displayed on the screen. In some embodiments, the processor 21 may also include an Artificial Intelligence (AI) processor, which is used to handle computational operations related to machine learning.

[0142] The memory 20 can include one or more computer-readable storage media. The memory 20 can also include high-speed random access memory and non-volatile, computer-readable storage media such as one or more magnetic disk storage devices, flash memory devices. In this embodiment, the memory 20 is used to store at least the following computer program 201, wherein the computer program is loaded and executed by the processor 21, and can implement the steps of the chip prototype verification method disclosed in any of the preceding embodiments. In addition, the resources stored in the memory 20 can also include an operating system 202 and data 203, and the storage mode can be temporary storage or permanent storage. The operating system 202 can include Windows, Unix, Linux, etc. The data 203 can include but is not limited to a chip prototype verification method, etc.

[0143] In some embodiments, the chip prototype verification device can further include a display screen 22, an input / output interface 23, a communication interface 24, a power supply 25, and a communication bus 26.

[0144] Those skilled in the art can understand that the structure shown in the above embodiments does not constitute a limitation on the chip prototype verification device, and can include more or fewer components than those shown in the figure. Figure 6

[0145] The chip prototype verification device provided by the embodiments of the present application includes a memory and a processor, and the processor can implement the following method when executing the program stored in the memory: a chip prototype verification method.

[0146] Finally, the present application also provides an embodiment corresponding to a non-volatile storage medium. The non-volatile storage medium stores a computer program, and the computer program is executed by the processor to implement the steps described in the above method embodiments.

[0147] It can be understood that if the method in the above embodiments is implemented in the form of a software function unit and sold or used as an independent product, it can be stored in a non-volatile storage medium. Based on this understanding, the technical solutions of the present application essentially or the part that contributes to the prior art or the whole or part of the technical solutions can be embodied in the form of a software product. The computer software product is stored in a storage medium, and executes all or part of the steps of the method described in each embodiment of the present application. The foregoing storage medium includes: a U disk, a mobile hard disk, a read-only memory (Read-Only Memory, ROM), a random access memory (Random Access Memory, RAM), a magnetic disk or an optical disk, and various media that can store program codes.

[0148] ​The chip prototype verification method, system, device and medium provided by the present application are described in detail above. Each embodiment in the specification is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts of each embodiment can be understood by mutual reference. For the device disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple, and the relevant parts can be understood by referring to the method part. It should be pointed out that, for ordinary technical personnel in the technical field, some improvements and modifications can be made to the present application without departing from the principles of the present application, and these improvements and modifications also fall within the protection scope of the present application.

[0149] It should also be noted that in this specification, relationship terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between the entities or operations. Moreover, the terms "include", "contain" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such process, method, article or device. Without further limitation, the element defined by the statement "including a" does not exclude the presence of other identical elements in the process, method, article or device including the element.

Claims

1. A method of chip prototyping, the method comprising: The method comprises the following steps: testing network connectivity between the chip under test and the tester through the network connectivity test tool command in the serial port debugging assistant; when the network connectivity test fails, configuring a first delay parameter of a receiving clock signal in a register through the serial port debugging assistant; delaying the receiving clock signal based on the first delay parameter through an input delay module; if the network connectivity test still fails after the delaying, readjusting the first delay parameter and returning to the step of configuring the first delay parameter of the receiving clock signal in the register through the serial port debugging assistant; the first delay parameter comprises an enable state bit, an inversion state bit and a delay value configuration bit; the delay value configuration bit takes effect when the enable state bit changes from an initial state to an effective state; the enable state bit is reset and then takes effect again every time the first delay parameter is configured; the inversion state bit takes effect when the input delay module cannot meet the minimum delay requirement of the receiving clock signal; the receiving clock signal is delayed through an inverter when the inversion state bit takes effect.

2. The chip prototyping method of claim 1, wherein, before the step of configuring the first delay parameter of the receiving clock signal in the register through the serial port debugging assistant, the method further comprises the following steps: determining whether a sending action performed by the chip under test during the network connectivity test is successful; if not, measuring a phase difference between a sending clock signal and a sending control signal, adjusting the phase of the sending clock signal through an engineering change instruction, and returning to the step of determining whether the sending action performed by the chip under test during the network connectivity test is successful.

3. The chip prototyping method of claim 2, wherein, after the step of determining whether the sending action performed by the chip under test during the network connectivity test is successful, the method further comprises the following steps: if yes, obtaining a post-engineering layout and routing timing report, and checking a wiring delay between a receiving control signal and each bit of data signal in the post-engineering layout and routing timing report; if the wiring delay between the receiving control signal and any bit of data signal is greater than a wiring delay threshold, adjusting a phase difference between the receiving control signal and the data signal.

4. The chip prototyping method of claim 3, wherein, the step of adjusting the phase difference between the receiving control signal and the data signal comprises the following steps: configuring a second delay parameter of the receiving control signal and / or the data signal in a register through the serial port debugging assistant; the second delay parameter comprises the enable state bit and the delay value configuration bit; delaying the receiving control signal and / or the data signal based on the second delay parameter through the input delay module.

5. The chip prototyping method of claim 4, wherein, the data signal has N bits; N is any positive integer; the input delay module has N+2 input delay modules corresponding to the receiving clock signal, the receiving control signal and the N bits of data signal; the delaying action performed by each input delay module is controlled by the corresponding delay parameter stored in the register.

6. The chip prototyping method of claim 5, wherein, N=4； The registers include: a first register, a second register and a third register; wherein the first register is used to store the first delay parameter corresponding to the receiving clock signal and the second delay parameter corresponding to the receiving control signal; the second register is used to store the second delay parameter corresponding to the first bit and the second bit of the data signal; and the third register is used to store the second delay parameter corresponding to the third bit and the fourth bit of the data signal. The configuration of the first delay parameter / second delay parameter in the registers through the serial debugging assistant includes: Writing the first delay parameter / second delay parameter into the corresponding register through the address of the register corresponding to the first delay parameter / second delay parameter to be configured.

7. The chip prototyping method of claim 6, wherein, The writing of the first delay parameter / second delay parameter into the corresponding register includes: Modifying the value in the corresponding register through a memory write command in a universal bootloader stage; Accessing the corresponding register through a device memory access tool and modifying the value in the register after entering a kernel system.

8. The chip prototyping method of claim 6, wherein, The input delay module exists 2 M minimum delay units; wherein M is any positive integer; The delay value configuration bit is M bits, and the enable state bit and the inversion state bit are each 1 bit; The first register, the second register and the third register are 2 K bit registers; where K is any positive integer, and 2 K greater than or equal to 2M+3.

9. The chip prototyping method of claim 8, wherein, The adjustment of the first delay parameter / second delay parameter includes: Adjusting the delay value configuration bit by a preset step; wherein the preset step is greater than the minimum delay unit and is an integer multiple of the minimum delay unit.

10. The chip prototyping method of claim 9, wherein, After adjusting the first delay parameter / second delay parameter, it further includes: Determining whether the network connectivity test is successful; if the network connectivity test fails, returning to the step of adjusting the first delay parameter / second delay parameter; When the network connectivity test is successful for the first time, recording the value of the delay value configuration bit in the current first delay parameter / second delay parameter as a first delay value; and returning to the step of adjusting the first delay parameter / second delay parameter; When the network connectivity test fails for the first time after being successful, recording the value of the delay value configuration bit in the current first delay parameter / second delay parameter as a second delay value; Determining an optimal delay value according to the average of the first delay value and the second delay value.

11. The chip prototyping method according to any one of claims 1 to 10, wherein The adjustment of the first delay parameter includes: The inversion state bit is in a non-effective state by default; When the delay value configuration bit of the first delay parameter is configured as a maximum value, if the network connectivity test still fails, the inversion state bit is configured as an effective state.

12. The chip prototyping method of claim 2, wherein, The network connectivity test of the chip under test and a test machine through a network connectivity test tool command in a serial debugging assistant includes: Configuring a network for the chip under test through the serial debugging assistant, and configuring the network segment of the test machine as the same network segment as the chip under test; Commanding the chip under test to send a request to the test machine through the serial debugging assistant, and checking whether the chip under test receives a response returned by the test machine through the serial debugging assistant; If the request is received, it is determined that the network connectivity test is successful; otherwise, it is determined that the network connectivity test fails.

13. The chip prototyping method of claim 12, wherein, The determining whether the sending action performed by the chip under test when performing the network connectivity test is successful comprises: The sending action is determined to be successful if the request sent by the chip under test is received by network packet analysis software deployed on the tester; otherwise, the sending action is determined to fail.

14. A chip prototyping system, comprising: The chip prototype verification method comprises the following steps: The tester and the hardware platform; The tester and the hardware platform are connected through serial communication and network communication. The hardware platform comprises a field programmable logic gate array and a non-volatile storage medium. The field programmable logic gate array is configured to perform code synthesis and layout routing on the code of the chip under test through a software tool to generate a data stream file. The non-volatile storage medium is configured to store the data stream file.

15. The chip prototyping system of claim 14, wherein, The field programmable logic gate array comprises a minimum system, an Ethernet controller, a mixed mode clock management unit / phase-locked loop module, an input delay module, a bus interface module, and a register. The bus interface module is configured to convert data sent by the minimum system through an advanced high-performance bus into a read operation or a write operation on the register.

16. The chip prototyping system of claim 15, wherein, The field programmable logic gate array comprises a cross-clock domain processing module. The cross-clock domain processing module is configured to synchronize the reset signal, transfer the value of the register in the advanced high-performance bus clock domain to the clock domain of the mixed mode clock management unit / phase-locked loop module, and generate a delay valid signal, which is a signal for resetting and regenerating the corresponding enable state bit.

17. A chip prototyping device, comprising: The chip prototype verification method comprises the following steps: The network test module is configured to perform network connectivity testing on the chip under test and the tester through a network connectivity testing tool in a serial debug helper. The parameter configuration module is configured to configure a first delay parameter of a receive clock signal in a register through the serial debug helper when the network connectivity test fails. The delay processing module is configured to perform delay processing on the receive clock signal through an input delay module based on the first delay parameter. The parameter adjustment module is configured to re-adjust the first delay parameter and trigger the parameter configuration module if the network connectivity test still fails after delay processing.

18. A computer program product comprising computer programs / instructions, characterized in that, The computer program / instruction is executed by the processor to implement the steps of the chip prototype verification method according to any one of claims 1 to 13.

19. A chip prototyping device, comprising: The chip prototype verification method comprises the following steps: The memory is configured to store a computer program. The processor is configured to execute the computer program to implement the steps of the chip prototype verification method according to any one of claims 1 to 13.

20. A non-volatile storage medium, comprising: The non-volatile storage medium stores a computer program, and the computer program is executed by the processor to implement the steps of the chip prototype verification method according to any one of claims 1 to 13.

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