Embedded germanium-silicon devices and their fabrication methods, electronic devices

Abstract

This application relates to an embedded germanium-silicon device and its fabrication method, as well as an electronic device, comprising: providing a substrate; the substrate having sigma trenches extending into the substrate via a first surface; forming a buffer layer on the inner surface of the sigma trench, followed by forming a germanium-ene transition layer covering the buffer layer; the germanium-ene transition layer including protrusions formed due to lattice mismatch and local stress in the initial buffer layer; selectively etching and removing the protrusions and the buffer layer covering the protrusions using a pulsed plasma etching process; simultaneously repairing damage to the buffer layer and removing the germanium-ene transition layer in the same process steps; and forming a germanium-silicon seed layer that at least fills the sigma trench. This method can avoid the risk of impurity contamination, reduce the dislocation density of the buffer layer, and improve the growth quality of silicon-germanium.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to an embedded germanium-silicon device and its fabrication method, as well as electronic equipment. Background Technology

[0002] As semiconductor device sizes continue to shrink, the pursuit of higher performance and lower power consumption becomes increasingly urgent. Embedded germanium-silicon devices form embedded silicon-germanium / silicon-carbon source-drain structures (i.e., e-SiGe / e-SiC) by epitaxially growing silicon-germanium or silicon-carbon in source-drain grooves (PSR / NSR) formed by etching the source-drain regions. This provides compressive stress extrusion channels or tensile stress stretching channels to suppress short-channel effects.

[0003] In the fabrication of embedded germanium-silicon devices, a common technique involves growing a buffer layer with a gradient germanium concentration on a silicon substrate to alleviate lattice mismatch stress. However, due to the mismatch between the epitaxially grown SiGe buffer layer and the lattice constant of the silicon substrate, the buffer layer's quality is often suboptimal. This significantly increases the likelihood of dislocations forming in the seed layer, impairing device performance. Ultimately, this severely negatively impacts the critical electrical properties of embedded germanium-silicon devices, such as carrier mobility, drive current, and leakage current, severely limiting improvements in device performance and product yield. Summary of the Invention

[0004] Based on this, it is necessary to address the technical problems in the existing technology by providing an embedded germanium-silicon device and its fabrication method, as well as an electronic device, which can at least improve the quality of the germanium-silicon seed layer in the sigma trench.

[0005] In a first aspect, this application provides a method for fabricating an embedded germanium-silicon device, comprising: providing a substrate; the substrate including a sigma trench extending into the substrate via a first surface of the substrate;

[0006] After an initial buffer layer is formed on the inner surface of the sigma trench, a germanene transition layer is formed covering the initial buffer layer; the germanene transition layer includes protrusions formed due to lattice mismatch and local stress in the initial buffer layer.

[0007] The protrusions and the portion of the initial buffer layer covered by the protrusions were selectively etched and removed using a pulsed plasma etching process.

[0008] In the same process steps, the initial buffer layer is simultaneously damaged and repaired to obtain the target buffer layer, and the germanene transition layer is removed.

[0009] On the top surface of the target buffer layer, a germanium-silicon seed layer is formed that at least fills the sigma trench.

[0010] In the above-described method for fabricating embedded germanium-silicon devices, a germanene transition layer is grown on a buffer layer containing surface damage. Utilizing its sensitive strain response characteristics, the germanene transition layer spontaneously forms wrinkles (i.e., protrusions) at the damaged areas of the buffer layer due to lattice mismatch and local stress. Because the protrusions have greater local curvature, the electric field is enhanced at the peak (radius of curvature effect). During plasma etching, free radicals generated by plasma dissociation migrate directionally towards the protrusions under the drive of the electric field gradient, efficiently and selectively etching the protrusions and the area covered at the bottom to remove the damaged buffer layer. Finally, the surface lattice damage of the buffer layer is repaired, achieving lattice reconstruction, avoiding the risk of impurity contamination, reducing the dislocation density of the buffer layer, and improving the growth quality of the germanium-silicon seed layer.

[0011] In some embodiments, the initial buffer layer comprises germanium-silicon;

[0012] Selective etching using pulsed plasma etching process includes:

[0013] Based on the set processing conditions, fluorine-containing plasma etching with inert gas was used to remove the protrusions and part of the germanene transition layer.

[0014] In some embodiments, a nitrogen trifluoride plasma containing argon is used to remove the protrusions and part of the germanene transition layer;

[0015] The gas flow ratio of nitrogen trifluoride to argon is 1:5 to 1:10.

[0016] In some embodiments, the process conditions include at least one of the following features:

[0017] The plasma radio frequency power supply operates at a frequency of 8Hz-12Hz;

[0018] Pulse duty cycle 10%-30%;

[0019] The processing time ranges from 5s to 180s;

[0020] The output power of the RF power supply is no more than 80W.

[0021] In some embodiments, damage repair is performed on the initial buffer layer, and the germanene transition layer is removed, including:

[0022] In the target gas environment, while removing the germanene transition layer, the initial buffer layer is simultaneously repaired, and the dangling bonds on the surface of the initial buffer layer are saturated.

[0023] In some embodiments, the substrate is annealed in a hydrogen atmosphere based on the set annealing temperature and annealing time.

[0024] The annealing temperature range is 300℃-400℃;

[0025] The annealing time ranges from 10s to 30s.

[0026] In some embodiments, the substrate includes gates spaced apart along a first direction parallel to a first surface of the substrate;

[0027] Sigma trenches are located between adjacent gates.

[0028] In some embodiments, forming an initial buffer layer includes:

[0029] An initial buffer layer is formed using an epitaxial growth process, and the remaining sigma trenches are used to form grooves; the width of the grooves remains constant in the direction toward the substrate and then gradually decreases.

[0030] The width is used to characterize the dimension along a first direction parallel to the first surface.

[0031] Secondly, this application also provides an embedded germanium-silicon device, fabricated using the fabrication method described in any of the above embodiments. The fabrication method provided by this application can effectively solve the problems of poor buffer layer quality and easy dislocation generation in germanium-silicon seed layers in related technologies, thereby significantly improving the key electrical performance of embedded germanium-silicon devices in terms of carrier mobility, drive current, and leakage current.

[0032] Thirdly, this application also provides an electronic device, including the embedded germanium-silicon device as described in the above embodiments. The novel fabrication method provided by this application can effectively improve the electrical performance of the embedded germanium-silicon device, and is expected to help the chip achieve higher performance and lower power consumption, laying the foundation for the advancement of integrated circuit technology to a higher level.

[0033] The embedded germanium-silicon device, its fabrication method, and the electronic device provided in this application have the following unexpected technical effects:

[0034] To address the issues of dislocation formation and surface defects in SiGe buffer layers grown in related technologies, this application provides a method for selectively repairing SiGe crystal damage and maintaining atomic-level flatness at low temperatures. By utilizing a monolayer germanene, a near-two-dimensional material, dislocation defects within the buffer layer are targeted and located. Then, NF3 / Ar pulse etching is used to selectively remove the corresponding damaged areas. Finally, H2 annealing repairs the etched damage while optimizing the surface state of the buffer layer, achieving atomic-level flatness. This provides conditions for high-quality seed layer nucleation, contributing to improved device performance and product yield. Attached Figure Description

[0035] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0036] Figure 1 A schematic cross-sectional view of the structure obtained from each step of the relevant technical process;

[0037] Figure 2 This is a schematic flowchart of a method for fabricating an embedded germanium-silicon device according to an embodiment of this application;

[0038] Figure 3a This is a cross-sectional schematic diagram of the structure obtained after forming the initial trench in step S102 of the preparation method provided in one embodiment of this application;

[0039] Figure 3b for Figure 3a A schematic diagram of the cross-section of the structure after sigma trenches are formed;

[0040] Figure 4a This is a cross-sectional schematic diagram of the structure obtained after forming the initial buffer layer and the germanene transition layer in step S104 of the preparation method provided in one embodiment of this application.

[0041] Figure 4b for Figure 4a Microscopic image of the inner surface of the groove in the image;

[0042] Figure 5 This is a cross-sectional schematic diagram of the structure obtained after removing the protrusion and part of the buffer layer in step S106 of the preparation method provided in one embodiment of this application.

[0043] Figure 6 This is a cross-sectional schematic diagram of the structure obtained after removing the germanene transition layer and obtaining the target buffer layer in step S108 of the preparation method provided in one embodiment of this application.

[0044] Figure 7 This is a cross-sectional schematic diagram of the structure obtained after forming a germanium-silicon seed crystal layer in step S110 of the preparation method provided in one embodiment of this application.

[0045] Figure 8 The image shows a comparison of the morphology of the germanium-silicon seed crystal layer formed by the related techniques and the preparation method of this application.

[0046] Explanation of reference numerals in the attached figures:

[0047] 10. Substrate; 20. Sigma trench; 201. Initial trench; 202. Groove; 21. Initial buffer layer; 22. Germanene transition layer; 221. Protrusion; 23. Target buffer layer; 30. Germanium-silicon seed layer. Detailed Implementation

[0048] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate preferred embodiments of the application. However, this application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0049] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0050] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, parts, regions, layers, doping types, and / or portions, these elements, parts, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, part, region, layer, doping type, or portion from another element, part, region, layer, doping type, or portion. Therefore, without departing from the teachings of this application, the first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0051] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “below,” “under,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.

[0052] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that when the terms “comprise” and / or “comprising” are used in this specification, the presence of the stated feature, integer, step, operation, element, and / or part is established, but the presence or addition of one or more other features, integers, steps, operations, elements, parts, and / or groups is not excluded. Meanwhile, when used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0053] Embodiments of the invention are described herein with reference to cross-sectional views illustrating ideal embodiments (and intermediate structures) of this application, thus allowing for variations in the illustrated shapes due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of this application should not be limited to the specific shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing techniques. For instance, implantation regions shown as rectangular typically have rounded or curved features at their edges and / or implantation concentration gradients, rather than a binary change from implantation regions to non-implantation regions. Similarly, the buried regions formed by implantation can result in some implantation in the region between the buried region and the surface traversed during implantation. Therefore, the regions shown in the figures are substantially schematic, and their shapes do not represent the actual shapes of regions of the device and do not limit the scope of this application.

[0054] As advanced devices continue to miniaturize, the thickness of the SiGe epitaxial layer within the sigma trench in embedded silicon germanium (SiGe) devices has significantly decreased, necessitating a higher germanium concentration gradient to alleviate lattice mismatch stress. However, a high gradient can induce dislocation multiplication, resulting in an uneven and rough surface morphology. Quality defects (dislocations, surface roughness) in the buffer layer can be directly transferred and severely degrade the epitaxial quality of the SiGe bulk layer with the target high germanium concentration grown on it.

[0055] In related technologies, high-temperature etching with hydrochloric acid (HCl) is often used to optimize the epitaxial quality of SiGe buffer layers. Figure 1 The diagram shows cross-sectional schematics of the structures obtained at each step of the specific process flow. Due to the anisotropy of HCl etching, the {111} crystal plane is over-etched, and the superimposed etching back effect alters the morphology of the original buffer layer, which is not conducive to the subsequent growth of the seed layer. In addition, under high temperature conditions, boron (B) and phosphorus (P) impurities in the silicon substrate are more easily activated, causing the junction diffusion and drift in the active region, which damages the electrical characteristics of the device.

[0056] Based on this, please refer to Figure 2 This application provides a method for fabricating a semiconductor structure, including steps S102-S110. In this embodiment, the substrate may include a first surface located on the front side and a back surface, i.e., a second surface, opposite to the front side. Ignoring the flatness of the first and second surfaces, a first direction parallel to the first surface is defined, and the direction toward the substrate includes a second direction perpendicular to the first surface of the substrate. The first and second directions are perpendicular to each other. In this embodiment, the first direction is defined as the Y-axis direction, and the second direction is defined as the Z-axis direction.

[0057] The specific method is as follows:

[0058] Step S102: Provide a substrate 10; the substrate 10 includes a sigma trench 20 extending into the substrate via a first surface 10a of the substrate 10.

[0059] Step S104: After forming an initial buffer layer 21 on the inner surface of the sigma trench 20, a germanene transition layer 22 is formed covering the initial buffer layer 21; the germanene transition layer 22 includes protrusions 221 formed due to lattice mismatch and local stress of the initial buffer layer 21.

[0060] Step S106: Selectively etch and remove the protrusion 221 and the portion of the initial buffer layer 21 covered by the protrusion 221 using a pulsed plasma etching process.

[0061] Step S108: In the same process step, the initial buffer layer 21 is damaged and repaired to obtain the target buffer layer 23, and the germanene transition layer 22 is removed.

[0062] Step S110: On the top surface of the target buffer layer 23, a germanium-silicon seed layer 30 is formed that at least fills the sigma trench 20.

[0063] The embedded germanium-silicon device obtained after steps S102-S110 can be found in [reference]. Figure 7 For the purpose of understanding this application, it should be understood that... Figure 7This application provides an example of an embedded germanium-silicon device fabricated using the method described herein. Other suitable examples of embedded germanium-silicon devices fabricated using this application are also possible, and no limitations are imposed herein.

[0064] The following is combined Figures 3a to 7 The steps of the embedded germanium-silicon device formation method in this embodiment are described in detail below:

[0065] Please see Figures 3a-3b In the extension step of step S102, the following steps are included: firstly, gates (not shown) spaced apart along the OY direction and sidewall structures (not shown) covering the gate sidewalls are formed on the first surface 10a of the substrate 10; subsequently, photolithography and etching are performed on the substrate 10 to obtain initial trenches 201 extending along the OZ direction between the sidewall structures, as shown in the specific structure. Figure 3a As shown. Utilizing the etching selectivity ratio of tetramethylammonium hydroxide (TMAH) solution, which allows for greater etching rates on the {100} and {110} crystal planes of the silicon substrate than on the {111} crystal plane, the initial trench 201 was subjected to plane-selective wet etching to further obtain the sigma trench 20, as shown in the figure. Figure 3b As shown.

[0066] For example, substrate 10 can be a single-layer structure or a multi-layer structure. For instance, the substrate may include Si / SiGe, Si / SiC, silicon-on-insulator (SOI), or silicon-germanium-on-insulator substrates. A shallow trench isolation structure (STI) can be formed within substrate 10, isolating several spaced-apart active areas (AA) within the substrate 10. The active areas can be P-type or N-type active areas. P-type active areas can form NMOS devices, and N-type active areas can form PMOS devices. When forming a PMOS transistor, the buffer layer material is silicon-germanium; when forming an NMOS transistor, the buffer layer material is silicon-carbon. In the embodiments mentioned in this application, the embedded germanium-silicon device to be formed is a PMOS transistor structure.

[0067] Please see Figures 4a-4b Step S104: SiGe with a high germanium concentration gradient is formed as an initial buffer layer 21 through epitaxial growth. The remaining sigma trenches 20 are used to form the grooves 202. On the inner surface of the grooves 202, a germane thin film can be epitaxially grown at a temperature of 200℃-300℃, followed by thermal annealing to remove hydrogen, forming a germanene transition layer 22; alternatively, a germanene transition layer 22 can be directly deposited in an ultra-high vacuum (UHV) environment using molecular beam epitaxy (MBE) technology. The specific structure obtained is as follows: Figure 4a As shown.

[0068] Specifically, the width of groove 202 (its dimension along the OY direction) initially remains constant in the OX direction, then gradually decreases. Germanene, as a graphene-like two-dimensional material, during epitaxial growth on the SiGe surface, exhibits a sensitive response to compressive strain, spontaneously forming wrinkled structures due to lattice mismatch and localized stress. Its microstructure is as follows: Figure 4b As shown in the figure, F· represents the F free radical, E represents the electric field, and the protrusion is the protrusion 221.

[0069] Please see Figure 5 Step S106: Based on the set processing conditions, selective etching with fluorine-containing plasma containing inert gas is used to remove the protrusion 221 and part of the germanene transition layer 22.

[0070] For example, the plasma radio frequency power supply operates at a frequency of 8Hz-12Hz, such as 8Hz, 9Hz, 10Hz, 11Hz or 12Hz; the pulse duty cycle is 10%-30%, such as 10%, 20% or 30%; the processing time ranges from 5s to 180s, such as 5s, 50s, 100s, 150s or 180s; and the output power of the radio frequency power supply is no greater than 80W, such as 60W, 70W or 80W.

[0071] For example, the fluorine-containing reactive gas can be selected from, but is not limited to, chlorine difluoride (ClF₂O) or nitrogen trifluoride (NF₃); the inert gas includes, but is not limited to, one or more of argon (Ar), helium (He), or nitrogen (N). When using NF₃, the ratio of NF₃:Ar must be 1:5 to 1:10. Because the local curvature of the wrinkled region is significantly higher than that of the flat surface, the electric field is significantly enhanced at the peak. The F radicals generated by the dissociation of NF₃ migrate directionally towards the protrusion 221, which serves as a positioning marker, driven by the electric field gradient, resulting in a local concentration that is more than five times higher than in other regions, thereby achieving targeted etching of the damaged buffer layer. On the other hand, in the healthy lattice region of the buffer layer covered by the remaining germanene transition layer 22, the etching rate remains at an extremely low level because the diffusion of F radicals is suppressed and the surface dangling bonds are saturated.

[0072] Furthermore, in this embodiment, the process conditions are set as follows: temperature below 250°C, pulse duty cycle 10%-30%, operating frequency 10Hz, and output power ≤80W. By reasonably setting the pulse duty cycle, the operating frequency of the radio frequency power supply (RF), and its output power, the diffusion of by-products can be effectively promoted to reduce redeposition by means of an appropriate off-period, desorption balance can be achieved by matching the surface reaction kinetics cycle, and the proportion of high-energy electrons can be suppressed to reduce ion bombardment damage, thereby ensuring the quality of the germanium-silicon seed layer 30 subsequently formed in the groove 202.

[0073] For example, the processing time is related to the damage depth of the buffer layer to be removed. In this embodiment, the processing time ranges from 5s to 180s, enabling the directional removal of a 5nm-20nm damaged area on the surface of the buffer layer. The etching rate difference between the germanene protrusions and other flat areas is fully utilized; that is, when the damaged layer is completely removed and the complete SiGe lattice is exposed, the etching rate automatically and significantly decreases, thereby avoiding over-etching of the underlying substrate. The etching endpoint can be aided by monitoring the intensity of the characteristic peaks of germanium tetrafluoride (GeF4) using in-situ optical emission spectroscopy (OES). Using the preparation method described in this application, combined with this OES monitoring method, the deviation control accuracy of the etching depth can be stably achieved to ±0.3 nm.

[0074] Compared to the process method that uses high-temperature HCl etching back to optimize the quality of the buffer layer, the preparation method provided in this application has a lower etching temperature, which is not only safer and more controllable, but also suppresses the diffusion of dopant elements, thus contributing to improved device stability. Furthermore, F is lighter than Cl, resulting in a gentler bombardment of the Si surface and better suppression of amorphization damage. In addition, Ar, as an auxiliary gas, mainly provides an inert gas environment through physical sputtering and interaction with the buffer layer surface, suppressing microtrench formation while promoting isotropic etching and reducing the risk of surface contamination of the SiGe buffer layer.

[0075] In some embodiments, by designing tilted electrodes to optimize the ion incident angle distribution, the convex side is bombarded uniformly, further avoiding the formation of microgrooves.

[0076] Please see Figure 6 Step S108: In an annealing environment of hydrogen (H2) at an annealing temperature of 300℃-400℃, a time of 10s-30s, and a pressure of 1Torr-10Torr, while removing the germanene transition layer 22, the initial buffer layer 21 is simultaneously repaired to obtain the target buffer layer 23.

[0077] For example, the annealing temperature can be 300℃, 350℃ or 400℃, etc.; the annealing time can be 10s, 20s or 30s, etc.; the pressure can be 1 Torr, 5 Torr or 10 Torr, etc.

[0078] Specifically, the germanene transition layer 22 is converted into gaseous germane (GeH4↑) by H2 and removed from the inner surface of the groove 202 by volatilization. The Si / Ge dangling bonds on the surface of the initial buffer layer 21 are saturated by H free radicals, thereby effectively inhibiting oxidation and reducing the interface state density. The H2 atmosphere can also promote the migration ability of the surface atoms of the buffer layer, enabling them to spontaneously fill the surface micro-pits, and finally achieve the repair and global smoothing of the buffer layer.

[0079] Please see Figure 7Step S110: A germanium-silicon seed layer 30 may be formed in the groove 202 using any of the following processes, including but not limited to Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), and High Density Plasma (HDP). The thickness of the target buffer layer 23 is less than the thickness of the germanium-silicon seed layer 30, and its germanium content is less than that of the germanium-silicon seed layer 30.

[0080] It should be understood that, although Figure 2 The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order requirement for the execution of these steps; they can be executed in other orders. Furthermore, Figure 2 At least some of the steps in the process may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least some of the steps or stages in other steps.

[0081] Please see Figure 8 In some embodiments, this application also provides an embedded germanium-silicon device, which is prepared using the preparation method described in any of the above embodiments. Figure 8 (a) shows a schematic diagram of the morphology of the germanium-silicon seed layer in the related technology. Figure 8 Image (b) shows a schematic diagram of the morphology of the germanium-silicon seed layer obtained by the preparation method provided in this application. As can be seen from the comparison of the morphology images, the germanium-silicon (SiGe) seed layer grown on the surface of the repaired target buffer layer has a lower dislocation density and a higher surface flatness compared with related technology products.

[0082] In some embodiments, this application also provides an electronic device including the embedded germanium-silicon device described in the above embodiments. Since the electronic device in the above embodiments and the embedded germanium-silicon device and its preparation method provided by the present invention are based on the same inventive concept, the electronic device using this embedded germanium-silicon device has all the advantages of the preparation method provided by the present invention, which will not be elaborated here.

[0083] In the above embodiments, the unexpected technical effect of this application is:

[0084] Compared to processes that use high-temperature HCl etching back to optimize buffer layer quality, the fabrication method provided in this application first grows a low-quality initial buffer layer at the bottom of the sigma trench. Then, by utilizing the strain response characteristics of a single layer of germanene, a near-two-dimensional material, dislocation defects within the initial buffer layer are precisely marked. Next, NF3 / Ar pulse etching is used to selectively remove the corresponding damaged areas, while in-situ annealing achieves lattice reconstruction, avoiding the risk of impurity contamination and providing conditions for high-quality seed layer nucleation. This contributes to improved device performance and product yield.

[0085] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0086] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A method for fabricating an embedded germanium-silicon device, characterized in that, include: Provide substrate; The substrate includes sigma trenches extending into the substrate via a first surface of the substrate; After an initial buffer layer is formed on the inner surface of the sigma trench, a germanene transition layer is formed covering the initial buffer layer; the germanene transition layer includes protrusions formed due to lattice mismatch and local stress in the initial buffer layer. The protrusion and the portion of the initial buffer layer covered by the protrusion are selectively etched and removed using a pulsed plasma etching process. In the same process steps, the initial buffer layer is simultaneously damaged and repaired to obtain the target buffer layer, and the germanene transition layer is removed. On the top surface of the target buffer layer, a germanium-silicon seed layer is formed that at least fills the sigma trench.

2. The preparation method according to claim 1, characterized in that, The initial buffer layer comprises germanium-silicon; Selective etching using the pulsed plasma etching process includes: Based on the set processing conditions, the protrusions and part of the germanene transition layer are removed by fluorine-containing plasma etching containing inert gas.

3. The preparation method according to claim 2, characterized in that, The protrusions and part of the germanene transition layer were removed using a nitrogen trifluoride plasma containing argon. The gas flow ratio of nitrogen trifluoride to argon is 1:5 to 1:

10.

4. The preparation method according to claim 3, characterized in that, The process conditions include at least one of the following characteristics: The etching temperature should not exceed 250℃; The plasma radio frequency power supply operates at a frequency of 8Hz-12Hz; Pulse duty cycle 10%-30%; The processing time ranges from 5s to 180s; The output power of the RF power supply is no more than 80W.

5. The preparation method according to claim 1, characterized in that, Repairing the damage to the initial buffer layer and removing the germanene transition layer includes: In the environment of the target gas, when the germanene transition layer is removed, the initial buffer layer is simultaneously repaired and the dangling bonds on the surface of the initial buffer layer are saturated.

6. The preparation method according to claim 1, characterized in that, When removing the germanene transition layer, the initial buffer layer is repaired simultaneously, including: Based on the set annealing temperature and annealing time, the substrate is annealed in a hydrogen atmosphere. The annealing temperature range is 300℃-400℃; The annealing time ranges from 10s to 30s.

7. The preparation method according to any one of claims 1-6, characterized in that, The substrate includes gates spaced apart along a first direction parallel to a first surface of the substrate; The sigma trench is located between adjacent gates.

8. The preparation method according to any one of claims 1-6, characterized in that, Forming the initial buffer layer includes: The initial buffer layer is formed using an epitaxial growth process, and the remaining sigma trenches are used to form grooves; the width of the grooves remains constant in the direction toward the substrate and then gradually decreases; The width is used to characterize the dimension along a first direction parallel to the first surface.

9. An embedded germanium-silicon device, characterized in that, It is prepared by the preparation method according to any one of claims 1-8.

10. An electronic device, characterized in that, include: The embedded germanium-silicon device as described in claim 9.

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