Low-inductance lamination assembly method of pulse power module

Abstract

The invention belongs to the field of manufacturing of printed circuits and assemblies thereof, and discloses a low-inductance lamination assembly method of a pulse power module, which comprises the following steps: placing a power semiconductor device and a decoupling capacitor into a cavity of a core substrate in a coplanar manner; laminating insulating layers and selectively windowing by using a closed-loop control method based on plasma spectrum monitoring; and finally, a bridging conductive layer directly bridging the top terminal of the element is formed through metal deposition. According to the invention, a lamination step is multiplexed as a key electrical connection forming process, and the dimension of a traditional three-dimensional commutation loop is reduced to a quasi-two-dimensional plane on a topological structure; therefore, current path geometric abrupt change and inductance bottleneck caused by vertical via holes are broken, and a structural basis is established for improving the electrical performance and electromagnetic compatibility of the module.

Description

TECHNICAL FIELD

[0001] The present application relates to a low-inductance laminated assembly method of a pulse power module, belonging to the technical field of printed circuit and its assembly. BACKGROUND

[0002] At present, with the popularization of wide-bandgap semiconductor devices, especially silicon carbide devices, the switching frequency and power density of power electronic modules have been improved, which puts forward requirements for the suppression of parasitic inductance of the high-frequency commutation loop inside the module; the technical path is to shorten the physical distance between the power semiconductor device and the high-frequency decoupling capacitor to achieve this purpose, and thus the assembly method of three-dimensional vertical stacking on the printed circuit board or substrate has become the current mainstream and continuously optimized technical direction.

[0003] However, when this kind of vertical stacking method is pushed to higher frequency and density, the change of the geometry of the current path leads to the concentration of the electromagnetic field, thereby generating parasitic inductance; the working path of the current in the module inevitably needs to shrink from a wide two-dimensional conductor plane, such as the pad of the device, and enter a nearly one-dimensional linear vertical interconnection structure, such as the pin of the via or the pin of the laminated busbar, and then expand to another two-dimensional conductor plane, such as the pad of the capacitor; this geometric mutation from plane to line to plane physically constitutes a bottleneck of the current path, causing current congestion and magnetic field concentration, so that the vertical interconnection structure itself becomes an irremovable source of parasitic inductance.

[0004] To alleviate this problem, the most direct improvement idea is to continuously optimize the vertical interconnection structure, such as using shorter and thicker vias, or using multiple vias in parallel, but this does not change the nature that the current path must undergo geometric mutation, and the optimization effect has physical limits and marginal diminishing returns; another idea is to use a more complex laminated copper busbar, but this increases the manufacturing process complexity and cost of the module, making it difficult to popularize in cost-sensitive applications; Specifically, the existing technology mainly has the following deficiencies: 1, the topology of the current path is limited by three-dimensional stacking, and the inherent geometric mutation is the fundamental source of parasitic inductance; 2, the optimization of the vertical interconnection structure is trapped in the trade-off between performance and cost; 3, the potential of the existing printed circuit manufacturing process has not been fully tapped, and it itself is solidified as a structural tool to realize three-dimensional stacking, rather than a functional means to reconstruct the loop topology. Therefore, how to break out of the thinking mode of continuous optimization in the vertical direction, and instead use the characteristics of the printed circuit manufacturing technology to construct a low-inductance commutation loop that avoids geometric mutation of the current path in the topology form, becomes the technical problem to be solved by the present application. SUMMARY

[0005] The application provides a low-inductance laminated assembly method of a pulse power module, which mainly aims to solve the problem of parasitic inductance caused by the geometric mutation of the commutation loop current path due to the adoption of a three-dimensional vertical stacking mode in the prior art.

[0006] To achieve the above-mentioned purpose, the application provides a low-inductance laminated assembly method of a pulse power module, which comprises the following steps: Step a: preparing a core substrate with cavities, and embedding a power semiconductor device and a decoupling capacitor into the cavities respectively, so that the top terminals of the power semiconductor device and the top terminals of the decoupling capacitor are in a coplanar state with the surface of the core substrate; Step b: laminating and pressing an insulating layer on the core substrate and the embedded power semiconductor device and decoupling capacitor to cover the top terminals of the power semiconductor device and the top terminals of the decoupling capacitor; Step c: selectively removing the part of the insulating layer directly above the top terminals by laser ablation to form a connection window, and monitoring the optical characteristics of the plasma generated by the removal process in real time during the removal of the insulating layer, and automatically terminating the removal process at the position when the characteristic spectral line intensity of the metal element constituting the top terminal reaches the judgment threshold; Step d: forming a bridging conductive layer by depositing metal on the surface of the insulating layer and in the connection window, the bridging conductive layer directly electrically connecting the top terminals of the power semiconductor device and the corresponding top terminals of the decoupling capacitor, thereby forming a low-inductance loop in the key commutation loop without through-hole vias through the substrate.

[0007] Preferably, the bridging conductive layer is a composite structure, which comprises a layer of resistive material in contact with the top terminals, a layer of dielectric material covering the layer of resistive material, and a layer of main conductive material covering the layer of dielectric material.

[0008] Preferably, the low-inductance loop is a quasi-two-dimensional planar loop, which is composed of the bridging conductive layer as the current path and the bottom conductive layer in the core substrate below the bridging conductive layer as the current loop.

[0009] Preferably, the step of forming the bridging conductive layer by depositing metal on the surface of the insulating layer and in the connection window in step d specifically comprises: first, chemically depositing a conductive seed layer on the surface of the insulating layer and the inner wall of the connection window; and then, through electroplating, growing the metal layer from the top terminals upward through the connection window and finally extending laterally on the surface of the insulating layer to form the bridging conductive layer.

[0010] Preferably, the composite structure is such that for direct current or power frequency current, the layer of main conductive material forms the main path of a low inductance loop; while for high frequency oscillating current generated during switching transient of the power semiconductor device, the layer of resistive material and the layer of dielectric material together form a distributed energy dissipation path in parallel with the main path.

[0011] Preferably, the core substrate is a metal substrate, and in the step of co-planarly embedding the power semiconductor device in step a, the heat dissipation surface of the power semiconductor device is fixed to the metal bottom of the cavity to establish a heat dissipation path.

[0012] Preferably, the method further comprises the step of, after forming the bridging conductive layer, patterning the bridging conductive layer to form a circuit pattern.

[0013] Preferably, the co-planar state means that the absolute value of the height difference between the top terminal of the power semiconductor device and the top terminal of the decoupling capacitor relative to the surface of the core substrate is less than 20% of the thickness of the insulating layer after compression curing.

[0014] Preferably, the contact interface between the bridging conductive layer and the top terminal is a solder-free direct metallization connection interface.

[0015] Compared with the prior art, the present application has the following beneficial effects: 1. Forming a cavity on the core substrate for accommodating electrical components, and co-planarly embedding the power semiconductor device and the decoupling capacitor in the cavity, this series of operations makes the top terminals of the separate components together form a flat reference surface; the subsequent lamination and compression step directly bridges and connects these co-planar terminals using the overlying conductive layer, which changes the traditional indirect path that needs to pass through vertical vias between different layers to a wide-body conductor that directly communicates in a single plane, so that the geometry of the high-frequency commutation loop is no longer a three-dimensional loop containing Z-axis jumps, but is physically constrained to a quasi-two-dimensional planar structure, the current path mutation and congestion phenomenon is avoided, and the electromagnetic field pattern of the loop is also changed, which establishes a structural basis for the overall electrical performance of the subsequent module that is different from the prior art.

[0016] 2. When step c is changed to first stacking an insulating layer to cover all components, and then selectively opening windows and building a bridging conductive layer by additive manufacturing, the primary task of the lamination is no longer to achieve electrical connection simultaneously. Instead, it utilizes the fluidity of the prepreg to completely replicate and solidify the height inconsistencies caused by the components' own tolerances and assembly errors under a flat insulating layer. Subsequent laser windowing and electroplating deposition are performed on this solidified substrate with a defined morphology. This arrangement of separating the adaptation of mechanical morphology and the construction of electrical connection in sequence and using different processes makes the reliability of the final connection no longer subject to the initial physical height of the components. The entire manufacturing method thus has the ability to accept fluctuations in upstream component materials and mounting processes.

[0017] 3. In the step of applying the bridging conductive layer, if a multi-layer composite structure is adopted, that is, the resistive material, dielectric material and main conductive material are stacked in sequence and pressed together, then the bridging conductor itself transcends the simple path function. For the DC or power frequency main current in the module operation, it mainly flows through the low impedance main conductive layer; while for the high-frequency oscillating current generated by switching transients, the resistive and dielectric material layers in the composite structure form a distributed energy dissipation path in parallel with it. This frequency-selective response formed inside the interconnect structure makes the high-frequency noise suppression function integrated into the basic electrical connection, avoiding the need to set up separate RC components and their introduced secondary parasitic parameters to solve the oscillation problem, so that the integration degree and high-frequency electrical performance of the module are synergistically improved. Attached Figure Description

[0018] Fig. 1 A schematic diagram of the process flow for constructing the quasi-two-dimensional planar commutation circuit of this invention; Fig. 2 This diagram shows the effectiveness of the present invention in suppressing switching voltage overshoot and oscillation. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of the present invention clearer, the technical solutions of the present invention will be described in detail below. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0020] The application discloses a low-inductance laminated assembly method of a pulse power module. The process flow is to embed power semiconductor devices and decoupling capacitors in a coplanar manner first, and then generate a flat and wide bridge conductive layer on the top of the devices by using the lamination and metallization process in the printed circuit manufacturing technology to build a high-frequency commutation loop. The method mainly includes the following steps: preparing a core substrate with cavities and embedding electrical elements in a coplanar manner, laminating an insulating layer and selectively opening a window by using a closed-loop feedback controlled laser ablation process, and building a bridge conductive layer by additive metal deposition.

[0021] In one specific application, the method is used to manufacture a high-power-density silicon carbide power module applied to a new energy automobile main drive inverter. The module requires that the parasitic inductance of the commutation loop be suppressed below 1 nH at a switching frequency of hundreds of kilohertz to control voltage overshoot and reduce switching loss. In order to achieve this goal, the existing technology adopts a vertical stacking structure, and the geometric mutation of the current path is the main source of inductance, which is difficult to meet the design requirements. In view of this, the method of the application provides a manufacturing path to avoid this problem at the topological structure level. The specific steps are as follows: first, perform step a, prepare a core substrate with cavities, and place the power semiconductor device and the decoupling capacitor in the cavities respectively, so that the top terminals of the power semiconductor device and the decoupling capacitor are in a coplanar state with the surface of the core substrate. The implementation of this step aims to establish a unified and high-precision mechanical reference surface for all subsequent lamination and connection processes. In one embodiment, an aluminum nitride ceramic-based copper-clad plate (AMB) with a thermal conductivity not less than 150 W / (m·K) is selected as the core substrate, and the thickness of the copper layer thereon is 0.3 mm. A picosecond laser with a focused spot diameter of 25 μm is used to process two shallow cavities with a depth of 0.8 mm on the top copper foil and ceramic layer of the core substrate, and the planar sizes of the two cavities are matched with the outlines of the power semiconductor device and the decoupling capacitor to be embedded respectively, and the tolerance is controlled within ±20 μm. Then, a silver sintering paste with a thickness of 50 μm is applied to the bottom of the cavities by an automatic dispensing device, and the above-mentioned devices and capacitors are attached to the corresponding cavities, wherein the heat dissipation surface of the power semiconductor device is fixed to the metal bottom of the cavity to establish a heat dissipation path. After a sintering process at a pressure of 250 After the sintering process at a pressure of 10 MPa, the elements are firmly fixed. At this time, it can be confirmed by laser profilometry that the absolute value of the height difference between the top terminals of the power semiconductor device and the decoupling capacitor relative to the surface of the core substrate is less than 20% of the final thickness of the insulating layer after compression and curing, for example, less than 20 μm, thereby achieving a coplanar state.

[0022] After step b, an insulating layer is laminated on the core substrate and the embedded power semiconductor device and decoupling capacitor to cover the top terminals of the power semiconductor device and the top terminals of the decoupling capacitor; the purpose of this step is to use the flowability of the prepreg material under heat and pressure to adapt to and solidify the micro-topography inconsistencies that may exist in the previous process, thereby generating an overall flat working surface that subsequent fine processing relies on; specifically, a high-frequency prepreg with a thickness of 100 μm after curing is covered on the core substrate after the component embedding is completed; then, the laminated assembly is placed in a vacuum laminator for heat and pressure curing at a temperature of 200 and a pressure of for 90 minutes; during this process, the resin of the prepreg flows sufficiently, filling all the gaps around the components and closely fitting the top terminal surfaces of all the components, regardless of any micron-level deviations in their original height, and after curing, a solid and highly flat insulating top layer is formed.

[0023] Step c is then performed, in which a laser is used to selectively remove the part of the insulating layer directly above the top terminal to form a connection window; to solve the problem of difficult control of the processing depth in open-loop laser processing due to fluctuations in material thickness or laser power drift, a closed-loop feedback control mechanism based on physical phenomena is introduced in this step; a small spectral analyzer is installed in the optical path of the laser processing equipment and is linked to the main controller, which monitors the optical characteristics of the plasma generated by the interaction of laser and matter in real time; in the initial stage of removing the insulating layer, the laser acts on the resin and glass fibers of the prepreg, and the plasma spectrum collected by the spectral analyzer mainly presents the characteristic lines of elements such as carbon, hydrogen, oxygen, and silicon; the control system continues to ablate until the characteristic spectrum of the metal element constituting the top terminal, such as copper, appears in the spectrum, and when the intensity of the characteristic spectrum of this copper element reaches a preset judgment threshold, the control system determines that the ablation process has reached the surface of the metal terminal and automatically terminates the removal process at this position; the judgment threshold is set through a deterministic calibration procedure, i.e., during the process development stage, by ablation of the insulating layer of known thickness and simultaneous cross-section metallographic analysis, the spectral intensity at which the insulating layer is completely removed and the copper surface is not damaged is determined, and it is set as the judgment threshold in mass production, for example, set to trigger the termination signal when the ratio of copper characteristic spectrum signal intensity to background noise reaches 5:1; in this way, the formation process of each connection window becomes an adaptive and self-terminating operation, ensuring the cleanliness of the window bottom and the integrity of the component terminal.

[0024] Finally, step d is performed to form a bridging conductive layer by depositing metal on the surface of the insulating layer and within the connection windows; this step uses a pressureless additive manufacturing method to eliminate internal stress that can be caused by mechanical pressing and to form a solder-free direct metallization connection interface; the specific implementation is as follows: first, the substrate treated in the previous step is immersed in a chemical copper plating solution, and a conductive seed layer with a thickness of 0.5 μm is uniformly deposited on the entire flat insulating top layer surface and the inner walls of all connection windows through a chemical deposition process; then, the substrate is used as a cathode to perform pattern plating, so that the copper layer grows from the top terminal as an electrode, through the connection windows upward, and finally expands laterally on the surface of the insulating layer to connect with each other until a bridging conductive layer with a thickness of 70 μm is formed; the bridging conductive layer directly electrically connects the top terminal of the power semiconductor device and the corresponding top terminal of the decoupling capacitor, thereby forming a low-inductance loop in the key commutation loop that does not contain a through-substrate via; this loop is a quasi-two-dimensional planar loop, in which the formed bridging conductive layer serves as a current path, and the bottom conductive layer located below the bridging conductive layer in the core substrate serves as a current loop, and the two are separated only by a thin insulating medium, and the structure is similar to a low-impedance parallel plate transmission line, thereby reducing the loop inductance to a low level; after the bridging conductive layer is formed, it can also be patterned and etched to form a circuit pattern, such as precisely defining the width of the connection, or making other signal traces required by the module, such as gate drive; in an embodiment designed to further suppress switching oscillation, the bridging conductive layer is constructed as a composite structure, which is adjusted during the metal deposition step of step d; specifically, after the seed layer is formed by chemical copper plating, instead of directly electroplating the main conductive copper layer, a layer of nickel-chromium alloy resistive material with a thickness of 5-10 μm is first deposited on the seed layer by sputtering; then, a layer of dielectric material with a thickness of 1-2 μm and a high dielectric constant, such as aluminum oxide, is coated on the resistive material layer by chemical vapor deposition technology; finally, the main copper conductive layer is formed on the dielectric material layer by electroplating process; the composite structure thus formed allows the current to mainly flow through the low-resistance main conductive material layer for direct current or power frequency current, constituting the main path of the low-inductance loop; and for high-frequency oscillation current generated during the switching transient of the power semiconductor device, the resistive material layer and the dielectric material layer together constitute a distributed energy dissipation path parallel to the main path, which can absorb oscillation energy, thereby achieving suppression of electromagnetic interference without adding discrete resistive and capacitive elements.

[0025] In addition, the method of the present application can also integrate a function for online diagnosis of the module structure health state; this function is realized through the built-in control system after the module is assembled, and its method comprises: after each switching action of the power semiconductor device is completed, the existing sensing pin on the gate drive chip is used to collect the oscillation ringing signal with a time length of 50 ns in the voltage signal across the power semiconductor device at a sampling rate of not less than 1 GSa / s; the digital signal processing unit in the controller extracts the characteristic frequency of the oscillation ringing signal by executing the fast Fourier transform algorithm ; when the module is tested for the first time after being put on the market, the characteristic frequency in the brand-new state is recorded as the health baseline frequency , for example =250 MHz, and a degradation judgment relative threshold is stored in the non-volatile memory, for example =5%; during the long-term operation of the module, the controller periodically extracts the current , and compares it with ; when the condition is met, for example, the current measured =235 MHz, the calculated is greater than 0.05, the controller determines that the internal interconnection structure of the module may be deteriorated due to thermal fatigue or mechanical stress, and sends a pre-warning maintenance signal to the upper-level system controller; this process re-uses an electrical noise signal as an index reflecting the structure health state, and provides the possibility of predictive maintenance for critical application scenarios; the core of the structure health state judgment is a differential comparison logic that excludes the influence of the working state, that is, not only the health baseline frequency under a single working condition is recorded before the module is put on the market , but also the scanning test is performed in the preset entire working temperature and bus voltage range, for example, -40 to 125 , 600 V to 900 V, the characteristic frequencies corresponding to different working points are collected, and a two-dimensional lookup table or a polynomial fitting model for describing the functional relationship between the characteristic frequency and the temperature T and the voltage V is constructed and stored in the non-volatile memory; during the long-term operation of the module, the controller also synchronously collects the real-time temperature and the DC bus voltage of the module substrate while collecting the current oscillation ringing signal and extracting its characteristic frequency , and then calculates the expected characteristic frequency of the module in the healthy state under the current working condition by calling the model , and finally, the condition for judging whether the structure is deteriorated is based on the normalized deviation of the current frequency and the expected frequency, that is, when the condition Only in this condition, the irreversible physical degradation of the internal interconnect structure of the module is determined.

[0026] Embodiment 1: This embodiment is a specific operation example of the foregoing technical solution in a specific scenario, in a manufacturing project of high-density blade server power modules designed for supercomputing centers, the technical challenge faced is that when multiple power modules work in parallel at high physical density, even if the voltage overshoot of a single module is controlled within a safe threshold, the high-frequency electromagnetic noise generated by the respective switching transients will superimpose in space, forming a sustained broadband electromagnetic interference background, which in turn causes occasional logic errors in adjacent data processing units; In this project, the low-inductance laminated assembly method of the present application is used to manufacture the power module; When performing step a of co-planar embedding electrical components, due to the manufacturing tolerances of the incoming power semiconductor devices and decoupling capacitors themselves, and the thickness of the silver sintering paste at the bottom of the cavity also fluctuates when pasting, the top terminals of each component are not in the ideal coplanar surface; If the direct compression of the conductive layer is used for connection, the terminals that are too high will bear stress, and the terminals that are too low may form a virtual connection. This dependence on mechanical precision limits the process window and yield of large-scale manufacturing; This solution first laminates and compresses a pure insulating layer in step b, which completely reproduces and fixes the height inconsistency caused by tolerances and assembly errors under a flat insulating layer. This step uses the insulating layer to fix the actual physical position of the components, so that the subsequent electrical connection is no longer directly subject to the initial height deviation of the components.

[0027] Furthermore, this way of solidifying the pattern of the insulating layer first provides a stable processing base for the implementation of the closed-loop control laser ablation process based on plasma spectrum monitoring in step c; since the absolute height of the underlying element terminal is no longer a variable affecting the connection quality, the closed-loop control laser ablation process can focus its control target on ensuring the cleanliness and undamagedness of the bottom of each connection window, thereby providing a high-quality starting interface for the additive metal deposition in step d; the two steps are related to each other in the process, that is, the deterministic pattern created in step b enables the closed-loop control in step c to be effectively implemented, and the interface quality guaranteed in step c ensures the reliability of the solderless direct metallization connection formed in step d; when the power module manufactured by this method is finally completed and put into operation, the geometric shape of the key commutation loop inside it is no longer a three-dimensional loop in which the current must shrink from a wide pad into an approximately linear vertical via and then expand to another pad as in the traditional way; instead, the current always flows in the wide conductor in the quasi-two-dimensional planar loop formed by the bridging conductive layer and the bottom conductive layer, so the parasitic inductance originally related to the vertical via is no longer the main influencing factor in this loop; accordingly, the distribution pattern of the high-frequency electromagnetic field also changes, and the magnetic field is constrained between the two parallel conductive planes, reducing the outward radiation intensity; finally, the blade server cabinet deployed with such a power module has a lower overall electromagnetic interference background level inside, and the previously occasional data processing unit logic error phenomenon no longer occurs, improving the stability of the entire system.

[0028] Example 2: To quantitatively evaluate the influence of the low-inductance lamination assembly method of the present application on the key electrical performance of the pulse power module, a set of comparative tests were conducted; two groups of half-bridge power module samples were prepared, one using the traditional printed circuit board surface mounting and via interconnection method as the control group, and one using the method of the present application as the test group; it should be noted that both groups of samples used exactly the same silicon carbide MOSFET devices and high-frequency decoupling capacitors, and were tested under the same gate drive parameters, taking the packaging and assembly structure as the only variable; the test was conducted on a standard double-pulse test platform consisting of a DC power supply that can provide a voltage of up to 1000V, a 100μH load inductance, and corresponding gate drive circuit; the data acquisition equipment includes an oscilloscope with a bandwidth of 1GHz, a high-voltage differential probe with a bandwidth of 400MHz, and a Rogowski coil current probe with a bandwidth of 200MHz; the test working condition parameters are set as follows: DC bus voltage 800V, turn-off current 100A, gate drive voltage +18V / -3V, ambient temperature 25 This working condition is designed to simulate the working state of silicon carbide devices in applications such as electric vehicle main inverters.

[0029] During the experiment, a double-pulse gate signal was applied to both the control group and the experimental group, and the drain-source voltage during the turn-off period of the second pulse was accurately captured. and drain current The transient waveforms; from the acquired waveforms, it was observed that at the moment of turn-off, the two sample groups... Both waveforms exhibited voltage overshoot and subsequent oscillations. Analysis of the waveform data revealed that the control group experienced a drain-source voltage overshoot of 128V at a current change rate of 2550 A / ns, while the experimental group, at a similar current change rate of 2610 A / ns, only experienced a voltage overshoot of 25V. Based on the formula... The calculated parasitic inductance of the commutation circuit was approximately 5.02 nH in the control group and 0.96 nH in the experimental group. This reduction in inductance is due to the quasi-two-dimensional planar circuit constructed by the method of this invention, which structurally eliminates the geometric abrupt changes in the current path caused by vertical vias. Its current loop area is smaller than the loop area formed by the current having to jump between different layers of the circuit board through vias in the control group. Experimental data shows that, under the same test conditions, the parasitic inductance of the key commutation circuit of the power module assembled using the method of this invention is reduced by about 80% compared with the module assembled using the traditional vertical interconnection method. Correspondingly, the voltage overshoot during the switching process is also suppressed.

[0030] Example 3: This example combines Figs. 1-2 A method for assembling a low-inductance stacked module for a pulse power module is described, such as... Fig. 1As shown, the process begins with a core substrate, power semiconductor devices, and decoupling capacitors as core inputs. Step a is performed first, fabricating a core substrate with cavities and embedding components coplanarly. The purpose is to establish a unified and high-precision mechanical reference surface. Next, step b is performed, where an insulating layer is laminated onto the substrate with embedded components. This step aims to utilize the fluidity of the insulating material to cover and solidify the microstructure caused by assembly tolerances, thereby forming a flat working surface. Then, step c is performed, selectively opening windows in the insulating layer to expose the underlying component terminals. The unique feature of this step is the use of a closed-loop control method based on plasma spectral monitoring. By monitoring the plasma spectrum generated during the ablation process in real time, when the plasma spectrum is detected... The ablation process automatically terminates when the intensity of the characteristic spectral lines representing the terminal metal reaches a preset threshold, thus forming a high-precision connection window. Next, step d is executed, where a bridging conductive layer is constructed through additive metal deposition. The purpose is to form a solderless, directly metallized quasi-two-dimensional planar loop. After the bridging conductive layer is formed, the final process, patterning etching, can be performed to form a fine circuit pattern and optimize the high-frequency current distribution. Through the above series of steps, a low-inductance pulse power module is finally produced. Furthermore, by utilizing the structural characteristics of this module, an online diagnostic function for the structural health status can be realized. That is, by extracting the characteristic frequency of the oscillation residual signal of the switching transient and comparing it with the health baseline, it can be determined whether the module's structure has deteriorated.

[0031] like Fig. 2 As shown in the figure, the vertical axis represents the drain-source voltage. The unit is volts (V), and the horizontal axis is time (nanoseconds (ns). The solid line in the figure represents the module using the traditional vertical interconnect method; at the moment of shutdown, its... The voltage experienced a severe overshoot from the 800V bus voltage level, with a peak value exceeding 925V, accompanied by prolonged, high-amplitude oscillations. In stark contrast, the module represented by the dashed line, which employs the low-inductance stack-up assembly method of this invention, exhibited suppressed voltage overshoot under the same test conditions, with a peak value of only about 825V, and the subsequent oscillations were rapidly attenuated. This comparative result demonstrates the effectiveness of the method of this invention in suppressing parasitic inductance and switching noise.

[0032] Example 4: This example aims to supplement the explanation of the key process parameter calibration and functional module implementation logic in the aforementioned technical solution. In the manufacturing process of a pulse power module for an aerospace power conversion system, high requirements are placed on process stability and module reliability; even minor process deviations can lead to potential failure risks. In this manufacturing context, to ensure that the laser ablation process in step c terminates precisely at the interface between the insulating layer and the metal terminal at each connection window, a calibration procedure for determining the plasma spectral characteristic threshold needs to be established. This procedure is executed in an offline process development phase, and its steps are as follows: First, prepare multiple test samples with the same structure as the actual product and perform steps a and b on them; second, set a laser energy density gradient, and... arrive Within the scope, To achieve the step-by-step process, laser pulses of different energy densities are used to ablate the connection windows in different regions. Simultaneously, the signal intensity ratio of the characteristic spectral lines of copper representing the metal terminal and the characteristic spectral lines of carbon representing the insulating layer in the plasma spectrum generated during the ablation process is recorded at each energy density. Finally, cross-sectional analysis of each ablated window is performed using a scanning electron microscope to determine the energy density point that completely removes the insulating layer without causing microscopic damage to the copper surface below. The spectral signal intensity ratio corresponding to this point, 10:1, is set as the threshold for automatically terminating the ablation process on the mass production line.

[0033] Furthermore, this embodiment describes the internal algorithm logic path of the function used to diagnose the health status of the module structure. During the initial power-on test of the module, the control system collects the oscillation aftershock signal under healthy conditions and performs a Fast Fourier Transform to obtain a frequency domain energy spectrum. Given that the physical structure of the module determines that its intrinsic oscillation frequency falls within a predictable range, the algorithm first applies a digital bandpass filter with a passband of 150MHz to 350MHz to filter out DC components and high-frequency noise interference. Subsequently, the algorithm searches for the frequency point with the maximum energy amplitude in the filtered spectrum data and records this frequency point as the healthy baseline frequency. In subsequent long-term operation, this process is repeated periodically to obtain the current characteristic frequency. And through judgment Whether it holds true or not is used to determine the structural health status of the module; the setting of this prior frequency band enables the algorithm to stably and unambiguously lock the effective frequency as a health status indicator from the noisy background.

[0034] Furthermore, for the composite structure bridge conductive layer to suppress the switching oscillation, the embodiment provides an engineering design method for the selection of the resistance material layer; the target is to make the built-in distributed RC network of the composite structure form effective damping to the RLC oscillation of the commutation loop; the first step of the method is to obtain the equivalent output capacitance of the power semiconductor device under the target working voltage through a network analyzer , and the measured value is 300 pF under the working condition; it is known that the method can stabilize the parasitic inductance of the commutation loop to about 1 nH; the characteristic impedance of the RLC loop is , and the calculation is about 1.83 Ω; in order to realize the near-critical damping to attenuate the oscillation, a parallel resistance with a characteristic impedance needs to be introduced; for a bridge conductive layer with a current path length of 10 mm and a width of 5 mm, the calculated sheet resistance value of the required resistance material should be 0.915 Ω / sq; therefore, during manufacturing, the embedded resistance film with the sheet resistance value closest to the calculated value is selected as the resistance material layer in the composite structure; the procedure changes the selection of the material from relying on experience to a calculation process based on device physical characteristics and circuit theory.

[0035] In the batch production process of a pulse power module, in order to ensure that the built-in structural health state diagnosis function has consistent criteria between different production batches, a pre-deployment calibration procedure needs to be performed to set the health baseline frequency ; in the procedure, first, at least 5% of the samples are randomly selected from the modules of the same production batch, and a short aging screening program is run under the rated working condition on a standardized power-on test platform; then, the oscillation residual signal after the switching action of each sample module is collected, and the initial characteristic frequency is extracted according to the algorithm logic; finally, the arithmetic mean of the initial characteristic frequencies of all samples is calculated, and the average value is taken as the health baseline frequency of the entire production batch , which is programmed and written into the non-volatile memory of all modules of the batch.

[0036] In order to determine a degradation judgment relative threshold for the diagnosis function , a parameter calibration procedure based on accelerated aging test needs to be performed; in the procedure, a part of the samples that have completed the initial characteristic frequency calibration are selected again for accelerated thermal cycle aging test, and the test conditions are set to perform rapid temperature change cycles between -40 and 125 ; during the test, every 100 cycles, the sample is taken out, and the current characteristic frequency is measured on the standard test bench and simultaneously, the internal micro-cracks or delamination and other early failure signs are checked by ultrasonic scanning microscope; the correlation between the characteristic frequency drift and the occurrence time of internal microstructure damage is established through the test, and the statistical average of the frequency drift corresponding to the first observation of the repeatable early failure signs is taken as the basis for setting the deterioration judgment relative threshold When the average of the drift is 5%, it is set as 5%.

[0037] In a production introduction process of applying the assembly method of the application to a new type of power semiconductor device, in order to ensure the accurate adaptation of manufacturing parameters and the stability of the production process, a set of system deployment pre-set calibration procedures need to be performed; the first step of the procedure is to determine the cavity depth for achieving the coplanar state, and the calculation method is to add the nominal thickness of the conductive adhesive after curing to the nominal device height in the data sheet of the new type of power semiconductor device, and then subtract a planarization correction amount reserved for the subsequent lamination process, which is set to be 10% of the thickness of the insulation layer used in step b after curing; the cavity depth calculated in this way can make the top terminal surface of the element slightly lower than the core substrate surface after embedding, providing process allowance for resin flow and final planarization of the insulation layer during the pressing process; in order to deal with the possible micron-level element position offset during the element mounting process in step a, which may cause the target point of laser ablation in step c to deviate from the center of the element top terminal, an online quality monitoring and abnormality judgment logic is added based on closed-loop control logic; in addition to monitoring whether the characteristic spectral line intensity of the metal element in the plasma spectrum reaches the judgment threshold, the logic also synchronously calculates the time from the start of ablation to the appearance of the metal characteristic spectral line, and accumulates the total signal integral value of the metal characteristic spectral line during the ablation process; by ablation and data collection on the normal window and multiple known offset windows during process development, a statistical distribution model of the above-mentioned time parameters and signal integral values can be established; during mass production, if the ablation time or signal integral value of a window deviates from the normal range defined by the statistical model by more than three standard deviations, the control system will mark the module as a suspected abnormal product and transfer it to the manual inspection station, thereby avoiding the flow of connection defects caused by element mounting offset into the subsequent process.

[0038] ​In one specific embodiment of the present application, after the deposition of the bridging conductive layer is completed in step d, a step of patterning etching the bridging conductive layer is performed, which is not only for forming the auxiliary circuit pattern required by the module, such as gate drive and signal sensing, but also for performing final geometric optimization on the conductor part carrying the main commutation current; specifically, the design of the etching pattern follows a principle that, under the premise of meeting the electrical clearance requirement, the projection overlapping area between the current path and the loop conductor constituting the quasi-two-dimensional planar loop is maximized, and the corners of the etching pattern are processed with circular arcs by electromagnetic field simulation software to suppress the current crowding effect; in this way, the patterning etching step is transformed from a standard circuit manufacturing process into a functional step for fine regulation of high-frequency current distribution and further reduction of the local inductance of the loop.

[0039] It is obvious for those skilled in the art that the present application is not limited to the details of the above exemplary embodiments, and can be implemented in other specific forms without departing from the spirit or essential characteristics of the present application.

[0040] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application and are not limiting, and although the present application has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solutions of the present application can be modified or replaced equivalently without departing from the spirit and scope of the technical solutions of the present application.

Claims

1. A low inductance stack assembly method for a pulse power module, characterized by, The method comprises the following steps: Step a, preparing a core substrate with cavities, and embedding a power semiconductor device and a decoupling capacitor into the cavities respectively, so that the top terminals of the power semiconductor device and the decoupling capacitor are coplanar with the surface of the core substrate; Step b, laminating and pressing an insulating layer on the core substrate and the embedded power semiconductor device and decoupling capacitor to cover the top terminals of the power semiconductor device and the decoupling capacitor; Step c, selectively removing the part of the insulating layer directly above the top terminals by laser ablation to form a connection window, and monitoring the optical characteristics of the plasma generated by the removal process in real time during the removal of the insulating layer, and automatically terminating the removal process at this position when the characteristic spectral line intensity of the metal element constituting the top terminal reaches the judgment threshold; Step d, forming a bridging conductive layer by depositing metal on the surface of the insulating layer and in the connection window, the bridging conductive layer directly electrically connecting the top terminals of the power semiconductor device and the corresponding top terminals of the decoupling capacitor, thereby forming a low-inductance loop in the key commutation loop without through-substrate vias.

2. A low inductance stack assembly method for a pulse power module according to claim 1, wherein, The bridging conductive layer is a composite structure comprising a layer of resistive material in contact with the top terminals, a layer of dielectric material covering the layer of resistive material, and a layer of main conductive material covering the layer of dielectric material.

3. A low inductance stack assembly method for a pulse power module according to claim 1, wherein, The low-inductance loop is a quasi-two-dimensional planar loop, which is composed of the bridging conductive layer as the current path and the bottom conductive layer in the core substrate below the bridging conductive layer as the current loop.

4. A low inductance stack assembly method for a pulse power module according to claim 1, wherein, The step of forming the bridging conductive layer by depositing metal on the surface of the insulating layer and in the connection window in step d specifically comprises: first, chemically depositing a conductive seed layer on the surface of the insulating layer and the inner wall of the connection window; then, through electroplating, the metal layer grows upward from the top terminals through the connection window and finally expands laterally on the surface of the insulating layer to form the bridging conductive layer.

5. A low inductance stack assembly method for a pulse power module according to claim 2, wherein, The composite structure makes the main conductive material layer constitute the main path of the low-inductance loop for direct current or power frequency current, and the resistive material layer and the dielectric material layer together constitute a distributed energy dissipation path in parallel with the main path for high-frequency oscillation current generated in the switching transient of the power semiconductor device.

6. A low inductance stack assembly method for a pulse power module according to claim 1, wherein, The core substrate is a metal substrate, and in the step of coplanarly embedding the power semiconductor device in step a, the heat dissipation surface of the power semiconductor device is fixed to the metal bottom of the cavity.

7. A low inductance stack assembly method for a pulse power module according to claim 1, wherein, The method further comprises the step of patterning and etching the bridging conductive layer to form a circuit pattern after forming the bridging conductive layer.

8. A low inductance stack assembly method for a pulse power module according to claim 1, wherein, The coplanar state refers to the absolute value of the height difference of the top terminals of the power semiconductor device and the decoupling capacitor relative to the surface of the core substrate is less than 20% of the thickness of the insulating layer after pressing and curing.

9. A low inductance stack assembly method for a pulse power module according to claim 1, wherein, The contact interface between the bridging conductive layer and the top terminals is a solder-free direct metallization connection interface.

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