Packaging structure, circuit board and manufacturing method of packaging structure

Abstract

The invention discloses a packaging structure, a circuit board and a manufacturing method of the packaging structure, and the packaging structure comprises a packaging substrate which comprises a plurality of sub-boards which are arranged in an array, and each sub-board is provided with a functional circuit pattern; the edge of each daughter board is provided with a test pattern and a test connecting piece, and the test pattern is electrically connected with the corresponding test connecting piece; at least part of the test pattern and the functional circuit pattern have the same impedance, and the test pattern and the functional circuit are mutually insulated. Through the mode, various test requirements can be met, product test data can be obtained through the test structure during production, subsequent packaging and the like, the product reliability and yield are effectively improved, and the production cost is reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of integrated circuit manufacturing, and in particular to a packaging structure, a circuit board and a manufacturing method of the packaging structure. BACKGROUND

[0002] The circuit board is a core component of modern electronic devices, and its production process is complex and requires high precision. In the production process of the circuit board, strict testing is required to ensure product quality, and various environmental conditions are simulated to ensure the performance and reliability of the circuit board.

[0003] The existing test structure design often cannot adapt to the requirements of new production processes, may not meet the test standards, and the test conditions designed during production often differ from the actual use environment, which cannot accurately evaluate the performance in the actual use process, and also affects the production cost and production efficiency, leaving room for improvement and optimization. SUMMARY

[0004] The technical problem solved by the present application is to provide a packaging structure, a circuit board and a manufacturing method of the packaging structure, which can meet various testing requirements, obtain product test data through the test structure during production and subsequent packaging, effectively improve product reliability and yield, and reduce production cost.

[0005] To solve the above technical problems, the first aspect of the present application provides a packaging structure, wherein the packaging structure comprises: a packaging substrate comprising a plurality of sub-boards arranged in an array, the sub-boards being provided with functional circuit patterns; each sub-board edge is provided with a test pattern and a test connecting piece, the test pattern being electrically connected with the corresponding test connecting piece; at least part of the test patterns have the same impedance as the functional circuit patterns, and the test patterns and the functional circuits are insulated from each other.

[0006] The test pattern comprises a test line, and the sub-board comprises at least one layer of circuit packaging, at least one layer of the sub-board being provided with the test line, the test line having the same impedance as the functional circuit pattern in the same layer; the test lines in each layer are electrically connected with each other through the test connecting piece.

[0007] The test connecting piece comprises a blind hole filling hole stacking structure and / or an electroplated through hole structure, and the test connecting piece structure is arranged correspondingly to the functional circuit pattern.

[0008] The test pattern comprises a test pad, and the sub-board is provided with the test pad on at least one side surface, the test pad being connected with the corresponding test connecting piece.

[0009] The packaging structure further comprises: a packaging edge plate surrounding the outer edge of the packaging substrate; the packaging edge plate is provided with a test pattern and a test connecting piece; the test patterns of the packaging edge plate and the test patterns of each sub-board are insulated from each other.

[0010] To solve the above technical problems, the second aspect of the present application provides a circuit board, which is a circuit board processed from any of the sub-boards.

[0011] To solve the above technical problems, the third aspect of the present application provides a manufacturing method of a packaging structure.

[0012] The manufacturing method is used to manufacture any of the packaging structures, and the manufacturing method comprises the following steps: obtaining a base material, the base material comprising a plurality of to-be-processed sub-boards arranged in an array; sequentially arranging an insulating layer and a metal layer on the base material for packaging, forming corresponding functional circuit patterns in functional areas of the to-be-processed sub-boards, and forming test patterns and test connecting pieces in non-functional areas of edges of the to-be-processed sub-boards; and performing surface treatment to obtain the packaging structure.

[0013] The step of sequentially arranging the insulating layer and the metal layer on the base material for packaging, forming the corresponding functional circuit patterns in the functional areas, and forming the test patterns and the test connecting pieces in the non-functional areas of the edges of the to-be-processed sub-boards comprises the following steps: etching to form test lines and the functional circuit patterns when the corresponding insulating layer and the metal layer are pressed together, and making the test lines and the functional circuit patterns in the same layer have the same impedance; and / or punching and electroplating to form the test connecting pieces.

[0014] The step of obtaining the base material comprises that the base material is formed with to-be-processed edge plates surrounding outer edges of the to-be-processed sub-boards; and the step of sequentially arranging the insulating layer and the metal layer on the base material for packaging, and forming the corresponding functional circuit patterns, the test patterns, and the test connecting pieces when the corresponding insulating layer and the metal layer are pressed together comprises the following step: forming the test patterns and the test connecting pieces on the edge plates of the base material.

[0015] The step of forming the test patterns and the test connecting pieces on the edge plates of the packaging structure comprises the following steps: detecting the test patterns and the test connecting pieces formed on the edge plates of the packaging structure; and cutting the packaging structure with the to-be-processed sub-boards reserved.

[0016] Compared with the prior art, the packaging structure, the circuit board, and the manufacturing method of the packaging structure provided by the present application can meet various testing requirements, not only can test during production, but also can still obtain test data through the test structure after the product is processed by subsequent packaging and the like, so as to realize performance detection of the whole life cycle of the product, ensure that there is no difference between the test data of the test structure and the actual delivery product structure, effectively improve the product reliability and yield, and reduce the production cost. BRIEF DESCRIPTION OF DRAWINGS

[0017] Figure 1 is a structural schematic diagram of a first embodiment of the packaging structure of the present application;

[0018] Figure 2is a partial structure schematic diagram of a second embodiment of the packaging structure of the present application;

[0019] Figure 3 is a structure cross-sectional view of one embodiment of the second embodiment of the packaging structure of the present application;

[0020] Figure 4 is a structure cross-sectional view of another embodiment of the second embodiment of the packaging structure of the present application;

[0021] Figure 5 is a partial structure schematic diagram of a third embodiment of the packaging structure of the present application;

[0022] Figure 6 is a structure schematic diagram of a fourth embodiment of the packaging structure of the present application;

[0023] Figure 7 is a structure schematic diagram of a first embodiment of the circuit board of the present application;

[0024] Figure 8 is a flow schematic diagram of the processing steps of a first embodiment of the manufacturing method of the packaging structure of the present application;

[0025] Figure 9 is a flow schematic diagram of the processing steps of a second embodiment of the manufacturing method of the packaging structure of the present application;

[0026] Figure 10 is a flow schematic diagram of the processing steps of a third embodiment of the manufacturing method of the packaging structure of the present application. DETAILED DESCRIPTION

[0027] The present application will be described in detail below in conjunction with the accompanying drawings and embodiments.

[0028] The packaging structure appearing in the structure schematic diagram of Figures 1-6 The structure schematic diagram of the circuit board appearing in Figure 7 The specific testing structure, packaging structure and manufacturing method of the packaging structure are determined based on the production needs of the circuit board and are not limited.

[0029] The application first provides a packaging structure as an intermediate product of circuit board production, the circuit board is processed through a plurality of sub-boards arranged in an array in the packaging structure, and the circuit board is further formed. In order to test the reliability of the production product, generally, test patterns are arranged in a waste area outside the packaging substrate of the packaging structure to perform reliability testing and solder mask testing, etc. This method cannot accurately simulate the use environment of the final product; or, by selecting a sub-board sample, simulating the packaging process of the finished circuit board on the sub-board sample, performing reliability testing and solder mask testing, etc., obtaining simulation test data, and verifying product reliability, since part of the reliability testing is destructive testing, the data tested by this method is limited, and if a large amount of data is required, the scrap cost of the delivered product will be increased.

[0030] Please refer to Figure 1 , Figure 1 is a structural schematic diagram of the first embodiment of the packaging structure of the application.

[0031] The packaging structure 100 comprises: a packaging substrate 101 comprising a plurality of sub-boards 102 arranged in an array, the sub-boards 102 being provided with functional circuit patterns 103; each sub-board 102 is provided with test patterns 104 and test connecting pieces 105, the test patterns 104 being electrically connected with the corresponding test connecting pieces 105; at least part of the test patterns 104 have the same impedance as the functional circuit patterns 103, and the test patterns 104 and the functional circuit patterns 103 are insulated from each other.

[0032] The packaging structure 100 comprises a plurality of sub-boards 102 arranged in an array, each sub-board 102 is provided with functional circuit patterns 103, which can include patterns for connecting elements, transmitting signals, circuit vias or pads connecting different layers, and patterns for power supply, filtering, impedance matching, etc., the specific structure is not shown and can be set according to production needs.

[0033] Please refer to Figure 2 , Figure 2 is a partial structural schematic diagram of the second embodiment of the packaging structure of the application, Figure 2 is a structural schematic diagram of part A in Figure 1 .

[0034] The sub-boards 102 are provided with test patterns 104 and test connecting pieces 105, and the test patterns 104 and the test connecting pieces 105 realize test signal transmission through electrical connection.

[0035] The test pattern 104 has the same impedance characteristics as the corresponding functional circuit pattern 103, and the test pattern 104 and the functional circuit pattern 103 can be manufactured by the same process, for example, using the same material, or by ensuring that the width and length of the test line 1041 are the same as those of the functional circuit pattern 103 or using the same impedance control process to ensure impedance consistency, thereby improving the accuracy of the test results. The test connector 105 can be designed as a filling hole or a through hole for testing the alignment accuracy between layers, and can also be designed as a test pin, a test socket, etc., to facilitate contact by external test equipment.

[0036] The test pattern 104 and the functional circuit pattern 103 of each layer are electrically isolated by an insulating layer or an isolation structure, and the insulation between the test pattern 104 and the functional circuit pattern 103 of the same metal layer can be achieved by setting a dielectric layer or a physical isolation, for example, by setting an insulating medium such as a prepreg, resin, etc., or a reserved gap between the test pattern 104 and the functional circuit pattern 103. Such insulation design avoids interference with the functional circuit pattern 103 during testing, ensures testing reliability, and also protects the functional circuit pattern 103.

[0037] In specific embodiments, the test pattern 104 is arranged in the non-functional area at the edge of the sub-board 102, so that the test pattern 104 of the sub-board 102 is tested after the packaging process is completed synchronously with the actual product structure, and then the non-functional area at the edge of the sub-board 102 is discarded to form the final product, ensuring that the test environment matches the actual application conditions. Integrating the test structure in the non-functional area at the edge of the sub-board 102 enables it to be delivered together with the packaging substrate 101, and after packaging, the test structure can be directly used for reliability testing and impedance testing, avoiding the scrap cost caused by traditional destructive testing. The reliability testing of the circuit board 200 can be realized without additional cost, and the scrap loss caused by destructive testing is reduced. The test pattern 104 is designed synchronously with the actual product structure, which makes the test environment closer to the real application scenario, improves the performance evaluation accuracy of the product after packaging, and ultimately improves the product yield and reduces the production cost.

[0038] Please refer to Figure 3 and Figure 4 , Figure 3 is a structural cross-sectional view of the first embodiment of the second embodiment of the packaging structure of the present application, Figure 4 is a structural cross-sectional view of another embodiment of the second embodiment of the packaging structure of the present application.

[0039] In an alternative embodiment, the test pattern 104 includes test lines 1041, and the sub-board 102 includes at least one layer of circuit package, and at least one layer of the sub-board 102 is provided with the test lines 1041, and the test lines 1041 have the same impedance as the functional circuit pattern 103 in the same layer; and the test lines 1041 in different layers are electrically connected through the test connectors 105.

[0040] The test lines 1041 are mainly used for signal impedance testing, and the sub-board 102 includes at least one layer of circuit package, and the test lines 1041 have the same impedance as the functional circuit pattern 103 in the same layer, so as to ensure that the test data is consistent with the actual product data, and the accuracy of the test result is improved.

[0041] In some embodiments, the sub-board 102 is a multi-layer circuit structure, the test lines 1041 are electrically connected through the test connectors 105 between different layers, the test lines 1041 can be made of the same material as the functional circuit pattern 103, the width and length of the test lines 1041 can be adjusted according to the design requirements of the functional circuit pattern 103 to ensure the same impedance, and the test lines 1041 are designed synchronously with the functional circuit pattern 103, so that no additional adjustment is required in the test process, the interlayer connection design of the test connectors 105 ensures the integrity of the test signal, realizes impedance testing of the multi-layer circuit, and improves the test accuracy and test efficiency.

[0042] The impedance test lines 1041 designed together with the test connectors 105 can directly test the impedance characteristics of the test lines 1041, so that the test result more truly reflects the actual performance of the client product. This structure design makes the test structure not only as a delivery product provided with the package substrate 101, but also can be used for reliability and impedance verification after packaging, which significantly improves the accuracy and practicality of the test data.

[0043] In an alternative embodiment, the test connectors 105 include a blind hole filling hole stacking structure and / or a plated through hole structure, and the test connectors 105 are arranged correspondingly with the functional circuit pattern 103.

[0044] As shown in Figure 3 , the blind hole filling hole stacking structure refers to that, in the layered processing of the multi-layer sub-board 102, blind holes are punched in each layer, and then conductive materials are filled into the blind holes to realize electrical connection with the test pattern 104 in the same layer, and then the connectors are connected between layers through the blind hole filling hole stacking structure.

[0045] As shown in Figure 4 , the plated through hole structure refers to that, after the sub-board is processed, a conductive layer is formed on the inner wall of the through hole through electroplating process to realize electrical connection with the connection test pattern in each layer.

[0046] The test connector is arranged at a position corresponding to the functional circuit pattern, so as to ensure that the test signal can be accurately transmitted to the target test area. The connector structure can be realized by laser drilling, chemical copper plating, and electroplating filling processes.

[0047] The test connector is selected as the same conductive connector as the functional circuit, so as to ensure that the test signal path is consistent with the electrical characteristics of the actual functional circuit, thereby obtaining test data closer to the real working condition.

[0048] Please refer to Figure 5 , Figure 5 is a partial structure schematic diagram of the third embodiment of the packaging structure of the present application.

[0049] In an embodiment, the test pattern 104 includes test pads 1042, and the test pads 1042 are arranged on at least one side surface of the sub-board 102 and connected to the corresponding test connectors 105.

[0050] The test pads 1042 are arranged on the surface of the sub-board 102 for connecting the test equipment, and the test pads 1042 are electrically connected to the test connectors 105, so that the test equipment can be connected to the test pattern 104 of the sub-board 102 through the test pads 1042.

[0051] In an embodiment, the test pads 1042 are arranged at positions aligned with the edges of the hole ring for providing test probe contact points. Based on the design of the test pads 1042 on one side surface of the sub-board 102, the size and layout of the test pads 1042 need to match the contact requirements of the test equipment, and the test pads 1042 can be formed by a copper foil layer or through an electroplating process.

[0052] By arranging the test pads 1042 on the surface of the sub-board 102, the actual electrical characteristic data of the sub-board 102 after packaging can be directly obtained, so as to ensure the consistency of the test results with the final product. The layout design of the test pads 1042 can be adapted to various test equipment, thereby improving the test efficiency. The connection mode of the test pads 1042 and the test connectors 105 avoids the damage to the product caused by the traditional destructive test, thereby reducing the test cost.

[0053] When the test is performed after the packaging is completed, the test pads 1042 can accurately reflect the influence of the process parameters on the product performance in the actual production process, thereby improving the reliability of the test data.

[0054] The connection of the test pads 1042, the test pattern 104, and the test connectors 105 enables the test equipment to complete the impedance test and reliability test through the test pads 1042, reduces the layout space required by the test structure, and meets various test requirements.

[0055] In other embodiments, the circuit of a layer of the multi-layer board structure can also be used as the test pad 1042 to realize the test function in cooperation with the test probe.

[0056] Please refer to Figure 6 , Figure 6 is a structural schematic diagram of the fourth embodiment of the packaging structure of the present application.

[0057] In an embodiment, the packaging structure 100 further comprises a packaging edge board 106 surrounding the outer edge of the packaging substrate 101.

[0058] In order to improve the production efficiency, the packaging structure 100 is composed of the packaging substrate 101 containing multiple sub-boards 102 and the packaging edge board 106. In the production process, the packaging structure 100 is divided, and the packaging edge board 106 is discarded, and only the sub-boards 102 of the packaging substrate 101 delivered as products are reserved for subsequent packaging.

[0059] The packaging edge board 106 is provided with the test pattern 104 and the test connecting piece 105, and the test pattern 104 of the packaging edge board 106 and the test pattern 104 of each sub-board 102 are insulated from each other. As shown in Figure 6 , the test pattern 104 and the test connecting piece 105 are provided at A of the packaging substrate 101, and the test pattern 104 and the test connecting piece 105 are provided at B of the packaging edge board 106, and the specific structure can refer to the test structure of the packaging structure 100 of Figures 2-5 .

[0060] The test pattern 104 can be formed on the surface of the edge board by electroplating or etching process, and the test structure on the packaging edge board 106 is made by using the same manufacturing process as the test structure of the sub-board 102, which can ensure the consistency of the test results between the test structures and the accuracy of the test.

[0061] The test pattern 104 of the packaging edge board 106 and the test pattern 104 of each sub-board 102 can be kept in an electrically insulated state by means of solder mask covering or physical isolation, for example, an insulating layer or an isolation groove is provided at the connection between the edge board and the sub-board 102, or an insulating ink is coated around the test pattern 104. By providing independent test patterns 104 on the packaging edge board 106 and realizing the insulation of the test patterns 104 of the sub-boards 102, it can be ensured that the data distortion caused by current leakage or signal interference in the test process is avoided, and the insulation design also effectively prevents the interference of the sub-boards 102 functional circuits and test structures during the test of the packaging edge board 106, thereby improving the test efficiency and data reliability.

[0062] Before the board is divided, the test pattern 104 and the test connector 105 on the packaging edge board 106 are tested, which can quickly locate the fault point, avoid waste in the subsequent packaging process, reduce product loss and overall cost, avoid material loss caused by traditional destructive testing, and ensure the packaging structure 100 and the reliability of subsequent test data in the production process.

[0063] Please refer to Figure 7 , Figure 7 is a structural schematic diagram of a first embodiment of a circuit board of the present application.

[0064] The second aspect of the present application provides a circuit board, which is a circuit board processed from any of the sub-boards.

[0065] The circuit board 200 is formed by completing the packaging processing of the cut sub-boards (not marked in the figure). The circuit board 200 is provided with functional circuit patterns (not marked in the figure), which can include lines for connecting components, transmitting signals, circuit vias or pads for connecting different layers, and patterns for power supply, filtering, impedance matching, etc.

[0066] The delivered circuit board 200 is provided with test patterns (not marked in the figure) and test connectors (not marked in the figure) at the edge C of the non-functional area. The test patterns and the test connectors are electrically connected to realize test signal transmission, so that the test patterns of the sub-boards and the functional circuit patterns (not marked in the figure) are tested after completing the packaging process, and then the non-functional area of the edge of the circuit board 200 is discarded to form the final product, ensuring that the test environment matches the actual application conditions.

[0067] The test patterns and the corresponding functional circuit patterns have the same impedance characteristics, and the test patterns and the functional circuit patterns can be manufactured by the same process, such as using the same material, or by ensuring that the width and length of the test lines are the same as the functional circuit patterns or using the same impedance control process to ensure impedance consistency, thereby improving the accuracy of the test results.

[0068] In some optional embodiments, the test connector of the circuit board 200 includes at least one of a via hole filling hole and a blind hole stacking hole, and the conductive pattern includes at least one of an impedance line and a test pad. The test connector, the impedance line and the test pad are set according to the design requirements of the client, and the width and length are consistent with the client product, and the hole ring edge is configured with a test pad.

[0069] The test pattern is arranged at the non-functional area C of the edge of the circuit board 200, so that the test pattern of the sub-board is synchronized with the functional circuit pattern to complete the packaging process, and then the test is performed to make the test data consistent with the actual product, and the non-functional area of the edge of the circuit board 200 is discarded to form the final product, and the test environment is matched with the actual application condition. The test pattern is designed synchronously with the actual product structure to make the test environment more close to the real application scene, improve the performance evaluation accuracy of the product after packaging, and finally improve the product yield and reduce the production cost.

[0070] To solve the above technical problems, the third aspect of the present application provides a manufacturing method of a circuit board, the manufacturing method being used for manufacturing any one of the packaging structures Figures 1-6 or Figure 7 circuit board.

[0071] Please refer to Figure 8 , Figure 8 is a flowchart of the processing steps of the first embodiment of the manufacturing method of the packaging structure of the present application. The manufacturing method comprises:

[0072] In an alternative embodiment, the manufacturing method of the packaging structure comprises: wherein the manufacturing method is used for manufacturing any one of the packaging structures, and the manufacturing method comprises:

[0073] S101: obtaining a base material, the base material comprising a plurality of sub-boards to be processed arranged in an array.

[0074] The base material has moderate electrical properties, mechanical strength and thermal stability, and is comprehensively considered according to specific application requirements, such as overall performance and application range of the product.

[0075] S102: sequentially arranging an insulating layer and a metal layer on the base material for packaging, forming corresponding functional circuit patterns in the functional area of the sub-boards to be processed, and forming test patterns and test connectors in the non-functional area of the edge of the sub-boards to be processed.

[0076] Each sub-board is provided with a functional circuit pattern, which can include a circuit for connecting elements, transmitting signals, connecting circuit vias or pads between different layers, and patterns for power supply, filtering, impedance matching, etc.

[0077] The edge of the sub-board is provided with test patterns and test connectors, and the test patterns and the test connectors realize test signal transmission through electrical connection.

[0078] When the metal layer is arranged, the functional circuit pattern, the test pattern and the test connector can be simultaneously arranged in a layer of metal layer through processes such as electroplating, laser or chemical etching.

[0079] The insulation between the test pattern and the power supply circuit pattern of the same metal layer can be achieved by setting a dielectric layer or a physical isolation. The test pattern and the functional circuit of each layer are electrically isolated by an insulation layer or an isolation structure, for example, an insulation medium such as a prepreg, a resin, or a reserved gap is arranged between the test pattern and the functional circuit. Such insulation design avoids interference with the functional circuit during the test process, ensures the test reliability, and also protects the functional circuit pattern.

[0080] The test pattern and the corresponding functional circuit pattern have the same impedance characteristics, and the test pattern and the functional circuit pattern can be manufactured by the same process, for example, the same material is used, or the width, length of the test line is ensured to be the same as the functional circuit pattern or the same impedance control process is used to ensure the impedance consistency, thereby improving the accuracy of the test result. The test connecting piece can be designed as a filling hole or a through hole for testing the alignment accuracy between layers, and can also be designed as a test pin, a test socket, etc., to facilitate the contact of the external test equipment.

[0081] S103: performing surface treatment to obtain the packaging structure.

[0082] The surface of the packaging structure, including the surface of the sub-plate, is subjected to cleaning, anti-oxidation treatment, surface protection, and other treatments to obtain the final delivery product. In some embodiments, according to production requirements, the packaging structure needs to be segmented to obtain individual sub-plates for convenient transportation and delivery.

[0083] Please refer to Figure 9 , Figure 9 is a flowchart of the processing steps of the second embodiment of the packaging structure manufacturing method of the present application.

[0084] In an alternative embodiment, the steps of sequentially arranging an insulation layer and a metal layer on a substrate for packaging, forming a corresponding functional circuit pattern in a functional area, and forming a test pattern and a test connecting piece in a non-functional area at the edge of the sub-plate include:

[0085] S1021: etching to form the test line and the functional circuit pattern when pressing the corresponding insulation layer and the metal layer.

[0086] When the metal layer is arranged, the functional circuit pattern, the test pattern, and the test connecting piece can be simultaneously arranged in one metal layer by processes such as electroplating, laser etching, or chemical etching.

[0087] The test pattern and the functional circuit of each layer are electrically isolated by an insulation layer or an isolation structure, for example, an insulation medium such as a prepreg, a resin, or a reserved gap is arranged between the test pattern and the functional circuit. Such insulation design avoids interference with the functional circuit during the test process, ensures the test reliability, and also protects the functional circuit pattern.

[0088] The test pattern and the corresponding functional circuit pattern have the same impedance characteristics, and the test pattern and the functional circuit pattern can be manufactured by the same process, for example, using the same material, or by ensuring that the width and length of the test line are the same as those of the functional circuit pattern or using the same impedance control process to ensure impedance consistency, thereby improving the accuracy of the test results. The test connecting piece can be designed as a filling hole or a through hole for testing the alignment accuracy between layers, and can also be designed as a test pin, a test socket, etc., to facilitate the contact of external test equipment.

[0089] and S1022: punching and electroplating to form the test connecting piece.

[0090] The test connecting piece includes a blind hole filling hole stack structure and / or an electroplated through hole structure. The blind hole filling hole stack structure refers to a connecting piece structure in which blind holes are punched in each layer during layered processing of a multi-layer sub-board, and then conductive materials are filled into the blind holes to realize electrical connection with the test pattern in the same layer, and then the blind holes in each layer are stacked to realize interlayer connection. The electroplated through hole structure refers to a structure in which a conductive layer is formed on the inner wall of the through hole by electroplating after the sub-board is processed, to realize electrical connection with the test pattern in each layer.

[0091] The test connecting piece is arranged at a position corresponding to the functional circuit pattern to ensure that the test signal can be accurately transmitted to the target test area. The connecting piece structure can be realized by laser drilling, chemical copper plating, electroplating filling, etc. The test connecting piece is selected to be the same as the conductive connecting piece of the functional circuit, which can ensure that the test signal path and the electrical characteristics of the actual functional circuit remain consistent, thereby obtaining test data closer to the actual working condition.

[0092] Please refer to Figure 10 , Figure 10 is a flowchart of the processing steps of the third embodiment of the manufacturing method of the packaging structure.

[0093] S201: obtaining a base material, the base material including a plurality of to-be-processed sub-boards arranged in an array and a to-be-processed edge plate surrounding the outer edges of the to-be-processed sub-boards.

[0094] The base material has moderate electrical properties, mechanical strength, and thermal stability, which are comprehensively considered according to specific application requirements, such as the overall performance and application range of the product. In order to improve production efficiency, the packaging structure is composed of a packaging substrate including a plurality of sub-boards and a packaging edge plate. In the production process, the packaging structure is divided, the packaging edge plate is discarded, and only the sub-boards of the packaging substrate delivered as products are reserved for subsequent packaging.

[0095] S202: An insulating layer and a metal layer are sequentially disposed on the substrate for encapsulation. Corresponding functional circuit patterns are formed in the functional area of ​​the sub-board to be processed, and test patterns and test connectors are formed in the non-functional area of ​​the sub-board to be processed. Test patterns and test connectors are formed on the edge board to be processed.

[0096] Each daughterboard has a functional circuit diagram, which may include lines for connecting components, transmitting signals, circuit vias or pads connecting different layers, and diagrams for power supply, filtering, impedance matching, etc.

[0097] The edge of the sub-board is provided with test patterns and test connectors. The test patterns and test connectors are electrically connected to realize the transmission of test signals. The test patterns on the edge board are insulated from the test patterns on each sub-board.

[0098] When setting up the metal layer, functional circuit patterns, test patterns, and test connectors can be simultaneously set within a single metal layer using processes such as electroplating, laser etching, or chemical etching. During the lamination of the metal layers, the test structure of the edge board uses the same manufacturing process as the test structure of the sub-board, ensuring consistency of test results between the test structures and guaranteeing test accuracy.

[0099] S203: Test patterns are formed on the packaging edge board and the test connectors are inspected.

[0100] S204: The packaged structure retains the sub-board after the cutting inspection has passed.

[0101] Testing the test patterns and test connectors on the packaging edge board before splitting the board can quickly locate the fault point, avoid waste in the subsequent packaging process, reduce product loss, and lower the overall cost. This avoids material loss caused by traditional destructive testing and ensures the reliability of the packaging structure in the production process and subsequent test data.

[0102] S205: Perform surface treatment to obtain the encapsulation structure.

[0103] The final product is obtained by cleaning, anti-oxidation treatment, and surface protection of the packaging structure surface, including the sub-board surface. In some embodiments, depending on production needs, the packaging structure needs to be segmented to obtain individual sub-boards for convenient transportation and delivery.

[0104] Through the above manner, the packaging structure or the delivered circuit board can meet various test requirements, not only can test in production, but also can still obtain test data through the test structure after the product is processed through subsequent packaging and the like, so that the performance detection of the whole life cycle of the product is realized, the performance detection of the whole life cycle of the product is realized, the difference between the test data of the test structure and the actual delivered product structure is ensured, the product reliability and yield are effectively improved, and the production cost is reduced.

[0105] In several embodiments provided in the present application, it should be understood that the disclosed system and device can be implemented in other manners. Obviously, the embodiments described are only a part of the embodiments of the present application, and not all the embodiments. Based on the embodiments in the present application, all the other embodiments obtained by a person of ordinary skill in the art without creative work shall fall within the protection scope of the present application. For example, the division of the above-described device embodiments is only a logical function division, and there can be another division manner in actual implementation. For example, a plurality of units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the units shown or discussed can be indirect coupling or communication connection through some interfaces, devices or units, and can be electrical, mechanical or in other forms.

[0106] It should be noted that if the directionality indication (such as up, down, left, right, front, back, etc.) is involved in the embodiments of the present application, the directionality indication is only used to explain the relative position relationship, motion condition, etc. between components in a certain posture (as shown in the drawings), and if the certain posture changes, the directionality indication also changes accordingly.

[0107] In the description of the present application, it should be noted that unless otherwise explicitly specified and limited, the terms "coupling", "connection", "connecting", "setting", "mounting" should be understood in a broad sense, for example, can be fixedly connected, can be detachably connected, or integrally connected; can be mechanically connected, or electrically connected; can be directly connected, or indirectly connected through an intermediate medium; can be internal communication of two elements. For those skilled in the art, the specific meanings of the above terms in the present application can be understood according to the specific circumstances.

[0108] The units described as separate components can or can not be physically separate, and the components shown as units can or can not be physical units, i.e. can be located in one place, or can be distributed on multiple network units. Part or all of the units can be selected to achieve the purpose of the present embodiment scheme according to actual needs.

[0109] In addition, the technical solutions among various embodiments can be combined with each other, but it must be based on that a person skilled in the art can realize, when the combination of the technical solutions appears contradictory or cannot be realized, it should be considered that the combination of the technical solutions does not exist, and is not within the protection scope required by the present application.

[0110] The above is only the implementation of the present application, and does not limit the patent scope of the present application, and any equivalent structure or equivalent process transformation using the content of the present application specification and drawings, or direct or indirect application in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A package structure, characterized by, The packaging structure comprises: a packaging substrate comprising a plurality of sub-boards arranged in an array, the sub-boards being provided with functional circuit patterns; each of the sub-boards is provided with a test pattern and a test connector, the test pattern being electrically connected to the corresponding test connector; at least part of the test pattern has the same impedance as the functional circuit pattern, and the test pattern and the functional circuit are insulated from each other.

2. The package structure of claim 1, wherein, The test pattern comprises a test circuit, and the sub-boards comprise at least one layer of circuit packaging, at least one layer of the sub-boards being provided with the test circuit, the test circuit having the same impedance as the functional circuit pattern in the same layer; each layer of the test circuit is electrically connected to each other through the test connector.

3. The package structure of claim 1, wherein, The test connector comprises a blind hole filling hole stacking structure and / or an electroplated through hole structure, and the test connector structure is arranged correspondingly to the functional circuit pattern.

4. The package structure of claim 1, wherein, The test pattern comprises a test pad, and at least one side surface of the sub-boards is provided with a test pad, the test pad being connected to the corresponding test connector.

5. The package structure of claim 1, wherein, The packaging structure further comprises a packaging edge plate surrounding the outer edge of the packaging substrate, and the packaging edge plate is provided with the test pattern and the test connector; the test pattern of the packaging edge plate is insulated from the test pattern of each of the sub-boards.

6. A circuit board, characterized by The circuit board is formed by processing the sub-boards according to any one of claims 1-5.

7. A method for fabricating a package structure, the method comprising: The manufacturing method is used to manufacture the packaging structure according to any one of claims 1-5, and the manufacturing method comprises: obtaining a base material, the base material comprising a plurality of to-be-processed sub-boards arranged in an array; sequentially arranging insulating layers and metal layers on the base material for packaging, forming corresponding functional circuit patterns in functional areas of the to-be-processed sub-boards, and forming test patterns and test connectors in non-functional areas of edges of the to-be-processed sub-boards; performing surface treatment to obtain the packaging structure.

8. The method of manufacturing according to claim 7, wherein, The step of sequentially arranging insulating layers and metal layers on the base material for packaging, forming corresponding functional circuit patterns in functional areas, and forming test patterns and test connectors in non-functional areas of edges of the to-be-processed sub-boards comprises: when the corresponding insulating layers and metal layers are pressed, etching is performed to form the test circuit and the functional circuit pattern, and the test circuit has the same impedance as the functional circuit pattern in the same layer; and / or, punching and electroplating are performed to form the test connector.

9. The method of manufacturing according to claim 7, wherein, The step of obtaining the base material comprises that the base material is formed with a to-be-processed edge plate surrounding the outer edge of the to-be-processed sub-boards; The step of sequentially arranging insulating layers and metal layers on the base material for packaging, and forming corresponding functional circuit patterns, test patterns and test connectors when the corresponding insulating layers and metal layers are pressed comprises: forming the test pattern and the test connector on the edge plate of the to-be-processed base material.

10. The method of manufacturing according to claim 9, wherein, The step of forming the test pattern and the test connector on the packaging edge plate comprises: detecting the test pattern and the test connector formed on the packaging edge plate; and cutting the packaging structure to retain the sub-boards when the test pattern and the test connector are qualified.

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