A system and method for dynamic adjustment of SOC bus transmission performance

Abstract

The application provides a SOC bus transmission performance dynamic adjustment system and method, monitors bandwidth data and transmission delay data of each master device under corresponding transaction types, compares and analyzes the bandwidth data and the transmission delay data and outputs bandwidth delay analysis results, dynamically adjusts the effective signal duty cycle and the maximum number of unfinished transactions allocated to the master device according to the priority order of the master device and the bandwidth delay analysis results. Thus, the bus bandwidth utilization is improved, the transmission congestion is reduced, the delay is reduced, the real-time requirement is met, and the system energy efficiency is optimized.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of SOC bus transmission technology, and particularly relates to a SOC bus transmission performance dynamic adjustment system and method. BACKGROUND

[0002] In modern System-on-Chip (SOC) architecture, the bus is the core communication channel connecting multiple master devices and slave devices, and its data transmission efficiency directly affects the overall performance, real-time performance and power consumption of the system. At present, the bus arbitration mechanism in the SOC mainly relies on Round Robin or Fixed-Priority Arbiter to coordinate the access of multiple master devices to shared bus resources.

[0003] Traditional arbiters usually adopt preset static strategies for scheduling, such as allocating bus usage rights according to fixed priority order or cyclic rotation. Under this mechanism, the access rights and timing of each master device are determined at the design stage, and lack the ability of dynamic adjustment at runtime. Although such methods are simple to implement and have predictable timing, they expose many limitations when faced with complex and variable system loads and diversified application requirements.

[0004] Firstly, low resource utilization is a significant problem of traditional arbitration mechanisms. Due to the inability to perceive real-time transmission load, channel bandwidth status and task urgency, fixed arbitration strategies are difficult to dynamically allocate bus resources according to actual needs. In the scenario of concurrent access by multiple master devices, it often appears that some bus channels are "idle" while other channels are "congested", resulting in low overall bandwidth utilization, with an average utilization rate of only 50%-60% in actual measurement, causing waste of valuable on-chip bandwidth resources.

[0005] Secondly, the lack of priority protection capability affects the real-time performance of the system. When high-priority tasks (such as real-time control signals, interrupt responses, etc.) and low-priority data transmission compete for the bus at the same time, fixed timing allocation may force critical tasks to wait for non-critical tasks to complete, resulting in critical data transmission delay. Such delay can reach milliseconds in some application scenarios, seriously affecting the response speed and stability of the system, and making it difficult to meet the needs of high real-time applications.

[0006] In addition, the lack of power consumption optimization mechanism further restricts the energy efficiency performance. The traditional arbiter does not have the ability to dynamically adjust the power consumption mode according to the bus load. Even when the system is in a low load or standby state, the bus still maintains a high frequency and high voltage operation mode, resulting in unnecessary static and dynamic power consumption. Studies have shown that the resulting power waste under light load conditions can be as high as 30%, severely limiting the application potential of SOC in mobile devices, Internet of Things terminals and other energy-sensitive fields. SUMMARY

[0007] The application provides a SOC bus transmission performance dynamic adjustment system and method, aiming to solve the technical problems of low utilization rate of SOC bus transmission resources, power consumption optimization and the like in the prior art.

[0008] A SOC bus transmission performance dynamic adjustment system comprises a transaction channel regulator for a corresponding transaction type, and the transaction channel regulator comprises: a bandwidth monitoring module for monitoring bandwidth data of the corresponding transaction type of each master device; a delay monitoring module for monitoring transmission delay data of the corresponding transaction type between each master device and a slave device; a bandwidth comparison module connected to the bandwidth monitoring module, for comparing and analyzing the bandwidth data and outputting a bandwidth analysis result; a delay comparison module connected to the delay monitoring module, for comparing and analyzing the transmission delay data and outputting a delay analysis result; a quality of service management module connected to the bandwidth comparison module and the delay comparison module respectively, for dynamically adjusting an effective signal duty cycle allocated to the master device according to a priority order of the master device, the bandwidth analysis result and the delay analysis result; and a waterline value management module connected to the bandwidth comparison module and the delay comparison module respectively, for dynamically adjusting a maximum number of unfinished transactions allocated to the master device according to the priority order of the master device, the bandwidth analysis result and the delay analysis result.

[0009] Further, the transaction channel regulator further comprises: a transaction control module connected to the quality of service management module and the waterline value management module respectively, for processing transactions of the transaction type based on the adjusted effective signal duty cycle and the maximum number of unfinished transactions; the transaction type is divided into two types of read transaction type and write transaction type; and the transaction channel regulator is a channel regulator for the read transaction type or a channel regulator for the write transaction type.

[0010] Further, the bandwidth monitoring module comprises: a request byte accumulation unit configured to accumulate the total number of bytes of the request burst to obtain a request byte accumulation result; a request bandwidth output unit connected to the request byte accumulation unit, configured to obtain and store the request byte accumulation result, and calculate and output the request bandwidth in the preset time window based on the request byte accumulation result; an actual byte accumulation unit configured to accumulate the number of bytes of a single transmission of the data channel to obtain an actual byte accumulation result; and an actual bandwidth output unit connected to the actual byte accumulation unit, configured to obtain and store the actual byte accumulation result, and calculate and output the actual bandwidth in the preset time window based on the actual byte accumulation result.

[0011] Further, the bandwidth data comprises the request bandwidth and the actual bandwidth in the preset time window; the bandwidth comparison module comprises: an actual bandwidth comparison unit configured to compare the actual bandwidth with the upper bandwidth threshold and the lower bandwidth threshold respectively, output a bandwidth excess upper limit comparison result when the actual bandwidth is greater than the upper bandwidth threshold, and output a bandwidth deficiency comparison result when the actual bandwidth is less than the lower bandwidth threshold; a bandwidth excess limit statistical unit connected to the actual bandwidth comparison unit, configured to continuously count the bandwidth excess upper limit comparison result according to a bandwidth excess limit statistical strategy to obtain a bandwidth excess limit statistical result; an excess limit statistical comparison unit connected to the bandwidth excess limit statistical unit, configured to compare the bandwidth excess limit statistical result with a preset bandwidth excess limit statistical threshold, and output a bandwidth analysis result of the bandwidth excess upper limit when the bandwidth excess limit statistical result is greater than the bandwidth excess limit statistical threshold; a bandwidth deficiency statistical unit connected to the actual bandwidth comparison unit, configured to continuously count the bandwidth deficiency comparison result according to a bandwidth deficiency statistical strategy to obtain a bandwidth deficiency statistical result; and a deficiency statistical comparison unit connected to the bandwidth deficiency statistical unit, configured to compare the bandwidth deficiency statistical result with a preset bandwidth deficiency statistical threshold, and output a bandwidth analysis result of the bandwidth deficiency when the bandwidth deficiency statistical result is greater than the bandwidth deficiency statistical threshold.

[0012] Further, the delay monitoring module comprises: a handshake success accumulation unit configured to accumulate the number of handshake successes between the master device and the slave device to obtain a success number accumulation result; a handshake success output unit connected to the handshake success accumulation unit, configured to calculate and output the total number of handshake successes in the preset time window according to the success number accumulation result; an actual delay calculation unit configured to obtain the actual number of delay periods of a single handshake success of the master-slave device and accumulate the actual delay accumulation result; and an actual delay statistical unit connected to the actual delay calculation unit, configured to calculate and output the total number of actual delay periods in the preset time window according to the actual delay accumulation result.

[0013] Further, the transmission delay data includes actual total delay cycle numbers in a preset time window; the delay comparison module includes: an expected delay accumulation unit, configured to accumulate expected delay cycle numbers of single handshake success of the master and the slave device to obtain an expected delay accumulation result; an expected delay output unit, connected to the expected delay accumulation unit, configured to calculate expected total delay cycle numbers in the preset time window according to the expected delay accumulation result; a delay initial comparison unit, connected to the expected delay output unit, configured to compare the actual total delay cycle numbers and the expected total delay cycle numbers, and output a delay timeout comparison result when the actual total delay cycle numbers are greater than the expected total delay cycle numbers; a delay timeout statistical unit, connected to the delay initial comparison unit, configured to continuously count the delay timeout comparison result according to a delay timeout statistical strategy to obtain a delay timeout statistical result; and a delay statistical comparison unit, connected to the delay timeout statistical unit, configured to compare the delay timeout statistical result with a preset delay timeout statistical threshold, and output a delay analysis result of delay timeout when the delay timeout statistical result is greater than the delay timeout statistical threshold.

[0014] Further, the bandwidth over-limit statistical strategy is to count total times or total time lengths of continuous bandwidth over-limit comparison results, and the bandwidth shortage statistical strategy is to count total times or total time lengths of continuous bandwidth shortage comparison results.

[0015] Further, the delay timeout statistical strategy is to count total times or total time lengths of continuous delay timeout comparison results.

[0016] Further, the delay timeout statistical threshold includes a first delay timeout statistical threshold and a second delay timeout statistical threshold, the first delay timeout statistical threshold is smaller than the second delay timeout statistical threshold, a delay analysis result of high delay is output when the delay timeout statistical result is greater than the first delay timeout statistical threshold, and a delay analysis result of super high delay is output when the delay timeout statistical result is greater than the second delay timeout statistical threshold.

[0017] A SOC bus transmission performance dynamic adjustment method using the SOC bus transmission performance dynamic adjustment system, including: step A1, monitoring bandwidth data of each master device under a corresponding transaction type and monitoring transmission delay data between each master device and the slave device under the corresponding transaction type; step A2, comparing and analyzing the bandwidth data and outputting a bandwidth analysis result, comparing and analyzing the transmission delay data and outputting a delay analysis result; and step A3, dynamically adjusting an effective signal duty cycle and a maximum unfinished transaction number allocated to the master device according to a priority order of the master device, the bandwidth analysis result and the delay analysis result.

[0018] The beneficial technical effect of the present application is that the waterline value depth and the effective signal duty cycle are dynamically adjusted by monitoring the bandwidth data and the delay data, so as to improve the bus bandwidth utilization, reduce the transmission congestion, reduce the delay, meet the real-time requirement, and optimize the system energy efficiency. BRIEF DESCRIPTION OF DRAWINGS

[0019] Figure 1 A module schematic diagram of the SOC bus transmission performance dynamic adjustment system of the present application;

[0020] Figure 2 A general structure schematic diagram of the SOC bus transmission performance dynamic adjustment system of the present application;

[0021] Figure 3 A data processing flow schematic diagram of the SOC bus transmission performance dynamic adjustment system of the present application;

[0022] Figure 4 A bandwidth monitoring module schematic diagram of the SOC bus transmission performance dynamic adjustment system of the present application;

[0023] Figure 5 A bandwidth comparison module schematic diagram of the SOC bus transmission performance dynamic adjustment system of the present application;

[0024] Figure 6 A delay monitoring module schematic diagram of the SOC bus transmission performance dynamic adjustment system of the present application;

[0025] Figure 7 A delay comparison module schematic diagram of the SOC bus transmission performance dynamic adjustment system of the present application;

[0026] Figure 8 A step flow chart of the SOC bus transmission performance dynamic adjustment method of the present application. DETAILED DESCRIPTION

[0027] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the protection scope of the present application.

[0028] It should be noted that the embodiments in the present application and the features in the embodiments can be combined with each other without conflict.

[0029] The present application will be further described below with reference to the drawings and specific embodiments, but is not limited to the present application.

[0030] ParticipationFigure 1 and Figure 2 The application provides a SOC bus transmission performance dynamic adjustment system, comprising a transaction channel regulator 100 for a corresponding transaction type, the transaction channel regulator 100 comprising: a bandwidth monitoring module 1 for monitoring bandwidth data of each master device under the corresponding transaction type, including an outstanding value and a quality of service (QoS) of an advanced extensible interface (AXI) bus protocol under a read-write transaction type, the outstanding value representing a number of current unfinished transactions, and the quality of service representing a transaction priority for arbitration and bandwidth control; a delay monitoring module 2 for monitoring transmission delay data between each master device and a slave device under the corresponding transaction type; a bandwidth comparison module 3 connected with the bandwidth monitoring module 1, for comparing and analyzing the bandwidth data and outputting a bandwidth analysis result; a delay comparison module 4 connected with the delay monitoring module 2, for comparing and analyzing the transmission delay data and outputting a delay analysis result; a quality of service management module 5 connected with the bandwidth comparison module 3 and the delay comparison module 4 respectively, for dynamically adjusting an effective signal duty cycle allocated for the master device according to a priority order of the master device, the bandwidth analysis result and the delay analysis result; and an outstanding value management module 6 connected with the bandwidth comparison module 3 and the delay comparison module 4 respectively, for dynamically adjusting a maximum number of unfinished transactions allocated for the master device according to the priority order of the master device, the bandwidth analysis result and the delay analysis result.

[0031] Referring to Figure 2 The system is also equipped with multiple interfaces, specifically including a data interface 8, a data export corresponding bus 9 and a configuration interface 10. The data interface 8 and the data export corresponding bus 9 respectively perform signal transmission with the transaction channel regulator 100 through an advanced extensible interface (AXI4), and the configuration interface 10 performs presetting and configuration on each parameter of the transaction channel regulator 100 through an advanced peripheral bus (APB).

[0032] A preset time window (such as 1ms-100ms) is configured, and bandwidth data (data throughput per unit time) corresponding to each Master device (master device) ID in the preset time window is counted in real time.

[0033] A measurement packet (such as a Ping packet) with a timestamp is sent, the round-trip time (RTT) from when the Master device sends a request to when the Slave (slave device) replies is monitored, and transmission delay data (such as a current delay of 50ns) is calculated.

[0034] The preset demand bandwidth threshold (e.g., Master device demand bandwidth ≥ 1 GB / s) and latency threshold (e.g., ≤ 30 ns) of each Master device are compared with the real-time bandwidth and latency, and a comparison result is output, such as insufficient bandwidth and excessive latency. According to the output signal of the comparator, the duty cycle of the valid signal of the read or write transaction, i.e., the Valid signal, and the maximum number of outstanding transactions, i.e., the Outstanding waterline value, are dynamically adjusted. The Outstanding number is the number of transactions that have been sent but have not been responded by the corresponding BID / RID. For example, the enable state of the Master device to initiate a read / write request is controlled, the Valid signal effective time of the Master device with insufficient bandwidth is reduced (e.g., from 100% duty cycle to 60%), and resources are released for high-priority Masters. For another example, the maximum number of outstanding transactions is adjusted (e.g., from 8 to 4), the waterline value depth of low-priority tasks is reduced, bus competition is reduced, and power consumption optimization is achieved by reducing the flip frequency (e.g., dynamic power consumption is reduced by 20%).

[0035] By dynamically adjusting the waterline value depth and the effective signal duty cycle through monitoring the bandwidth data and the delay data, the bus bandwidth utilization is improved, the transmission congestion is reduced, the delay is reduced, the real-time requirement is met, and the system energy efficiency is optimized.

[0036] Further, the transaction channel regulator 100 further comprises a transaction control module 7 connected to the quality of service management module 5 and the waterline value management module 6, respectively, for processing transactions of a transaction type based on the adjusted effective signal duty cycle and the maximum number of outstanding transactions; the transaction type is divided into read transaction type and write transaction type; see Figure 3 The transaction channel regulator 100 is a channel regulator 101 for read transaction type or a channel regulator 102 for write transaction type.

[0037] The channel regulator 101 for read transaction type comprises read address input signal AR IN and read address output signal AR OUT corresponding to read address channel (read address channel), and read data input signal R IN and read data output signal R OUT corresponding to read data channel (read data address channel).

[0038] The read transaction type channel regulator 101 comprises a first bandwidth monitoring module la, a first latency monitoring module 2a, a first bandwidth comparator 3a, a second bandwidth comparator 3b, a first latency comparator 4a, a second latency comparator 4b, a first quality of service management module 5a, a first water line value management module 6a, a read transaction controller 7a and a read water line value monitor 131. The first bandwidth monitoring module la is connected to the first bandwidth comparator 3a and the second bandwidth comparator 3b, the first latency monitoring module 2a is connected to the first latency comparator 4a and the second latency comparator 4b, the first quality of service management module 5a is connected to the second bandwidth comparator 3b and the second latency comparator 4b, the first water line value management module 6a is connected to the first bandwidth comparator 3a and the first latency comparator 4a, the read transaction controller 7a is connected to the first quality of service management module 5a and the first water line value management module 6a, and the read water line value monitor 131 is connected to the first bandwidth monitoring module la and the read transaction controller 7a.

[0039] The write transaction type channel regulator 102 comprises a write address input signal AW IN and a write address output signal AW OUT corresponding to a write address channel, a read data input signal W IN and a write data output signal W OUT corresponding to a write data channel, and a write response input signal B IN and a write response output signal B OUT corresponding to a write response channel.

[0040] The module architecture of the write transaction type channel regulator 102 is similar to that of the read transaction type channel regulator 101. The write transaction type channel regulator 102 comprises a second bandwidth monitoring module lb, a second latency monitoring module 2b, a third bandwidth comparator 3c, a fourth bandwidth comparator 3d, a third latency comparator 4c, a fourth latency comparator 4d, a second quality of service management module 5b, a second water line value management module 6b, a write transaction controller 7b and a write water line value monitor 132. The second bandwidth monitoring module lb is connected to the third bandwidth comparator 3c and the fourth bandwidth comparator 3d, the second latency monitoring module 2b is connected to the third latency comparator 4c and the fourth latency comparator 4d, the second quality of service management module 5b is connected to the fourth bandwidth comparator 3d and the fourth latency comparator 4d, the second water line value management module 6b is connected to the third bandwidth comparator 3c and the third latency comparator 4c, the write transaction controller 7b is connected to the second quality of service management module 5b and the second water line value management module 6b, and the write water line value monitor 132 is connected to the second bandwidth monitoring module lb and the write transaction controller 7b.

[0041] Referring to Figure 3The transaction channel regulator 100 further comprises a time pulse generator 103 for generating a time pulse signal and a configuration register 104 for storing preset and configured parameters.

[0042] Referring to Figure 4 Further, the bandwidth monitoring module 1 comprises a request byte accumulation unit 11 for accumulating the total number of bytes of the request burst to obtain an accumulated result of the number of bytes of the request, a request bandwidth output unit 12 connected to the request byte accumulation unit 11 for obtaining and storing the accumulated result of the number of bytes of the request, calculating the request bandwidth in the current preset time window based on the accumulated result of the number of bytes of the request and outputting the request bandwidth, an actual byte accumulation unit 13 for accumulating the number of bytes of single transmission of the data channel to obtain an accumulated result of the number of actual bytes, and an actual bandwidth output unit 14 connected to the actual byte accumulation unit 13 for obtaining and storing the accumulated result of the number of actual bytes, calculating the actual bandwidth in the current preset time window based on the accumulated result of the number of actual bytes and outputting the actual bandwidth.

[0043] Referring to Figure 4 The structural diagram of the bandwidth monitoring module is shown in the figure. As to the input and output signals in the figure, the following explanations are given. Figure 4

[0044] The aresetn signal represents an asynchronous reset signal (active low) for resetting all registers and counters in the module. Wherein, X represents the direction of the data channel, X as R represents a read transaction, and X as W represents a write transaction. When an exception occurs in the system, the module needs to be reset as a whole or a function is not used, and before next use, the asynchronous reset can be used to achieve initialization before use, so that all registers, pointers and state machines return to the initial state completely.

[0045] The signals at the input side of the bandwidth monitoring module 1 are as follows.

[0046] The aclk is an AXI bus clock signal, and the timing logic of the module is synchronized therewith. All data transmission, address sending, control signal changes (such as handshake signals) related to AXI must be performed under the driving of the clock.

[0047] The axlen represents the length of the burst transmission (Burst Length), and axlen = burst transmission times - 1 (for example, axlen = 3 corresponds to 4 times of transmission).

[0048] The axsize represents the transmission size (if arsize, it represents the read transmission size, and if awsize, it represents the write transmission size): 2^axsize is the number of bytes of a single beat (such as axsize = 2 corresponds to 4 bytes.

[0049] ​axvalid represents an address channel valid signal valid, indicating that the address and control signals on the current address channel are valid, and must be used in cooperation with the axready of the slave device.

[0050] axready represents an address channel ready signal ready, and the slave device declares that it is ready to receive address / control information, which is the "reception capability feedback" of the slave device to the master device, and is the "response" part in the AXI bidirectional handshake mechanism.

[0051] Time_pulse is a time pulse signal, triggering a preset time window update (clearing the counter and counting the bandwidth in the preset time window).

[0052] xvalid, X=R→rvalid (read data valid), X=W→wvalid (write data valid), represents a data channel valid signal valid, and the master device (write) or the slave device (read) declares that the data is valid, which must be used in cooperation with the corresponding xready signal (wready / rready) to complete the handshake.

[0053] xready, X=R→rready (read ready), X=W→wready (write ready), represents a data channel ready signal ready, and the slave device (write) or the master device (read) declares that it is ready to receive and transmit data.

[0054] XDATA_BYTE_NUM, X=R→read data single beat byte number, X=W→write data single beat byte number, represents the number of bytes transmitted in a single transmission of the data channel (determined by the bus width, such as 8 bytes for a 64-bit bus).

[0055] The signals on the output side of the bandwidth monitoring module 1 are as follows.

[0056] Cur_bw_req_byte_num, represents the total number of bytes of burst requests successfully handshaked in the current preset time window of the address channel, which is the accumulation result of (axlen+1)×(2^axsize), that is, the request bandwidth.

[0057] Cur_bw_req_byte_num_valid, indicates whether the request bandwidth Cur_bw_req_byte_num is valid (set high when there is address handshake in the window).

[0058] Cur_bw_rt_byte_num, represents the actual number of bytes of data channel handshake successfully in the current preset time window, that is, the actual bandwidth, which is the accumulation result of XDATA_BYTE_NUM.

[0059] Cur_bw_rt_byte_num_valid, a second indication signal indicating whether the actual bandwidth Cur_bw_rt_byte_num is valid (set high when there is corresponding direction data handshake in the window).

[0060] Specifically, referring to Figure 4 , the request byte accumulation unit 11 includes a multiplier Mul1, a first AND gate AND1, a first multiplexer Sel1, a first adder ADD1 and a first flip-flop D1; the first input end of the multiplier Mul1 inputs the burst transmission length axlen, the second output end of the multiplier Mul1 inputs the request transmission size axsize, and the output end of the multiplier Mul1 outputs the request burst total byte number; the first input end and the second input end of the first AND gate AND1 input the address channel ready signal axready and the address channel valid signal axvalid respectively, the first input end of the first multiplexer Sel1 is connected with the output end of the multiplier Mul1, the second input end of the first multiplexer Sel1 inputs a 0 value, the third input end of the first multiplexer Sel1 is connected with the output end of the first AND gate AND1, and the first multiplexer Sel1 is used for: when the output end of the first AND gate AND1 outputs a high level, the output end of the first multiplexer Sel1 selects the first input end of the first multiplexer Sel1 to output; when the output end of the first AND gate AND1 outputs a low level, the output end of the first multiplexer Sel1 selects the second input end of the first multiplexer Sel1 to output; the first input end of the first adder ADD1 is connected with the output end of the first multiplexer Sel1; the D input end of the first flip-flop D1 is connected with the output end of the first adder ADD1, the Q output end of the first flip-flop D1 is connected with the second input end of the first adder ADD1, and the Q output end of the first flip-flop D1 is also connected with the input end of the request bandwidth output unit 12 as the output end of the request byte accumulation unit 11.

[0061] Specifically, the request bandwidth output unit 12 includes a first accumulation unit SUM1, a first shift register Seg1, and a first load counter LC1 (i.e., load counter 1); the Q output end of the first flip-flop D1 is respectively connected to the positive input end of the first accumulation unit SUM1 and the input end of the first shift register Seg1; the first shift register Seg1 is composed of a plurality of flip-flops, and the output end of the first shift register Seg1 is connected to the negative input end of the first accumulation unit SUM1; the first load counter LC1 is used to load and count a preset time window according to a time pulse signal Time_pulse and a load signal, and output a first indication signal Cur_bw_req_byte_num_valid indicating whether the request bandwidth output is valid, a high level indicating validity, and if there is no address handshake in the time window, Cur_bw_req_byte_num_valid = 0, i.e., a low level (the output request bandwidth is invalid).

[0062] The first accumulation unit SUM1 outputs the valid request bandwidth in the current preset time window when the first indication signal is at a high level.

[0063] Master-slave device handshake triggers accumulation. For an address channel, whether it is a read request or a write request, as long as axvalid = 1 & axready = 1 (handshake success), the output end of the first AND gate AND1 outputs a high level 1, the total number of bytes of the burst (axlen + 1) × (2^axsize) is immediately calculated and accumulated to the request bandwidth output unit 12, the first load counter LC1 loads a preset time window, and the first accumulation unit SUM1 outputs the total number of bytes of the request burst accumulated in the current preset time window to form the request bandwidth output, and then the first load counter LC1 is cleared according to the clear signal to reload the preset time window, and the first accumulation unit SUM1 performs a subtraction operation on the output of the first shift register Seg1 to realize clearing. The load signal and the clear signal trigger the window loading and clearing of the first load counter LC1, so as to ensure that Cur_bw_req_byte_num only counts the request bandwidth in the current preset time window (such as 1 ms or 1 s), and supports periodic monitoring.

[0064] Further, the actual byte accumulation unit 13 comprises a second AND gate AND2, a second multiplexer Sel2, a second adder ADD2 and a second flip-flop D2; the first and second inputs of the second AND gate AND2 are inputted with the data channel valid signal xvalid and the data channel ready signal xready respectively; the first input of the second multiplexer Sel2 is inputted with the single transmission byte number XDATA_BYTE_NUM of the data channel, the second input of the second multiplexer Sel2 is inputted with 0, and the third input of the second multiplexer Sel2 is connected with the output of the second AND gate AND2, for: when the output of the second AND gate AND2 outputs high level, the output of the second multiplexer Sel2 selects the first input of the second multiplexer Sel2 to output; when the output of the second AND gate AND2 outputs low level, the output of the second multiplexer Sel2 selects the second input of the second multiplexer Sel2 to output; the first input of the second adder ADD2 is connected with the output of the second multiplexer Sel2; the D input of the second flip-flop D2 is connected with the output of the second adder ADD2, the Q output of the second flip-flop D2 is connected with the second input of the second adder ADD2, and the Q output of the second flip-flop D2 is also used as the input of the actual bandwidth output unit 14.

[0065] Further, the actual bandwidth output unit 14 comprises: a second accumulation unit SUM2, a second shift register Seg2 and a second load counter LC2 (i.e. load counter 2); the Q output of the second flip-flop D2 is connected with the positive input of the second accumulation unit SUM2 and the input of the second shift register Seg2 respectively; the second shift register Seg2 is composed of a plurality of flip-flops, and the output of the second shift register Seg2 is connected with the negative input of the second accumulation unit SUM2; the second load counter LC2 (i.e. load counter 2) is used for time counting according to the load signal and the time pulse signal Time_pulse to load the preset time window, and is used for outputting a second indication signal Cur_bw_rt_byte_num_valid indicating whether the actual bandwidth output is valid, if high level, it means that the output is valid, if there is no data handshake of the corresponding direction (read / write) in the window, Cur_bw_rt_byte_num_valid = 0 (actual bandwidth data is invalid).

[0066] When the second indication signal Cur_bw_rt_byte_num_valid is high level, the actual bandwidth Cur_bw_rt_byte_num outputted by the second accumulation unit SUM2 is valid.

[0067] For the write transaction scenario (X = W): wvalid & wready = 1, accumulate XDATA_BYTE_NUM (the number of bytes of the single beat of the write data, that is, the number of bytes of the single transmission of the data channel) to the actual bandwidth output unit 14.

[0068] For the read transaction scenario (X = R): rvalid & rready = 1, accumulate XDATA_BYTE_NUM (the number of bytes of the single beat of the read data) to the actual bandwidth output unit 14.

[0069] The second accumulation unit SUM2 outputs the actual transmission total byte number in the current preset time window, that is, the request bandwidth output, and then the first loading counter LC1 is cleared according to the clear signal to reload the preset time window, and the second accumulation unit SUM2 performs a subtraction operation on the output of the second register Seg2 to realize the clearing. The load signal and the clear signal trigger the window loading and clearing of the second loading counter LC2, so as to ensure that the Cur_bw_rt_byte_num only counts the actual bandwidth in the current preset time window (such as 1 ms or 1 s).

[0070] Referring to Figure 5 , further, the bandwidth data includes the request bandwidth and the actual bandwidth in the preset time window; the bandwidth comparison module 3 includes: an actual bandwidth comparison unit 31, configured to compare the actual bandwidth with an upper bandwidth threshold and a lower bandwidth threshold respectively, output a bandwidth excess upper limit comparison result when the actual bandwidth is greater than the upper bandwidth threshold, and output a bandwidth deficiency comparison result when the actual bandwidth is less than the lower bandwidth threshold; a bandwidth excess limit statistical unit 32 connected to the actual bandwidth comparison unit 31, configured to continuously count the bandwidth excess upper limit comparison result according to a bandwidth excess limit statistical strategy, and obtain a bandwidth excess limit statistical result; an excess limit statistical comparison unit 33 connected to the bandwidth excess limit statistical unit 32, configured to compare the bandwidth excess limit statistical result with a preset bandwidth excess limit statistical threshold, and output a bandwidth analysis result of the bandwidth excess upper limit when the bandwidth excess limit statistical result is greater than the bandwidth excess limit statistical threshold; a bandwidth deficiency statistical unit 34 connected to the actual bandwidth comparison unit 31, configured to continuously count the bandwidth deficiency comparison result according to a bandwidth deficiency statistical strategy, and obtain a bandwidth deficiency statistical result; and a deficiency statistical comparison unit 35 connected to the bandwidth deficiency statistical unit 34, configured to compare the bandwidth deficiency statistical result with a preset bandwidth deficiency statistical threshold, and output a bandwidth analysis result of the bandwidth deficiency when the bandwidth deficiency statistical result is greater than the bandwidth deficiency statistical threshold.

[0071] The bandwidth comparison module 3 can adjust and converge the currently monitored actual bandwidth data to the target set demand bandwidth on the basis that the physical hardware is satisfied.

[0072] Referring to Figure 5Fig. 1 is a structural schematic diagram of a bandwidth comparison module of the present application.

[0073] The input side signals are shown as follows.

[0074] Bw_over_cnt_bound, bandwidth over-limit statistical threshold, statistical upper limit of bandwidth over-limit events, limits the number of consecutive "bandwidth over-limit".

[0075] Bw_over_bound, bandwidth upper limit threshold, when the actual bandwidth Cur_bw monitored by Monitor is greater than Bw_over_bound, trigger "over-limit" judgment;

[0076] Bw_under_bound, bandwidth lower limit threshold, when Cur_bw is less than Bw_under_bound, trigger "low bandwidth" judgment.

[0077] Bw_under_cnt_bound, bandwidth shortage statistical threshold, statistical upper limit of bandwidth shortage events, limits the number of consecutive "bandwidth shortage".

[0078] Cur_bw, actual bandwidth, actual bandwidth Cur_bw_rt_byte_num output from bandwidth monitoring module 1.

[0079] Cur_bw_valid, a third indication signal indicating whether the current input actual bandwidth is valid, a second indication signal indicating whether the actual bandwidth output from the bandwidth monitoring module is valid Cur_bw_rt_byte_num_valid. Actual bandwidth Cur_bw.

[0080] Time_pulse, time pulse signal.

[0081] Register_update, shift register update / clear signal, triggers the reset of the shift register (such as clearing after the period ends, preparing for the next round of statistics).

[0082] The output side signals are shown as follows.

[0083] Bw_over_flag, indicates the bandwidth analysis result of bandwidth over-limit, i.e. bandwidth over-limit.

[0084] Bw_over_flag_valid, a fourth indication signal indicating whether the bandwidth analysis result output of bandwidth over-limit is valid, for example, high level indicates valid and low level indicates invalid.

[0085] Bw_under_flag, indicates the bandwidth analysis result of bandwidth shortage, i.e. bandwidth lower limit.

[0086] Bw_under_flag_valid, a fifth indication signal indicating whether the bandwidth analysis result output of the bandwidth deficiency is valid, for example, indicating valid when being high level and indicating invalid when being low level.

[0087] Further, the actual bandwidth comparison unit 31 comprises a first comparator Com1 and a second comparator Com2; the first input end of the first comparator Com1 inputs the bandwidth upper limit threshold Bw_over_bound, the second input end of the first comparator Com1 inputs the actual bandwidth Cur_bw, the output end of the first comparator Com1 outputs the comparison result of the actual bandwidth Cur_bw and the bandwidth upper limit threshold Bw_over_bound, for example, outputting high level indicating the bandwidth over upper limit comparison result when the actual bandwidth Cur_bw is greater than the bandwidth upper limit threshold Bw_over_bound, outputting low level indicating the bandwidth not over upper limit comparison result when the actual bandwidth Cur_bw is not greater than the bandwidth upper limit threshold Bw_over_bound. The output end of the first comparator Com1 is connected to the input end of the bandwidth over limit statistics unit 32.

[0088] The first comparator Com1 is a greater than comparator, the second input end of the first comparator Com1 is the comparison former input end, the first input end of the first comparator Com1 is the comparison latter input end, outputting true value 1, i.e. high level, if the former is greater than the latter, outputting true value 0, i.e. low level, if the former is not greater than the latter.

[0089] The first input end of the second comparator Com2 inputs the bandwidth lower limit threshold Bw_under_bound, the second input end of the second comparator Com2 inputs the actual bandwidth Cur_bw, the output end of the second comparator Com2 outputs the comparison result of the actual bandwidth Cur_bw and the bandwidth lower limit threshold Bw_under_bound, for example, outputting high level indicating the bandwidth deficiency comparison result when the actual bandwidth Cur_bw is less than the bandwidth lower limit threshold Bw_under_bound, outputting low level indicating the bandwidth sufficient comparison result when the actual bandwidth Cur_bw is not less than the bandwidth lower limit threshold Bw_under_bound. The output end of the second comparator Com2 is connected to the input end of the bandwidth deficiency statistics unit 34.

[0090] The second comparator Com2 is a less than comparator, the second input end of the second comparator Com2 is the comparison former input end, the first input end of the second comparator Com2 is the comparison latter input end, outputting true value 1, i.e. high level, if the former is less than the latter, outputting true value 0, i.e. low level, if the former is not less than the latter.

[0091] The bandwidth comparison module further comprises a third AND gate AND3, a first input end of the third AND gate AND3 inputs the third indication signal Cur_bw_valid, a second input end of the third AND gate AND3 inputs the time pulse signal Time_pulse, and an output end of the third AND gate AND3 outputs a window loading signal load, and a loading counter load counter starts counting according to the loading of the new preset time window according to the loading signal load.

[0092] The actual bandwidth comparison unit 31 is further configured to receive a third indication signal Cur_bw_valid, and start the first comparator Com1 and the second comparator Com2 when the third indication signal Cur_bw_valid is a valid indication.

[0093] Further, the bandwidth over-limit statistics unit 32 comprises a third accumulation unit SUM3, a third shift register Seg3, and a third loading counter LC3 (i.e., load counter 3); an output end of the first comparator Com1 is connected to a positive input end of the third accumulation unit SUM3 and an input end of the third shift register Seg3, respectively; the third shift register Seg3 is composed of a plurality of flip-flops, and an output end of the third shift register Seg3 is connected to a negative input end of the third accumulation unit SUM3; the third loading counter LC3 (i.e., load counter 3) is configured to perform time counting according to the load signal and the time pulse signal Time_pulse to load a preset time window, and output a fourth indication signal Bw_over_flag_valid indicating whether the bandwidth analysis result indicating that the bandwidth is over the upper limit is valid.

[0094] The third accumulation unit SUM3 outputs a bandwidth over-limit statistics result.

[0095] Further, the over-limit statistics comparison unit 33 comprises a third comparator Com3; a first input end of the third comparator Com3 inputs a bandwidth over-limit statistics threshold Bw_over_cnt_bound, a second input end of the third comparator Com3 is connected to an output end of the third accumulation unit SUM3 and inputs a bandwidth over-limit statistics result, and an output end of the third comparator Com3 outputs a comparison result of the bandwidth over-limit statistics result and the bandwidth over-limit statistics threshold, for example, when the bandwidth over-limit statistics result is greater than the bandwidth over-limit statistics threshold, a high level is output to indicate the bandwidth analysis result Bw_over_flag indicating that the bandwidth is over the upper limit, and when the bandwidth over-limit statistics result is not greater than the bandwidth over-limit statistics threshold, a low level is output to indicate the bandwidth analysis result indicating that the bandwidth is not over the upper limit.

[0096] The third comparator Com3 is a greater than comparator. The second input terminal of the third comparator Com3 is a preceding input terminal for comparison, and the first input terminal of the third comparator Com3 is a subsequent input terminal for comparison. If the preceding input is greater than the subsequent input, a true value 1, i.e. a high level, is output; if the preceding input is not greater than the subsequent input, a true value 0, i.e. a low level, is output.

[0097] The fourth indication signal Bw_over_flag_valid is high when the bandwidth analysis result of the bandwidth over threshold output by the third comparator Com3 is valid.

[0098] Further, the bandwidth deficiency statistics unit 34 comprises a fourth accumulation unit SUM4, a fourth shift register Seg4 and a fourth load counter LC4 (i.e. load counter 4). The output terminal of the second comparator Com2 is connected to the positive input terminal of the fourth accumulation unit SUM4 and the input terminal of the fourth shift register Seg4, respectively. The fourth shift register Seg4 is composed of a plurality of flip-flops. The output terminal of the fourth shift register Seg4 is connected to the negative input terminal of the fourth accumulation unit SUM4. The fourth load counter LC4 is used for time counting according to the load signal and the time pulse signal Time_pulse to load a preset time window. The fourth load counter LC4 is used for outputting a fifth indication signal Bw_under_flag_valid indicating whether the bandwidth analysis result output of the bandwidth deficiency is valid. If the fifth indication signal Bw_under_flag_valid is high, it means that the output is valid.

[0099] The fourth accumulation unit SUM4 outputs the bandwidth deficiency statistics result.

[0100] Further, the deficiency statistics comparison unit 35 comprises a fourth comparator Com4. The first input terminal of the fourth comparator Com4 inputs a bandwidth deficiency statistics threshold Bw_under_cnt_bound. The second input terminal of the fourth comparator Com4 is connected to the output terminal of the fourth accumulation unit SUM4, and inputs the bandwidth deficiency statistics result. The output terminal of the fourth comparator Com4 outputs the comparison result of the bandwidth deficiency statistics result and the bandwidth deficiency statistics threshold. For example, when the bandwidth deficiency statistics result is greater than the bandwidth deficiency statistics threshold, a high level is output, indicating the bandwidth analysis result Bw_under_flag of the bandwidth deficiency over threshold. When the bandwidth deficiency statistics result is not greater than the bandwidth deficiency statistics threshold, a low level is output, indicating the bandwidth analysis result of the bandwidth deficiency not below the lower limit.

[0101] The fourth comparator Com4 is a greater than comparator. The second input terminal of the fourth comparator Com4 is a preceding input terminal for comparison, and the first input terminal of the fourth comparator Com4 is a subsequent input terminal for comparison. If the preceding input is greater than the subsequent input, a true value 1, i.e. a high level, is output; if the preceding input is not greater than the subsequent input, a true value 0, i.e. a low level, is output.

[0102] The fifth indication signal Bw_under_flag_valid is high when indicating that the bandwidth analysis result of the bandwidth output by the fourth comparator Com4 is valid.

[0103] Referring to Figure 6 Further, the delay monitoring module comprises: a handshake success accumulation unit 21, configured to accumulate the number of successful handshakes between the master device and the slave device to obtain a success number accumulation result; a handshake success output unit 22, connected to the handshake success accumulation unit 21, configured to calculate and output the total number of successful handshakes within a preset time window according to the success number accumulation result; an actual delay calculation unit 23, configured to accumulate the actual number of delay cycles of a single successful handshake between the master device and the slave device to obtain an actual delay accumulation result; and an actual delay statistical unit 24, connected to the actual delay calculation unit 23, configured to calculate and output the actual total number of delay cycles within the preset time window according to the actual delay accumulation result.

[0104] Referring to Figure 6 The structure of the delay monitoring module is shown in the figure. The signals on the input side are as follows.

[0105] The meanings of aresetn, aclk, axvalid, axready and Time_pulse have been described above and will not be repeated here.

[0106] Cur_ost_num represents the number of delay cycles of a single successful handshake between the devices, i.e., the actual number of delay cycles of a single successful handshake between the devices (externally provided, such as the number of cycles from request to completion).

[0107] The signals on the output side are as follows.

[0108] Cur_trans_num represents the number of transmissions of the address channel within a preset time window, i.e., the total number of successful handshakes (axvalid & axready trigger count).

[0109] Cur_trans_num_valid is a sixth indication signal indicating whether the output of the total number of successful handshakes is valid (set high when there is a handshake within the window, otherwise 0).

[0110] Cur_tol_latency represents the actual total number of delay cycles within the current time window (Cur_ost_num real-time accumulation).

[0111] Cur_tol_latency_valid is a seventh indication signal indicating whether the output of the actual total number of delay cycles is valid (set high when there is transmission within the window, otherwise 0).

[0112] Specifically, the handshake success accumulation unit 21 comprises a fourth AND gate AND4, a third adder ADD3 and a third flip-flop D3; the first input end and the second input end of the fourth AND gate AND4 input the address channel valid signal axvalid and the address channel ready signal axready respectively, for counting the number of axready==1&axvalid==1 completed in the current time window, so as to count the number of read and write commands issued by the bus; the first input end of the third adder ADD3 is connected to the output end of the fourth AND gate AND4, the second input end of the third adder ADD3 is connected to the Q output end of the third flip-flop D3; the output end of the third adder ADD3 is connected to the D input end of the third flip-flop D3; the Q output end of the third flip-flop D3 also serves as an input end of the handshake success output unit 22.

[0113] Specifically, the handshake success output unit 22 comprises a fifth accumulation unit SUM5, a fifth shift register Seg5 and a fifth load counter LC5 (i.e. load counter 5); the Q output end of the third flip-flop D3 is connected to the positive input end of the fifth accumulation unit SUM5 and the input end of the fifth shift register Seg5 respectively; the fifth shift register Seg5 is composed of a plurality of flip-flops, and the output end of the fifth shift register Seg5 is connected to the negative input end of the fifth accumulation unit SUM5; the fifth load counter LC5 is used for time counting according to the load signal and the time pulse signal Time_pulse to load a preset time window, and a sixth indication signal Cur_trans_num_valid for indicating whether the handshake success total number Cur_trans_num output in the preset time window is valid, if it is high, it means that the output is valid.

[0114] The fifth accumulation unit SUM5 outputs the handshake success total number.

[0115] Specifically, the actual delay calculation unit 23 comprises a fourth adder ADD4 and a fourth flip-flop D4; the first input end of the fourth adder ADD4 inputs the actual delay cycle number Cur_ost_num of single device handshake success; the second input end of the fourth adder ADD4 is connected to the Q output end of the fourth flip-flop D4; the output end of the fourth adder ADD4 is connected to the D input end of the fourth flip-flop D4; the Q output end of the fourth flip-flop D4 also serves as an input end of the real-time delay counting unit 24.

[0116] In particular, the actual latency counting unit 24 comprises a sixth accumulation unit SUM6, a sixth shift register Seg6 and a sixth load counter LC6; the Q output terminal of the fourth flip-flop D4 is connected to the positive input terminal of the sixth accumulation unit SUM6 and the input terminal of the sixth shift register Seg6, respectively; the sixth shift register Seg6 is composed of a plurality of flip-flops, and the output terminal of the sixth shift register Seg6 is connected to the negative input terminal of the sixth accumulation unit SUM6; the sixth load counter LC6 (i.e., load counter 3) is used to count time according to the load signal and the time pulse signal Time_pulse to load the preset time window, and the seventh indication signal Cur_tol_latency_valid indicating whether the actual total latency cycle number output is valid is high, i.e., the output is valid.

[0117] The sixth accumulation unit SUM6 outputs the actual total latency cycle number.

[0118] The number of read-write instructions issued in the current time window is counted and compared with the accumulated tolerance value that can be received, and the read-write instructions exceeding the accumulated tolerance value need to be waited for, and the accumulated value of the waiting time is counted.

[0119] Referring to Figure 7 Further, the transmission latency data comprises the actual total latency cycle number in the preset time window; the latency comparison module 4 comprises: an expected latency accumulation unit 41, used to accumulate the expected latency cycle number of the single handshake success of the master-slave device to obtain an expected latency accumulation result; an expected latency output unit 42, connected to the expected latency accumulation unit 41, used to calculate the expected total latency cycle number in the preset time window according to the expected latency accumulation result; a latency initial comparison unit 43, connected to the expected latency output unit 42, used to compare the actual total latency cycle number and the expected total latency cycle number, and output a latency timeout comparison result when the actual total latency cycle number is greater than the expected total latency cycle number; a latency timeout counting unit 44, connected to the latency initial comparison unit 43, used to continuously count the latency timeout comparison result according to a latency timeout counting strategy to obtain a latency timeout counting result; a latency counting comparison unit 45, connected to the latency timeout counting unit 44, used to compare the latency timeout counting result with a preset latency timeout counting threshold, and output a latency analysis result of the latency timeout when the latency timeout counting result is greater than the latency timeout counting threshold.

[0120] Referring to Figure 7 The structure diagram of the latency comparison module 4.

[0121] The signals on the input side are as follows.

[0122] areset, aclk, axvalid, axready, Time_pulse, Register_update have been described above, and will not be described here.

[0123] Des_lat, represents the expected number of latency cycles for a single master-slave handshake success, i.e., the expected number of latency cycles for a single transaction transmission (as the ideal latency required by the design)

[0124] Cur_tot_lat, the actual total number of latency cycles (Cur_tol_latency from the latency monitoring module, i.e., the sum of the latency of all master-slave handshake successes)

[0125] Current_tot_lat_valid, a seventh indication signal indicating whether the actual total number of latency cycles output is valid, i.e., Cur_tol_latency_valid output by the latency monitoring module, ensuring that Cur_tot_lat is valid

[0126] Lat_cnt_high_bound, a first latency timeout statistical threshold, i.e., a high latency threshold, the actual total latency exceeding this value triggers Lat_high_flag.

[0127] Lat_cnt_ultra_high_bound, a second latency timeout statistical threshold, i.e., an ultra-high latency threshold, the actual total latency exceeding this value triggers Lat_ultra_high_flag.

[0128] The signals on the output side are as follows.

[0129] des_tol_lat, the expected total number of latency cycles (Des_lat x transmission times, accumulated by axvalid & axready handshake)

[0130] des_tol_lat_valid, an eighth indication signal indicating whether the expected total number of latency cycles output is valid, i.e., the validity flag of the expected total number of latency cycles (set high when the transmission times statistics are valid, i.e., there is an ax handshake event).

[0131] Lat_high_flag, representing the latency analysis result of high latency, set high when the latency timeout statistical result is greater than Lat_cnt_high_bound (validity needs to be compared).

[0132] Lat_ultra_high_flag, representing the latency analysis result of ultra-high latency, set high when the latency timeout statistical result is greater than Lat_cnt_ultra_high_bound (validity needs to be compared).

[0133] Lat_flag_valid, a ninth indication signal indicating whether the latency analysis result output of the latency timeout (high latency / ultra-high latency) is valid, is high only when Current_tot_lat_valid and Time_pulse are both valid (to avoid invalid comparison).

[0134] Specifically, the expected latency accumulation unit 41 includes a fifth AND gate AND5, a third multiplexer Sel3, a fifth adder ADD5, and a fifth flip-flop D5; the first input terminal and the second input terminal of the fifth AND gate AND5 input the address channel valid signal axvalid and the address channel ready signal axready, respectively; the first input terminal of the third multiplexer Sel3 inputs the expected latency period number Des_lat indicating the success of the single handshake of the master-slave device, the second input terminal of the third multiplexer Sel3 inputs a 0 value, the third input terminal of the third multiplexer Sel3 is connected to the output terminal of the fifth AND gate AND5, and the output terminal of the third multiplexer Sel3 is connected to the first input terminal of the fifth adder ADD5; the second input terminal of the fifth adder ADD5 is connected to the Q output terminal of the fifth flip-flop D5, and the output terminal of the fifth adder ADD5 is connected to the D input terminal of the fifth flip-flop D5; the Q output terminal of the fifth flip-flop D5 is also connected to the input terminal of the expected latency output unit 42.

[0135] The expected latency accumulation unit 41 starts counting when receiving a valid Reset signal, and resets when receiving a valid clear signal. In the first small window time range, there may be some errors in the counting result. However, since the data before the large window is not filled is inaccurate, the final focus is on the data after the large window reaches a stable state, so as long as the subsequent small window data remains stable.

[0136] Specifically, the expected latency output unit 42 includes a seventh accumulation unit SUM7, a seventh shift register Seg7, and a seventh load counting unit LC7 (i.e., load counter 7)

[0137] The Q output terminal of the fifth flip-flop D5 is connected to the positive input terminal of the seventh accumulation unit SUM7 and the input terminal of the seventh shift register Seg7, respectively; the seventh shift register Seg7 is composed of a plurality of flip-flops, and the output terminal of the seventh shift register Seg7 is connected to the negative input terminal of the seventh accumulation unit SUM7; the seventh load counting unit LC7 is used for time counting according to the load signal and the time pulse signal Time_pulse to load the preset time window, and the eighth indication signal des_tot_lat_valid indicating whether the expected total latency period number output is valid, which is high if the expected total latency period number output is valid.

[0138] The seventh accumulation unit SUM7 outputs the number of expected total latency periods.

[0139] Specifically, the latency comparison module 4 further comprises a sixth AND gate AND6 and a seventh AND gate AND7; the first input end of the sixth AND gate AND6 inputs the eighth indication signal des_tol_lat_valid outputted by the output end of the seventh loading counter LC7, the second input end of the sixth AND gate AND6 inputs the seventh indication signal Current_tot_lat_valid indicating whether the number of actual total latency periods is valid, the output end of the sixth AND gate AND6 is connected to the latency initial comparison unit 43, and the latency initial comparison unit 43 starts comparison when the output end of the sixth AND gate AND6 outputs a high level; the first input end of the seventh AND gate AND7 is connected to the output end of the sixth AND gate AND6, the second input end of the seventh AND gate AND7 inputs the time pulse signal Time_pulse, and the output end of the seventh AND gate AND7 is connected to the latency timeout statistical unit 44, and the latency timeout statistical unit 44 performs statistics on the latency timeout comparison result according to the latency timeout statistical strategy when the output end of the seventh AND gate AND7 outputs a high level.

[0140] Specifically, the latency initial comparison unit 43 comprises a fifth comparator Com5; the first input end of the fifth comparator Com5 is connected to the output end of the seventh accumulation unit SUM7 and inputs the number of expected total latency periods des_tol_lat, the second input end of the fifth comparator Com5 inputs the number of actual total latency periods Cur_tot_lat, and the output end of the fifth comparator Com5 outputs the comparison result of the number of actual total latency periods and the number of expected total latency periods, for example, outputs a high level to indicate the latency timeout comparison result when the number of actual total latency periods is greater than the number of expected total latency periods, and outputs a low level to indicate the latency non-timeout comparison result when the number of actual total latency periods is not greater than the number of expected total latency periods.

[0141] The fifth comparator Com5 is a greater-than comparator, the second input end of the fifth comparator Com5 is a prior input end, the first input end of the fifth comparator Com5 is a posterior input end, and if the prior is greater than the posterior, a true value 1, i.e., a high level, is outputted, and if the prior is not greater than the posterior, a true value 0, i.e., a low level, is outputted.

[0142] The output end of the fifth comparator Com5 is connected to the input end of the latency timeout statistical unit 44.

[0143] Specifically, the delay timeout statistics unit 44 comprises an eighth accumulation unit SUM8, an eighth shift register Seg8 and an eighth load counter LC8; the output of the fifth comparator Com5 is connected to the positive input of the eighth accumulation unit SUM8 and the input of the eighth shift register Seg8 respectively; the eighth shift register Seg8 is composed of several flip-flops, and the output of the eighth shift register Seg8 is connected to the negative input of the eighth accumulation unit SUM8; the eighth load counter LC8 is used to count time according to the load signal and the time pulse signal Time_pulse to load the preset time window, and output a ninth indication signal Lat_flag_valid indicating whether the delay analysis result output of the delay timeout is valid, i.e. high level indicating that the delay analysis result output of the delay timeout is valid.

[0144] The eighth load counter LC8 outputs the delay timeout statistics result.

[0145] Further, the bandwidth over-limit statistics strategy is to count the total number or total time length of the comparison results of continuous bandwidth over-limit; and the bandwidth shortage statistics strategy is to count the total number or total time length of the comparison results of continuous bandwidth shortage.

[0146] If it is the total time length, i.e. the total time of several preset time windows of continuous bandwidth over-limit / bandwidth shortage. The bandwidth over-limit / bandwidth shortage statistics threshold is a time threshold.

[0147] If it is the total number, i.e. the total number of preset time windows of continuous bandwidth over-limit / bandwidth shortage. The bandwidth over-limit / bandwidth shortage statistics threshold is a number value.

[0148] By analyzing the bandwidth over-limit or bandwidth shortage for several times in succession, subsequent parameter adjustment is performed, avoiding frequent flipping and frequent parameter adjustment caused by bandwidth over-limit or bandwidth shortage of only one time window, and reducing power consumption.

[0149] Further, the delay timeout statistics strategy is to count the total number or total time length of the comparison results of continuous delay timeout.

[0150] If it is the total time length, i.e. the total time of several preset time windows of continuous delay timeout. The delay timeout statistics threshold is a time threshold.

[0151] If it is the total number, i.e. the total number of preset time windows of continuous delay timeout. The delay timeout statistics threshold is a number value.

[0152] Further, the delay timeout statistical threshold is divided into a first delay timeout statistical threshold and a second delay timeout statistical threshold, the first delay timeout statistical threshold is smaller than the second delay timeout statistical threshold; when the delay timeout statistical result is greater than the first delay timeout statistical threshold, output the high delay delay analysis result; when the delay timeout statistical result is greater than the second delay timeout statistical threshold, output the super high delay delay analysis result.

[0153] Referring to Figure 8 The application further provides a SOC bus transmission performance dynamic adjustment method, using the SOC bus transmission performance dynamic adjustment system, comprising: step A1, monitoring the bandwidth data of each master device under the corresponding transaction type and monitoring the transmission delay data between each master device and the slave device under the corresponding transaction type; step A2, comparing and analyzing the bandwidth data and outputting the bandwidth analysis result, comparing and analyzing the transmission delay data and outputting the delay analysis result; step A3, dynamically adjusting the effective signal duty cycle and the maximum number of outstanding transactions allocated to the master device according to the priority order of the master device, the bandwidth analysis result and the delay analysis result.

[0154] Application scenario 1 of the application

[0155] In the scene of concurrent transmission of a video coding master (Master1) and a storage master (Master2), the preset Master1 bandwidth lower limit threshold is 1.2GB / s, the current monitoring shows that the actual bandwidth is only 1GB / s (insufficient), and the delay is 50ns (delay exceeds standard).

[0156] The bandwidth monitoring module 1 outputs the current actual bandwidth data of Master1 as 1GB / s, and the delay monitoring module outputs 50ns.

[0157] The bandwidth comparison module 3 and the delay monitoring module 2 trigger the "insufficient bandwidth + delay exceeds standard" signal.

[0158] The service quality management module 5 increases the read-write Valid duty cycle of Master1 from 70% to 90%, and the water line value management module 6 reduces the Outstanding water line of Master2 from 10 to 6. By increasing the read-write Valid duty cycle of Master1, the transmission bandwidth of Master1 is improved, the real-time coding requirement is met, and the overall utilization of the bus is improved.

[0159] Application scenario 2 of the application

[0160] In the scene of entering low power consumption mode and only periodic transmission of sensor I2C Master (Master3) data, the request bandwidth data is less than or equal to 10MB / s, the current actual bandwidth is 50MB / s (bandwidth exceeds limit, i.e. bandwidth is sufficient), and the delay is 80ns (meets the standard).

[0161] Bandwidth monitoring module 1 detects that the actual bandwidth data of the continuous 5 preset time windows (50 ms) are all less than or equal to 50 MB / s. Since entering the low-power mode, the preset bandwidth upper limit threshold is set to 10 MB, the current actual bandwidth is higher than the preset bandwidth upper limit threshold, and a high level is output to represent the bandwidth analysis result Bw_over_flag that the bandwidth is over the upper limit, the read-write speed of the Master device is reduced, so that the bandwidth demand is met and the power consumption is reduced. Bandwidth comparison module 3 triggers the “low load” signal; quality of service management module 5 reduces the read-write Valid duty cycle of Master 3 to 30%, water line management module 6 reduces the Outstanding water line from 4 to 2, and the clock domain of the non-active Master is closed, so that the sensor data is normally transmitted while reducing the dynamic power consumption and static power consumption of the bus.

[0162] Application scenario 3 of the application

[0163] The application scenario in which the Master (Master 4), the communication Master (Master 5) and the debugging Master (Master 6) work at the same time, and the priority is Master 4> Master 5> Master 6 in turn.

[0164] Bandwidth monitoring module 1 feeds back the actual bandwidth data (Master 4: 1.5 GB / s, Master 5: 800 MB / s, Master 6: 200 MB / s) and the delay data (Master 4: 40 ns, Master 5: 60 ns, Master 6: 100 ns) of each Master in real time; bandwidth comparison module 3 triggers the adjustment signal according to the priority threshold (Master 4 delay threshold ≤ 30 ns, Master 5 bandwidth offline threshold ≥ 1 GB / s); quality of service management module 5 allocates exclusive bandwidth (Valid duty cycle 100%) for Master 4, and water line management module 6 improves the Outstanding water line of Master 5 to 12, and implements bandwidth limitation (Valid duty cycle 20%) on Master 6.

[0165] Through adjustment, the delay of Master 4 is reduced to 28 ns, the actual bandwidth data of Master 5 is improved to 1.1 GB / s, Master 6 is normally transmitted, the bus is not congested, and the overall power consumption is reduced by 18% compared with the fixed strategy.

[0166] The above merely preferred embodiments of the present application and are not intended to limit the embodiments and protection scope of the present application. Those skilled in the art should be able to understand that any equivalent substitutions and obvious changes made according to the present application description and drawings should be included in the protection scope of the present application.

Claims

1. A system for dynamically adjusting the transmission performance of an SOC bus, characterized in that, Includes a transaction channel regulator for the corresponding transaction type, the transaction channel regulator comprising: The bandwidth monitoring module is used to monitor bandwidth data for each master device under the corresponding transaction type. The latency monitoring module is used to monitor the transmission latency data between each master device and slave device under the corresponding transaction type. The bandwidth comparison module is connected to the bandwidth monitoring module and is used to compare and analyze the bandwidth data and output the bandwidth analysis results. When the bandwidth over-limit statistical result is greater than the bandwidth over-limit statistical threshold, the bandwidth analysis result of bandwidth exceeding the upper limit is output. When the bandwidth under-limit statistical result is greater than the bandwidth under-limit statistical threshold, the bandwidth under-limit statistical result of bandwidth is output. The delay comparison module, connected to the delay monitoring module, is used to compare and analyze the transmission delay data and output the delay analysis result. When the delay timeout statistical result is greater than the delay timeout statistical threshold, the delay analysis result of the delay timeout is output. The Quality of Service (QoS) management module is connected to the bandwidth comparison module and the latency comparison module, respectively, and is used to dynamically adjust the effective signal duty cycle allocated to the master device according to the priority order of the master device, the bandwidth analysis result, and the latency analysis result; The waterline value management module, connected to the bandwidth comparison module and the latency comparison module respectively, is used to dynamically adjust the maximum number of uncompleted transactions allocated to the master device based on the priority order of the master device, the bandwidth analysis results, and the latency analysis results; for master devices with insufficient bandwidth according to the bandwidth analysis results, the effective signal duty cycle is increased, and the maximum number of uncompleted transactions is decreased; for master devices with latency timeouts according to the latency analysis results, the effective signal duty cycle is increased, and the maximum number of uncompleted transactions is decreased; for master devices with bandwidth exceeding the upper limit according to the bandwidth analysis results, the effective signal duty cycle is decreased, and the maximum number of uncompleted transactions is decreased.

2. The SOC bus transmission performance dynamic adjustment system as described in claim 1, characterized in that, The transaction channel regulator also includes: The transaction control module is connected to the service quality management module and the waterline value management module, and is used to process transactions under the transaction type based on the adjusted effective signal duty cycle and the maximum number of incomplete transactions. The transaction types are divided into two types: read transaction type and write transaction type; The transaction channel regulator is either a read transaction type channel regulator or a write transaction type channel regulator.

3. The SOC bus transmission performance dynamic adjustment system as described in claim 1, characterized in that, The bandwidth monitoring module includes: The request byte accumulation unit is used to accumulate the total number of bytes in the request burst to obtain the accumulated request byte count result; The request bandwidth output unit is connected to the request byte accumulation unit and is used to acquire and store the request byte count accumulation result, calculate the request bandwidth within the current preset time window based on the request byte count accumulation result, and output it. The actual byte accumulation unit is used to accumulate the number of bytes transmitted in a single data channel to obtain the actual byte count accumulation result; The actual bandwidth output unit is connected to the actual byte accumulation unit and is used to acquire and store the actual byte count accumulation result, calculate the actual bandwidth within the current preset time window based on the actual byte count accumulation result, and output it.

4. The SOC bus transmission performance dynamic adjustment system as described in claim 1, characterized in that, The bandwidth data includes the requested bandwidth and the actual bandwidth within a preset time window; The bandwidth comparison module includes: The actual bandwidth comparison unit is used to compare the actual bandwidth with the upper bandwidth threshold and the lower bandwidth threshold respectively. When the actual bandwidth is greater than the upper bandwidth threshold, it outputs the bandwidth exceeding the upper limit comparison result, and when the actual bandwidth is less than the lower bandwidth threshold, it outputs the bandwidth insufficient comparison result. A bandwidth over-limit statistics unit, connected to the actual bandwidth comparison unit, is used to continuously count the bandwidth over-limit comparison results according to the bandwidth over-limit statistics strategy, and obtain bandwidth over-limit statistics results. The bandwidth over-limit statistics comparison unit is connected to the bandwidth over-limit statistics unit and is used to compare the bandwidth over-limit statistics result with a preset bandwidth over-limit statistics threshold. When the bandwidth over-limit statistics result is greater than the bandwidth over-limit statistics threshold, the bandwidth analysis result of the bandwidth exceeding the upper limit is output. A bandwidth insufficiency statistics unit is connected to the actual bandwidth comparison unit and is used to continuously count the bandwidth insufficiency comparison results according to the bandwidth insufficiency statistics strategy to obtain bandwidth insufficiency statistics results. The bandwidth insufficiency statistics comparison unit is connected to the bandwidth insufficiency statistics unit and is used to compare the bandwidth insufficiency statistics result with a preset bandwidth insufficiency statistics threshold. When the bandwidth insufficiency statistics result is greater than the bandwidth insufficiency statistics threshold, the bandwidth analysis result of insufficient bandwidth is output.

5. The SOC bus transmission performance dynamic adjustment system as described in claim 1, characterized in that, The delay monitoring module includes: The handshake success accumulation unit is used to accumulate the number of successful handshakes between the master device and the slave device to obtain the accumulated success count result. A handshake success output unit is connected to the handshake success accumulation unit and is used to calculate and output the total number of handshake successes within a preset time window based on the success count accumulation result. The actual delay calculation unit is used to obtain the actual delay cycle number of a single successful handshake between the master and slave devices and accumulate it to obtain the actual delay accumulation result; The actual delay statistics unit is connected to the actual delay calculation unit and is used to calculate and output the actual total delay cycle number within a preset time window based on the actual delay accumulation result.

6. The SOC bus transmission performance dynamic adjustment system as described in claim 1, characterized in that, The transmission delay data includes the actual total number of delay cycles within a preset time window; The delay comparison module includes: The expected delay accumulation unit is used to accumulate the expected delay cycle number of a single successful handshake between the master and slave devices to obtain the expected delay accumulation result; The expected delay output unit is connected to the expected delay accumulation unit and is used to calculate the expected total delay cycle number within a preset time window based on the expected delay accumulation result. The initial delay comparison unit is connected to the expected delay output unit and is used to compare the actual total delay cycle number with the expected total delay cycle number. When the actual total delay cycle number is greater than the expected total delay cycle number, the delay timeout comparison result is output. A delay timeout statistics unit, connected to the initial delay comparison unit, is used to continuously count the delay timeout comparison results according to the delay timeout statistics strategy to obtain delay timeout statistics results; The delay statistics comparison unit is connected to the delay timeout statistics unit and is used to compare the delay timeout statistics result with a preset delay timeout statistics threshold. When the delay timeout statistics result is greater than the delay timeout statistics threshold, the delay analysis result of the delay timeout is output.

7. The SOC bus transmission performance dynamic adjustment system as described in claim 4, characterized in that, The bandwidth over-limit statistics strategy is to count the total number of times or the total duration of consecutive bandwidth over-limit comparison results. The bandwidth insufficiency statistics strategy is to count the total number of times or the total duration of consecutive bandwidth insufficiency comparison results.

8. The SOC bus transmission performance dynamic adjustment system as described in claim 6, characterized in that, The delay timeout statistics strategy is to count the total number of consecutive delay timeout comparison results or the total duration.

9. The SOC bus transmission performance dynamic adjustment system as described in claim 6, characterized in that, The delay timeout statistical threshold is divided into a first delay timeout statistical threshold and a second delay timeout statistical threshold, wherein the first delay timeout statistical threshold is less than the second delay timeout statistical threshold; When the delay timeout statistics result is greater than the first delay timeout statistics threshold, the delay analysis result for high latency is output; When the delay timeout statistics result is greater than the second delay timeout statistics threshold, the delay analysis result of ultra-high delay is output.

10. A method for dynamically adjusting the transmission performance of an SOC bus, characterized in that, A dynamic adjustment system for SOC bus transmission performance as described in any one of claims 1-9 includes: Step A1: Monitor the bandwidth data of each master device under the corresponding transaction type and monitor the transmission latency data between each master device and slave device under the corresponding transaction type; Step A2: Compare and analyze the bandwidth data and output the bandwidth analysis results; compare and analyze the transmission delay data and output the delay analysis results. Step A3: Dynamically adjust the effective signal duty cycle and maximum number of incomplete transactions allocated to the master device based on the priority order of the master device, the bandwidth analysis results, and the latency analysis results.

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