Power device and preparation method thereof, power module, power conversion circuit and vehicle
By employing a double-layer epitaxial structure in silicon carbide power devices, the trench corner electric field is reduced, the problem of easy breakdown of the gate oxide layer is solved, and the reliability and conduction performance of the devices are improved.
Patent Information
- Application Number
- CN202511427927.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-09-30
- Publication Date
- 2025-12-23
AI Technical Summary
The high electric field at the bottom and corners of existing trench-type silicon carbide power devices makes the gate oxide layer prone to breakdown, affecting device reliability.
The epitaxial layer structure with a double-layer second conductivity type is adopted. By forming a second region in the second epitaxial layer, the electric field strength at the trench corner is reduced, and the first insulating layer is prevented from being broken down in the device blocking state, while ensuring normal conduction when conducting.
This improves device reliability, reduces the electric field strength of the first insulating layer in the trench, avoids breakdown, reduces turn-on loss and dynamic breakdown risk, and improves turn-on speed.
Smart Images
Figure CN121194491A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor technology, and in particular to a power device and its fabrication method, a power module, a power conversion circuit, and a vehicle. Background Technology
[0002] Silicon carbide power devices have evolved from planar to trench types. By improving the gate structure, the direction of current flow on the gate has changed from planar to vertical. However, the high electric field at the bottom and corners of the trench in existing trench-type silicon carbide power devices results in a very high electric field on the gate oxide layer, which is prone to breakdown and affects device reliability. Summary of the Invention
[0003] This application provides a power device and its fabrication method, a power module, a power conversion circuit, and a vehicle, to improve device reliability.
[0004] According to one aspect of this application, a power device is provided, comprising:
[0005] A semiconductor body includes a first surface and a second surface disposed opposite to each other; the semiconductor body also includes a first region, the first region being configured with a first conductivity type and located on the first surface; the semiconductor body further includes a first epitaxial layer, a second epitaxial layer, and a third epitaxial layer, the first epitaxial layer being configured with a second conductivity type and located on the side of the first region away from the first surface, the first conductivity type and the second conductivity type being different; the second epitaxial layer being configured with a second conductivity type and located on the side of the first epitaxial layer away from the first surface, and the third epitaxial layer being configured with a first conductivity type and located on the side of the second epitaxial layer away from the first surface; the semiconductor body also includes a second region, the second region being configured with a first conductivity type and located within the second epitaxial layer, the opposite sides of the second region being in contact with the first epitaxial layer and the third epitaxial layer respectively; a trench is provided on the first surface, the trench penetrating into the second epitaxial layer, and the corner of the trench penetrating into the second region;
[0006] A first insulating layer is located within the trench and covers the inner wall of the trench;
[0007] A gate is located within the trench and disposed on the side of the first insulating layer away from the inner wall of the trench;
[0008] The drain electrode is located on the second surface;
[0009] The source electrode is located on the first surface.
[0010] Optionally, the power device further includes:
[0011] The third region is configured with a first conductivity type and is located within the second epitaxial layer; the third region is disposed on the side of the trench adjacent to the second surface, and the trench extends from the first surface to the third region; a portion of the third region is located within the second region, and the third region does not contact either the first epitaxial layer or the third epitaxial layer; the doping concentration of the third region is greater than that of the second region.
[0012] Optionally, along the width direction of the trench, the first region is located on at least one side of the trench, the width of the third region is greater than the width of the trench, and at least a portion of the two opposite sides of the third region along the width direction of the trench is located within the second region.
[0013] Optionally, along the width direction of the trench, at least two of the second regions are located on either side of the third region.
[0014] Optionally, at least two second regions are arranged alternately along the length of the trench; or, along the length of the trench, the length of the second region is the same as the length of the third region.
[0015] Optionally, the surface of the second region adjacent to the second surface is located within the third epitaxial layer;
[0016] Along the direction from the first surface to the second surface, the thickness of the second region located within the third epitaxial layer is greater than or equal to 0.2 micrometers and less than or equal to 0.5 micrometers.
[0017] Optionally, the semiconductor body further includes a fourth region, which is configured with a second conductivity type and is located on the first surface, and the fourth region is in contact with the first region;
[0018] The semiconductor body further includes a substrate, which is configured with a first conductivity type and is located on the side of the third epitaxial layer away from the first surface.
[0019] According to another aspect of this application, a power module is provided, characterized in that it includes a substrate and at least one power device as described in any embodiment of this application, the substrate being used to carry the power device.
[0020] According to another aspect of this application, a power conversion circuit is provided, which is used for one or more of current conversion, voltage conversion, and power factor correction;
[0021] The power conversion circuit includes a circuit board and at least one power device as described in any embodiment of this application, wherein the power device is electrically connected to the circuit board.
[0022] According to another aspect of this application, a vehicle is provided, including a load and a power conversion circuit as described in any embodiment of this application, the power conversion circuit being used to convert alternating current to direct current, convert alternating current to alternating current, convert direct current to direct current, or convert direct current to alternating current and then input the converted direct current to the load.
[0023] According to another aspect of this application, a method for fabricating a power device is provided, comprising:
[0024] A semiconductor body is provided, comprising a first surface and a second surface disposed opposite to each other; the semiconductor body further comprises a first region, the first region being configured with a first conductivity type and located on the first surface; the semiconductor body further comprises a first epitaxial layer, a second epitaxial layer, and a third epitaxial layer, the first epitaxial layer being configured with a second conductivity type and located on the side of the first region away from the first surface, the first conductivity type and the second conductivity type being different; the second epitaxial layer being configured with a second conductivity type and located on the side of the first epitaxial layer away from the first surface, and the third epitaxial layer being configured with a first conductivity type and located on the side of the second epitaxial layer away from the first surface; the semiconductor body further comprises a second region, the second region being configured with a first conductivity type and located within the second epitaxial layer, the opposite sides of the second region being in contact with the first epitaxial layer and the third epitaxial layer, respectively; a trench is provided on the first surface, the trench penetrating into the second epitaxial layer, and the trench corner penetrating into the second region;
[0025] A first insulating layer and a gate are formed in the trench; wherein the first insulating layer covers the inner wall of the trench, and the gate is disposed on the side of the first insulating layer away from the inner wall of the trench;
[0026] A drain is formed on the second surface, and a source is formed on the first surface.
[0027] Optionally, a semiconductor body is provided, including:
[0028] A third epitaxial layer, a second epitaxial layer, and a first epitaxial layer are formed and stacked sequentially.
[0029] The second epitaxial layer and the third epitaxial layer are doped to form the second region;
[0030] The first epitaxial layer is doped to form the first region;
[0031] The groove is formed.
[0032] Optionally, the second epitaxial layer and the third epitaxial layer are doped to form the second region, and the process further includes:
[0033] The second epitaxial layer is doped to form a third region; wherein the third region is configured with a first conductivity type and is located within the second epitaxial layer; the third region is disposed on the side of the trench adjacent to the second surface, and the trench extends from the first surface to the third region, a portion of the third region is located within the second region, and the third region is not in contact with either the first epitaxial layer or the third epitaxial layer; the doping concentration of the third region is greater than the doping concentration of the second region.
[0034] Optionally, the second epitaxial layer is doped to form a third region, including:
[0035] A first mask structure is formed on the surface of the first epitaxial layer, wherein the first mask structure includes a first opening that exposes the first epitaxial layer;
[0036] The third region is formed by doping the second epitaxial layer through the first opening;
[0037] The second epitaxial layer and the third epitaxial layer are doped to form the second region, including:
[0038] A sidewall structure is formed on the sidewall of the first opening;
[0039] A second mask structure is formed in the first opening, and the second mask structure and the sidewall structure fill the first opening; wherein the second mask structure, the sidewall structure and the first mask structure are all made of different materials;
[0040] At least a portion of the sidewall structure is removed to form a second opening;
[0041] The second region is formed by doping the second epitaxial layer and the third epitaxial layer through the second opening;
[0042] Remove the first mask structure, the remaining sidewall structure, and the second mask structure.
[0043] Optionally, at least a portion of the sidewall structure may be removed to form a second opening, including:
[0044] The sidewall structure is removed to form the second opening; or, a third mask structure is formed on the surface of the first mask structure, the third mask structure including a third opening, through which a portion of the sidewall structure is removed.
[0045] Optionally, the third mask structure includes a plurality of third openings, which are respectively disposed on both sides of the second mask structure along the width direction of the second mask structure; and / or, at least two third openings disposed on one side of the second mask structure are arranged sequentially along the extension direction of the sidewall structure along the width direction of the second mask structure.
[0046] Optionally, at least a portion of the sidewall structure may be removed to form a second opening, including:
[0047] While removing at least a portion of the sidewall structure, a portion of the first mask structure adjacent to the sidewall structure is also removed to form the second opening.
[0048] Optionally, while removing at least a portion of the sidewall structure, a portion of the first mask structure adjacent to the sidewall structure is also removed to form the second opening, including:
[0049] While removing at least a portion of the sidewall structure using the same etching solution, a portion of the first mask structure adjacent to the sidewall structure is also removed to form the second opening.
[0050] Optionally, the first mask structure and the sidewall structure are made of silicon dioxide and silicon nitride, respectively; the second mask structure is made of polycrystalline silicon.
[0051] This application embodiment employs a double-layer epitaxial layer of the second conductivity type, consisting of a first epitaxial layer and a second epitaxial layer. A second region is formed within the second epitaxial layer. This second region ensures that when the device is operating, it can conduct the inversion layer and the third epitaxial layer in the first epitaxial layer, enabling the power device to conduct normally. The second epitaxial layer reduces the electric field at the trench corners during the device's blocking state, thereby reducing the electric field strength of the first insulating layer within the trench, preventing the first insulating layer from being broken down, and improving the device's reliability.
[0052] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this application, nor is it intended to limit the scope of this application. Other features of this application will become readily apparent from the following description. Attached Figure Description
[0053] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0054] Figure 1 This is a schematic diagram of a power device provided in an embodiment of this application.
[0055] Figure 2 This is a top view of a second region and a third region provided in an embodiment of this application.
[0056] Figure 3 This is another top view of the second and third regions provided in the embodiments of this application.
[0057] Figure 4 This is a schematic diagram of another power device provided in the embodiments of this application.
[0058] Figure 5 This is a flowchart of a method for fabricating a power device according to an embodiment of this application.
[0059] Figure 6 This is a schematic diagram of a third epitaxial layer after being formed, provided in an embodiment of this application.
[0060] Figure 7 This is a schematic diagram of the formation of the third region provided in the embodiments of this application.
[0061] Figure 8 This is a flowchart of another method for fabricating a power device provided in the embodiments of this application.
[0062] Figure 9 This is a schematic diagram of the sidewall structure formed according to an embodiment of this application.
[0063] Figure 10 This is a schematic diagram of the second mask structure after it has been formed, as provided in an embodiment of this application.
[0064] Figure 11 This is a schematic diagram of the second opening after it has been formed, provided in an embodiment of this application.
[0065] Figure 12 This is a schematic diagram of the formation of the second region provided in the embodiments of this application.
[0066] Figure 13 This is a schematic diagram after the mask structure has been removed.
[0067] Figure 14 This is a schematic diagram of the first region after it has been formed, provided in an embodiment of this application.
[0068] Figure 15 This is a schematic diagram of the trench formed according to an embodiment of this application.
[0069] Figure 16 This is a schematic diagram of the formation of the first insulating layer and the gate provided in the embodiments of this application.
[0070] Figure 17 This is a schematic diagram of the second insulating layer after its formation, provided in an embodiment of this application.
[0071] Figure 18 This is a schematic diagram of the third mask structure after it has been formed, as provided in the embodiments of this application.
[0072] Figure 19 This is a top view of the third mask structure after it has been formed, as provided in the embodiments of this application.
[0073] Figure 20 This is another schematic diagram of the second region after it has been formed, provided in an embodiment of this application. Detailed Implementation
[0074] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort should fall within the scope of protection of the present application.
[0075] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.
[0076] This application provides a power device. Figure 1 This is a schematic diagram of a power device provided in an embodiment of this application, with reference to... Figure 1 Power devices include:
[0077] Semiconductor body 10 includes a first surface 01 and a second surface 02 disposed opposite to each other; semiconductor body 10 also includes a first region 11, which is configured with a first conductivity type and located on the first surface 01; semiconductor body 10 also includes a first epitaxial layer 101, a second epitaxial layer 102 and a third epitaxial layer 103, the first epitaxial layer 101 being configured with a second conductivity type and located on the side of the first region 11 away from the first surface 01, the first conductivity type and the second conductivity type being different; the second epitaxial layer 102 being configured with a second conductivity type and located on the side of the first region 11 away from the first surface 01. On the side of the first epitaxial layer 101 away from the first surface 01, the third epitaxial layer 103 is configured with a first conductivity type and is located on the side of the second epitaxial layer 102 away from the first surface 01; the semiconductor body 10 also includes a second region 12, which is configured with a first conductivity type and is located within the second epitaxial layer 102, with the two sides of the second region 12 respectively contacting the first epitaxial layer 101 and the third epitaxial layer 103; a trench 15 is provided on the first surface 01, which penetrates into the second epitaxial layer 102, and the corner of the trench 15 penetrates into the second region 12;
[0078] The first insulating layer 21 is located within the trench 15 and covers the inner wall of the trench 15;
[0079] The gate 20 is located in the trench 15 and is disposed on the side of the first insulating layer 21 away from the inner wall of the trench 15;
[0080] Drain electrode 40 is located on the second surface 02;
[0081] Source electrode 30 is located on the first surface 01.
[0082] The power device can be a metal-oxide-semiconductor field-effect transistor (MOSFET). One of the first and second conductivity types is N-type or P-type. For example, the first conductivity type is N-type, the second conductivity type is P-type, the first region 11 is an N+ region, the second region 12 is an N region, the first epitaxial layer 101 and the second epitaxial layer 102 are both P-type epitaxial layers, and the third epitaxial layer 103 is an N-type epitaxial layer. The first region 11 is the source region of the power device. The first region 11 can be formed by doping the first epitaxial layer 101, or by directly depositing material on the surface of the first epitaxial layer 101. When the power device is operating, by applying a voltage to the source 30, gate 20, and drain 40, when the voltage between the source 30 and gate 20 meets the conduction condition, an inversion layer is formed in the region adjacent to the gate 20 of the first epitaxial layer 101, i.e., a conductive channel is formed. Current flows through the source 30, the first region 11, the inversion layer, the second region 12, and the third epitaxial layer 103 to the drain 40.
[0083] The first insulating layer 21 is a gate insulating layer. For example, the first insulating layer 21 may include an oxide layer such as silicon dioxide. The second epitaxial layer 102 is used to reduce the electric field strength at the first insulating layer 21 within the trench 15. Specifically, when the power device is turned off, the second epitaxial layer 102 and the third epitaxial layer 103 form a PN junction. The built-in electric field of the PN junction can offset part of the electric field when the device is turned off, reducing the electric field at the corner of the trench 15, thereby reducing the electric field strength at the first insulating layer 21 within the trench 15, preventing the first oxide layer from being broken down, and improving device reliability. Furthermore, by setting a second region 12, the surface of the second region 12 adjacent to the first surface 01 contacts the first epitaxial layer 101, and the surface away from the first surface 01 contacts the third epitaxial layer 103. The corner of the trench 15 extends into the second region 12, that is, the second region 12 is adjacent to the corner 15. The second region 12 is in contact with the first epitaxial layer 101 adjacent to the trench 15, and the second region 12 and the third epitaxial layer 103 have the same conductivity type. This allows the second region 12 to conduct with the inversion layer in the first epitaxial layer 101 and the third epitaxial layer 103 when the power device is working, so that the power device can conduct normally.
[0084] In addition, two or more second regions 12 can be provided, each adjacent to a corner of the trench 15. The doping concentration and size of the second region 12 can be set according to the on-resistance requirements of the power device, and this embodiment does not impose specific limitations.
[0085] This application embodiment employs a double-layer epitaxial layer of the second conductivity type, consisting of a first epitaxial layer 101 and a second epitaxial layer 102. A second region 12 is formed within the second epitaxial layer 102. The second region 12 ensures that when the device is working, it can conduct the inversion layer and the third epitaxial layer 103 in the first epitaxial layer 101, enabling the power device to conduct normally. The second epitaxial layer 102 reduces the electric field at the corner of the trench 15 under the device blocking state, thereby reducing the electric field strength of the first insulating layer 21 within the trench 15, preventing the first insulating layer 21 from being broken down, and improving the reliability of the device.
[0086] Based on the above embodiments, optionally, the power device further includes:
[0087] The third region 13 is configured with a first conductivity type and is located within the second epitaxial layer 102. The third region 13 is disposed on the side of the trench 15 adjacent to the second surface 02, and the trench 15 extends from the first surface 01 to the third region 13. A portion of the third region 13 is located within the second region 12, and the third region 13 does not contact either the first epitaxial layer 101 or the third epitaxial layer 103. The doping concentration of the third region 13 is greater than that of the second region 12.
[0088] Specifically, the third region 13 can be an N+ region, and the second region 12 can be an N region. The third region 13 can be prepared by doping the second epitaxial layer 102, for example, by ion implantation. The third region 13 is located within the second epitaxial layer 102, that is, the third region 13 is entirely covered by the second epitaxial layer 102.
[0089] When a power device is turned on, a large parasitic capacitance Cgd increases turn-on losses and reduces turn-on speed. Conversely, a small parasitic capacitance during turn-off increases the Vds spike, increasing the risk of dynamic breakdown and reducing device reliability. This embodiment addresses this by providing a third region 13. When the power device is turned on, due to the smaller forward voltage, the depletion region of the second region 12 is thinner. The second region 12, the third epitaxial layer 103, and the third region 13 are interconnected, giving the third region 13 a certain potential. A PN junction is formed between the third region 13 and the second epitaxial layer 102. This PN junction has a certain capacitance. The gate oxide capacitance between the gate 20 and the first insulating layer 21 is connected in series with the capacitance of the PN junction. This reduces the parasitic capacitance during device turn-on, decreases turn-on losses, and improves turn-on speed. When the device is turned off, due to the large reverse voltage, the second epitaxial layer 102 depletes the second region 12, making the second region 12 a depletion region. The third region 13 is in a floating state and cannot form a PN junction when turned off. The parasitic capacitance of the device includes the gate oxide capacitance. When turned off, it has a relatively large parasitic capacitance, which avoids the occurrence of Vds spikes due to the parasitic capacitance being too small when turned off, reduces the risk of dynamic breakdown, and improves the reliability of the device.
[0090] Based on the above embodiments, optionally, along the width direction X of the groove 15, the first region 11 is located on at least one side of the groove 15, the width of the third region 13 is greater than the width of the groove 15, and at least a portion of the two opposite sides of the third region 13 along the width direction X of the groove 15 is located within the second region 12.
[0091] Specifically, along the width direction X of the trench 15, the third region 13 extends beyond the corner of the trench 15 by a certain distance. The portion of the third region 13 that contacts the second region 12 is located inside the second region 12. For example, along the width direction X of the trench 15, the portion of the third region 13 extending beyond the trench 15 is entirely located inside the second region 12. Since the second epitaxial layer 102 depletes the edge region of the second region 12 when the device is turned on, resulting in a depletion region of a certain thickness at the edge of the second region 12, by setting at least a portion of the side of the third region 13 to be located inside the second region 12, the third region 13 can be prevented from being located within the depletion region of the second region 12. This ensures that when the device is turned on, the second region 12 can conduct with the third region 13, giving the third region 13 a potential. The third region 13 and the second epitaxial layer 102 form a PN junction, reducing the parasitic capacitance of the device during conduction. Furthermore, the third region 13 is embedded inside the second region 12, so that when the device is turned on, the third region 13 and the second region 12, which extend beyond the trench 15, together serve as a conductive channel. Since the third region 13 has a higher doping concentration, the on-resistance of the device can be reduced.
[0092] Figure 2 This is a top view of a second and third region provided in an embodiment of this application. Figure 3 This is a top view of another second and third region provided in the embodiments of this application, with reference to... Figures 1-3 Based on the above embodiments, optionally, along the width direction X of the groove 15, at least two second regions 12 are located on both sides of the third region 13.
[0093] The semiconductor body 10 includes at least two second regions 12, which are located on either side of the third region 13. This arrangement ensures that when the device is turned on, the second regions 12 can better conduct with the third region 13, reducing parasitic capacitance during device turn-on. Furthermore, when the device is turned off, each second region 12 can be depleted by the second epitaxial layer 102, leaving the third region 13 in a floating state. The fact that at least two second regions 12 are located on either side of the third region 13 also ensures that the device has at least two conduction paths when turned on, reducing on-resistance and increasing conduction speed.
[0094] Based on the above embodiments, optionally, at least two second regions 12 are arranged sequentially at intervals along the length direction Y of the trench 15. Figure 2 Alternatively, along the length Y of the trench 15, the length of the second region 12 is the same as the length of the third region 13. Figure 3 ).
[0095] For details, please refer to Figure 1 and Figure 2Along the length Y of the trench 15, two or more second regions 12 can be provided. These two or more second regions 12 ensure better conduction between the second region 12 and the third region 13 when the device is turned on, reducing parasitic capacitance during device turn-on. Furthermore, the gap between adjacent second regions allows the second epitaxial layer 102 located on the side of the third region 13 adjacent to the second surface 02 to communicate with the second epitaxial layer 102 of other regions. This allows the second region 12 to be better depleted by the second epitaxial layer 102 when the device is turned off, resulting in the third region 13 being in a floating state. This allows the power device to have a larger parasitic capacitance when turned off, avoiding Vds spikes.
[0096] In addition, refer to Figure 3 When the length of the third region 13 is the same as the length of the second region 12, the manufacturing process can be made easier.
[0097] It should be noted that when at least two second regions 12 are arranged alternately along the length Y of the trench, Figure 1 A cross-sectional view of the power device along section line AA is shown. Figure 4 This is a schematic diagram of yet another power device provided in an embodiment of this application. Figure 4 A cross-sectional view of the power device profile line BB is shown.
[0098] Based on the above embodiments, optionally, the surface of the second region 12 adjacent to the second surface 02 is located within the third epitaxial layer 103; along the direction from the first surface 01 to the second surface 02, the thickness D of the region of the second region 12 located inside the third epitaxial layer 103 is greater than or equal to 0.2 micrometers and less than or equal to 0.5 micrometers.
[0099] Specifically, the second region 12 extends into the third epitaxial layer 103, which increases the contact area between the second region 12 and the third epitaxial layer 103, reduces the contact resistance, and allows the second region 12 to quickly conduct with the third epitaxial layer 103 when the device is turned on, thus improving the conduction speed. Since the second region 12 is formed through doping, if it extends too deeply into the third epitaxial layer 103, it increases the doping difficulty. For example, if the second region 12 is formed through ion implantation, a larger ion implantation depth is required if it extends too deeply into the third epitaxial layer 103, increasing the process difficulty. By setting the thickness D of the region of the second region 12 within the third epitaxial layer 103 to be greater than or equal to 0.2 micrometers and less than or equal to 0.5 micrometers, the contact area between the second region 12 and the third epitaxial layer 103 can be increased while reducing the process difficulty.
[0100] Based on the above embodiments, optionally, refer to Figure 1The semiconductor body 10 also includes a fourth region 14, which is configured as a second conductivity type and is located on the first surface 01. The fourth region 14 is in contact with the first region 11.
[0101] The semiconductor body 10 also includes a substrate 104, which is configured with a first conductivity type and is located on the side of the third epitaxial layer 103 away from the first surface 01.
[0102] Specifically, the fourth region 14 contacts the source 30, which can reduce contact resistance and thus reduce the on-resistance of the device. The surface of the substrate 104 away from the second surface 02 is the second surface 02 of the semiconductor body 10, and the drain 40 is disposed on this surface. The power device also includes a second insulating layer 90, which is disposed on the first surface 01. The second insulating layer 90 includes an opening 91 that exposes the first region 11 and the fourth region 14. The source 30 is disposed on the side of the second insulating layer 90 away from the semiconductor body 10, and the source 30 contacts the first region 11 and the fourth region 14 through the opening 91. The substrate 104 can be a silicon carbide substrate.
[0103] Based on the above embodiments, this application also provides a power module, including a substrate and at least one power device as described in any embodiment of this application, wherein the substrate is used to support the power device.
[0104] The power module provided by the technical solution of this application has the same beneficial effects as the power device described in any embodiment of this application.
[0105] Based on the above embodiments, this application also provides a power conversion circuit. The power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction.
[0106] The power conversion circuit includes a circuit board and at least one power device as described in any embodiment of this application, the power device being electrically connected to the circuit board.
[0107] The power conversion circuit provided in the embodiments of this application has the same beneficial effects as the power devices described in any embodiment of this application.
[0108] Based on the above embodiments, this application also provides a vehicle, characterized in that it includes a load and a power conversion circuit as described in any embodiment of this application. The power conversion circuit is used to convert AC power to DC power, convert AC power to AC power, convert DC power to DC power, or convert DC power to AC power and then input it to the load.
[0109] The vehicle provided by the technical solution of this application has the same beneficial effects as the power device described in any embodiment of this application.
[0110] This application also provides a method for fabricating a power device. Figure 5 This is a flowchart of a method for fabricating a power device according to an embodiment of this application, see reference. Figure 1 and Figure 5 The fabrication methods for power devices include:
[0111] S110. A semiconductor body 10 is provided. The semiconductor body 10 includes a first surface 01 and a second surface 02 disposed opposite to each other. The semiconductor body 10 also includes a first region 11, which is configured with a first conductivity type and located on the first surface 01. The semiconductor body 10 further includes a first epitaxial layer 101, a second epitaxial layer 102, and a third epitaxial layer 103. The first epitaxial layer 101 is configured with a second conductivity type and located on the side of the first region 11 away from the first surface 01, and the first conductivity type and the second conductivity type are different. The second epitaxial layer 102 is configured with a second conductivity type and located on the side of the first region 11 away from the first surface 01. The epitaxial layer 101 is located on the side away from the first surface 01, and the third epitaxial layer 103 is configured with a first conductivity type and is located on the side of the second epitaxial layer 102 away from the first surface 01. The semiconductor body 10 also includes a second region 12, which is configured with a first conductivity type and is located within the second epitaxial layer 102. The two opposite sides of the second region 12 are in contact with the first epitaxial layer 101 and the third epitaxial layer 103, respectively. The first surface 01 is provided with a trench 15, which extends into the second epitaxial layer 102, and the corner of the trench 15 extends into the second region 12.
[0112] S120, A first insulating layer 21 and a gate 20 are formed in the trench 15; wherein the first insulating layer 21 covers the inner wall of the trench 15, and the gate 20 is disposed on the side of the first insulating layer 21 away from the inner wall of the trench 15.
[0113] S130, a drain electrode 40 is formed on the second surface 02, and a source electrode 30 is formed on the first surface 01.
[0114] The fabrication method of the power device provided in this application embodiment belongs to the same application concept as the power device provided in any embodiment of this application, and has corresponding beneficial effects. For technical details not covered in this embodiment, please refer to the power device described in any embodiment of this application.
[0115] Figure 6 This is a schematic diagram of a third epitaxial layer formed according to an embodiment of this application, with reference to... Figure 1 and Figure 6 Optionally, based on the above embodiments, a semiconductor body 10 is provided, comprising:
[0116] A third epitaxial layer 103, a second epitaxial layer 102, and a first epitaxial layer 101 are formed and stacked sequentially.
[0117] The second epitaxial layer 102 and the third epitaxial layer 103 are doped to form the second region 12;
[0118] The first epitaxial layer 101 is doped to form the first region 11;
[0119] Forming a trench 15.
[0120] Specifically, a mask structure can be formed on the surface of the third epitaxial layer 103, and the second epitaxial layer 102 can be doped through the mask structure to form the second region 12. Doping can include methods such as ion implantation, ion diffusion, or vapor deposition. For example, N-type ion implantation is performed on the second epitaxial layer 102 to form the second region 12. Similarly, the first epitaxial layer 101 can be doped to form the first region 11. For example, N-type ion implantation is performed on the first epitaxial layer 101 to form the first region 11. The first epitaxial layer 101 and the second epitaxial layer 102 are etched to form a trench 15. For example, the trench 15 is formed by dry etching.
[0121] Figure 7 This is a schematic diagram showing the formation of the third region 13 according to an embodiment of this application. (Refer to...) Figure 1 and Figure 7 Based on the above embodiments, optionally, the second epitaxial layer 102 and the third epitaxial layer 103 are doped to form the second region 12, and the process further includes:
[0122] The second epitaxial layer 102 is doped to form a third region 13. The third region 13 is configured with a first conductivity type and is located within the second epitaxial layer 102. The third region 13 is disposed on the side of the trench 15 adjacent to the second surface 02, and the trench 15 extends from the first surface 01 to the third region 13. A portion of the third region 13 is located within the second region 12, and the third region 13 does not contact either the first epitaxial layer 101 or the third epitaxial layer 103. The doping concentration of the third region 13 is greater than that of the second region 12.
[0123] Specifically, a first mask structure 50 can be formed on the surface of the first epitaxial layer 101, and the second epitaxial layer 102 can be doped through the first opening 51 of the first mask structure 50 to form a third region 13. For example, N-type ion implantation is performed on the second epitaxial layer 102 to form an N+ type third region 13.
[0124] Based on the above embodiments, optionally, the second epitaxial layer is doped to form a third region, including:
[0125] A first mask structure is formed on the surface of the first epitaxial layer 101, wherein the first mask structure includes a first opening that exposes the first epitaxial layer 101;
[0126] The second epitaxial layer 102 is doped through the first opening to form the third region 13.
[0127] Specifically, the first mask structure can be made of materials such as silicon dioxide. A first mask material layer can be formed on the surface of the first epitaxial layer 101, and the first mask structure with the first opening can be formed by etching the first mask material layer.
[0128] Figure 8 This is a flowchart illustrating another method for fabricating a power device provided in this application. Figure 9 This is a schematic diagram of the sidewall structure formed according to an embodiment of this application. Figure 10 This is a schematic diagram of the second mask structure after its formation, provided in an embodiment of this application. Figure 11 This is a schematic diagram showing the formation of the second opening according to an embodiment of this application. Figure 12 This is a schematic diagram showing the formation of the second region 12 according to an embodiment of this application. Figure 13 This is a schematic diagram after removing the mask structure. (See reference) Figure 1 , Figures 8-13 The fabrication methods for power devices include:
[0129] S111, forming a third epitaxial layer 103, a second epitaxial layer 102, and a first epitaxial layer 101 stacked sequentially. Figure 6 ).
[0130] S112. A first mask structure 50 is formed on the surface of the first epitaxial layer 101, wherein the first mask structure 50 includes a first opening 51, the first opening 51 exposing the first epitaxial layer 101. Figure 7 ).
[0131] S113, The second epitaxial layer 102 is doped through the first opening to form the third region 13. Figure 7 ).
[0132] S114, A sidewall structure 60 is formed on the sidewall of the first opening 51.
[0133] For details, please refer to Figure 9 Sidewall material layers can be deposited on the surface of the first mask structure 50 and the exposed first epitaxial layer 101, and then anisotropic etching is performed to form the sidewall structure 60. For example, silicon nitride is deposited on the surface of the first mask structure 50 and the exposed first epitaxial layer 101 and anisotropic etching is performed to form the sidewall structure 60.
[0134] S115, A second mask structure 70 is formed in the first opening 51, and the second mask structure 70 and the sidewall structure 60 fill the first opening 51. The second mask structure 70, the sidewall structure 60 and the first mask structure 50 are all made of different materials.
[0135] refer to Figure 10 A second mask material is deposited and then etched back to remove the second mask material outside the first opening 51, forming a second mask structure 70.
[0136] S116. Remove at least part of the sidewall structure 60 to form a second opening 71.
[0137] refer to Figure 11 The side wall structure 60 is etched to remove part or all of the side wall structure 60, forming a second opening 71.
[0138] S117. The second epitaxial layer 102 and the third epitaxial layer 103 are doped through the second opening 71 to form the second region 12.
[0139] refer to Figure 12 The second epitaxial layer 102 is doped through the second opening 71 to form the second region 12.
[0140] S118. Remove the first mask structure 50, the remaining sidewall structure 60, and the second mask structure 70.
[0141] refer to Figure 13 The first mask structure 50, the remaining sidewall structure 60, and the second mask structure 70 are removed by etching.
[0142] S119. The first epitaxial layer 101 is doped to form the first region 11.
[0143] Figure 14 This is a schematic diagram of the first region after its formation, provided in an embodiment of this application. (Refer to...) Figure 14 The first epitaxial layer 101 is subjected to N-type ion implantation to form a first region 11. Alternatively, the first epitaxial layer 101 can be subjected to P-type ion implantation to form a fourth region 14, exemplarily an N+ region. The first region 11 and the fourth region 14 are the source regions.
[0144] S1191, forming a groove 15.
[0145] Figure 15 This is a schematic diagram of the trench formed according to an embodiment of this application, with reference to... Figure 15 , etching to form grooves 15.
[0146] S120, A first insulating layer 21 and a gate 20 are formed in the trench 15; wherein the first insulating layer 21 covers the inner wall of the trench 15, and the gate 20 is disposed on the side of the first insulating layer 21 away from the inner wall of the trench 15.
[0147] Figure 16This is a schematic diagram of the formation of the first insulating layer and the gate provided in an embodiment of this application, with reference to... Figure 16 The first insulating layer 21 can be formed by processes such as deposition or thermal oxidation, and a polycrystalline silicon gate can be formed by deposition.
[0148] S130, a drain electrode 40 is formed on the second surface 02, and a source electrode 30 is formed on the first surface 01.
[0149] refer to Figure 1 Metal is deposited on the first surface 01 and the second surface 02 to form the source electrode 30 and the drain electrode 40. Figure 17 This is a schematic diagram of the second insulating layer after its formation, provided in an embodiment of this application. (Refer to...) Figure 17 Before forming the source electrode 30 and the drain electrode 40, a second insulating layer 90 can be formed on the first surface 01.
[0150] Figure 18 This is a schematic diagram of the third mask structure formed according to an embodiment of this application. Figure 19 This is a top view of the third mask structure formed according to an embodiment of this application, with reference to... Figure 12 , Figure 18 and Figure 19 Based on the above embodiments, optionally, at least a portion of the sidewall structure 60 is removed to form a second opening 71, including:
[0151] The sidewall structure 60 is removed to form a second opening 71; or, a third mask structure 80 is formed on the surface of the first mask structure 50, the third mask structure 80 including a third opening 81, through which part of the sidewall structure 60 is removed.
[0152] Specifically, when it is necessary to form two or more second regions 12, the sidewall structure 60 can be selectively removed. A third mask material layer can be formed on the surface of the first mask structure 50, and a third opening 81 can be formed at the location where the second region 12 needs to be formed. The second epitaxial layer 102 can be doped through the third opening 81 to form the second region 12.
[0153] It should be noted that, Figure 18 It is not necessary to remove the cross-sectional view of the side wall structure, that is, the cross-sectional view of the section other than the third opening.
[0154] refer to Figure 19 Based on the above embodiments, optionally, the third mask structure 80 includes a plurality of third openings 81, and the plurality of third openings 81 are respectively disposed on both sides of the second mask structure 70 along the width direction (i.e., the X direction); and / or, along the width direction of the second mask structure 70, at least two third openings 81 disposed on one side of the second mask structure 70 are arranged sequentially along the extension direction (i.e., the Y direction) of the sidewall structure 60.
[0155] Specifically, Figure 19 The third mask structure 80 shown can be correspondingly formed Figure 2 The second region 12 is shown. The third mask structure 80 can be made of photoresist. The third opening 81 exposes the sidewall structure 60. By etching the sidewall structure 60 through the third opening 81, at least a portion of the sidewall structure 60 can be removed to form the second opening 71. Figure 20 This is another schematic diagram showing the formation of the second region provided in the embodiments of this application, see reference. Figure 20 , Figure 20 The diagram shows a cross-sectional view of the area blocked by the third mask structure 90, where there is no second region.
[0156] Furthermore, when all the side wall structures 60 are removed, a corresponding structure can be formed. Figure 3 The second region 12 is shown. When all sidewalls are removed, the result 60 does not require a third mask structure 80, which reduces the number of process steps and lowers the process difficulty.
[0157] Based on the above embodiments, optionally, refer to the following: Figure 12 Removing at least a portion of the sidewall structure 60 to form a second opening 71 includes:
[0158] While removing at least a portion of the sidewall structure 60, a portion of the first mask structure 50 adjacent to the sidewall structure 60 is also removed to form a second opening 71.
[0159] Specifically, the sidewall structure 60 can be removed using an etching solution. By adjusting the etching solution, it can be made to have a certain etching effect on the first mask structure 50, thereby removing part of the first mask structure 50 and adjusting the size of the second opening 71 and the size of the second region 12. Alternatively, different etching solutions can be used to etch the sidewall structure 60 and the first mask structure 50 separately.
[0160] Based on the above embodiments, optionally, while removing at least a portion of the sidewall structure 60, a portion of the first mask structure 50 adjacent to the sidewall structure 60 is also removed to form a second opening 71, including:
[0161] While removing at least a portion of the sidewall structure 60 using the same etching solution, a portion of the first mask structure 50 adjacent to the sidewall structure 60 is also removed to form a second opening 71.
[0162] Specifically, the sidewall structure 60 and the first mask structure 51 are made of similar materials. By adjusting the etching selectivity, the etching solution for etching the sidewall structure 60 can have a certain etching effect on the first mask structure 50.
[0163] Based on the above embodiments, optionally, the first mask structure 50 and the sidewall structure 60 are made of silicon dioxide and silicon nitride, respectively; the second mask structure 70 is made of polycrystalline silicon.
[0164] Specifically, by setting the materials used for the first mask structure 50 and the sidewall structure 60 to be silicon dioxide and silicon nitride respectively, the etching selectivity can be adjusted so that the etching solution for etching the sidewall structure 60 can have a certain etching effect on the first mask structure 60, so that a single etching process can form a second opening 70 of the required size, thereby reducing process costs.
[0165] The fabrication method of the power device in this application embodiment belongs to the same application concept as the power device provided in any embodiment of this application, and has corresponding beneficial effects. For technical details not covered in this embodiment, please refer to the power device described in any embodiment of this application.
[0166] It should be understood that the various forms of processes shown above can be used to rearrange, add, or delete steps. For example, the steps described in this application can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this application can be achieved, and this is not limited herein.
[0167] The specific embodiments described above do not constitute a limitation on the scope of protection of this application. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this application should be included within the scope of protection of this application.
Claims
1. A power device, characterized in that, include: A semiconductor body includes a first surface and a second surface disposed opposite to each other; the semiconductor body also includes a first region, the first region being configured with a first conductivity type and located on the first surface; the semiconductor body further includes a first epitaxial layer, a second epitaxial layer, and a third epitaxial layer, the first epitaxial layer being configured with a second conductivity type and located on the side of the first region away from the first surface, the first conductivity type and the second conductivity type being different; the second epitaxial layer being configured with a second conductivity type and located on the side of the first epitaxial layer away from the first surface, and the third epitaxial layer being configured with a first conductivity type and located on the side of the second epitaxial layer away from the first surface; the semiconductor body also includes a second region, the second region being configured with a first conductivity type and located within the second epitaxial layer, the opposite sides of the second region being in contact with the first epitaxial layer and the third epitaxial layer respectively; a trench is provided on the first surface, the trench penetrating into the second epitaxial layer, and the corner of the trench penetrating into the second region; A first insulating layer is located within the trench and covers the inner wall of the trench; A gate is located within the trench and disposed on the side of the first insulating layer away from the inner wall of the trench; The drain electrode is located on the second surface; The source electrode is located on the first surface.
2. The power device according to claim 1, characterized in that, Also includes: The third region is configured with a first conductivity type and is located within the second epitaxial layer; The third region is located on the side of the trench adjacent to the second surface, and the trench extends from the first surface to the third region. A portion of the third region is located within the second region, and the third region does not contact either the first epitaxial layer or the third epitaxial layer. The doping concentration of the third region is greater than that of the second region.
3. The power device according to claim 2, characterized in that: Along the width direction of the trench, the first region is located on at least one side of the trench, the width of the third region is greater than the width of the trench, and at least a portion of the two opposite sides of the third region along the width direction of the trench is located within the second region.
4. The power device according to claim 2, characterized in that: Along the width direction of the trench, at least two of the second regions are located on either side of the third region.
5. The power device according to claim 2, characterized in that: Along the length of the trench, at least two second regions are arranged alternately; or, along the length of the trench, the length of the second region is the same as the length of the third region.
6. The power device according to claim 1, characterized in that: The surface of the second region adjacent to the second surface is located within the third epitaxial layer; Along the direction from the first surface to the second surface, the thickness of the second region located within the third epitaxial layer is greater than or equal to 0.2 micrometers and less than or equal to 0.5 micrometers.
7. The power device according to claim 1, characterized in that: The semiconductor body further includes a fourth region, which is configured as a second conductivity type and is located on the first surface, and the fourth region is in contact with the first region; The semiconductor body further includes a substrate, which is configured with a first conductivity type and is located on the side of the third epitaxial layer away from the first surface.
8. A power module, characterized in that, It includes a substrate and at least one power device as described in any one of claims 1-7, wherein the substrate is used to carry the power device.
9. A power conversion circuit, characterized in that, The power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction; The power conversion circuit includes a circuit board and at least one power device as described in any one of claims 1-7, wherein the power device is electrically connected to the circuit board.
10. A vehicle, characterized in that, The device includes a load and a power conversion circuit as described in claim 9, the power conversion circuit being used to convert AC power to DC power, convert AC power to AC power, convert DC power to DC power, or convert DC power to AC power and then input it to the load.
11. A method for fabricating a power device, characterized in that, include: A semiconductor body is provided, comprising a first surface and a second surface disposed opposite to each other; the semiconductor body further comprises a first region configured with a first conductivity type and located on the first surface; the semiconductor body further comprises a first epitaxial layer, a second epitaxial layer, and a third epitaxial layer, wherein the first epitaxial layer is configured with a second conductivity type and located on the side of the first region away from the first surface, and the first conductivity type and the second conductivity type are different; the second epitaxial layer is configured with a second conductivity type and located on the side of the first epitaxial layer away from the first surface, and the third epitaxial layer is configured with a first conductivity type and located on the side of the second epitaxial layer away from the first surface; the semiconductor body further comprises a second region configured with a first conductivity type and located within the second epitaxial layer, wherein opposite sides of the second region are in contact with the first epitaxial layer and the third epitaxial layer, respectively; a trench is provided on the first surface, the trench penetrating into the second epitaxial layer, and the trench corner penetrating into the second region; A first insulating layer and a gate are formed in the trench; wherein the first insulating layer covers the inner wall of the trench, and the gate is disposed on the side of the first insulating layer away from the inner wall of the trench; A drain is formed on the second surface, and a source is formed on the first surface.
12. The method for fabricating a power device according to claim 11, characterized in that, Provide semiconductor bodies, including: A third epitaxial layer, a second epitaxial layer, and a first epitaxial layer are formed and stacked sequentially. The second epitaxial layer and the third epitaxial layer are doped to form the second region; The first epitaxial layer is doped to form the first region; The groove is formed.
13. The method for fabricating a power device according to claim 12, characterized in that, The second epitaxial layer and the third epitaxial layer are doped to form the second region, and the process further includes: The second epitaxial layer is doped to form a third region; wherein the third region is configured with a first conductivity type and is located within the second epitaxial layer; the third region is disposed on the side of the trench adjacent to the second surface, and the trench extends from the first surface to the third region, a portion of the third region is located within the second region, and the third region is not in contact with either the first epitaxial layer or the third epitaxial layer; the doping concentration of the third region is greater than the doping concentration of the second region.
14. The method for fabricating a power device according to claim 13, characterized in that, The second epitaxial layer is doped to form a third region, including: A first mask structure is formed on the surface of the first epitaxial layer, wherein the first mask structure includes a first opening that exposes the first epitaxial layer; The third region is formed by doping the second epitaxial layer through the first opening; The second epitaxial layer and the third epitaxial layer are doped to form the second region, including: A sidewall structure is formed on the sidewall of the first opening; A second mask structure is formed in the first opening, and the second mask structure and the sidewall structure fill the first opening; wherein the second mask structure, the sidewall structure and the first mask structure are all made of different materials; At least a portion of the sidewall structure is removed to form a second opening; The second region is formed by doping the second epitaxial layer and the third epitaxial layer through the second opening; Remove the first mask structure, the remaining sidewall structure, and the second mask structure.
15. The method for fabricating a power device according to claim 14, characterized in that, Removing at least a portion of the sidewall structure to form a second opening includes: The sidewall structure is removed to form the second opening; or, a third mask structure is formed on the surface of the first mask structure, the third mask structure including a third opening, through which a portion of the sidewall structure is removed.
16. The method for fabricating a power device according to claim 15, characterized in that: The third mask structure includes a plurality of third openings, which are respectively disposed on both sides of the second mask structure along the width direction of the second mask structure; And / or, along the width direction of the second mask structure, at least two third openings disposed on one side of the second mask structure are arranged sequentially along the extension direction of the sidewall structure.
17. The method for fabricating a power device according to claim 14, characterized in that, Removing at least a portion of the sidewall structure to form a second opening includes: While removing at least a portion of the sidewall structure, a portion of the first mask structure adjacent to the sidewall structure is also removed to form the second opening.
18. The method for fabricating a power device according to claim 17, characterized in that, Removing at least a portion of the sidewall structure while simultaneously removing a portion of the first mask structure adjacent to the sidewall structure to form the second opening includes: While removing at least a portion of the sidewall structure using the same etching solution, a portion of the first mask structure adjacent to the sidewall structure is also removed to form the second opening.
19. The method for fabricating a power device according to claim 14, characterized in that, The first mask structure and the sidewall structure are made of silicon dioxide and silicon nitride, respectively; the second mask structure is made of polycrystalline silicon.