An automated test system for detecting IO ports on MCU controllers

Abstract

The application discloses an automatic test system for detecting IO ports on MCU controllers, and particularly relates to the technical field of automatic test and hardware-in-the-loop verification, wherein the system takes TSMaster as an upper computer, combines a programmable power supply, a digital multimeter and a controllable relay matrix, and realizes input injection, output measurement and controlled power supply disturbance through CAN / Ethernet / SCPI. The system comprises input injection and channel switching, output driving and high-resistance isolation, power supply disturbance and alarm verification, unified collection and self-calibration compensation, criterion evaluation / reporting and regression, etc. modules, and realizes alignment and online small signal calibration, crosstalk compensation under a unified time base, constructs a minimum evidence unit, and implements interval criterion and timing robustness evaluation. The system outputs an auditable report and triggers a regression schedule, realizes high coverage and repeatable verification of IO port functions and boundary working conditions.

Description

Technical Field

[0001] This invention relates to the fields of automated testing and hardware-in-the-loop verification technology, and more specifically, to an automated testing system for testing I / O ports on an MCU controller. Background Technology

[0002] As the reliability requirements of automotive electronics, industrial control, and consumer electronics products continue to increase in complex environments, the number and types of MCU I / O ports are constantly increasing. These include digital input / output, analog signal acquisition (ADC), PWM / pulse counting, external interrupts, pull-up / pull-down and high-impedance management, as well as timing and threshold consistency verification under different load and power supply disturbance conditions. R&D, production line release, and version regression testing all require high-coverage verification under repeatable and traceable conditions.

[0003] Current testing largely relies on engineers using instruments such as multimeters, oscilloscopes, and programmable power supplies for manual or scripted semi-automatic operations: switching channels between the device under test and the instrument, injecting high / low / reference levels, applying different loads, and recording readings. Frequent manual operation makes it difficult to maintain strict consistency in channel switching and engagement / disengagement timings. Factors such as relay contact bounce, parallel networks, and lateral coupling can easily introduce transient errors, leading to unstable threshold neighborhood criteria. Inconsistent timing and sampling rates among multiple source instruments, insufficient time alignment between setpoints, readback values, and bus messages, and a lack of a clear evidence chain for occurrence, detection, reporting, and clearing make results difficult to audit and reproduce. Furthermore, various input / output drive types, such as ADCs and PWM, need to cover boundary conditions like high / low / high impedance / pull-up / pull-down, and manual programming often fails to exhaustively cover all possible combinations, limiting test coverage and execution efficiency.

[0004] Furthermore, for verification of abnormal power supply conditions such as undervoltage / overvoltage and instantaneous drops / overshoots, existing methods often struggle to maintain stable residence near thresholds and precisely control the rise / fall rate, making it difficult to quantify the timing of alarm triggering, holding, and clearing logic. Bias and crosstalk across different batches and environments are also not uniformly modeled and compensated, resulting in insufficient comparability of cross-batch conclusions. On the data side, there is a general lack of unified time base and fixed step size data organization, and online calibration and health measurement are missing, making it difficult for the measurement link to detect and correct drift in a timely manner during long-term operation. The reporting side also lacks structured minimum evidence units and regression scheduling mechanisms. Summary of the Invention

[0005] To overcome the aforementioned deficiencies of the prior art, embodiments of the present invention provide an automated testing system for detecting I / O ports on an MCU controller to solve the problems mentioned in the background art.

[0006] To achieve the above objectives, the present invention provides the following technical solution:

[0007] An automated testing system for testing I / O ports on an MCU controller includes the following modules:

[0008] The host computer is used to provide a unified time base and schedule the execution of test programs;

[0009] The input injection and channel switching module is used to switch preset high level, low level or reference level to the target input IO terminal of the MCU under test through a controllable relay matrix under the control of the host computer.

[0010] The output driver and high-impedance isolation module is used to control the target output IO of the MCU under test under the control of the host computer, and to implement high-impedance isolation and load constraint on the external electrical path during the setting period.

[0011] The power disturbance and alarm verification module is used to generate a controlled power disturbance trajectory through a programmable power supply under the control of the host computer, so as to verify the self-test and alarm logic of the MCU under test under under-voltage and over-voltage conditions.

[0012] The unified acquisition and self-calibration compensation module is used to uniformly acquire, time-align and quality-control CAN messages from analog acquisition devices, digital multimeters, programmable power supplies and MCUs under the control of the host computer, and perform online self-calibration and crosstalk compensation, outputting a standardized data stream with corrected physical quantity estimates, uncertainty information and channel health.

[0013] The criterion evaluation, reporting, and regression module is used to receive the standardized data stream and execution event time anchors under the unified time base of the host computer, organize an auditable chain of evidence, and comprehensively obtain the uncertainty weighted compliance index based on the corrected physical quantity estimate, uncertainty range, specification allowable range, and channel health. It also synthesizes the disturbance response robustness index based on the delay, disturbance slope, and hysteresis width of the threshold crossing to alarm reporting / clearing. Based on the uncertainty weighted compliance index and the disturbance response robustness index, it generates a test report and triggers regression scheduling.

[0014] In a preferred embodiment, the input injection and channel switching module operates under mutual exclusion and safety state machine constraints to ensure that the same injection source is connected to only one target port in the same time window, and that the high-level and low-level injection paths are interlocked.

[0015] In a preferred embodiment, when the output driver and high-impedance isolation module perform controlled setting, they follow the order of isolating the external electrical path first, then setting the bit, and removing the bit first, then restoring the external network.

[0016] In a preferred embodiment, the power disturbance and alarm verification module generates a segmented ramp-stay-ramp power disturbance trajectory through the trajectory generation unit, which is used to stay near the undervoltage and overvoltage thresholds to observe the alarm logic.

[0017] In a preferred embodiment, the unified acquisition and self-calibration compensation module performs online self-calibration by applying a micro-amplitude DC multi-level or small-amplitude sweep frequency reference excitation to the target channel, and calculates a correction operator for inter-channel crosstalk compensation and bias correction based on the calibration data.

[0018] In a preferred embodiment, the unified acquisition and self-calibration compensation module obtains the corrected physical quantity estimate by subtracting the channel offset estimate from the original measurement vector and then applying the correction operator for linear transformation.

[0019] In a preferred embodiment, when the criterion evaluation, reporting and regression module calculates the uncertainty weighted compliance index, the following steps are adopted: calculate the compliance based on the uncertainty interval and specification allowable interval of the corrected physical quantity estimate, limit the compliance within the range of [0,1], and then multiply by the channel health to obtain the uncertainty weighted compliance index value.

[0020] In a preferred embodiment, when the criterion evaluation, reporting and regression module calculates the disturbance response robustness index, it performs a weighted synthesis based on the delay from threshold crossing to alarm reporting, the delay of alarm clearing, the disturbance slope and the hysteresis width, and then multiplies it by the channel health to obtain the disturbance response robustness index.

[0021] In a preferred embodiment, the auditable report generated by the criterion evaluation, reporting and regression module includes a dual-channel format of machine track and manual track. The machine track is output as a structured data object, and the manual track is presented in PDF or HTML format.

[0022] In a preferred embodiment, the regression scheduling triggered by the criterion evaluation, reporting and regression module dynamically adjusts the priority and execution strategy of test cases based on the values ​​of the uncertainty-weighted compliance index and the disturbance response robustness index, as well as the channel health.

[0023] The technical effects and advantages of this invention are as follows:

[0024] This invention significantly overcomes the core shortcomings of existing technologies, such as inconsistent human operation, difficulty in aligning multi-source data, and low test coverage, by constructing an automated testing system with unified time base and coordinated scheduling. The system ensures high repeatability of the level application and port setting processes through controlled and interlocked mechanisms in the input injection and channel switching modules, and the output drive and high-impedance isolation modules. Furthermore, by utilizing a power supply disturbance and alarm verification module to generate precise disturbance trajectories, it achieves quantifiable verification of alarm logic near undervoltage and overvoltage thresholds. This system effectively solves the problem of unstable criteria caused by relay contact bounce, lateral coupling, and timing jitter in traditional testing.

[0025] This invention further enhances the accuracy and cross-batch comparability of measurement results by employing a unified acquisition and self-calibration compensation module to perform time alignment and online calibration on multi-source heterogeneous data. This outputs a standardized data stream with uncertainty and channel health indicators, fundamentally improving the accuracy of measurement results. The criterion evaluation, reporting, and regression modules comprehensively adjudicate based on the uncertainty-weighted compliance index and the disturbance response robustness index, incorporating the reliability of measured values ​​and dynamic performance into a unified evaluation system and driving adaptive regression test scheduling. This solution generates a dual-channel auditable report with a complete chain of evidence, providing a highly comprehensive, repeatable, and reliable automated verification method for the functional and boundary condition testing of MCU controller I / O ports. Attached Figure Description

[0026] To facilitate understanding by those skilled in the art, the present invention will be further described below with reference to the accompanying drawings;

[0027] Figure 1 This is a schematic diagram of the structure of an automated testing system for detecting I / O ports on an MCU controller according to the present invention;

[0028] Figure 2 Workflow diagram for the criteria assessment, reporting, and regression modules. Detailed Implementation

[0029] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0030] Example 1: This invention provides an automated testing system for detecting I / O ports on an MCU controller, such as... Figure 1 As shown, it includes the following modules:

[0031] Module M1: Input injection and channel switching module;

[0032] This module is used to control the TSMaster graphical test program on the host computer to stably and repeatedly switch the preset high level VCC, low level GND or reference level to the target input IO terminal of the MCU under test through a controllable relay matrix, so as to realize the automated verification of input recognition capability and boundary conditions.

[0033] This module is based on a multi-channel relay unit. In a preferred embodiment, this multi-channel relay unit can be the K-8518 model, combined with a port and channel mapping table, a mutual exclusion and safety state machine, and a unified time base. The module forms a closed loop with the evidence archiving interface. Structurally, this module includes: a CAN communication adaptation layer for TSMaster, a relay channel management and interlocking subunit, an injection source selection and current limiting buffer subunit, a status acquisition and time stamping subunit, and an evidence output and anomaly handling subunit. Functionally, it realizes the time-series management of the entire process of injection pre-verification, controlled engagement / disengagement, steady-state maintenance, and removal / reset, and writes key status and measurement evidence into a unified data link, providing reliable input for subsequent criterion evaluation and report generation.

[0034] Before use, the system establishes a port and channel mapping table based on the connection list of the MCU under test, and maps the physical pins, wire harness terminals and specific channels of K-8518 one by one, and saves them to the configuration repository for version management.

[0035] To avoid channel contention and cross-network short circuits, this module maintains mutual exclusion rules and a state machine: the same injection source is only allowed to connect to one target port within the same time window; the same port rejects other injection requests while it is occupied; high-level and low-level injection paths are interlocked, and the other side remains open when one side is closed. This is combined with a unified time base. Before execution, this module performs an atomic check on four conditions: injection allowed, channel idle, current limiting ready, and MCU operating condition safe. If the conditions are not met, the module will not be executed and will output the rejection reason and timestamp.

[0036] During the injection execution phase, TSMaster issues specific action commands via the CAN channel. After receiving the commands, this module executes them in the order of configuration, engagement, hold, and deactivation. The configuration phase completes the selection of the injection source and the establishment of the current-limiting buffer link. The engagement phase drives the target K-8518 channel to close and reads back the relay contact status. If the contact readback is inconsistent with expectations, it is determined to be an abnormal operation and automatically deactivates, recording the event and fault code. The hold phase maintains the channel closed for a preset dwell time and applies gradual rise and fall edge control to the reference level as needed to suppress surges. The rise / fall time is preferably set in the range of 1–10ms to balance stability and efficiency. The deactivation phase disconnects the channel and restores it to a high-impedance state, clears the temporary mutex marker, and prepares for the next round of commands. To protect the device under test (DUT) and the fixture, this module configures a current-limiting resistor in the injection link. It is preferred to select Rs≥10 kΩ in the case of digital high-impedance input and limit the port current to within the input specifications of the MCU under test in the case of reference level injection. For ports that may have pull-up / pull-down, this module performs a micro-amplitude pre-detection before energizing to confirm that the external pull-up / pull-down will not cause an unexpected short circuit or overcurrent.

[0037] In terms of status monitoring and evidence generation, this module synchronously collects and solidifies command acceptance time, channel action time, contact readback status, injection source status, and corresponding measurement evidence, such as voltage readings from a K-8512 or digital multimeter at the port side, under a unified time base; and calculates process parameters such as pull-in delay, steady-state achievement time, and dwell time. If it is necessary to extend the coverage of the input boundary, this module can set the reference level to a multi-level level sequence near the high / low threshold, and use a slow slope switching to explore the impact of hysteresis intervals and debouncing strategies on the recognition results. The corresponding measurement evidence is written into the log and report data structure in the form of original value, correction value, timestamp, channel ID, and script version, forming a traceable evidence chain.

[0038] This module provides clearly defined selectable ranges and preferred values ​​for key parameters. The injection level is determined by the system power supply. The choice between ground and reference level is preferred; if it is a reference level, it should be set to ground. The safe range; the dwell time is determined based on the input sampling and debouncing configuration of the MCU under test, and is preferably set in the range of 20–200ms; the edge control can be set to the fastest reachable in scenarios without debouncing requirements, and should be relaxed to millisecond-level gradual change when debouncing verification is required; when contact readback fails, overcurrent or short circuit is suspected, this module immediately enters the fault-safe state and disconnects all related channels, and at the same time marks the abnormality type, associated port and time of occurrence in the log, so as to facilitate quick reproduction and location.

[0039] In its collaboration with other modules of the system, this module externally uses standardized event notifications—injection start, steady-state achievement, and injection end—to drive the criterion evaluation module for input recognition and judgment, and provides time alignment anchors to the unified acquisition and self-calibration compensation module. When the system enables online self-calibration and crosstalk compensation functions, this module outputs a small-amplitude stimulus and returns action and time evidence for a short period during non-business windows as planned, without affecting the normal test case cycle. Through the above structure and process, this module achieves controllable application, mutual exclusion safety, process visibility, and evidence traceability of the input ports of the MCU under test under high / low level and reference level conditions, ensuring the consistency and reproducible experimental conditions of input recognition testing in mass production and regression scenarios.

[0040] Module M2: Output driver and high-impedance isolation module;

[0041] This module, under the control of the TSMaster graphical test program on the host computer, performs controlled setting of the target output I / O of the MCU under test. During the setting period, it implements high-impedance isolation and load constraints on the external electrical path to accurately reflect the port's driving capability and threshold behavior. Simultaneously, it provides stable, low-disturbance measurement conditions for the vector measurement link. This module uses the MCU-side control channel as the setting trigger entry, the isolated topology of a controllable relay matrix as the means of external network status management, and K-8512 analog signal acquisition or digital multimeter readings as the measurement output of the port's physical response. To ensure process traceability and reproducibility, this module uses a unified time base... The key events of setting actions, isolation actions, measurement times and steady-state judgments are time-stamped and written into the system data link in an evidentiary structure.

[0042] In terms of execution flow, this module first performs a consistency verification of the current operating condition of the target output IO, confirming that the MCU under test is in a safe state that allows remote setting and that related interrupts, watchdog timers, or low-power strategies will not change the port mode within the setting window. Subsequently, TSMaster issues a setting command to make the target IO enter the predetermined high-level or low-level output state. After the setting command is accepted, this module immediately switches the external relay channel directly connected or in parallel with the port to a high-impedance or disconnected state to eliminate the influence of external strong pull, lateral coupling, or unplanned load on the port, while retaining the high input impedance of the measurement channel for easy reading. After isolation is completed, this module enters the steady-state determination stage. By continuously acquiring the time series of port voltage, it identifies the earliest moment when the output enters the steady state from the transient state, and performs multiple samplings within the steady-state window to obtain representative values. For outputs with duty cycle or frequency characteristics (such as PWM), this module completes the separation measurement of the mean and peak values ​​within a single test cycle without changing the port configuration, and records the duty cycle, average level, and threshold comparison results together.

[0043] This module sets a configurable micro-delay between isolation and measurement actions to absorb minor bounces from relay contacts and transient responses from the output loop, preferably configured within the range of 1–10ms. In scenarios with stricter transient criteria, this module allows time alignment with other devices (such as power readback and CAN messages) using a unified time base before steady-state confirmation.

[0044] Regarding criterion integration, the port voltage output by this module, along with its timestamp, channel identifier, set command identifier, and script version, forms the smallest unit of evidence for the criterion evaluation module to perform interval concatenation determination. To facilitate clear expression of technical effects, this module supports using thresholds given in the MCU's datasheet or model specification as physical criterion boundaries, for example... Indicates the lower limit voltage of the high-level allowed range, and Indicates the upper limit voltage of the low-level allowable range, and is expressed as... This represents the port voltage value after system self-calibration and crosstalk compensation. When a high-level setting is performed, the qualification condition can be expressed as... When a low-level setting is performed, the qualified condition can be expressed as follows: .in, This is the estimated value after sampling the port voltage within the steady-state window and processing it with a correction operator; and Limited by the electrical characteristics of the MCU under test, it is often given in the form of a proportion of the supply voltage or an absolute voltage. For example, a typical device may use... , The reference range is provided, but the specific value is subject to the target device specification. For open-drain or open-collector outputs, this module adaptively adjusts the criteria based on the external pull-up resistor configuration and power rail constraints while isolating the device, and only initiates the qualification judgment when the pull-up path is confirmed to be valid and the port function settings match.

[0045] To avoid backfeeding and latch-up risks, this module follows the principle of isolating first, then setting; and de-setting first, then restoring the external network. It will refuse to set the device if any abnormal differential pressure, overcurrent indication, or external network not being at high impedance is detected, and will log the abnormal state along with the corresponding port and time. A safe-state rollback will be triggered if necessary. This module provides clearly configurable ranges for key parameters. The dwell time after setting is determined based on the digital filtering and firmware debouncing settings of the port under test, preferably set in the range of 20–200ms to balance efficiency and statistical stability. The input impedance of the measurement channel is preferably not less than 1MΩ to reduce the additional load on the port under test. In scenarios with external pull-up resistors, this module performs a pre-verification with a very small amplitude reference level perturbation after isolation to confirm that the pull-up resistor has not been accidentally bypassed or shorted. All control commands, readback statuses, and time stamps for setting, isolation, steady-state confirmation, and measurement processes are collected under a unified time base and compared with the port status reports from the CAN message side. This ensures that logical and physical consistency can be verified simultaneously and form an auditable chain of evidence in the report.

[0046] Through the structured process described above, this module accurately presents the driving capability and threshold compliance of the tested MCU output port under high, low, and duty cycle conditions without introducing external forced loads. Utilizing high-impedance isolation and steady-state identification mechanisms, it effectively suppresses interference from relay contact bounce, lateral coupling, and parallel networks. In conjunction with the unified acquisition and self-calibration compensation module, the port voltage readings can obtain quantifiable uncertainties and correction values, thus providing accurate, traceable, and reusable basic data for subsequent interval criteria and qualification assessments.

[0047] Module M3: Power Disturbance and Alarm Verification Module;

[0048] This module is used to generate a controlled power disturbance trajectory through an SCPI session established with a programmable DC power supply under the control of the TSMaster graphical test program on the host computer. It verifies the self-test and alarm logic of the MCU under test under under-voltage and over-voltage conditions, and uses a unified time base to perform timing correlation on power setting / readback, analog measurement and CAN message to form a complete evidence chain of disturbance, threshold crossing, alarm reporting and rollback clearing.

[0049] Structurally, this module consists of a trajectory generation unit, an execution and interlocking unit, a threshold crossing detection unit, an alarm matching and rollback verification unit, and an evidence archiving interface. Functionally, it manages the entire process from trajectory synthesis, distribution and readback, time-series anchor point identification to qualification determination, and shares a unified time base with other modules in the system. Include script version information to ensure the reproducibility and auditability of the results.

[0050] Before the test begins, this module first identifies the power supply topology and nominal voltage of the MCU under test, confirming that the target power rail, power supply circuit, and readback channel are configured correctly, and that the power supply's voltage / current limiting and overvoltage / overcurrent protection are in an adjustable state. To avoid damage to the device under test and the fixture, this module activates safety preconditions by executing and interlocking the unit, including constraints on the maximum output voltage, minimum output voltage, maximum voltage change slope, and maximum output current. If the interlocking conditions are not met, the module refuses to enter the disturbance process and records the reason for refusal and the timestamp.

[0051] Subsequently, the trajectory generation unit generates a voltage-time function that is continuous in time but limited in amplitude, according to the test plan, to cover the undervoltage and overvoltage trigger ranges. Preferably, the trajectory adopts a segmented ramp-dwell-ramp parameterized form to maintain sufficient dwell time near the threshold to observe the MCU's alarm criteria and hysteresis characteristics. If a formula is required, the trajectory can be written as... ;in, In order to unify the time base The target power supply voltage is as follows. The starting voltage of the trajectory. The slope of the voltage change. This indicates the amplitude limiting operator. and These represent the minimum and maximum allowable output voltage boundaries. When the trace reaches the preset dwell interval, the trace generation unit sets the slope to zero and maintains the dwell time to observe the stable performance of the MCU near the threshold and the alarm hold / clear logic. The above parameters are configured by the test script to meet the common constraints of the device under test datasheet and tooling capabilities.

[0052] During the trajectory distribution process, the execution and interlocking units will communicate via SCPI session. Discrete sampling points are sent to the programmable power supply in fixed steps, and each sending and device readback result is recorded as a triplet of set value, readback value, and timestamp. Simultaneously, a unified acquisition link is connected to the port-side voltage reading of a K-8512 or digital multimeter in a synchronous sampling manner to enhance the sensing capability of the actual endpoint voltage. When the trajectory crosses the undervoltage and overvoltage criterion regions of the MCU under test, the threshold crossing detection unit identifies the crossing moment and generates an anchor point on the combined curve of power supply readback and port measurement.

[0053] To accommodate differences in threshold definitions across various devices, this module allows for simultaneous determination using both absolute voltage and proportional voltage methods: when using absolute voltage, the threshold is determined by... and This indicates the undervoltage and overvoltage thresholds given in the device specification, and the crossover event in... Or the port test first met the requirements or Time marker; when using proportional voltage, to and Indicates relative to nominal voltage The proportion threshold, the crossing event in or Time marker. The physical meanings of the above parameter symbols are as follows: The undervoltage / overvoltage criterion voltage defined in the device datasheet. It is expressed as a ratio relative to the nominal voltage. This is the nominal supply voltage set during testing. To suppress the effects of measurement noise and ripple, the threshold pass-through detection unit applies a short window to the readback curve and port measurement before judgment, ensuring robust smoothness, and sets a small hysteresis band to avoid repeated triggering due to jitter near the threshold.

[0054] The alarm matching and rollback verification unit continuously monitors the MCU's CAN bus alarm messages throughout the entire trajectory execution and performs timing matching with the threshold crossing anchor point. It records the first reporting times of undervoltage and overvoltage alarms and calculates the delay from crossing to reporting to evaluate the response speed and correctness of the MCU alarm link. After the power trajectory recovers to the safe range and enters dwell mode, this unit continues to observe alarm clearing messages and status bit rollback, calculating whether the clearing delay and holding behavior meet the design requirements. For devices with latch-up characteristics, this module automatically adds a short power-down to power-up reset sequence during the rollback phase to verify the latch-up clearing path. All timing-related quantitative indicators are based on a unified time base. The data is labeled and written into the evidence archiving interface along with the script version hash, device serial number, and test batch identifier. If the system has self-calibration and crosstalk compensation capabilities enabled, this module will prioritize using the calibrated port measured voltage and its uncertainty range for threshold crossover and delay calculations, and will provide both the original and calibrated values ​​in the report for cross-sectional comparison during review.

[0055] This module sets up anomaly detection and fast rollback paths at key nodes. When the power supply readback and setting deviation exceed the allowable tolerance, the output current triggers overcurrent protection, or the measured voltage at the port abnormally exceeds the limit, the execution and interlocking unit immediately stops the trajectory transmission and switches the voltage back to the nominal value, triggers the safety state, and freezes all current buffer data. Subsequently, it writes the abnormal event, cause, time, affected channel, and protection action into the log.

[0056] This module externalizes parameters such as threshold, slope, dwell time, and hysteresis width in the form of a data dictionary, allowing for differentiated adaptation through configuration without modifying the main program. At the same time, this module has self-check items for trajectory quality and message integrity, including indicators such as trajectory coverage, readback sampling loss rate, message frame loss rate, and clock offset. If the values ​​are below the threshold, the module automatically determines that the current test is invalid and suggests a retest.

[0057] Module M4: Unified data acquisition and self-calibration compensation module;

[0058] This module, under the control of the TSMaster graphical test program on the host computer, performs unified acquisition, time alignment, and quality control of raw CAN messages from K-8512 analog acquisition, digital multimeter readings, programmable power supply settings / readback, and the MCU. Within a preset calibration window, it performs online small-signal self-calibration and crosstalk compensation, outputting a standardized data stream with correction values ​​and uncertainty information for use by the criterion evaluation module. This module uses a unified time base. Using this as the core organizational mechanism, combined with buffer queues and timestamp services, data consistency is achieved across devices, sampling rates, and communication protocols. Under the condition that the health of the measurement link meets the requirements, the channel fingerprint update and correction operator are released in a way with minimal disturbance, ensuring that the measurement values ​​in the subsequent formal testing phase have quantifiable accuracy and traceable sources.

[0059] On the data access side, this module establishes a session and buffer for each data source, receiving the channel voltage of the K-8512, the reference reading of the multimeter, the voltage / current readback of the power supply, and the message stream of the CAN bus, respectively, and mapping their respective device timestamps to a unified time base. When the device has a fixed clock offset, this module performs a one-time correction based on the offset obtained from the power-on self-detection. When there is a slow offset caused by temperature drift or queue jitter, this module estimates the minute drift within a finite time window and performs interpolation resampling, thus ensuring that the same physical event has a consistent time anchor point across different data streams. To avoid data contamination, this module performs outlier masking and robust noise reduction after sampling, preferably using short-window median or Huber-type smoothing, which suppresses transient spikes without disrupting boundary transitions. All records output by this module simultaneously carry the device identifier, channel number, test script version, and unified timestamp to form the basic metadata for subsequent evidence chains.

[0060] Within the calibration window, this module, based on the system's scheduling plan and safety interlocks, applies a small-amplitude DC multi-level or small-amplitude sweep frequency reference excitation to the target channel via a relay matrix without changing the logic state of the MCU under test. The typical amplitude is preferably set to the nominal supply voltage. The frequency sweep range is preferably 5%–20% covering the low-frequency band from 50Hz to 5kHz to enhance sensitivity to contact impedance and harness parasitic parameters. The corresponding channel voltage response is acquired in parallel by a K-8512 and a multimeter and written to the unified buffer of this module, forming a closed loop with power readback and CAN silent state under the same time base. After sampling a set of levels or frequencies, this module approximates the coupling relationship between channels with a linear small-signal approximation to obtain the equivalent crosstalk matrix and channel bias, and fuses the estimation results with historical priors to output the latest correction operator and confidence index.

[0061] To maintain clarity and minimize the complexity of the formulas, this module uses only two necessary expressions. The first is the time alignment offset correction, which employs... ,in This is the device's original timestamp. For this device relative to a unified time base offset estimation, The first is a unified timestamp after alignment. The second is linear correction of the measured values, using... ,in For the original measurement vectors under a unified time base (e.g., multi-channel port voltages). For channel bias estimation, The correction operator is constructed from the online calibration results. These are the corrected estimated values ​​of the physical quantities. The physical meanings of the above symbols are as follows: This represents an estimate of a fixed offset or slow drift of the clock across devices. This indicates the zero-point deviation caused by the contact resistance of the contact point and the bias of the measurement link. It reflects the combined effect of inter-channel coupling compensation and proportional correction. The data is standardized and can be used for criterion evaluation. The least squares method is used to fit the linear relationship between channels to obtain the correction operator matrix. And ridge regression is used to prevent overfitting.

[0062] Regarding uncertainty handling, this module simultaneously provides confidence intervals and health indicators for the calibrated measurement values. The confidence interval is derived from the error propagation of the calibration operator and measurement noise, considering both the uncertainty of inter-channel compensation and the statistical fluctuations of the device's own readings. The health indicator is based on the difference between the current calibration and the previous valid calibration, comprehensively reflecting the impact of relay contact aging, wiring harness contact status, and environmental temperature drift on link stability. When the health level drops below a preset threshold, this module will issue maintenance suggestions or degradation strategies through the scheduling interface, such as shortening the calibration interval, automatically isolating suspicious channels, or increasing the confidence requirements of the criteria during formal testing. To ensure the stable cycle time of the automated production line, this module constrains the duration and injection density of the calibration window, preferably inserting it during batch gaps or test case switching intervals. The dwell time and number of injected channels for a single calibration are determined collaboratively by the test plan and available computing power, achieving a reasonable balance between calibration overhead and test throughput.

[0063] During formal testing, this module performs posterior correction and time alignment on real-time measurements in a streaming manner, and pushes a complete record of the original value, corrected value, confidence interval, health status, timestamp, channel ID, and script version to the criterion evaluation module. For use cases highly sensitive to timing, this module uses the identification result of the steady-state achievement moment as a time anchor to ensure that the criterion is executed at the correct physical stage. For use cases sensitive to amplitude boundaries, such as high / low level thresholds and ADC quantization intervals, this module provides representative values ​​and dispersion from multiple samples within a unified sampling window to enhance statistical robustness. If channel drift or device offset exceeding the allowable range is found during the correction process, this module will mark the validity of the current batch as an event and identify and recommend retesting for the affected use cases in the reporting phase, thereby avoiding writing unreliable conclusions into the final results.

[0064] Regarding evidence archiving, this module version-based solidifies key processes and outputs, including the calibration of original fragments, the version and timestamp of the correction operator matrix, the corresponding prior / posterior parameters, the serial number and firmware version of the data source device, the offset estimate of the unified time base, and the health evolution curve. All evidence is written to persistent storage in a structured format and generates an evidence index with hash pointers, facilitating subsequent regression analysis, auditing, and quantitative presentation of technical effects in opinion statements. Through the above-mentioned structured data governance and online self-calibration compensation, this module significantly improves measurement consistency and conclusion credibility under cross-channel, cross-batch, and cross-environment conditions without changing the functional logic of the MCU under test, providing a solid data foundation for the stable operation of the system in mass production and long-term maintenance scenarios.

[0065] Module M5: Criterion Evaluation, Reporting, and Regression Module;

[0066] like Figure 2 As shown, this module serves as the system's adjudication and output hub. Under the unified time base of the host computer TSMaster, it receives standardized data streams from the unified acquisition and self-calibration compensation module, as well as time anchors for execution events such as input injection, output setting, and power disturbances. It organizes scattered measurements and messages into an auditable chain of evidence and completes use case-level criterion evaluation, conclusion generation, report publication, and regression scheduling without altering the functional logic of the MCU under test. When data enters this module, it has already been mapped to the unified time base. The original measurement vectors are transformed into corrected physical quantity estimates through correction operators and bias baseline transformation. And simultaneously carry the uncertainty interval at a given confidence level. And channel health H. This module first uses the timestamp as the anchor point to connect the physical side. The uncertainty and logic side are consistently assembled by the state semantics reported by the MCU on the CAN bus to form the smallest evidence unit containing key nodes such as execution events, steady-state achievement, threshold crossing, and alarm reporting / clearing. To ensure the objectivity and reproducibility of the decision, the evidence unit must meet the data quality threshold and security threshold before entering the criterion calculation: if the unified time base alignment residual, sampling loss rate, or device self-test status is not up to standard, or the health level H is lower than the set threshold, this module will mark the confidence of the batch of data as downgraded and trigger recalibration, retesting, or channel isolation suggestions; only after meeting the threshold can it enter the decision process.

[0067] For amplitude / static class use cases, this module does not use a single-point threshold for judgment, but instead uses an interval discrimination with uncertainty: when If the interval is completely contained within the specification allowable range [L,U] and the logic state matches the expectation, it is considered qualified; if the interval only partially intersects with [L,U] or the logic deviates briefly and then recovers, it is marked as critical and a retest suggestion is generated; if the interval mostly falls outside the specification or the logic continues to deviate, it is considered unqualified.

[0068] To incorporate the reliability of values ​​and link status into a unified quantification, this module calculates the Uncertainty Weighted Consistency Index (UWCI) while performing interval discrimination. Its mathematical expression follows the principle of minimum necessity: In the formula, These are the corrected estimated values ​​of the physical quantities. Let [L,U] be the upper and lower limits of the estimated value at a given confidence level, [L,U] be the specification range given for this project in the test plan or device manual, and H∈[0,1] be the channel health. This represents an operator that restricts the result to the interval [0,1].

[0069] This module characterizes the robustness of the fit with specification boundaries, taking into account measurement uncertainty and link health. A higher exponent indicates a better safety margin and more reliable conclusions. For dynamic / time-series use cases (e.g., undervoltage / overvoltage alarms), this module matches the threshold crossing point of the trajectory with the MCU's first alarm report and alarm clearing time on a unified time base to obtain the delay from crossing to alarm. Delay from recovery to clearing And combine the perturbation slope r with the hysteresis width Calculate the robustness index of disturbance response ( ): .in, and The maximum response and cleanup time allowed by the test plan. For the target hysteresis width, The normalization severity for the perturbation slope (the greater the slope, the stricter the normalization). The closer to 1), , This represents the actual perturbation slope. The maximum perturbation slope allowed by the test plan; to ∈[0,1] represents the weights and their sum is 1, for example =0.2, =0.3, =0.4, =0.1. A single [0,1] index is used to comprehensively reflect the timing robustness of fast triggering, fast clearing, moderate hysteresis, and insensitivity to slope. The higher the index, the better the stability in dynamic environments.

[0070] When there is a discrepancy between the physical conclusion and the logical report, this module will not directly give a qualified judgment. Instead, it will generate a conflict label in the evidence and retain the time configuration of the conflict, the relevant original fragments and correction parameters. If the conflict is located in the threshold neighborhood and the uncertainty is large, this module will automatically increase the confidence requirement or extend the steady-state observation window to suppress misjudgments caused by random factors.

[0071] For use cases that meet the qualification criteria, the module records... and Simultaneously, a comprehensive report is provided, including conclusion level, credibility level, and safety margin. For critical and non-compliant use cases, this module generates retesting or maintenance suggestions and includes them in the high-priority regression list when time quotas are limited. To ensure the auditability of the conclusions, a self-consistency check is performed before the report is released. The check items include the temporal relationship between execution events and response events, the consistency between power settings and readbacks and endpoint measurements, the matching degree between physical measurements and logical messages, and the consistency between corrected asset versions and data calibers. Items that do not meet the self-consistency constraints are automatically downgraded in credibility level and accompanied by retesting suggestions or tooling maintenance prompts.

[0072] The report is released using a dual-channel approach: machine-based and manual-based. The machine-based approach outputs structured data objects for MES / QMS and regression platforms, including the smallest unit of evidence, interval criterion results, etc. / Numerical values, thresholds and weighting parameters, health and uncertainty, device and script versions, and timestamps are all included. The manual track is presented in PDF / HTML format, visually displaying key waveforms, message fragments, and decision semantics on the same timeline, and automatically generating explanatory paragraphs, mapping each conclusion to its upstream data fragments, correction parameters, specification boundaries, and comprehensive indices. To form an end-to-end traceable chain, this module generates an evidence pointer and a replayable package for each report: the evidence pointer includes the device serial number, firmware and script version hashes, unified time base offset estimation, key timestamp summary, and archived data packet hash; the replayable package, after necessary anonymization, includes the original fragment, correction assets, uncertainty and health parameters, and a rendering template; the correction assets include correction operators. Bias b.

[0073] Regression scheduling is uniformly orchestrated by this module, aiming to maximize risk coverage and information gain within a fixed time quota. The scheduling strategy uses a comprehensive index and health status as core signals: when... and Simultaneously, when the level is high and the health is stable, the system executes a baseline sampling strategy to maintain coverage; when Gao Er When the amplitude is low, it is marked as meeting the standard but dynamically fragile, and priority is given to retesting and increasing sampling related to disturbances; when When a test degrades due to a decrease in health, the unified data collection and self-calibration compensation module shortens the online calibration interval or isolates suspicious channels, and lowers the confidence level of the conclusions for affected use cases until retesting is completed. Scheduling decisions and their rationale are logged together to ensure that the reasons for selecting a particular batch of use cases can be traced at any point in time, and to support differential comparison and trend analysis across batches.

[0074] Through the aforementioned structure and process, this module integrates physical quantity estimates, reliability, health, timing stringency, and hysteresis quality into a unified auditable measurement framework. On a unified time base, it transforms disparate measurements and messages into clear, interpretable, and reproducible decisions and reports, and maintains long-term operational stability and efficiency through risk-driven regression scheduling. Compared to traditional methods relying solely on single thresholds and fixed delays, this module introduces comprehensive analysis indices along both amplitude and dynamic lines, elevating the conclusion from mere compliance to the degree of reliability and dynamic robustness of compliance. This provides robust data and methodological support for production release and quality traceability in automated testing systems used to inspect MCU controller I / O ports.

[0075] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0076] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0077] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0078] In addition, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0079] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. An automated testing system for detecting I / O ports on an MCU controller, characterized in that, Includes the following modules: The host computer is used to provide a unified time base and schedule the execution of test programs; The input injection and channel switching module is used to switch preset high level, low level or reference level to the target input IO terminal of the MCU under test through a controllable relay matrix under the control of the host computer. The output driver and high-impedance isolation module is used to control the target output IO of the MCU under test under the control of the host computer, and to implement high-impedance isolation and load constraint on the external electrical path during the setting period. The power disturbance and alarm verification module is used to generate a controlled power disturbance trajectory through a programmable power supply under the control of the host computer, so as to verify the self-test and alarm logic of the MCU under test under under-voltage and over-voltage conditions. The unified acquisition and self-calibration compensation module is used to uniformly acquire, time-align and quality-control CAN messages from analog acquisition devices, digital multimeters, programmable power supplies and MCUs under the control of the host computer, and perform online self-calibration and crosstalk compensation, outputting a standardized data stream with corrected physical quantity estimates, uncertainty information and channel health. The criterion evaluation, reporting, and regression module is used to receive the standardized data stream and the time anchor points of the execution events under the unified time base of the host computer, and to organize an auditable chain of evidence; wherein, the criterion evaluation, reporting, and regression module is configured to: calculate the compliance degree based on the uncertainty interval and the specification allowable interval of the corrected physical quantity estimate, limit the compliance degree to the range of [0,1], and then multiply it by the channel health degree to obtain the uncertainty weighted compliance degree index; The system performs a weighted synthesis based on the threshold crossing delay to alarm reporting, alarm clearing delay, disturbance slope, and hysteresis width, and then multiplies it by the channel health to obtain the disturbance response robustness index. Based on the uncertainty-weighted compliance index and the disturbance response robustness index, a test report is generated and regression scheduling is triggered.

2. The automated test system for detecting I / O ports on an MCU controller according to claim 1, characterized in that: The input injection and channel switching module operates under mutual exclusion and safety state machine constraints to ensure that the same injection source is connected to only one target port in the same time window, and that the high-level and low-level injection paths are interlocked.

3. The automated test system for detecting I / O ports on an MCU controller according to claim 1, characterized in that: When the output driver and high-impedance isolation module perform controlled setting, they follow the principle of isolating the external electrical path first, then setting the bit, and removing the bit first, then restoring the external network.

4. The automated test system for detecting I / O ports on an MCU controller according to claim 1, characterized in that: The power disturbance and alarm verification module generates a segmented ramp-stay-ramp power disturbance trajectory through the trajectory generation unit, which is used to stay near the undervoltage and overvoltage thresholds to observe the alarm logic.

5. The automated test system for detecting I / O ports on an MCU controller according to claim 1, characterized in that: The unified acquisition and self-calibration compensation module performs online self-calibration by applying a micro-amplitude DC multi-level or small-amplitude sweep frequency reference excitation to the target channel, and calculates the correction operator for inter-channel crosstalk compensation and bias correction based on the calibration data.

6. The automated test system for detecting I / O ports on an MCU controller according to claim 5, characterized in that: The unified acquisition and self-calibration compensation module obtains the corrected physical quantity estimate by subtracting the channel offset estimate from the original measurement vector and then applying the correction operator for linear transformation.

7. The automated test system for detecting I / O ports on an MCU controller according to claim 1, characterized in that: The auditable reports generated by the criteria evaluation, reporting, and regression modules include both machine-based and manual-based reports. The machine-based reports are output as structured data objects, while the manual-based reports are presented in PDF or HTML format.

8. The automated test system for detecting I / O ports on an MCU controller according to claim 1, characterized in that: The regression scheduling triggered by the criteria evaluation, reporting, and regression modules dynamically adjusts the priority and execution strategy of test cases based on the values ​​of the uncertainty-weighted compliance index and the disturbance response robustness index, as well as the channel health.

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