Data processor, method, electronic device and storage medium

Abstract

The present disclosure provides a data processor, a method, an electronic device and a storage medium, the data processor comprising an instruction scheduler and a replication engine, the instruction scheduler comprising a first tensor access register configured to store sub-tensor description information transmitted externally; the replication engine comprising a first queue structure, a second tensor access register configured to store sub-tensor description information received from the first queue structure, and an instruction decoder configured to parse instructions received from the first queue structure and generate control signals to drive data transfer; wherein the instruction scheduler is configured to dynamically detect a change parameter item of the sub-tensor description information, write the change parameter item into the first queue structure, so that the replication engine incrementally updates the sub-tensor description information in the second tensor access register based on the change parameter item. Thus, the embodiments of the present disclosure can reduce data transmission redundancy and improve instruction processing efficiency.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of processors, and in particular to a data processor, a method, an electronic device and a storage medium. BACKGROUND

[0002] With the rising demand for data transfer efficiency in the fields of artificial intelligence and high-performance computing, the performance of a copy engine directly affects the system computing power as the core hardware of tensor cross-memory transmission. In the current processor architecture, the instruction scheduler needs to send all the data of the tensor access register to the copy engine, resulting in redundant transmission. Moreover, due to the limited efficiency of the parsing instructions of the copy engine, it is difficult to handle high-concurrency data transfer requests, which limits the instruction throughput of the copy engine. SUMMARY

[0003] Embodiments of the present disclosure provide a data processor, a method, an electronic device and a storage medium, which can reduce data transmission redundancy and improve instruction processing efficiency.

[0004] In a first aspect, the embodiments of the present disclosure provide a data processor, comprising: an instruction scheduler and a copy engine, the instruction scheduler comprising a first tensor access register composed of physical circuits, the first tensor access register being configured to store sub-tensor description information transmitted externally; the copy engine comprising a first queue structure connected with the instruction scheduler, and a second tensor access register and an instruction decoder both composed of physical circuits, the second tensor access register being configured to store the sub-tensor description information received from the first queue structure, and the instruction decoder being configured to parse instructions received from the first queue structure and generate control signals to drive data transfer for the sub-tensor description information; wherein the instruction scheduler is configured to dynamically detect a change parameter item of the sub-tensor description information, write the change parameter item into the first queue structure, so that the copy engine incrementally updates the sub-tensor description information in the second tensor access register based on the change parameter item.

[0005] Further, the embodiments of the present disclosure further provide that the dynamic detection of the change parameter item of the sub-tensor description information comprises:

[0006] in response to receiving the first sub-tensor description information transmitted externally, taking the sub-tensor description information stored in the first tensor access register as a historical value, taking the first sub-tensor description information as a current value of the sub-tensor description information, and writing the first sub-tensor description information into the first tensor access register by overwriting;

[0007] comparing the current value and the historical value of the sub-tensor description information to determine the change parameter item of the sub-tensor description information.

[0008] Further, the embodiment of the present disclosure further proposes that the sub-tensor description information includes a plurality of component parameter items, and the comparing the current value with the historical value of the sub-tensor description information to determine the changed parameter item of the sub-tensor description information includes:

[0009] comparing the current value with the historical value of each of the component parameter items of the sub-tensor description information;

[0010] when the current value of the component parameter item is not equal to the historical value, adding an incremental mask to the component parameter item;

[0011] determining the component parameter item carrying the incremental mask as the changed parameter item.

[0012] Further, the embodiment of the present disclosure further proposes that the writing the changed parameter item into the first queue structure includes:

[0013] in response to receiving a target instruction transmitted externally, determining the position information of the changed parameter item in the sub-tensor description information;

[0014] writing the changed parameter item, the corresponding position information, and the target instruction into the first queue structure.

[0015] Further, the embodiment of the present disclosure further proposes that the sub-tensor description information includes a parameter item group composed of a plurality of component parameter items, and the comparing the current value with the historical value of the sub-tensor description information to determine the changed parameter item of the sub-tensor description information includes:

[0016] comparing the current value with the historical value of each of the component parameter items in the parameter item group;

[0017] when the current value of any of the component parameter items is not equal to the historical value, adding an incremental mask to the parameter item group;

[0018] determining all the component parameter items in the parameter item group carrying the incremental mask as the changed parameter item.

[0019] Further, the embodiment of the present disclosure further proposes that the writing the changed parameter item into the first queue structure includes:

[0020] in response to receiving a target instruction transmitted externally, determining the position information of the changed parameter item in the sub-tensor description information, wherein the total data length of the parameter item group is equal to the physical storage width of the first queue structure;

[0021] writing all the component parameter items in the changed parameter item group, the corresponding position information, and the target instruction into the first queue structure.

[0022] Further, the disclosure embodiments also propose that the write position of the target instruction is located at the tail of the write positions of both the change parameter item and the position information.

[0023] Further, the disclosure embodiments also propose that the copy engine is configured to:

[0024] obtain the change parameter item from the first queue structure and write the change parameter item into the second tensor access register to incrementally update the sub-tensor description information stored in the second tensor access register;

[0025] in response to the target instruction received from the first queue structure, perform data transfer according to the sub-tensor description information currently stored in the second tensor access register.

[0026] Further, the disclosure embodiments also propose that the instruction decoder is configured to:

[0027] in response to the target instruction received from the first queue structure, obtain the sub-tensor description information currently stored from the second tensor access register;

[0028] generate a transfer control signal based on the obtained sub-tensor description information to enable the copy engine to perform data transfer for the sub-tensor description information.

[0029] Further, the disclosure embodiments also propose that the copy engine is further configured to:

[0030] receive the change parameter item and the position information from the first queue structure;

[0031] incrementally update the sub-tensor description information stored in the second tensor access register using the change parameter item according to the position information.

[0032] In a second aspect, the disclosure embodiments also propose a data processing method applied to the data processor as described in the first aspect above, and the data processing method comprises:

[0033] through the instruction scheduler, write externally transmitted sub-tensor description information into a first tensor access register and dynamically detect a change parameter item of the sub-tensor description information and write the change parameter item into the first queue structure;

[0034] through the copy engine, receive the change parameter item from the first queue structure and incrementally update sub-tensor description information in the second tensor access register based on the change parameter item.

[0035] In a third aspect, the embodiments of the present disclosure further provide an electronic device, which comprises a memory, a processor, a program stored in the memory and executable on the processor, and a data bus for realizing connection communication between the processor and the memory, and the program, when executed by the processor, realizes the data processing method according to the second aspect.

[0036] In a fourth aspect, the embodiments of the present disclosure further provide a computer readable storage medium, characterized in that the computer readable storage medium stores one or more programs, and the one or more programs are executable by one or more processors to realize the data processing method according to the second aspect.

[0037] The data processor, the data processing method, the device and the medium provided by the present disclosure comprise an instruction scheduler and a replication engine, a hardware-implemented double tensor access register architecture is introduced in the instruction scheduler and the replication engine, the first tensor access register in the instruction scheduler stores the sub-tensor description information transmitted from the outside in real time, and the changed parameter items (such as address, size or coordinate, etc.) in the sub-tensor description information are identified through dynamic detection, and only these changed parameter items are transmitted to the first queue structure of the replication engine, the changed parameter item granularity transmission is used instead of the full amount transmission in the related art, the redundant transmission of unchanged data is eliminated, and the congestion problem is alleviated; and the replication engine performs incremental update after receiving the changed parameter items through the second tensor access register, and generates a control signal to drive data transfer quickly in combination with a hardware instruction decoder, so that the asynchronous operation of the instruction scheduler and the replication engine can be realized through the double register architecture, and the instruction throughput and the instruction processing efficiency are effectively improved.

[0038] Other features and advantages of the present disclosure will be set forth in the following description, and in part will become apparent from the description, or will be learned by practice of the present disclosure. The objects and other advantages of the present disclosure will be realized and achieved by the structures particularly pointed out in the specification, claims and drawings. BRIEF DESCRIPTION OF DRAWINGS

[0039] The accompanying drawings are included to provide a further understanding of the technical solutions of the present disclosure, and constitute a part of the specification, and are used to explain the technical solutions of the present disclosure together with the embodiments of the present disclosure, and do not constitute a limitation on the technical solutions of the present disclosure.

[0040] Figure 1 is a system architecture diagram of the data processor provided by the embodiments of the present disclosure;

[0041] Figure 2 is a flowchart of detection and writing of changed parameter items provided by the embodiments of the present disclosure;

[0042] Figure 3is a process schematic diagram of the incremental mask addition provided by the embodiment of the present disclosure;

[0043] Figure 4 is a process schematic diagram of the parameter item synchronization provided by the embodiment of the present disclosure;

[0044] Figure 5 is an effect schematic diagram of the data writing of the multiple data carrying processes provided by the embodiment of the present disclosure;

[0045] Figure 6 is an effect schematic diagram of the parameter item group division provided by the embodiment of the present disclosure;

[0046] Figure 7 is a process schematic diagram of the data transmission of the parameter item group provided by the embodiment of the present disclosure;

[0047] Figure 8 is an effect schematic diagram of the data writing of the multiple data carrying processes provided by another embodiment of the present disclosure;

[0048] Figure 9 is a specific schematic diagram of the data processing process provided by the embodiment of the present disclosure;

[0049] Figure 10 is an optional process schematic diagram of the data processing method provided by the embodiment of the present disclosure;

[0050] Figure 11 is an optional structural schematic diagram of the electronic device provided by the embodiment of the present disclosure. DETAILED DESCRIPTION

[0051] In order to make the objectives, technical solutions and advantages of the present disclosure clearer, the present disclosure will be further described in detail below in combination with the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present disclosure, and are not used to limit the present disclosure.

[0052] In the embodiment of the present disclosure, the term "module" or "unit" refers to a computer program or a part of a computer program with a predetermined function, and works together with other related parts to achieve a predetermined target, and can be implemented entirely or partially by using software, hardware (such as a processing circuit or a memory) or a combination thereof. Similarly, one processor (or multiple processors or memories) can be used to implement one or more modules or units. In addition, each module or unit can be a part of an overall module or unit that includes the functions of the module or unit.

[0053] In order to facilitate understanding of the technical solutions provided by the embodiments of the present disclosure, some key terms used by the embodiments of the present disclosure are explained first:

[0054] Graphics Processing Unit (GPU): A microprocessor designed specifically for handling graphics and image computations; GPUs were originally designed to accelerate the rendering of 2D and 3D graphics, improving the performance of games and professional graphics software. With thousands of cores, GPUs can handle large amounts of data simultaneously, making them ideal for parallel computing tasks. As technology has advanced, GPUs are no longer limited to graphics processing; they are now used for a variety of general-purpose computing tasks. GPUs play an important role in deep learning, machine learning, and artificial intelligence, as they can quickly process large amounts of data, speeding up the training and inference of neural networks. In scientific computing and data analysis, GPUs are used to accelerate complex numerical simulations and data analysis tasks. In cloud computing and data centers, GPUs are used to provide high-performance computing resources, supporting various compute-intensive applications. In professional applications such as video editing, 3D modeling, scientific visualization, and more, GPUs can provide real-time high-performance rendering.

[0055] Copy Engine (CE): A functional module in processor architecture responsible for data transfer across the storage hierarchy, typically located between on-chip memory and external storage devices (such as external storage devices), through data read-write operations, it realizes data transfer between different storage components, specifically, it moves specified tensor data from one memory region to the target memory. As a key node in the data transmission link, the copy engine receives transmission instructions from the upper-level scheduler and locates the position of the data to be transmitted by analyzing the meta-information (such as target address, source address, data size, dimension coordinates, etc.) carried in the instructions, and then executes the actual read-write operation.

[0056] Kernel: A core computing task unit in parallel computing architecture (such as GPU, dedicated accelerator) that is decomposed into a large number of parallel threads, each kernel can perform a type of parallelizable operation (such as tensor transfer, matrix operation), the execution of the kernel depends on the instruction scheduler to map data to computing cores, each thread independently executes the same code but processes different data, achieving parallel acceleration of large-scale data, for example, in the tensor replication scenario, the kernel can be responsible for generating replication instructions or configuring registers, improving task throughput through parallelization.

[0057] Instruction Scheduler (IS): A control kernel module in a processor or a dedicated computing unit responsible for managing the dynamic execution order of instructions and resource allocation. It can extract instructions to be executed from the core, analyze data dependencies (such as a certain instruction waiting for the results of a previous instruction) or resource conflicts (such as contention for shared functional units), and determine the instruction emission order based on optimization strategies (such as out-of-order execution, priority scheduling). For example, in a system with a replication engine, the instruction scheduler can coordinate the synchronization of data configuration instructions (such as updating data in registers) with target instructions to ensure that the necessary meta-information is ready for the replication engine to execute, avoiding execution blocking due to delayed data synchronization.

[0058] First In First Out Queue (FIFO): A linear data structure that follows the "first in, first out" principle, used to buffer data transmission between asynchronous modules. It is usually implemented using arrays or linked lists, with a head pointer (pointing to the data to be read) and a tail pointer (pointing to the position to be written) to manage data flow.

[0059] With the increasing demand for data transfer efficiency in the fields of artificial intelligence and high-performance computing, the performance of the replication engine, as the core hardware for tensor cross-memory transfer, directly affects the system's computing power. In current processor architectures, the instruction scheduler needs to send all the data of the tensor access register to the replication engine, resulting in redundant transmission. Full transmission not only occupies high-bandwidth resources, but also causes the instruction decoder of the replication engine to repeatedly analyze repeated data, causing the instruction processing pipeline to stall. Moreover, due to the limited efficiency of the replication engine in parsing instructions, it is difficult to handle high-concurrency data transfer requests, limiting the instruction throughput of the replication engine.

[0060] For example, in the context of deep neural network training, hundreds of sub-tensor transfer operations need to be performed continuously when processing inter-layer feature map transmission. Each sub-tensor description contains 5-dimensional coordinate parameters and 32-bit address data. The instruction scheduler needs to write all sub-tensor description information into the queue structure each time it responds to a data distribution instruction, resulting in a large amount of redundant data accumulated in the queue. The instruction decoder needs to analyze each complete data set written into the queue, causing the queue's enqueue rate and instruction decoding throughput to be unbalanced, leading to queue congestion and preventing the completion of data transfer operations within the predetermined period, thereby reducing overall performance.

[0061] Based on this, the data processor, the data processing method, the device and the medium are provided. The data processor comprises an instruction scheduler and a copy engine. A hardware-implemented double tensor access register architecture is introduced in the instruction scheduler and the copy engine. A first tensor access register in the instruction scheduler stores sub-tensor description information transmitted from outside in real time. By dynamically detecting and identifying changed parameter items (such as address, size or coordinate, etc.) in the sub-tensor description information, only these changed parameter items are transmitted to a first queue structure of the copy engine. The changed parameter item granularity transmission is used to replace the full amount transmission in the related art, so as to eliminate the redundant transmission of unchanged data and relieve the congestion problem. The copy engine performs incremental updating after receiving the changed parameter items through a second tensor access register, and generates a control signal to drive data transfer quickly in combination with a hardware instruction decoder. Therefore, the asynchronous operation of the instruction scheduler and the copy engine can be realized through the double register architecture, and the instruction throughput and the instruction processing efficiency are effectively improved.

[0062] In a first aspect, referring to Figure 1 , Figure 1 is a system architecture diagram of the data processor 100 provided by the embodiments of the present disclosure. The data processor 100 comprises a kernel 200, an instruction scheduler 110 and a copy engine 120. The kernel 200 can be a program or a function written and running on a parallel computing device. The kernel 200 describes a computing process that needs to be parallelized through code logic. A compiler will translate these logics into an instruction sequence that can be recognized by the device, i.e., kernel 200 instructions. The instruction scheduler 110 is a hardware control module, which is responsible for receiving these instructions and dynamically scheduling the execution order of the instructions according to the device resource state (such as the idle condition of the computing core, the memory access conflict), and allocating to the corresponding execution unit.

[0063] When the instruction scheduler 110 receives the kernel 200 instructions related to the copy engine 120, these instructions will be allocated to the copy engine 120 for execution. Specifically, in the instruction stream sent by the kernel 200, there are usually three types of instructions related to the copy engine 120: data configuration instructions, data distribution instructions and data transfer instructions. The data configuration instructions are used to guide the instruction scheduler 110 to save the meta-information of the sub-tensor in the current instruction, i.e., the sub-tensor description information. The data distribution instructions are used to instruct the instruction scheduler 110 to send the sub-tensor description information to the copy engine 120. The data transfer instructions are used to guide the copy engine 120 to perform data transfer for the sub-tensor description information. In response to the data configuration instructions, the instruction scheduler 110 will write the sub-tensor description information carried in the instructions into the corresponding components of the first tensor access register 111. The first tensor access register 111 is a local cache of the instruction scheduler 110, which is used to temporarily store the latest sub-tensor description information required by the current kernel 200 task, realizing the fast reception and temporary storage of instructions.

[0064] In this context, a subtensor refers to a local data segment that is divided from the original large tensor and has independent transmission requirements. It is the main transmission content of the copy operation and is located through the corresponding metadata, namely the subtensor description information. The subtensor is a multi-dimensional structure, and its dimension parameters are inherited from the original large tensor. The subtensor has an independent offset (i.e., coordinates) and length (i.e., size) in each dimension. Therefore, the subtensor description information, as a set of metadata that uniquely identifies the subtensor, can be stored in the form of a set of parameters. The subtensor description information may include the source address of the subtensor (i.e., the starting physical address in the original memory region), the destination address (i.e., the starting physical address in the target memory region to which it needs to be transmitted), the multi-dimensional subtensor coordinates (i.e., the offsets in each dimension), and the multi-dimensional size (i.e., the data length in each dimension). Thus, through the subtensor description information, the copy engine 120 can uniquely locate the subtensor segment that needs to be copied in memory and move it to the specified location. Moreover, the instruction scheduler 110 can dynamically configure the subtensor description information by filtering the changing parameters in the subtensor description information, thereby reducing redundant transmission.

[0065] like Figure 1 As shown, the instruction scheduler 110 includes a first tensor access register 111, which is a hardware register group integrated within the instruction scheduler 110. It is used to temporarily store sub-tensor description information, i.e., sub-tensor element information, such as dimension, size, source / target address, etc., sent by the kernel 200 and related to the copy engine 120. In general, the first tensor access register 111 can be understood as a local cache of the instruction scheduler 110. The first tensor access register 111 can respond to copy execution instructions sent by the kernel 200 and cooperate in execution. For example, when the instruction scheduler 110 receives a copy execution instruction from the kernel 200... When the sent "data configuration instructions", such as setting the destination address of the subtensor or updating the coordinate range, carry subtensor description information, the instruction scheduler 110 will extract the corresponding subtensor description information and directly write it into the corresponding component in the first tensor access register 111. Since the first tensor access register 111 is an independent hardware register group set in the instruction scheduler 110, it is only responsible for temporarily storing and managing the instruction data received by the instruction scheduler 110. It does not need to wait for the response status of the copy engine 120, that is, it does not need to communicate with the copy engine 120 every time configuration is performed, thereby reducing cross-module transmission latency and improving instruction throughput.

[0066] Notably, the first tensor access register 111 includes a history buffer, which can cache the data written last, i.e., the sub-descriptor information written in the first tensor access register 111 in response to the last "data configuration instruction" sent by the kernel 200, so that the first tensor access register 111 can cooperate with the instruction scheduler 110 to execute the "data distribution instruction" sent by the kernel 200, provide historical cache data and the latest data to perform comparison detection, so as to determine the changed parameter item. Specifically, in actual application, the dynamic detection of the changed parameter item of the sub-tensor descriptor information refers to identifying the part of the sub-tensor descriptor information stored in the first tensor access register 111 that has changed. The detection can be performed in a way of calculating data checksum, for example, generating a cyclic redundancy check code for the sub-tensor descriptor information, and comparing the new and old checksum codes to determine the changed area, i.e., the changed parameter item. Alternatively, the changed parameter item can be identified by tracking the modification history of the component parameter item. The dynamic detection of the changed parameter item of the sub-tensor descriptor information is to realize transmission of only changed data to reduce redundant transmission amount.

[0067] As shown in Figure 1 The copy engine 120 includes a first queue structure 122, a second tensor access register 121, and an instruction decoder 123. The first queue structure 122 is a special hardware queue structure integrated in the copy engine 120, which is a first-in-first-out queue structure following the first-in-first-out principle, and is used to buffer the data and instructions sent by the instruction scheduler 110. The first queue structure 122 serves as a "data pipeline" between the copy engine 120 and the instruction scheduler 110, and can receive the data entries and instruction entries continuously written by the instruction scheduler 110 in a single cycle. The data entries are the component parameter items or changed parameter items of the sub-tensor descriptor information, and the instruction entries are copy execution instructions, such as data transfer instructions. The copy engine 120 can read the entries from the first queue structure 122 according to its own processing sequence without waiting for the completion of the previous copy operation, so as to realize parallel work of the copy engine 120 and the instruction scheduler 110 and avoid blocking of the instruction scheduler 110 due to the execution delay of the copy engine 120. Notably, since the instruction scheduler 110 only transmits a small amount of changed parameter items, the first queue structure 122 can adopt a low-cost structure with narrow width but large depth, which can accommodate multiple rounds of data writing and instruction sending by the instruction scheduler 110. Even if the copy engine 120 cannot process new entries temporarily due to the transfer of large tensor data, the instruction scheduler 110 can still continuously fill the first queue structure 122, so as to avoid loss of instructions or pipeline stall due to full buffer, thereby realizing high instruction throughput.

[0068] The second tensor access register 121 is a hardware register group integrated inside the copy engine 120, used to store the sub-tensor description information required for performing the copy operation. For example, the copy engine 120 receives the sub-tensor description information required for the copy operation from the first queue structure 122, and the copy engine 120 can write this part of data to the corresponding position of the second tensor access register 121 to update the meta-information state of the copy engine 120 locally. At this time, the data of the second tensor access register 121 is updated incrementally, that is, only the corresponding changed part in the register is modified. For example, the update is achieved by directly writing the changed data block to the specified address, avoiding full rewriting operation, so that the copy engine 120 can directly read the complete updated sub-tensor description information from the second tensor access register 121 when executing the copy execution instruction, locate the source / destination memory area and perform the actual data transfer. It should be noted that the second tensor access register 121 only maintains the data required for the copy operation to be executed, and is decoupled from the first tensor access register 111 in the instruction scheduler 110, realizing stable and low-delay copy operation.

[0069] It should be noted that the first tensor access register 111 and the second tensor access register 121 are both composed of physical circuits, which can be understood as dedicated hardware storage units, and can be implemented by static random access memory or register file, for example, using an on-chip SRAM array or a register group composed of a chain of flip-flops. Due to the characteristics of the hardware register group, the access delay is much lower than that of the memory, which can meet the read / write requirements of the meta-information between the copy engine 120 and the instruction scheduler 110, and meet the high throughput requirement. Moreover, the first tensor access register 111 and the second tensor access register 121 are connected through the first queue structure 122, the instruction scheduler 110 independently receives the kernel 200 instructions and updates the data stored in the first tensor access register 111, and the copy engine 120 also independently reads the data from the second tensor access register 121 to perform the copy, without the need for synchronization and waiting. Combined with the buffering function of the first queue structure 122, the copy engine 120 and the instruction scheduler 110 are asynchronously decoupled, achieving high-speed and low-delay interaction effect, improving the instruction throughput of the copy engine 120 and the overall efficiency of the system.

[0070] The instruction decoder 123 is a control module implemented by a hardware logic circuit in the replication engine 120, responsible for parsing the data and instructions read from the first queue structure 122, and converting the data and instructions into control signals executable by the replication engine 120. For example, by pattern recognition and field extraction, the specific entry types such as data entries and instruction entries can be identified, and different control signals can be generated according to different entry types to enable the replication engine 120 to perform different operation processes. Since the instruction decoder 123 is implemented by a hardware logic circuit, it has lower power consumption than software parsing (such as microcontroller executing parsing instructions), and reduces instruction execution branch prediction errors and other problems, ensuring the reliability of the replication operation. Therefore, the first tensor access register 111, the second tensor access register 121, and the instruction decoder 123 implemented by hardware cooperate with each other to improve the processing efficiency of the replication engine 120 for the instructions and data sent by the instruction scheduler 110, and to improve the instruction throughput.

[0071] The change parameter item can be a field in the sub-tensor description information dynamically modified according to the instructions sent by the kernel 200, and specifically can be a component parameter item in the sub-tensor description. The component parameter item is a basic parameter unit that constitutes the sub-tensor description information, and includes at least one of a source / destination address, a dimension coordinate, and a dimension size. The change parameter item is a subset of the component parameter item, referring to a metadata field that needs to be updated from an "old value" / "historical value" to a "new value" / "current value" in multiple replication operations, or in other words, the component parameter item that changes is the change parameter item. For example, in the original sub-tensor description information, the "destination address" is 0x2000, and the new kernel 200 instruction indicates that the data is moved to address 0x3000. At this time, the "destination address" of the sub-tensor description information changes from 0x2000 to 0x3000, i.e., the "destination address" becomes a "change parameter item". Since other component parameter items in the sub-tensor description information such as "dimension coordinate" and "dimension size" do not change, they do not need to be change parameter items.

[0072] During operation, after the instruction scheduler 110 writes the new sub-tensor description information obtained from the kernel 200 into the first tensor access register 111, it can dynamically detect the change parameter item of the sub-tensor description information. For example, the instruction scheduler 110 can compare the historical value with the current value to identify the change part, and write the change part, i.e., the change parameter item, into the first queue structure 122. The replication engine 120 then obtains the change parameter item from the first queue structure 122, and performs incremental update on the sub-tensor description in the second tensor access register 121 using these change parameter items, thereby avoiding full data retransmission and only transmitting necessary update content, ensuring that the instruction decoder 123 can generate accurate control signals based on the updated sub-tensor description information, and achieving efficient data movement.

[0073] In a specific example, the first tensor access register 111 in the instruction scheduler 110 can be a register group composed of a trigger array, used to temporarily store the sub-tensor description information parsed by the instruction scheduler 110 receiving the kernel 200 instructions; the second tensor access register 121 of the copy engine 120 is also composed of a register group built by a physical circuit, used to store the currently effective sub-tensor description information. Referring to Figure 2 , Figure 2 is a flowchart of the detection and writing of the changed parameter item provided by the embodiment of the present disclosure, assuming that the data stored in the first tensor access register 111 is synchronized with the data stored in the second tensor access register 121, the currently effective sub-tensor description information includes the source address 0x1000, the destination address 0x2000, the dimension coordinates (4, 4, 4, 8, 8), and the size (1024, 1024, 1024, 512, 512), when the kernel 200 issues a new instruction, i.e., a new sub-tensor description information, the new sub-tensor description information source address 0x1000, destination address 0x3000, dimension coordinates (4, 4, 4, 8, 8), and size (1024, 1024, 1024, 512, 512), i.e., by comparing the historical field values in the first tensor access register 111, it is found that the destination address is updated from 0x2000 to 0x3000, and the remaining fields remain unchanged, wherein the instruction scheduler 110 can write the new sub-tensor description information to the first tensor access register 111, and write the "destination address" field "0x3000" as a changed parameter item to the first queue structure 122, or the instruction scheduler 110 directly writes the changed parameter item "destination address: 0x3000" to the first tensor access register 111; therefore, the instruction scheduler responds to the new instruction issued by the kernel 200, and writes the changed parameter item "destination address: 0x3000" to the first queue structure 122, for the copy engine 120 to read the changed parameter item from the first queue structure 122. When the copy engine 120 reads the changed parameter item from the first queue structure 122, it can write these changed parameter items to the corresponding field positions in the second tensor access register 121, to complete the partial update of the sub-tensor description information, i.e., update the destination address in the second tensor access register 121 from 0x2000 to 0x3000, and keep the remaining fields unchanged, thereby realizing the synchronization of the sub-tensor description information. Since only the changed parameter items are transmitted and processed, the transmission amount of the changed parameter items is much smaller than that of the complete sub-tensor description message, the load of the first queue structure 122 is reduced, thereby more kernel 200 instructions can be processed in parallel, and the overall throughput of the system is improved; at the same time, the incremental update mechanism avoids full rewriting operation, shortens the response time of the copy engine 120, and enables the instruction throughput of the high-concurrency data moving request to be improved.

[0074] In some possible implementation manners, in the process of dynamically detecting the changed parameter item, the instruction fetcher can first write, in response to receiving the externally transmitted first sub-tensor description information, the sub-tensor description information stored in the first tensor description storage as a historical value, and write the received first sub-tensor description information as a current value into the first tensor access register 111, and then perform a comparison operation on the historical value and the current value of the sub-tensor description information to identify the changed parameter item.

[0075] In the process of dynamically detecting the changed parameter item, the instruction fetcher can first write, in response to receiving the externally transmitted first sub-tensor description information, the sub-tensor description information stored in the first tensor description storage as a historical value, and write the received first sub-tensor description information as a current value into the first tensor access register 111, and then perform a comparison operation on the historical value and the current value of the sub-tensor description information to identify the changed parameter item.

[0076] In the process of dynamically detecting the changed parameter item, the instruction fetcher can first write, in response to receiving the externally transmitted first sub-tensor description information, the sub-tensor description information stored in the first tensor description storage as a historical value, and write the received first sub-tensor description information as a current value into the first tensor access register 111, and then perform a comparison operation on the historical value and the current value of the sub-tensor description information to identify the changed parameter item.

[0077] In a specific example, when the instruction scheduler 110 receives the copy execution instruction carrying the first sub-tensor description information transmitted by the core 200 through the data bus, the instruction scheduler 110 can parse the copy execution instruction, extract the first sub-tensor description information, and latch the output data currently stored in the first tensor access register 111 to a special history buffer as a history value; at the same time, the first sub-tensor description information newly received is written into the first tensor access register 111 to overwrite the old data, forming a current value; then, the instruction scheduler 110 can perform a bitwise XOR operation on the history value of the history buffer and the current value currently stored in the first tensor access register 111 through a preset hardware comparison circuit, and the difference signal output is used as an indication flag of the changed parameter item. For example, the hardware comparison circuit can be implemented by using a combination of logic gate arrays, and the comparison unit of each component parameter item can be implemented by using an XOR gate and an AND gate. When the history value and the current value are inconsistent, a high-level signal is output, which can be used as an incremental mask and added to the corresponding component parameter item. Therefore, the data processing flow provided by the present disclosure can identify the parameter item actually changed in the sub-tensor description information, and only write the changed parameter item into the first queue structure 122, thereby avoiding full transmission of the sub-tensor description information, effectively reducing the redundant load and data transfer delay of the first queue structure 122, and improving the data transfer efficiency of the copy engine 120.

[0078] In some possible implementations, the sub-tensor description information includes a plurality of component parameter items. Therefore, in the process of determining the changed parameter item of the sub-tensor description information, the current value and the history value of each component parameter item of the sub-tensor description information can be compared one by one. If the current value and the history value of the component parameter item are not equal, an incremental mask is added to the corresponding component parameter item, and the component parameter item carrying the incremental mask is determined as the changed parameter item.

[0079] In some possible implementations, the sub-tensor description information includes a plurality of component parameter items. Therefore, in the process of determining the changed parameter item of the sub-tensor description information, the current value and the history value of each component parameter item of the sub-tensor description information can be compared one by one. If the current value and the history value of the component parameter item are not equal, an incremental mask is added to the corresponding component parameter item, and the component parameter item carrying the incremental mask is determined as the changed parameter item.

[0080] For example, when the increment mask is 1, it indicates that the corresponding component parameter item is changed, i.e., the kernel 200 modifies a certain component parameter item through the data configuration instruction, such as changing the "destination address" from "0x2000" to "0x3000". At this time, the instruction scheduler 110 sets the increment mask corresponding to the component parameter item to 1, which is equivalent to adding the "need to update" increment mask to the component parameter item. This is for the instruction scheduler 110 to filter only the component parameter items with the increment mask of 1 as the changed parameter items when responding to the data distribution instruction to write data to the first queue structure 122, avoiding the transmission of redundant data that does not need to be updated. For the copy engine 120, when reading the data of the first queue structure 122, only the component parameter items with the increment mask of 1 need to be parsed and the corresponding fields of the second tensor access register 121 are updated, without the need to charge or overwrite the entire register, reducing the data read and write amount. For example, when the increment mask is 0, it indicates that the corresponding component parameter item is not changed. At this time, the instruction scheduler 110 can keep the increment mask of the component parameter item as 0, i.e., add the "no need to update" increment mask. For the instruction scheduler 110, there is no need to write the component parameter item to the first queue structure 122, reducing the data load of the first queue structure 122. For the copy engine 120, there is no need to process the component parameter item with the increment mask of 0, and the historical value of the local corresponding component parameter item can be directly retained.

[0081] It should be noted that the state of the increment mask of the component parameter item dynamically changes with the execution of the data configuration instruction of the kernel 200. Specifically, when the kernel 200 issues a data configuration instruction related to the copy engine 120 and carries new sub-tensor description information (i.e., first sub-tensor description information) in the data configuration instruction, the instruction scheduler 110 will parse the data configuration instruction, extract the new sub-tensor description information, and write the new sub-tensor description information into the first tensor access register 111 in a period, and compare the historical value and the current value of each component parameter item in the written sub-tensor description information. If a certain component parameter item changes, the corresponding increment mask is set to 1, otherwise it remains 0. When the instruction scheduler 110 receives the data distribution instruction issued by the kernel 200, the instruction scheduler 110 can scan all the component parameter items stored in the first tensor access register 111, and only write the component parameter items with the increment mask of 1 as the changed parameter items into the first queue structure 122. Subsequently, the copy engine 120 reads the entry data in the first queue structure 122, extracts the changed parameter items with the increment mask of 1, and updates the corresponding fields of the sub-tensor description information currently stored in the second tensor access register 121 using these changed parameter items, completing the incremental synchronization of the sub-tensor description information. Among them, the copy engine 120 only updates the metadata fields that need to be changed, and retains the corresponding fields of the non-changed parameter items. Therefore, this transmission processing mode can ensure that when only part of the component parameter items changes, the entire sub-tensor description information does not need to be transmitted, thereby avoiding redundant data transmission, optimizing the data processing flow of the copy engine 120, and improving the processing efficiency of the system.

[0082] In a specific example, referring to Figure 3 , Figure 3 is a flow diagram of the increment mask addition provided by the embodiments of the present disclosure. It is assumed that the sub-tensor description information includes 20 component parameter items (i.e., C0 to C19), specifically including a source address C0 item, a destination address C1 item, 5-dimensional offsets (C2 item to C6 item), 5-dimensional sizes (C7 item to C11 item), and the remaining component parameter items (C12 item to C19 item) can include data attribute class parameters such as data format, data precision, and transmission strategy class parameters. After receiving the new sub-tensor description information, the instruction scheduler 110 can compare the historical value and the current value of each component parameter item. For each component parameter item, an independent comparison operation is performed. If the current value and the historical value are different, an increment mask with a mark bit of 1 is added to identify the component parameter item as a changed parameter item. If the current value and the historical value are consistent, an increment mask with a mark bit of 0 is added to indicate that the component parameter item does not need to be transmitted. Specifically, as shown in Figure 3As shown, the current value of the source address C0 item is compared with the historical value, and it is found that the source address C0 item has changed, so an incremental mask with a flag bit of 1 is added to the source address C0 item; then, the current value of the destination address C1 item is compared with the historical value, and it is found that the destination address C1 item has changed, so an incremental mask with a flag bit of 1 is also added to the destination address C1 item; subsequently, the current values of the 5-dimensional offset C2 item to the C6 item are compared with the historical values one by one, and it is found that the offset C3 item, the C5 item and the C6 item have changed, so the offset C3 item, the C5 item and the C6 item are respectively added with an incremental mask with a flag bit of 1, and the offset C2 item and the C4 item are respectively added with an incremental mask with a flag bit of 0; the current values of the 5-dimensional size C7 item to the C11 item are compared with the historical values one by one, and it is found that the size C7 item and the C11 item have changed, so the size C7 item and the C11 item are both added with an incremental mask with a flag bit of 1, and the size C8 item to the C10 item are all added with an incremental mask with a flag bit of 0; then, the current values of the remaining component parameter items C12 item to the C19 item are compared with the historical values one by one, and it is found that the C12 item to the C19 item have not changed, so the C12 item to the C19 item are all added with an incremental mask with a flag bit of 0. The incremental masks of all component parameter items are screened, and the component parameter items with the incremental mask flag bit of 1 are taken as the changed parameter items, that is, the source address C0 item, the destination address C1 item, the dimensional offset C3 item, the C5 item and the C6 item, the dimensional size C7 item and the C11 item are all taken as the changed parameter items, so it can be seen that only a small number of component parameter items need to be updated in the sub-tensor description information containing 20 component parameter items, and these changed parameter items are written into the first queue structure 122 for the replication engine 120 to perform incremental update, which can reduce the resource consumption caused by full transmission and improve the instruction processing efficiency of the replication engine 120.

[0083] In some possible implementations, in the process of writing the changed parameter items into the first queue structure 122, the position information corresponding to the changed parameter items can be synchronously written into the first queue structure 122, so that the replication engine 120 can quickly locate the changed position of the sub-tensor description information by using the position information when analyzing the changed parameter items, thereby reducing additional calculation overhead and delay. Specifically, in response to receiving the target instruction transmitted externally, the position information of the changed parameter items in the sub-tensor description information is determined, and then the changed parameter items, the corresponding position information and the target instruction are written into the first queue structure 122.

[0084] The target instruction can be an instruction about the copy engine 120 issued by the kernel 200, such as a data distribution instruction and a data carrying instruction, and arrival of the target instruction is taken as a trigger signal for writing data into the first queue structure 122. The position information can be index information of the change parameter item in the sub-tensor description information, that is, a specific position number of the change parameter item in a component parameter item set of the sub-tensor description information, and the position information can be taken as a unique identifier of the component parameter item, such as Figure 3 The C0 shown in the figure represents position information of the change parameter item of the "source address", and similarly, the C1 shown in the figure represents position information of the change parameter item of the "destination address". When the change parameter item, the corresponding position information and the target instruction are written into the first queue structure 122, the three can be packaged as associated data units for synchronous transmission, so as to avoid analysis errors caused by decoupling of information. Figure 3

[0085] Specifically, real-time reception of the target instruction can trigger screening of the change parameter item and dynamic generation of the position information, so that the change parameter item and the position information can be bound with the instruction demand, and redundant calculation when there is no carrying request is avoided; meanwhile, the change parameter item, the position information and the target instruction are integrated into a single data packet and written into the first queue structure 122, so that the copy engine 120 can directly use the position information to perform directional incremental update on the sub-tensor description information in the second tensor access register 121 when reading data of the first queue structure 122, without the need to re-compare the entire sub-tensor description information, thereby optimizing data transmission amount and improving data update efficiency.

[0086] In a specific example, refer to Figure 4 , Figure 4 ​is a flowchart of a parameter item synchronization method provided by an embodiment of the present disclosure. The target instruction includes a data distribution instruction and a data transfer instruction. When the instruction scheduler 110 receives the data distribution instruction, the instruction scheduler 110 can filter out the component parameter item with an incremental mask of 1 from the first tensor access register 111, that is, determine the changed parameter item, and determine the position information of the changed parameter item in the sub-tensor description information, and then write the changed parameter item and the corresponding position information into the first queue structure 122. Then, when the data transfer instruction is received, the instruction scheduler 110 can write the data transfer instruction into the first queue structure 122. At this time, the writing position of the data transfer instruction in the first queue structure 122 is located after the writing position of the changed parameter item and the position information in the first queue structure 122. Therefore, when the copy engine 120 reads data from the first queue structure 122, the changed parameter item and the position information can be acquired first, and the sub-tensor description information in the second tensor access register 121 can be updated immediately. On this basis, when the copy engine 120 reads the data transfer instruction, at this time, the data transfer instruction in the first queue structure 122 can indicate that the changed parameter item has been transmitted completely, and the second tensor access register 121 of the copy engine 120 already has complete sub-tensor description information. Therefore, the data transfer operation can be directly responded to the data transfer instruction to generate a response control signal. This sequential writing design can avoid errors caused by missing parameter information in the instruction analysis process, and optimize the instruction processing flow.

[0087] In a specific example, when the instruction scheduler 110 receives the data distribution instruction, the instruction scheduler 110 can write the changed parameter item and the corresponding position information as a first entry into the first queue structure 122, and when the instruction scheduler receives the data transfer instruction, the instruction scheduler 110 can write the data transfer instruction as a second entry into the first queue structure 122. The first entry can be a “metadata update instruction” delivered by the instruction scheduler 110 to the copy engine 120, indicating which metadata fields have been updated and the updated values, and the copy engine 120 can update only the corresponding component parameter item in the local second tensor access register 121 by parsing the first entry. The second entry is an execution trigger instruction sent by the instruction scheduler 110 to the copy engine 120, and the second entry only includes the data transfer instruction sent by the kernel 200, i.e., requiring the copy engine 120 to perform data transfer based on the updated sub-tensor description information. The first entry and the second entry are two different types of data units, which are distinguished by different identification bits. When the copy engine 120 receives the data of the first entry from the first queue structure 122, the copy engine 120 can update the changed parameter item and the corresponding position information in the first entry. When the copy engine 120 receives the data of the second entry, it means that the data of the first entry has been transmitted, and the sub-tensor description information has been updated. The copy engine 120 can perform data transfer based on the data transfer instruction of the second entry. Specifically, when the instruction scheduler 110 receives the data distribution instruction, the instruction scheduler 110 parses the data distribution instruction, triggers scanning of the first tensor access register 111, filters out the changed parameter item with the incremental mask being 1, queries the position information of each changed parameter item corresponding to the sub-tensor description information, and then encapsulates the changed parameter item and the corresponding position information as the first entry and writes the first entry into the first queue structure 122. When the instruction scheduler 110 receives the data transfer instruction, the instruction scheduler 110 confirms that the copy operation needs to be triggered, encapsulates the data transfer instruction as the second entry, and writes the second entry into the first queue structure 122. At this time, the second entry is next to the first entry that has been written in the first queue structure 122. Therefore, when the copy engine 120 reads the entries from the first queue structure 122, the copy engine 120 first reads the first entry, parses the changed parameter item and the corresponding position information, updates the component in the second tensor access register 121, and then reads the second entry, determines that the sub-tensor description information has been completely updated, and triggers data transfer. The instruction scheduler 110 can continuously write multiple first entries (such as update destination address, multi-dimensional coordinates, size, etc.) and then write the second entry, without waiting for the copy engine 120 to complete execution. It is worth noting that the copy engine 120 reads the first entry and the second entry in strict accordance with the first-in-first-out characteristic of the first queue structure 122, which can ensure the timing accuracy of metadata update and instruction execution.

[0088] Referring to Figure 5 ,Figure 5 is an effect diagram of data writing of a plurality of data carrying processes provided by the embodiments of the present disclosure. It can be understood that when the data carrying is performed for the first time or the kernel 200 switches to a brand-new task without parameter overlap with the previous task, all component parameter items (such as source / destination address, multi-dimensional coordinate, size, etc.) of the sub-tensor description information need to be transmitted to the copy engine 120, that is, all component parameter items of the sub-tensor description information are changed parameter items, such as Figure 5 As shown in the figure, when the instruction scheduler 110 performs the data carrying task for the first time (i.e., the first data carrying task), all component parameter items C0 to C19 of the sub-tensor description information are changed parameter items, and the component parameter items C0 to C19 are sequentially written into the first queue structure 122, and then the first data carrying instruction Copy0 is written into the first queue structure 122. Then, the instruction scheduler 110 receives a new data carrying task (i.e., the second data carrying task), at this time, the changed parameter items of the sub-tensor description information are dynamically detected, and it is determined that the changed parameter items are C0, C4, C8, C9, C13, C14, C15 and C16, so the changed parameter items C0, C4, C8, C9, C13, C14, C15 and C16 of the second data carrying task are written into the first queue structure 122. It can be seen that the changed parameter items of the second data carrying task are immediately after the first data carrying instruction Copy0 of the first data carrying task, and at the same time, after the writing of the changed parameter items of the second data carrying task is completed, the second data carrying instruction Copy1 of the second data carrying task is also written into the first queue structure 122. Then, the instruction scheduler 110 receives a new data carrying task again (i.e., the third data carrying task), at this time, the changed parameter items of the sub-tensor description information are dynamically detected, and compared with the sub-tensor description information of the second data carrying task, the changed component parameter items are C2, C5, C7 and C9, so in the third data carrying task, only the changed parameter items C2, C5, C7 and C9 need to be written into the first queue structure 122, and the third data carrying instruction Copy2 is written into the first queue structure 122.

[0089] In some possible implementation ways, in the process of writing the component parameter items into the first queue structure 122, the parameter item groups composed of multiple component parameter items can be transmitted and written as a unit, and specifically, the current value and the historical value of each component parameter item in the parameter item group are compared one by one, and when the current value of any component parameter item is not equal to the historical value, an incremental mask is added to the parameter item group, and then all component parameter items in the parameter item group carrying the incremental mask are determined as changed parameter items.

[0090] The parameter item group can refer to a structure of organizing multiple component parameter items in the sub-tensor description information as a logical unit. Specifically, a fixed number of component parameter items can be combined to achieve this. The parameter item group can be adapted to the storage characteristics of the first queue structure 122, reducing the fragmentation problem caused by the transmission of a single changed parameter item. Comparing the current value and the historical value of each component parameter item in the parameter item group means comparing the current value and the historical value of each component parameter item in the parameter item group independently. The specific comparison process can be the same as the comparison process described above, and will not be described here. However, it is worth noting that the mask increment at this time refers to the marker information used to identify the change of the entire parameter item group, which can also be identified by binary bits "0 / 1".

[0091] Specifically, by organizing multiple component parameter items of the sub-tensor description information into a parameter item group, when any component parameter item in the parameter item group is detected to change during the comparison process, an increment mask is added to the entire parameter item group, thereby determining the entire parameter item group as a changed parameter item. This ensures that the changed data can be transmitted in the form of a complete parameter item group, which is adapted to the physical storage width of the first queue structure 122, reduces the space waste caused by the transmission of a single changed parameter item, and also reduces the number of entries of the first queue structure 122, improving the data transmission efficiency.

[0092] Referring to Figure 6 , Figure 6is an effect schematic diagram of parameter item group division provided by the embodiments of the present disclosure. The sub-tensor description information can include 20 component parameter items, namely C0 to C19, which can be divided into 5 parameter item groups, namely Segement0 to Segement4. Each parameter item group has a corresponding mask marker. When the instruction scheduler 110 receives new sub-tensor description information, the component parameter items in each parameter item group are compared. If it is found that the second component parameter item C1 in the first parameter item group Segement0 changes, an incremental mask with a marker bit of 1 is added to the entire first parameter item group Segement0, and all component parameter items C0 to C3 in the group are written as changed parameter items to the first queue structure 122. If all component parameter items C4 to C19 in other parameter item groups Segement1 to Segement4 do not change, the marker bits of the incremental masks of all component parameter items C4 to C19 in the parameter item groups Segement1 to Segement4 are set to 0. Therefore, when the changed parameter items are written to the first queue structure 122, all component parameter items C0 to C3 in the first parameter item group Segement0 need to be written to the first queue structure 122, so that the writing of the changed parameter items matches the storage units of the first queue structure 122, which can completely fill a queue slot, effectively solving the problem of data fragmentation caused by the change of a single component parameter item, improving the space utilization of the first queue structure 122, reducing the analysis burden of the instruction decoder 123, and thus improving the processing efficiency of the copy engine 120.

[0093] In some possible implementations, during the process of writing the entire group of changed parameter items to the first queue structure 122, the position information corresponding to the entire group of changed parameter items can also be written to the first queue structure 122. Specifically, in response to receiving a target instruction transmitted from outside, a parameter item group containing changed parameter items is taken as a changed group, the position information of the changed group in the sub-tensor description information is determined, and all component parameter items in the changed group, the corresponding position information, and the target instruction are written to the first queue structure 122.

[0094] Among them, the changed group can be a parameter item group instance carrying a marker bit of 1, used to indicate the specific data range that needs to be updated, and the position information of the changed group refers to the specific number of the changed group in the parameter item group set in the sub-tensor description information. The position information can be used as a unique identifier of the parameter item group to realize positioning of the parameter item group, such as Figure 6The "Segment0" represents the position information of the component parameter items "C0-C3" in the "first parameter item group", the "Segment1" represents the position information of the component parameter items "C4-C7" in the "second parameter item group", and so on. When all the component parameter items in the change group, the corresponding position information, and the target instruction are written into the first queue structure 122, the three can also be packaged as an associated data unit for synchronous transmission, avoiding parsing errors caused by decoupling of information.

[0095] The physical storage width of the first queue structure 122 can be the maximum data bit width that can be accommodated by a single storage operation of the hardware queue, which is determined by the bit number of the register array or the bus width. The total data length of the parameter item group matches the physical storage width of the first queue structure 122, so that the change group can completely fill a single storage unit of the first queue structure 122, and the copy engine 120 can obtain complete incremental update information and instruction context at a time. For example, Figure 7 Figure 7 is a flowchart of data transmission of a parameter item group provided by an embodiment of the disclosure. The sub-tensor description information includes 20 component parameter items C0-C19. Each parameter item group is composed of 4 component parameter items. The bit width of each component parameter item group is 16 bits. The total data length of each parameter item group is completely consistent with the 64-bit physical storage width of the first queue structure 122. When the instruction scheduler 110 receives the data distribution instruction transmitted externally, the parameter item group containing the change parameter item is packaged as a change group, and the position information of the change group is determined. Subsequently, all the component parameter items in the change group and the corresponding position information are written into the first queue structure 122. When the data carrying instruction is received, the data carrying instruction is directly written into the tail of the change group in the first queue structure 122. Therefore, after the copy engine 120 reads the change group and the corresponding position information from the first queue structure 122, the component parameter item groups in the change group can be written into the corresponding area of the second tensor access register 121 according to the position information, completing the incremental update of the sub-tensor description information. Thus, the number of segmented writing or padding operations caused by the mismatch between the change parameter item and the physical storage width of the queue structure can be reduced, and the instruction throughput of the instruction scheduler 110 and the copy engine 120 to the high-concurrency data carrying request can be improved.

[0096] Referring to Figure 8 , Figure 8 ​is an effect diagram of data writing of the multiple data carrying process provided by another embodiment of the present disclosure. It can be understood that when the data carrying is performed for the first time or the kernel 200 switches to a brand-new task without parameter overlap with the previous task, all component parameter items (such as source / destination address, multi-dimensional coordinate, size, etc.) of the sub-tensor description information need to be transmitted to the copy engine 120, that is, all component parameter items of the sub-tensor description information are changed parameter items, such as Figure 8 As shown in the figure, when the instruction scheduler 110 performs the data carrying task for the first time (i.e., the first data carrying task), all component parameter items C0 to C19 of the sub-tensor description information are changed parameter items, that is, the parameter item groups Segement0 to Segement4 are all written into the first queue structure 122, and then the first data carrying instruction Copy0 is written into the first queue structure 122. Then, the instruction scheduler 110 receives a new data carrying task (i.e., the second data carrying task), at this time, the changed parameter items of the sub-tensor description information are dynamically detected, and it is determined that the changed parameter items are located in the second parameter item group Segement1, that is, the second parameter item group Segement1 is a changed group, therefore, the changed group Segement1 of the second data carrying task is written into the first queue structure 122. As can be seen, the changed parameter group of the second data carrying task is immediately adjacent to the first data carrying instruction Copy0 of the first data carrying task, and at the same time, after the changed parameter items of the second data carrying task are written, the second data carrying instruction Copy1 of the second data carrying task is also written into the first queue structure 122. Then, the instruction scheduler 110 receives a new data carrying task again (i.e., the third data carrying task), at this time, the changed parameter items of the sub-tensor description information are dynamically detected, and compared with the sub-tensor description information of the second data carrying task, the changed component parameter items are located in the second parameter item group Segement1 and the third parameter item group Segement2, that is, the second parameter item group Segement1 and the third parameter item group Segement2 are changed groups, therefore, in the third data carrying task, the second parameter item group Segement1 and the third parameter item group Segement2 are written into the first queue structure 122, and the third data carrying instruction Copy2 is written into the first queue structure 122.

[0097] In some possible implementation manners, the copy engine 120 is configured to incrementally update the sub-tensor description information based on the changed parameter items, specifically, the changed parameter items are acquired from the first queue structure 122, and the changed parameter items are written into the second tensor access register 121 to incrementally update the sub-tensor description information stored in the second tensor access register 121; then, in response to the target instruction received from the first queue structure 122, data carrying is performed according to the sub-tensor description information currently stored in the second tensor access register 121.

[0098] Wherein, the copy engine 120 actively reads the stored entry information in the first queue structure 122 in the order of "first-in first-out", and reads the first entry preferentially (since the second entry needs to wait for the first entry update transmission to complete), when the changed parameter item is parsed from the read entry information, the sub-tensor description information stored in the second tensor access register 121 is updated and overwritten by using the changed parameter item, and other unmarked changed component parameter items of the sub-tensor description information stored in the second tensor access register 121 are retained. It is worth noting that the incremental update can be realized by using a mask-controlled write circuit or address mapping logic, so as to maintain data consistency while reducing the read-write overhead of the register. After the first entry processing is completed, that is, the target instruction, that is, the data transfer instruction is read, all the sub-tensor description information is read from the second tensor access register 121, according to the complete sub-tensor description information, the copy engine 120 reads the sub-tensor data corresponding to the dimension coordinates and the dimension size from the source address, and writes it to the target address, completing the data transfer.

[0099] In some possible implementations, the instruction decoder 123 can generate a transfer control signal to drive the copy engine 120 to perform data transfer. Specifically, the instruction decoder 123 is configured to, in response to the data transfer instruction received from the first queue structure 122, obtain the currently stored sub-tensor description information from the second tensor access register 121; and then generate a transfer control signal based on the obtained sub-tensor description information to enable the copy engine 120 to perform data transfer on the sub-tensor description information.

[0100] Wherein, the instruction decoder 123 can be a hardware circuit module for parsing instructions and generating control signals, which can be realized by using an application-specific integrated circuit or a programmable logic device. The instruction decoder 123 can generate control signals by using the sub-tensor description information stored in the second tensor access register 121 in real time. Specifically, when the instruction decoder 123 receives a data transfer instruction, it can obtain the currently stored sub-tensor description information from the second tensor access register 121, and generate a transfer control signal based on the updated sub-tensor description information, so as to ensure that the instruction decoder 123 always obtains a data source from an incrementally updated register, improve the reliability of the generated control signal, and further drive the copy engine 120 to perform more accurate data transfer operations.

[0101] In some possible implementations, when the copy engine 120 performs incremental updating on the sub-tensor description information of the second tensor access register 121, the data transmitted in the first queue structure 122 contains the changed parameter item and corresponding position information, so that when the changed parameter item and the position information are received from the first queue structure 122, the sub-tensor description information stored in the second tensor access register 121 can be updated incrementally according to the position information.

[0102] Specifically, the first entry transmitted in the first queue structure 122 can contain the changed parameter item and corresponding position information. The position information can be used to determine the target region to be updated in the second tensor access register 121, or in other words, the target storage position of the changed parameter item in the second tensor access register 121. Then, a data write operation is performed on the region, so that only the part of the sub-tensor description information that actually changes is updated, and repeated writing of the unchanged parameter item is avoided, thereby ensuring the accuracy of data updating and transmission efficiency.

[0103] In a specific example, the sub-tensor description information can include component parameter items such as source / destination address, dimension coordinate and dimension size. When the dimension size parameter changes, the position information indicates the relative offset position of the parameter in the second tensor access register 121. The copy engine 120 writes the changed dimension size value to the target region corresponding to the offset position through the address decoding circuit, thereby completing the local correction of the sub-tensor description information.

[0104] Referring to Figure 9 , Figure 9 is a specific schematic diagram of a data processing process provided by the embodiments of the present disclosure, such as Figure 9As shown, the data processing method can be applied in a data processor 100, which can include three main modules, i.e., a global memory, a copy engine 120 and an on-chip memory, as well as a kernel 200 and an instruction scheduler 110. The global memory controller and the on-chip memory controller are respectively connected to the external storage (i.e., the global memory) and the on-chip memory, and are responsible for the execution of memory read / write instructions, and the merging buffer and the splitting buffer are used to optimize the data transmission efficiency, for example, by arranging (e.g., splitting or merging) the data blocks to be transmitted so as to facilitate the reading of the global memory and the on-chip memory. The GMEM address generator, i.e., the global memory address generator, is used to generate the physical address for accessing the global memory, and the SRAM address generator, i.e., the on-chip memory address generator, is used to generate the physical address for accessing the on-chip memory, and the two address generators are used to determine the "read / write address" of the data. First, the kernel 200 issues the target instructions (including data configuration instructions, data distribution instructions and data transfer instructions) related to the copy engine 120 to the instruction scheduler 110, writes the sub-tensor description information carried by the target instructions into the first tensor access register 111 in the instruction scheduler 110, and then transmits the change parameter items of the sub-tensor description information and the data transfer instructions through the first queue structure 122, and the instruction decoder 123 parses the data transfer instructions transmitted by the first queue structure 122, and converts the data transfer instructions into control signals recognizable by the copy engine 120. The driver writes the metadata (such as dimensions, scales, coordinates, etc., i.e., "tensor description information") of the original tensor into the hardware through the "state machine write data channel", and the "state machine controller" takes over to generate standardized tensor description information for subsequent modules. Then, the iterator is responsible for converting the "control signals" generated by the instruction decoder 123 and the tensor description information generated by the "state machine controller" into "tensor coordinates" and "sub-tensor coordinates", and writing them into the "tensor coordinate queue structure" and the "sub-tensor coordinate queue structure" correspondingly, so as to correspond to the address generator, for example, the GMEM address generator can obtain the "tensor coordinates" from the "tensor coordinate queue structure", and generate the access address of the global memory according to the "tensor coordinates", and then store the access address of the global memory into the "GMEM address queue structure", while the SRAM address generator reads the "sub-tensor coordinates" from the "sub-tensor coordinate queue structure", and generates the access address of the on-chip memory according to the "sub-tensor coordinates", and then writes the access address of the on-chip memory into the "SRAM address queue structure"; then, according to the target instructions, the global memory controller obtains the access address of the global memory from the "GMEM address queue structure", reads the corresponding global memory data, and writes the global memory data into the on-chip memory through the merging buffer, or the on-chip memory controller obtains the access address of the on-chip memory from the "SRAM address queue structure", reads the on-chip memory data, and writes the on-chip memory data back to the global memory through the splitting buffer.

[0105] In a second aspect, the embodiments of the present disclosure provide a data processing method, which can be executed by a data processor, and the data processing method is described with reference to Figure 10 , Figure 10 An optional flowchart of the data processing method provided by the embodiments of the present disclosure is shown in FIG. 10, and the data processing method includes, but is not limited to, the following steps 1001 to 1002.

[0106] Step 1001: Write the externally transmitted sub-tensor description information into the first tensor access register through the instruction scheduler, and dynamically detect the change parameter item of the sub-tensor description information, and write the change parameter item into the first queue structure.

[0107] Step 1002: Receive the change parameter item from the first queue structure through the copy engine, and incrementally update the sub-tensor description information in the second tensor access register based on the change parameter item.

[0108] It can be understood that the instruction scheduler can obtain the metadata of the sub-tensor from the instructions provided by the external module such as the kernel, obtain the sub-tensor description information, and write the complete sub-tensor description information into the special hardware register, i.e., the first tensor access register local to the instruction scheduler. The instruction scheduler writes the sub-tensor description information into the first tensor access register within one cycle each time it receives the externally provided sub-tensor description information, quickly responds to the kernel instructions, reduces instruction blocking, and at the same time, the instruction scheduler can continuously compare the newly input sub-tensor description information with the old sub-tensor description information in the current register during the process of writing the new sub-tensor description information into the first tensor access register, and identify the change parameter item that has been modified. Then, the detected change parameter item can be packaged as a queue element and written into the first queue structure. Therefore, through the local hardware register storage and the temporary storage of the queue structure, the quick saving and hierarchical management of the sub-tensor description information can be achieved, the competition conflict caused by directly modifying the copy engine hardware register can be avoided, and through the dynamic detection of the parameter item, the changes can be sensed in real time, the full update is not needed when the data is transmitted subsequently, and the redundant data transmission is reduced.

[0109] It can be understood that the replication engine can extract the change parameter item to be processed from the output end of the first queue structure, and since only a small number of change parameter items are provided, the replication engine can directly modify only the field corresponding to the change parameter item according to the change parameter item, and the fields corresponding to the remaining component parameter items remain unchanged, that is, the update operation of the replication engine on the second tensor access register is simplified from "full register write" to "target area write", which can reduce the read-write power consumption and delay of the register. For example, in a high-concurrency data transfer scenario such as feature map slice transfer in deep learning training, batch data splitting and merging, and other tasks, the change of the sub-tensor description information often focuses on a small number of parameters (such as dimension coordinates, size), at this time, the incremental update can improve the instruction throughput of the first queue structure by several times, and ensure that the replication engine responds to the high-frequency data request of the kernel in time.

[0110] In some possible implementation manners, in the process of performing dynamic detection, the instruction scheduler can further include the following steps: in response to receiving the first sub-tensor description information transmitted externally, storing the sub-tensor description information stored in the first tensor access register as a historical value, storing the first sub-tensor description information as a current value of the sub-tensor description information, and writing the first sub-tensor description information into the first tensor access register by overwriting; comparing the current value and the historical value of the sub-tensor description information to determine the change parameter item of the sub-tensor description information.

[0111] In some possible implementation manners, in the process of writing the change parameter item, the instruction scheduler can further include the following steps: in response to receiving the target instruction transmitted externally, determining the position information of the change parameter item in the sub-tensor description information; and writing the change parameter item, the corresponding position information, and the target instruction into the first queue structure.

[0112] Specifically, the instruction scheduler can internally integrate a comparator array to compare the sub-tensor description information of the current task with the information of the previous task bit by bit, and quickly mark the changed component parameter item and the position information; at the same time, by caching the component parameter item of the previous task, the overhead of reading from the outside each time is avoided, and the data delay problem is reduced. The data incremental update in the replication engine depends on the association of the position information and the change parameter item, each change group entry in the first queue structure contains position information (such as parameter item group number or component parameter item number), and the replication engine can convert the position information into the physical offset of the second tensor access register through an address decoding circuit, and then write the change parameter item into the corresponding offset position through a mask control circuit, thereby preserving the data integrity of the unchanged area. Therefore, when the data transfer instruction is executed, the complete and accurate sub-tensor description information required by the current task is always stored in the second tensor access register, so that the replication engine can correctly read the sub-tensor data of the corresponding dimension from the source address and write it into the target address, thereby avoiding data errors caused by inconsistent parameters.

[0113] In some possible implementation manners, in the process of performing the dynamic detection, the instruction scheduler can further include the following steps: comparing the current value and the historical value of each component parameter item of the sub-tensor description information one by one; when the current value of the component parameter item is not equal to the historical value, adding an incremental mask to the component parameter item; and determining the component parameter item carrying the incremental mask as a changed parameter item.

[0114] It can be understood that each component parameter item can correspond to a marking bit of an independent incremental mask. When the instruction scheduler detects that a certain component parameter item is changed, the marking bit of the corresponding incremental mask is set to an effective state (for example, logical "1"), and the incremental mask is encapsulated and written into the first queue structure together with the changed parameter item. After the copy engine receives the changed parameter item carrying the incremental mask, the target area that needs to be updated in the second tensor access register can be quickly located through the incremental mask. For example, if the incremental mask bit of the dimension size is "1", the copy engine only performs a write operation on the field storing the dimension size in the register, and the component parameter items such as the source address and the destination address that are not marked by the incremental mask remain unchanged.

[0115] For example, in the feature map slicing task in deep learning training, the dimension coordinates (such as the starting row and the starting column) of the sub-tensor will frequently change with the change of the slicing position, while the total size of the feature map, the source / destination address and other component parameter items remain fixed. At this time, the instruction scheduler only marks the component parameter item of the dimension coordinates through the incremental mask, and the copy engine only needs to update the dimension coordinates field in the second tensor access register after receiving it, and the remaining fields do not need to be modified, so that the data transmission amount in the first queue structure can be reduced from "full parameter items" to "only changed parameter items", and the instruction throughput of the first queue structure is improved.

[0116] The incremental mask can also directly cooperate with the mask control write circuit inside the copy engine, for example, the incremental mask signal can be used as an enable signal of the mask control write circuit. When the marking bit of the incremental mask is valid, the write circuit is turned on to write the changed parameter item into the target area. When the marking bit of the incremental mask is invalid, the write circuit is turned off to avoid misoperation on the unchanged area, thereby ensuring the accuracy of data updating and reducing the power consumption of register read and write.

[0117] In some possible implementation manners, in the process of performing the dynamic detection, the instruction scheduler can further include the following steps: comparing the current value and the historical value of each component parameter item in the parameter item group one by one; when the current value of any component parameter item is not equal to the historical value, adding an incremental mask to the parameter item group; and determining all component parameter items in the parameter item group carrying the incremental mask as changed parameter items.

[0118] It can be understood that the division of the parameter item group can be based on the functional correlation of the component parameter items, for example, the base address, offset address and address step related to the source address are divided into a parameter item group, and the start coordinate, end coordinate and dimension size related to the dimension information are divided into another parameter item group. When any component parameter item in the parameter item group changes, it indicates that the configuration of the function module needs to be adjusted as a whole, for example, the base address in the source address group changes, which means that the starting position of data reading has changed, and at this time, the associated parameters such as offset address and address step also need to be updated synchronously to ensure the correctness of address generation. Therefore, by adding the incremental mask to the parameter item group and taking the whole group of component parameter items as the changed parameter item, the address calculation error caused by missing associated parameter update can be avoided, and the functional integrity of the sub-tensor description information is ensured. At the same time, the group detection method also reduces the comparison times of the instruction scheduler, for example, 10 component parameter items are divided into 2 parameter item groups, and the comparison times are reduced from 10 times to 2 times, which reduces the hardware overhead of the instruction scheduler and improves the efficiency of dynamic detection.

[0119] In some possible implementation ways, in the process of writing the changed parameter item, the instruction scheduler can further include the following steps: in response to receiving the target instruction transmitted externally, taking the parameter item group containing the changed parameter item as a changed group, and determining the position information of the changed group in the sub-tensor description information, wherein the total data length of the parameter item group is equal to the physical storage width of the first queue structure; writing all component parameter items in the changed group, the corresponding position information, and the target instruction into the first queue structure.

[0120] It can be understood that the size of the parameter item group and the component parameter items contained therein can be customized, for example, the size of the parameter item group is adjusted according to the physical storage width of the first queue structure, so that the total data length of each parameter item group matches the storage unit width of the queue structure, avoiding the waste of padding bytes, optimizing the efficiency of change detection and the amount of transmitted data, and at the same time, it can adapt to different hardware architectures and application scenarios, and has wide versatility.

[0121] In some possible implementation ways, in the process of data carrying processing, the copy engine can further include the following steps: obtaining the changed parameter item from the first queue structure, and writing the changed parameter item into the second tensor access register to incrementally update the sub-tensor description information stored in the second tensor access register; in response to the target instruction received from the first queue structure, performing data carrying according to the sub-tensor description information currently stored in the second tensor access register.

[0122] It can be understood that, since the second tensor access register is updated based on the data in the first tensor access register, when the data in the first tensor access register changes, only the changed parameter items can be transmitted, the copy engine extracts only the changed parameter items from the first queue structure, and writes the changed parameter items into the corresponding second tensor access register, so that the incremental update synchronization of the second tensor access register and the first tensor access register can be realized, and the bandwidth waste and time overhead of full rewriting of the register can be avoided. When the copy engine receives a target instruction (such as a data transfer instruction), it indicates that the sub-tensor description information of the current second tensor access register has been updated, and the locally updated sub-tensor description information can be used to respond to the target instruction for data transfer. The target instruction can be used to separate the changed parameter items of different tasks, so that the accuracy of data update can be ensured.

[0123] In some possible implementation manners, in the process of data transfer processing, the copy engine can further include the following steps: acquiring, by the instruction decoder, the currently stored sub-tensor description information from the second tensor access register in response to the target instruction received from the first queue structure; and generating a transfer control signal based on the acquired sub-tensor description information, so that the copy engine performs data transfer on the sub-tensor description information.

[0124] It can be understood that the transfer control signal generated by the instruction decoder can include basic information such as a source address, a destination address, a dimension size, and a dimension coordinate in the sub-tensor description information guiding data transfer. The instruction decoder can also generate a merge / split control signal according to the dimensions and scales in the sub-tensor description information. For example, when processing a task that requires merging multiple sub-tensors into a complete tensor, the instruction decoder can generate a write order control signal (such as row priority writing) of a merge buffer according to the starting coordinates and dimension sizes of the sub-tensors, to ensure that the sub-tensor data is spliced into a complete tensor in the correct spatial order. When processing a task that requires splitting a complete tensor into multiple sub-tensors, the instruction decoder can generate a read offset control signal (such as column priority reading) of a split buffer according to the dimensions and coordinates of the sub-tensors, to split the complete tensor into multiple independent sub-tensor data blocks according to the boundaries of the sub-tensors.

[0125] In some possible implementation manners, in the process of incremental updating of data, the copy engine can further include the following steps: receiving the changed parameter items and the position information from the first queue structure; and updating the sub-tensor description information stored in the second tensor access register using the changed parameter items according to the position information.

[0126] It can be understood that the position information can be an index code or a register offset address corresponding to each component parameter item structure of the sub-tensor description information, for example, the component parameter items of the sub-tensor description information, such as “destination address”, “first dimension coordinate”, “second dimension coordinate”, “first dimension size”, “second dimension size”, and the like, are sequentially assigned unique index values (such as C1 to C4), or correspond to fixed offset addresses (such as 0x00, 0x08, 0x10, 0x18, 0x20, and the like, each parameter item occupies 8 bytes) of the second tensor access register. The address decoding circuit inside the copy engine directly maps the received position information to the physical storage location of the second tensor access register, ensuring low latency of position resolution, and therefore, the use of position information for corresponding modification can ensure the accuracy of the write of the changed parameter items.

[0127] It can be understood that the above data processing method dynamically detects the changed parameter items of the sub-tensor description information through the instruction mobilizer and writes the changed parameter items into the first queue structure, and the copy engine incrementally updates the sub-tensor description information in the second tensor access register based on the changed parameter items, thereby avoiding redundant transmission caused by transmission of all description information, reducing the analysis burden of the copy engine, and improving the data carrying instruction throughput.

[0128] It can be understood that although each step in the above flowcharts is displayed in sequence according to the arrow, these steps are not necessarily executed in the order indicated by the arrow. Unless otherwise specified in this embodiment, the execution of these steps has no strict order limitation, and these steps can be executed in other orders. Moreover, at least part of the steps in the above flowcharts can include multiple steps or multiple stages, which are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily sequential, but can be alternately executed with at least part of other steps or steps or stages in other steps.

[0129] The embodiments of the present disclosure also provide an electronic device, including at least one processor, and a memory connected with the at least one processor in communication; wherein the processor and the memory are connected in communication through a data bus, the memory stores a program, and the program is executed by the at least one processor to enable the at least one processor to implement the method of any one of the above embodiments of the present disclosure when executing the instructions.

[0130] The following will be described in detail Figure 11 The hardware structure of the electronic device will be described in detail. The electronic device includes a processor 1110, a memory 1120, an input / output interface 1130, a communication interface 1140, and a bus 1150.

[0131] The processor 1110 can be implemented by a general-purpose central processing unit (CPU), a microprocessor, an application specific integrated circuit (ASIC), or one or more integrated circuits, and is configured to execute related programs to implement the technical solutions provided by the embodiments of the present disclosure.

[0132] The memory 1120 can be implemented by a read only memory (ROM), a static storage device, a dynamic storage device, or a random access memory (RAM). The memory 1120 can store an operating system and other application programs. When the technical solutions provided by the embodiments of the present disclosure are implemented by software or firmware, the related program codes are stored in the memory 1120 and are called and executed by the processor 1110 to implement the data processing method of the embodiments of the present disclosure.

[0133] The input / output interface 1130 is configured to implement information input and output.

[0134] The communication interface 1140 is configured to implement the communication interaction between the device and other devices. The communication can be realized by a wired manner (for example, a USB, a network cable, etc.) or a wireless manner (for example, a mobile network, WIFI, Bluetooth, etc.).

[0135] The bus 1150 is configured to transmit information between various components (for example, the processor 1110, the memory 1120, the input / output interface 1130, and the communication interface 1140) of the device.

[0136] The processor 1110, the memory 1120, the input / output interface 1130, and the communication interface 1140 are connected to each other through the bus 1150 to realize the communication connection between the device.

[0137] The embodiments of the present disclosure further provide a computer readable storage medium, which is configured to store a computer program. The computer program is configured to execute the data processing method of the above-mentioned embodiments.

[0138] The embodiments of the present disclosure further provide a computer program product, which includes a computer program stored in a computer readable storage medium. A processor of a computer device reads the computer program from the computer readable storage medium, and the processor executes the computer program to make the computer device execute the data processing method.

[0139] The terms "first", "second", "third", "fourth", and the like in the description of the disclosure and the above drawings, if any, are used to distinguish similar objects, and do not necessarily have to be used to describe a particular order or sequence. It should be understood that the data thus used can be interchanged under appropriate circumstances, so that the embodiments of the disclosure described herein can be implemented in an order other than that illustrated or described herein. In addition, the terms "include" and "contain" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device containing a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but can include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0140] It should be understood that in the present disclosure, "at least one" refers to one or more, and "multiple" refers to two or more. "And / or" is used to describe the relationship between the associated objects, which means that there can be three relationships, for example, "A and / or B" can represent three cases: only A exists, only B exists, and A and B exist at the same time, where A and B can be singular or plural. The character " / " generally represents an "or" relationship between the associated objects. "At least one of the following" or similar expressions means any combination of these items, including any combination of single or multiple items. For example, at least one of a, b or c can represent: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, and c can be single or multiple.

[0141] It should be understood that in the description of the embodiments of the present disclosure, the meaning of "multiple" (or "multiple items") is two or more, and greater than, less than, more than, etc. are not included in the number, and above, below, etc. are included in the number.

[0142] In several embodiments provided by the present disclosure, it should be understood that the disclosed system, device and method can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of units is only a logical function division, and actual implementation can have another division manner. For example, multiple units or components can be combined or integrated into another system, or some features can be omitted or not implemented. In addition, the coupling or direct coupling or communication connection between the displayed or discussed objects can be indirect coupling or communication connection through some interfaces, devices or units, which can be electrical, mechanical or other forms.

[0143] The units described as separate components may or may not be physically separate, and the components displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. Part or all of the units can be selected according to actual needs to achieve the purpose of the embodiment scheme.

[0144] In addition, each functional unit in various embodiments of the present disclosure can be integrated into one processing unit, or each unit can exist physically, or two or more units can be integrated into one unit. The integrated unit can be realized in the form of hardware or in the form of a software functional unit.

[0145] It should also be understood that various embodiments provided by the present disclosure can be combined in any manner to achieve different technical effects.

[0146] The above is a specific description of the embodiments of the present disclosure, but the present disclosure is not limited to the above embodiments. Those skilled in the art can make various equivalent modifications or replacements without departing from the spirit of the present disclosure, and these equivalent modifications or replacements are included in the scope defined by the claims of the present disclosure.

Claims

1. A data processor, characterized by include: The instruction scheduler includes a first tensor access register, which is composed of physical circuitry and is used to store externally transmitted sub-tensor description information. The replication engine includes a first queue structure connected to the instruction scheduler, and a second tensor access register and an instruction decoder, both of which are physical circuits. The second tensor access register is used to store the sub-tensor description information received from the first queue structure, and the instruction decoder is used to parse the instructions received from the first queue structure and generate control signals to drive data transfer for the sub-tensor description information. The instruction scheduler is configured to, in response to receiving first sub-tensor description information transmitted externally, use the sub-tensor description information stored in the first tensor access register as a historical value, use the first sub-tensor description information as the current value of the sub-tensor description information, and overwrite the first sub-tensor description information into the first tensor access register; compare the current value of the sub-tensor description information with the historical value, determine the changed parameter items of the sub-tensor description information, and write the changed parameter items into the first queue structure, so that the replication engine incrementally updates the sub-tensor description information in the second tensor access register based on the changed parameter items.

2. The data processor of claim 1, wherein, The sub-tensor description information includes multiple component parameter items. The step of comparing the current value and historical values ​​of the sub-tensor description information to determine the changed parameter items of the sub-tensor description information includes: Each component parameter item of the subtensor description information is compared with its current value and historical value one by one; When the current value of the component parameter is not equal to the historical value, an incremental mask is added to the component parameter. The component parameter item carrying the incremental mask is determined as the change parameter item.

3. The data processor of claim 2, wherein, The step of writing the changed parameter item into the first queue structure includes: In response to receiving a target instruction transmitted from an external source, determine the position information of the changed parameter item within the sub-tensor description information; The changed parameter item, the corresponding location information, and the target instruction are written into the first queue structure.

4. The data processor of claim 1, wherein, The subtensor description information includes a parameter item group consisting of multiple component parameter items. The step of comparing the current value and historical values ​​of the subtensor description information to determine the changed parameter items of the subtensor description information includes: Compare the current value with the historical value for each component parameter item in the parameter item group; When the current value of any of the component parameter items is not equal to the historical value, an incremental mask is added to the parameter item group; All component parameter items in the parameter item group carrying the incremental mask are identified as change parameter items.

5. The data processor of claim 4, wherein, The step of writing the changed parameter item into the first queue structure includes: In response to receiving a target instruction transmitted from the outside, the parameter item group containing the changed parameter item is taken as a change group, and the position information of the change group in the sub-tensor description information is determined, wherein the total data length of the parameter item group is equal to the physical storage width of the first queue structure. Write all the component parameter items in the change group, corresponding position information, and the target instruction into the first queue structure.

6. A data processor according to any one of claims 3 or 5, characterized in that, The write position of the target instruction is at the tail of the write positions of both the change parameter item and the position information.

7. The data processor of claim 1, wherein, The copy engine is configured to: Obtain the change parameter item from the first queue structure and write the change parameter item into the second tensor access register to incrementally update the sub-tensor description information stored in the second tensor access register; In response to the target instruction received from the first queue structure, perform data transfer according to the currently stored sub-tensor description information in the second tensor access register.

8. The data processor of claim 7, wherein, The instruction decoder is configured to: In response to the target instruction received from the first queue structure, obtain the currently stored sub-tensor description information from the second tensor access register; Generate a transfer control signal based on the obtained sub-tensor description information to enable the copy engine to perform data transfer for the sub-tensor description information.

9. The data processor of claim 3, wherein, The copy engine is further configured to: Receive the change parameter item and the position information from the first queue structure; According to the position information, incrementally update the sub-tensor description information stored in the second tensor access register using the change parameter item.

10. A data processing method, characterized by, Comprise: Through the instruction scheduler, write externally transmitted sub-tensor description information into the first tensor access register, and in response to receiving externally transmitted first sub-tensor description information, store the sub-tensor description information in the first tensor access register as a historical value, store the first sub-tensor description information as a current value of the sub-tensor description information, and overwrite the first sub-tensor description information into the first tensor access register; compare the current value and the historical value of the sub-tensor description information to determine a change parameter item of the sub-tensor description information, and write the change parameter item into the first queue structure; Through the copy engine, receive the change parameter item from the first queue structure and incrementally update the sub-tensor description information in the second tensor access register based on the change parameter item.

11. An electronic device, comprising: The electronic device comprises a memory, a processor, a program stored on the memory and executable on the processor, and a data bus for realizing connection communication between the processor and the memory, and the program realizes the data processing method of claim 10 when executed by the processor.

12. A computer-readable storage medium, characterized in that, The computer readable storage medium stores one or more programs executable by one or more processors to implement the data processing method of claim 10.

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