Preparation method of P-type boron-doped N-type silicon substrate through low-temperature ion implantation process

Abstract

The invention discloses a method for preparing a P-type boron-doped N-type silicon substrate through a low-temperature ion implantation process, and the method comprises the steps: preparing a substrate which is an N-type silicon wafer substrate bare chip; boron ions with different energies are injected into the substrate through multiple low-temperature ion injection processes to form a boron injection layer; wherein the doping concentration of each depth position in the boron injection layer is the same; after the cleaning step, the boron injection layer is recrystallized by a thermal annealing process. The depth of the P-type doping layer can be accurately controlled, the concentration uniformity is good and can be accurately controlled, the concentration of the P-type doping layer does not have an excessive diffusion phenomenon, and the surface layer and the deep layer of the P-type doping layer do not have defects. Compared with a traditional TOPCon pure boron diffusion process technology, the method has the advantages that a high-quality, high-uniformity and low-defect P-type boron doping layer can be effectively generated in the N-type silicon wafer substrate, the required P-type boron doping depth can be accurately controlled, and meanwhile, the process complexity can be further reduced.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor design and manufacturing technology, and specifically relates to a method for preparing a P-type boron-doped N-type silicon substrate by a low-temperature ion implantation process. Background Technology

[0002] Current TOPCon (Tunnel Oxide Passivated Contact) solar cell technology requires stacking a P-type structure on an N-type silicon substrate, necessitating solutions to charge accumulation and recombination issues at the N / P interface. Specifically, the P-emitter requires precise boron doping control in the emitter region. In existing PECVD or LPCVD processes, the diffusion depth of boron atoms within the N-type silicon wafer is difficult to control precisely, easily leading to uneven doping or over-diffusion, thus affecting the solar cell's photoelectric conversion efficiency. Furthermore, high-temperature processing can easily cause interface oxidation or metal paste burn-through, further increasing process complexity.

[0003] P-type emitters require the formation of a high-quality boron-doped single-crystal silicon layer, which places extremely high demands on the crystal quality, uniformity, and interfacial bonding with the substrate material. Defects or inhomogeneous doping in the doped layer can lead to an increase in localized carrier recombination rates, affecting photoelectric conversion efficiency.

[0004] The main purpose of boron doping and diffusion processes is to prepare PN junctions. Current boron doping processes primarily use high-temperature diffusion furnaces. Because boron's solid solubility in silicon is lower than that of phosphorus, doping is more difficult, making boron diffusion more challenging than conventional phosphorus diffusion. Therefore, a high-temperature and long-duration diffusion process is required to ensure that boron atoms diffuse uniformly and effectively to the desired depth in the silicon wafer. The actual boron atom diffusion temperature needs to reach 900℃-1100℃, and the diffusion time can be as long as 150 minutes. Furthermore, selecting a suitable boron diffusion source is crucial, as different sources will have different impacts on the production process. For example, chlorides are highly corrosive, while bromides are highly viscous, making their cleaning processes relatively cumbersome and potentially increasing maintenance costs. Summary of the Invention

[0005] Based on the technical problems existing in the prior art, the present invention provides a method for preparing a P-type boron-doped N-type silicon substrate by a low-temperature ion implantation process, which solves the problems in the prior art such as the difficulty in accurately controlling the depth of the P-type doped layer in the N-type silicon substrate, the difficulty in adjusting the concentration of the P-type doped layer and its uneven distribution, the excessive diffusion of the concentration of the P-type doped layer, and the presence of many surface or deep defects.

[0006] According to the technical solution of the present invention, the present invention provides a method for preparing a P-type boron-doped N-type silicon substrate by a low-temperature ion implantation process, comprising the following steps:

[0007] Step S1: Prepare the substrate, which is an N-type silicon wafer substrate bare die;

[0008] Step S2: Boron ions of different energies are implanted into the substrate through a multi-stage low-temperature ion implantation process to form a boron implantation layer; wherein the doping concentration is the same at each depth position in the boron implantation layer.

[0009] Step S3: After the cleaning step, the boron-implanted layer is recrystallized by hot annealing.

[0010] In some implementations, the temperature of the cryogenic ion implantation process is <60°C.

[0011] In some implementations, the temperature of the cryogenic ion implantation process is <0°C.

[0012] In some implementations, the ion energy of the cryogenic ion implantation process is 0.1 keV to 1 MeV.

[0013] In some implementations, the implantation dose for each cryogenic ion implantation process is 10. 11 ~10 16 ions / cm 2 .

[0014] In some embodiments, the heat annealing process is a high-temperature heat annealing process, wherein the heat annealing temperature is ≥500°C.

[0015] Compared with the prior art, the beneficial technical effects of the present invention are as follows:

[0016] The present invention utilizes a low-temperature ion implantation process to prepare a P-type boron-doped N-type silicon substrate. This process allows for the adjustment of the P-type doping layer concentration and resistance, precise control of the doping depth, and good and accurately controlled concentration uniformity. Furthermore, there is no excessive diffusion of the P-type doping layer concentration, and the surface and deep layers of the P-type doped layer are free of defects. Compared to the traditional TOPCon simple boron diffusion process, the application of low-temperature boron ion implantation technology in this invention can effectively generate a high-quality, highly uniform, and low-defect P-type boron-doped layer within an N-type silicon wafer substrate, precisely controlling the required P-type boron doping depth while further reducing process complexity. Attached Figure Description

[0017] Figure 1 This is a flowchart of the preparation method provided by the present invention.

[0018] Figure 2This is a comparison chart of the effects of room temperature ion implantation and low temperature ion implantation in this invention. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0020] It should also be noted that, for ease of description, only the parts relevant to the inventive point are shown in the accompanying drawings. Unless otherwise specified, the embodiments and features described herein can be combined with each other.

[0021] It should be noted that the concepts of "first" and "second" mentioned in this invention are only used to distinguish different devices, modules or units, and are not used to limit the order of functions performed by these devices, modules or units or their interdependencies.

[0022] It should be noted that the terms "a" and "a plurality of" used in this invention are illustrative rather than restrictive. Those skilled in the art should understand that, unless otherwise expressly indicated in the context, they should be understood as "one or more".

[0023] This invention provides a method for preparing a P-type boron-doped N-type silicon substrate using a low-temperature ion implantation process. It improves the preparation method of P-type atom doping on an N-type silicon wafer substrate, and mainly aims to solve the problems in the prior art such as the difficulty in accurately controlling the depth of the P-type doped layer in the N-type silicon substrate, the difficulty in adjusting the concentration of the P-type doped layer and its uneven distribution, the excessive diffusion of the P-type doped layer concentration, and the presence of many surface or deep defects.

[0024] Please see Figure 1 The present invention discloses a method for preparing a P-type boron-doped N-type silicon substrate by a low-temperature ion implantation process, comprising the following steps.

[0025] Step S1: Prepare substrate 1, which is an N-type silicon wafer substrate bare die.

[0026] Step S2 involves implanting boron ions of different energies into the substrate 1 using a multi-stage low-temperature ion implantation process to form a boron implantation layer 2. Preferably, the temperature of the low-temperature ion implantation process is <60°C; more preferably, the temperature of the low-temperature ion implantation process is <0°C. The ion energy of the low-temperature ion implantation process is, for example, 0.1 keV to 1 MeV. The implantation dose is preferably a high dose, for example, an implantation dose of 10 keV for each stage of the low-temperature ion implantation process. 11 ~1016 ions / cm 2 .

[0027] Step S3: After the cleaning step, the boron implantation layer 2 is recrystallized and activated through thermal annealing. This results in the formation of a high-quality, highly uniform, and defect-free P-type boron-doped layer within the N-type silicon substrate, with precise control over the required P-type boron doping concentration and depth. The thermal annealing process is specifically a high-temperature process, with a temperature, for example, ≥500℃.

[0028] In step S2, the doping concentration is the same at all depths in the boron implantation layer 2. The final P-type doped layer has a certain thickness. In this step, multiple implantation layers with different energies are formed, each with a different implantation depth but the same doping concentration. The overall size span of the multiple implantation layers reaches the required thickness. For example, the implantation energy of the multi-stage low-temperature ion implantation process decreases sequentially. Thus, the first layer of boron ions is implanted into a certain depth in the substrate. Subsequent implanted boron ions are then uniformly and tightly arranged on the substrate surface, resulting in a double-layer structure with a single-crystal silicon layer on the bottom and a boron-doped layer on the top. Then, after recrystallization in step S3, a structure is obtained with a P-type boron-doped silicon layer on top and an N-type silicon substrate on the bottom.

[0029] More specifically, the use of low-temperature ion implantation can reduce lattice displacement during ion implantation, reduce crystal damage, reduce the thickness of the amorphous layer and residual defects after thermal annealing, and the thickness of the amorphous layer can be reduced by more than 20-30% (compared to room temperature implantation); and preferably, high doses of boron ions are implanted into the substrate 1 to obtain a low resistivity P-type doped layer; the purpose of setting different energies during implantation is to ensure that the entire P-type doped layer has the same doping concentration, the implantation depth is determined by the ion energy, and the implantation dose is adjusted by the beam current density and implantation time.

[0030] Please see Figure 2Part (a) shows a schematic diagram of the microstructure using a room-temperature ion implantation process, and part (b) shows a schematic diagram of the microstructure using a low-temperature ion implantation process. The structure shown on the far left is a silicon substrate, where the white dots represent silicon atoms. After ion implantation, the doped boron enters the originally regularly arranged silicon atoms (the smaller white dots in the figure represent boron atoms). Under the same ion implantation energy and dosage conditions, the amorphous layer depth D2 caused by low-temperature ion implantation is smaller than that caused by room-temperature ion implantation, which is due to the reduction of lattice displacement during ion implantation, reducing crystal damage, reducing the amorphous layer thickness and residual defects after thermal annealing. The amorphous layer thickness can be reduced by more than 20-30% (compared to room-temperature implantation), improving transistor performance (such as short-channel effect and drain barrier reduction). Furthermore, the thermal annealing time required for low-temperature ion implantation is shorter than that required for room-temperature ion implantation, and the amorphous layer after low-temperature ion implantation can generate a defect-free, high-quality recrystallized layer after high-temperature thermal annealing, while the same effect cannot be achieved with room-temperature ion implantation.

[0031] In summary, the P-type boron-doped N-type silicon substrate of this invention is prepared by a low-temperature ion implantation process to perform P-type boron doping on an N-type silicon substrate. The concentration and resistance of the P-type doped layer are adjustable, the depth is precisely controlled, the concentration uniformity is good and can be accurately controlled, and there is no excessive diffusion of the P-type doped layer concentration. The surface and deep layers of the P-type doped layer are free of defects. Compared with the traditional TOPCon simple boron diffusion process, the application of the low-temperature boron ion implantation process in this invention can effectively generate a high-quality, highly uniform, and low-defect P-type boron doped layer in an N-type silicon wafer substrate, and precisely control the required P-type boron doping depth. At the same time, it can further reduce the process complexity.

[0032] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for producing a P-type boron-doped N-type silicon substrate by a low-temperature ion implantation process, characterized by, The method comprises the following steps: S1, preparing a substrate (1), which is an N-type silicon wafer substrate die; S2, implanting boron ions with different energies into the substrate (1) through a multi-pass low-temperature ion implantation process to form a boron implantation layer (2); wherein the doping concentration of each depth position in the boron implantation layer (2) is the same; S3, after a cleaning step, performing recrystallization of the boron implantation layer (2) through a thermal annealing treatment.

2. The method of claim 1, wherein the P-type boron-doped N-type silicon substrate is prepared by a low-temperature ion implantation process. The temperature of the low-temperature ion implantation process is <60℃.

3. The method of claim 1, wherein the P-type boron-doped N-type silicon substrate is prepared by a low-temperature ion implantation process. The temperature of the low-temperature ion implantation process is <0℃.

4. The method of claim 1, wherein the P-type boron-doped N-type silicon substrate is prepared by a low-temperature ion implantation process. The ion energy of the low-temperature ion implantation process is 0.1keV-1MeV.

5. The method of claim 1, wherein the P-type boron-doped N-type silicon substrate is prepared by a low-temperature ion implantation process. The implant dose for each low temperature ion implantation process is 10 11 ~ 10 16 ions / cm 2 .

6. The method of claim 1, wherein the P-type boron-doped N-type silicon substrate is prepared by a low-temperature ion implantation process. The thermal annealing treatment is a high-temperature thermal annealing treatment, and the temperature of the thermal annealing treatment is ≥500℃.

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