Overcurrent protection controllable blocking circuit

Abstract

The application relates to an overcurrent protection controllable clamp circuit, which comprises a current sampling module, a current limiting threshold setting module, a controllable module, a PWM control module and a MOS drive module. The current sampling module samples the main circuit current through a Hall sensor, outputs a differential signal which is proportionally amplified by an operational amplifier, then is compared with positive and negative threshold values of the current limiting threshold setting module, and the controllable module outputs a controllable level to control one input of a logic AND gate in the PWM control module, so that the hardware control PWM result is achieved. Therefore, when overcurrent occurs, the reliability is increased through multi-layer logic control, and the controllable module is added in the controllable module, so that the application is flexible and controllable, the resistance and the threshold value can be selected according to needs, and the overcurrent protection PWM control of the battery side, the high-voltage side, the PV side and the inverter side of an off-grid inverter can be widely applied.

Description

Technical Field

[0001] This invention relates to the field of overcurrent protection circuit technology in new energy power equipment, and specifically to a controllable overcurrent protection circuit. Background Technology

[0002] Currently, various power equipment such as inverters, UPS, and communication power supplies are widely used in new energy systems. For example, off-grid inverters are core equipment in new energy systems and are highly susceptible to overcurrent threats during operation, such as sudden load increases, instantaneous start-up impacts, and short circuits at the power output terminals. These overcurrent conditions can cause a rapid rise in the temperature of the switching transistors in a very short time, and if they cannot be shut off in time, they will lead to damage to the switching transistors.

[0003] Therefore, controllable overcurrent protection PWM control is very important to provide the inverter with practicality and reliability at the application end. Summary of the Invention

[0004] In view of this, a safe and reliable overcurrent protection controllable blocking circuit is provided. It adopts an overcurrent protection controllable blocking strategy, which can select long lockout and short lockout modes according to the actual ambient temperature, giving the switching transistor sufficient cooling time and reducing the risk of damage to the switching transistor under multiple or continuous overcurrent conditions.

[0005] An overcurrent protection controllable blocking circuit includes a current sampling module, a current limiting threshold setting module, a controllable module, a PWM control module, and a MOS drive module;

[0006] The current sampling module includes a Hall sensor HCT1 and a first operational amplifier chip U1; the Hall sensor HCT1 is connected to the main power supply circuit to sample the main current; the reference pin vREF of the Hall sensor HCT1 is connected to the out-of-phase input terminal of the first operational amplifier chip U1, and the output pin vOUT of the Hall sensor HCT1 is connected to the non-in-phase input terminal of the first operational amplifier chip U1; the output terminal of the first operational amplifier chip U1 is divided into a first branch and a second branch.

[0007] The current limiting threshold setting module includes a first comparator chip U2 and a second comparator chip U3. The first branch is connected to the out-of-phase input terminal of the first comparator chip U2, and the second branch is connected to the non-in-phase input terminal of the second comparator chip U3. The non-in-phase input terminal of the first comparator chip U2 is connected to a second voltage input source to provide a positive threshold voltage, and the out-of-phase input terminal of the second comparator chip U3 is connected to a third voltage input source to provide a negative threshold voltage.

[0008] The controllable module includes a third comparator chip U4, a fourteenth resistor R14, a fifteenth resistor R15, a sixteenth resistor R16, a second diode D2, a third transistor D3, and a switch control unit. The output terminals of the first comparator chip U2 and the second comparator chip U3 are connected in parallel and then connected to the non-inverting input terminal of the third comparator chip U4 through the fourteenth resistor R14. One end of the fifteenth resistor R15 is connected to the connection point between the fourteenth resistor R14 and the non-inverting input terminal of the third comparator chip U4, and the other end is grounded. The switch control unit is connected between a fourth voltage input source and the anode of the second diode D2. The cathode of the second diode D2 is connected to the non-inverting input terminal of the third comparator chip U4, and the non-inverting input terminal of the third comparator chip U4 is connected to a fifth voltage input source to provide a stable reference voltage. The third transistor D3 and the sixteenth resistor R16 are connected in series and in parallel between the non-inverting input terminal and the output terminal of the third comparator chip U4.

[0009] The PWM control module includes a seventeenth resistor R17 and a logic AND gate chip U5; the output of the third comparator chip U4 is connected to the first input pin of the logic AND gate chip U5 through the seventeenth resistor R17. The first input pin of the logic AND gate chip U5 is also connected to a sixth voltage input source, and the second input pin of the logic AND gate chip U5 is connected to the PWM signal.

[0010] The MOS driving module includes an optocoupler isolation chip U6 and a MOS transistor Q1; the collector of the secondary side of the optocoupler isolation chip U6 is connected to an eighth voltage input source, the emitter of the secondary side of the optocoupler isolation chip U6 is connected to the gate of the MOS transistor Q1, and the output of the AND gate chip U5 is connected to the primary side of the optocoupler isolation chip U6; the MOS transistor Q1 and the Hall sensor HCT1 are connected in series in the main power supply circuit to control the on / off state of the main power supply circuit through the optocoupler isolation chip U6.

[0011] Furthermore, the reference pin vREF of the Hall sensor HCT1 is connected to the out-of-phase input terminal of the first operational amplifier chip U1 via a first input resistor R1, and the output pin vOUT of the Hall sensor HCT1 is connected to the non-in-phase input terminal of the first operational amplifier chip U1 via a third input resistor R3. A first voltage input source is also connected at the connection between the non-in-phase input terminal of the first operational amplifier chip U1 and the third input resistor R3. The first voltage input source is connected to the non-in-phase input terminal of the first operational amplifier chip U1 via a fourth resistor R4, and a second filter capacitor C2 is connected in parallel with the fourth resistor. A first filter capacitor C1 and a second resistor R2 are connected in parallel with the out-of-phase input terminal and the output terminal of the first operational amplifier chip U1. The voltage of the first voltage input source is equal to the voltage of the sixth voltage input.

[0012] Furthermore, by configuring the resistance ratio of the first input resistor R1 to the third input resistor R3 and the resistance ratio of the feedback resistor R2 to the fourth resistor R4, the first operational amplifier chip U1 outputs a predetermined output voltage to the first comparator U2 and the second comparator U3 as a reference voltage, and compares it with the positive and negative threshold voltages to control whether the output terminals of the first comparator U2 and the second comparator U3 are turned on, which is the signal GND.

[0013] Furthermore, the first operational amplifier chip U1 has a fifth resistor R5 on its main output path, and the second voltage input source is connected to the non-inverting input of the first comparator chip U2 through a seventh resistor R7; the second voltage input source is connected to the signal GND after passing through the seventh resistor R7, the sixth resistor R6 connected in parallel, and the third capacitor C3; the midpoint of the connection between the sixth resistor R6 and the seventh resistor R7 is connected to the non-inverting input of the first comparator chip U2 to provide a first predetermined voltage division as a positive threshold voltage.

[0014] Furthermore, the third voltage input source power supply is connected to signal GND after passing through the ninth resistor R9, the tenth resistor R10, and the eleventh resistor R11. The midpoint of the ninth resistor R9 and the tenth resistor R10 is connected to the out-of-phase input terminal of the second comparator chip U3 to provide a second predetermined voltage division as a negative threshold voltage. The output terminal of the second comparator chip U3 is connected to the base of the second transistor Q2 via the thirteenth resistor R13. The collector of the second transistor Q2 is connected to the midpoint of the tenth resistor R10 and the eleventh resistor R11, and the emitter of the second transistor Q2 is connected to signal GND. The positive hysteresis voltage of the first comparator chip U2 is obtained by dividing the second voltage input source (minus the voltage drop of the first diode D1) using the seventh resistor R7 and the eighth resistor R8. The negative hysteresis voltage of the second comparator chip U3 is obtained by dividing the third voltage input source (minus the voltage drop of the second transistor Q2) using the ninth resistor R9 and the tenth resistor R10. The voltage of the second voltage input source is equal to the voltage of the third voltage input source.

[0015] Furthermore, a seventh voltage input source is connected to the base of transistor Q2 after passing through twelfth resistor R12 and thirteenth resistor R13. The midpoint of twelfth resistor R12 and thirteenth resistor R13 is connected to the output terminal of first comparator chip U2, the output terminal of second comparator chip U3, and one end of fourteenth resistor R14. The other end of fourteenth resistor R14 is connected to the non-inverting input terminal of third comparator chip U4. The midpoint of the connection between sixth resistor R6 and seventh resistor R7 is also connected to the anode of first diode D1. The cathode of first diode D1 is connected to the output terminals of first comparator chip U2 and second comparator chip U3 after passing through eighth resistor R8. The voltages of the second voltage input source, the third voltage input source, the fourth voltage input source, the sixth voltage input source, and the seventh voltage input source are all equal.

[0016] Furthermore, a seventh voltage input source is connected in parallel to the output terminals of the first comparator chip U2 and the second comparator chip U3. The voltage obtained by dividing the seventh voltage input source by the resistance of the twelfth resistor R12, the resistance of the fourteenth resistor R14, and the resistance of the fifteenth resistor R15 is less than the voltage of the first voltage input source. The resistance of the sixteenth resistor R16 in the hysteresis section is less than the resistance of the fifteenth resistor R15, so that the circuit of the controllable module remains locked.

[0017] Specifically, the overcurrent protection controllable blocking circuit has a non-overcurrent mode and an overcurrent mode;

[0018] In the non-overcurrent mode, the output voltage of the first operational amplifier chip U1 is lower than the positive threshold of the current limiting threshold setting module and higher than the negative threshold of the current limiting threshold setting module. The comparator voltage obtained at the non-inverting input terminal of the third comparator chip U4 is the voltage division value of the seventh voltage input source by the twelfth resistor R12, the fourteenth resistor R14, and the fifteenth resistor R15, and is higher than the voltage value of the fifth voltage input source. The output terminal of the third comparator chip U4 is not connected to the signal GND. The first input pin of the logic AND gate chip U5 is not connected to the sixth voltage input source. At this time, the MOS transistor Q1 will work normally according to the PWM control.

[0019] In overcurrent mode, the positive and negative thresholds of the overcurrent mode trigger current limiting threshold setting module are determined by the current direction in DC power circuits, while there is no direction distinction in AC power circuits. The output voltage of the first operational amplifier chip U1 will be greater than one of the thresholds of the current limiting threshold setting module, causing the outputs of the two comparator chips U2 and U3 in the current limiting threshold setting module to conduct with the signal GND, thereby pulling down the voltage at the non-inverting input of the third comparator chip U4. This also causes the output of the third comparator chip U4 to conduct with the signal GND, pulling down the voltage at the first input pin of the AND gate chip U5, keeping the output of the AND gate chip U5 continuously low to achieve hardware blocking. At this time, the MOSFET Q1 will turn off due to blocking, and the current will decrease rapidly. The current limiting threshold setting module can reset the current limiting threshold based on the voltage output by the real-time current sampling through the hysteresis value. The current limiting threshold setting module functions as follows: after the current limiting threshold setting module is reset, the voltage at the non-inverting input terminal of the third comparator chip U4 is obtained by dividing the voltage of the fourth voltage input source (subtracting the voltage drop of the third diode D3) by the twelfth resistor R12, the fourteenth resistor R14, and the sixteenth resistor R16. By configuring the resistance value of the sixteenth resistor R16, the voltage at the voltage divider point or the input voltage at the non-inverting input terminal of the third comparator chip U4 is made less than the voltage of the first voltage input source. The controllable module controls the fourth voltage input source to be input to the non-inverting input terminal of the third comparator chip U4 through the control of the switch control unit, realizing the long-term lockout and recoverable control of the entire circuit.

[0020] Furthermore, the emitter of the secondary side of the optocoupler isolation chip U6 is connected to the gate of the MOS transistor Q1 through a nineteenth resistor R19, and a twentieth resistor R20 is connected in parallel between the gate and source of the MOS transistor Q1; the source of the MOS transistor Q1 is connected to the negative terminal or ground terminal of the main power supply circuit through a twenty-first resistor R21.

[0021] Furthermore, the fifteenth resistor R15 is connected in parallel with a fourth filter capacitor C4; the switch control device is a manual switch, an automatic control switch, or a microcontroller-controlled switch, and the MOSFET Q1 is an N-channel MOSFET; the voltages of the second voltage input source, the third voltage input source, the fourth voltage input source, the sixth voltage input source, and the seventh voltage input source are all +3.3V; the voltages of the first voltage input source and the sixth voltage input source are both +1.65V; and the voltage of the eighth voltage input source is +15V.

[0022] In the aforementioned controllable overcurrent protection circuit, the main circuit current is sampled by a Hall sensor, and the output differential signal is proportionally amplified by an operational amplifier. This signal is then compared with a configured threshold to control the level of one input to the AND gate, thereby achieving hardware-controlled PWM. Another advantage of this circuit is that its overcurrent protection logic undergoes multi-layered logic control, increasing reliability and incorporating a controllable module. This circuit can be applied to the protection of any power module in an off-grid inverter, requiring only the configuration of a Hall sensor and resistor values ​​that meet the actual range requirements. Furthermore, this circuit can be used for overcurrent protection PWM control on the battery side, high-voltage side, PV side, and inverter side of off-grid inverters, depending on the type of Hall sensor used, offering flexibility and broad application prospects. Attached Figure Description

[0023] Figure 1 This is a schematic diagram of the overcurrent protection controllable blocking circuit according to an embodiment of the present invention. Detailed Implementation

[0024] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0025] Please see Figure 1 This illustration shows a basic structure of an overcurrent protection controllable blocking circuit provided by an embodiment of the present invention, which includes a current sampling module, a current limiting threshold setting module, a controllable module, a PWM control module, and a MOS drive module.

[0026] The current sampling module includes a Hall sensor HCT1 and a first operational amplifier chip U1. The Hall sensor HCT1 is connected to the main power supply circuit to sample the main current. The reference pin vREF of the Hall sensor HCT1 is connected to the out-of-phase input terminal of the first operational amplifier chip U1, and the output pin vOUT of the Hall sensor HCT1 is connected to the non-in-phase input terminal of the first operational amplifier chip U1. The output terminal of the first operational amplifier chip U1 is divided into a first branch and a second branch.

[0027] The current limiting threshold setting module includes a first comparator chip U2 and a second comparator chip U3. The first branch is connected to the out-of-phase input terminal of the first comparator chip U2, and the second branch is connected to the non-in-phase input terminal of the second comparator chip U3. The non-in-phase input terminal of the first comparator chip U2 is connected to a second voltage input source to provide a positive threshold voltage, and the out-of-phase input terminal of the second comparator chip U3 is connected to a third voltage input source to provide a negative threshold voltage.

[0028] The controllable module includes a third comparator chip U4, a fourteenth resistor R14, a fifteenth resistor R15, a sixteenth resistor R16, a second diode D2, a third transistor D3, and a switch control unit. The output terminals of the first comparator chip U2 and the second comparator chip U3 are connected in parallel and then connected to the non-inverting input terminal of the third comparator chip U4 through the fourteenth resistor R14. One end of the fifteenth resistor R15 is connected to the connection between the fourteenth resistor R14 and the non-inverting input terminal of the third comparator chip U4, and the other end is grounded. The switch control unit is connected between a fourth voltage input source and the anode of the second diode D2. The cathode of the second diode D2 is connected to the non-inverting input terminal of the third comparator chip U4, and the non-inverting input terminal of the third comparator chip U4 is connected to a fifth voltage input source to provide a stable reference voltage. The third transistor D3 and the sixteenth resistor R16 are connected in series and in parallel between the non-inverting input terminal and the output terminal of the third comparator chip U4.

[0029] The PWM control module includes a seventeenth resistor R17 and an AND gate chip U5. The output of the third comparator chip U4 is connected to the first input pin of the AND gate chip U5 through the seventeenth resistor R17. The first input pin of the AND gate chip U5 is also connected to a sixth voltage input source, and the second input pin of the AND gate chip U5 is connected to the PWM signal. The PWM signal can be provided by various types of ICs; the IC used in this invention is the DSP280037.

[0030] The MOS driving module includes an optocoupler isolation chip U6 and a MOS transistor Q1; the collector of the secondary side of the optocoupler isolation chip U6 is connected to an eighth voltage input source, the emitter of the secondary side of the optocoupler isolation chip U6 is connected to the gate of the MOS transistor Q1, and the output of the AND gate chip U5 is connected to the primary side of the optocoupler isolation chip U6; the MOS transistor Q1 and the Hall sensor HCT1 are connected in series in the main power supply circuit to control the on / off state of the main power supply circuit through the optocoupler isolation chip U6.

[0031] Furthermore, the reference pin vREF of the Hall sensor HCT1 is connected to the out-of-phase input terminal of the first operational amplifier chip U1 via a first input resistor R1, and the output pin vOUT of the Hall sensor HCT1 is connected to the non-in-phase input terminal of the first operational amplifier chip U1 via a third input resistor R3. A first voltage input source is also connected at the connection between the non-in-phase input terminal of the first operational amplifier chip U1 and the third input resistor R3. The first voltage input source is connected to the non-in-phase input terminal of the first operational amplifier chip U1 via a fourth resistor R4, and a second filter capacitor C2 is connected in parallel with the fourth resistor. A first filter capacitor C1 and a second resistor R2 are connected in parallel with the out-of-phase input terminal and the output terminal of the first operational amplifier chip U1. The voltage of the first voltage input source is equal to the voltage of the sixth voltage input source. The Hall sensor HCT1 converts the current signal into a voltage signal, which is then connected to the first resistor R1 and the third resistor R3 before being input into the first operational amplifier chip U1. The resistance ratio of the first resistor R1 to the second resistor R2 must be the same as the resistance ratio of the third resistor R3 to the fourth resistor R4, so that the differential signal output by the Hall sensor HCT1 is scaled proportionally. The scaling formula is: scaling ratio = R3 / R1(R4 / R2); for example, 15K / 10K = 1.5, so the scaling ratio is 1.5. The first capacitor C1 and the second capacitor C2 play a filtering role in the current sampling module.

[0032] Therefore, by configuring the resistance ratio of the first input resistor R1 to the third input resistor R3 and the resistance ratio of the feedback resistor R2 to the fourth resistor R4, the first operational amplifier chip U1 outputs a predetermined output voltage to the first comparator U2 and the second comparator U3 as a reference voltage, and compares it with the positive and negative threshold voltages to control whether the output terminals of the first comparator U2 and the second comparator U3 are turned on, which is the signal GND.

[0033] Furthermore, a fifth resistor R5 is located on the main output path of the first operational amplifier chip U1, which serves as a current limiter. The second voltage input source is connected to the non-inverting input of the first comparator chip U2 via a seventh resistor R7; the second voltage input source passes through the seventh resistor R7, then through a parallel sixth resistor R6 and a third capacitor C3, before being connected to the signal GND; the midpoint of the connection between the sixth resistor R6 and the seventh resistor R7 is connected to the non-inverting input of the first comparator chip U2 to provide a first predetermined voltage division as a positive threshold voltage.

[0034] Furthermore, the third voltage input source power supply is connected to signal GND after passing through the ninth resistor R9, the tenth resistor R10, and the eleventh resistor R11. The midpoint of the ninth resistor R9 and the tenth resistor R10 is connected to the out-of-phase input terminal of the second comparator chip U3 to provide a second predetermined voltage division as a negative threshold voltage. The output terminal of the second comparator chip U3 is connected to the base of the second transistor Q2 via the thirteenth resistor R13. The collector of the second transistor Q2 is connected to the midpoint of the tenth resistor R10 and the eleventh resistor R11, and the emitter of the second transistor Q2 is connected to signal GND. The positive hysteresis voltage of the first comparator chip U2 is obtained by dividing the second voltage input source (minus the voltage drop of the first diode D1) using the seventh resistor R7 and the eighth resistor R8. The negative hysteresis voltage of the second comparator chip U3 is obtained by dividing the third voltage input source (minus the voltage drop of the second transistor Q2) using the ninth resistor R9 and the tenth resistor R10. The voltage of the second voltage input source is equal to the voltage of the third voltage input source.

[0035] Furthermore, a seventh voltage input source is connected to the base of transistor Q2 after passing through twelfth resistor R12 and thirteenth resistor R13. The midpoint of twelfth resistor R12 and thirteenth resistor R13 is connected to the output terminal of first comparator chip U2, the output terminal of second comparator chip U3, and one end of fourteenth resistor R14. The other end of fourteenth resistor R14 is connected to the non-inverting input terminal of third comparator chip U4. The midpoint of the connection between sixth resistor R6 and seventh resistor R7 is also connected to the anode of first diode D1. The cathode of first diode D1 is connected to the output terminals of first comparator chip U2 and second comparator chip U3 after passing through eighth resistor R8. The voltages of the second voltage input source, the third voltage input source, the fourth voltage input source, the sixth voltage input source, and the seventh voltage input source are all equal. Preferably, the voltages of the second voltage input source, the third voltage input source, the fourth voltage input source, the sixth voltage input source, and the seventh voltage input source are all +3.3V; the voltages of the first voltage input source and the sixth voltage input source are both +1.65V; and the voltage of the eighth voltage input source is +15V.

[0036] Furthermore, a seventh voltage input source is connected in parallel to the output terminals of the first comparator chip U2 and the second comparator chip U3. The voltage obtained by dividing the seventh voltage input source by the resistance of the twelfth resistor R12, the resistance of the fourteenth resistor R14, and the resistance of the fifteenth resistor R15 is less than the voltage of the first voltage input source. The resistance of the sixteenth resistor R16 in the hysteresis section is less than the resistance of the fifteenth resistor R15, so that the circuit of the controllable module remains locked.

[0037] Specifically, the voltage of the second voltage input source is +3.3V. The positive threshold voltage is obtained by dividing the voltage of the second voltage input source (i.e., +3.3V) by the sixth resistor, the seventh resistor R6, and R7. The positive hysteresis voltage is obtained by dividing the +3.3V (minus the voltage drop of the first diode D1) by the seventh resistor, the eighth resistor R7, and R8. The negative threshold voltage is obtained by dividing the voltage of the second voltage input source by the ninth resistor R9, the tenth resistor R10, and the eleventh resistor R11. For example, when dividing the +3.3V voltage, the negative hysteresis voltage is obtained by dividing the +3.3V (minus the voltage drop of the second transistor Q2) by the ninth and tenth resistors R9 and R10. Whether the outputs of the second comparator chip U2 and the third comparator chip U3 are connected to the signal GND will affect the voltage at the non-inverting input of the third comparator chip U4. It is important to note that the voltage obtained by dividing the voltage of the seventh voltage input source (e.g., +3.3V) by the twelfth resistor R12, the fourteenth resistor R14, and the fifteenth resistor R15 is less than the voltage of the first voltage input source (e.g., +1.65V). Furthermore, the resistance of the sixteenth resistor R16 in the hysteresis section must be less than the resistance of the fifteenth resistor R15 to ensure the circuit remains locked. The switch control unit here mainly simulates external control; depending on the requirements, the switch control unit can be set to manual or controlled by a microcontroller. The logic AND gate chip U5 controls the N-channel MOSFET Q1 based on the output state of the third comparator chip U4 and the PWM control. The calculation of the output voltage of the first operational amplifier chip U1 in the circuit is related to the ratio of the Hall sensor HCT1. The calculation method is: V1 (output voltage of the first operational amplifier chip U1) = 1.65 - (I (actual power current flowing through the Hall sensor) * ratio of Hall sensor HCT1 * R1 / R2).

[0038] Specifically, the overcurrent protection controllable blocking circuit has a non-overcurrent mode and an overcurrent mode;

[0039] In the non-overcurrent mode, the output voltage of the first operational amplifier chip U1 is lower than the positive threshold of the current limiting threshold setting module and higher than the negative threshold of the current limiting threshold setting module. The comparator voltage obtained at the non-inverting input terminal of the third comparator chip U4 is the voltage division value of the seventh voltage input source by the twelfth resistor R12, the fourteenth resistor R14, and the fifteenth resistor R15, and is higher than the voltage value of the fifth voltage input source. The output terminal of the third comparator chip U4 is not connected to the signal GND. The first input pin of the logic AND gate chip U5 is not connected to the sixth voltage input source. At this time, the MOS transistor Q1 will work normally according to the PWM control.

[0040] In overcurrent mode, the output voltage of the first operational amplifier chip U1 will exceed one of the thresholds of the current limiting threshold setting module. This causes the outputs of the two comparator chips U2 and U3 in the current limiting threshold setting module to conduct with the signal GND, pulling down the voltage at the non-inverting input of the third comparator chip U4. The output of the third comparator chip U4 is also connected to the signal GND, pulling down the voltage at the first input pin of the AND gate chip U5, keeping the output of the AND gate chip U5 continuously low to achieve hardware blocking. At this time, the MOSFET Q1 will turn off due to blocking, and the current will decrease rapidly. The current limiting threshold setting module can be reset based on the voltage output by the real-time current sampling using the hysteresis value. The current limiting threshold setting module functions as follows: After the current limiting threshold setting module is reset, the voltage at the non-inverting input terminal of the third comparator chip U4 is obtained by dividing the voltage of the fourth voltage input source (subtracting the voltage drop of the third diode D3) by the twelfth resistor R12, the fourteenth resistor R14, and the sixteenth resistor R16. By configuring the resistance value of the sixteenth resistor R16, the voltage at the voltage divider point or the input voltage at the non-inverting input terminal of the third comparator chip U4 is made less than the voltage of the first voltage input source. The controllable module controls the fourth voltage input source to be input to the non-inverting input terminal of the third comparator chip U4 through the control of the switch control unit, realizing the long-term lockout and recoverable control of the entire circuit.

[0041] Furthermore, the emitter of the secondary side of the optocoupler isolation chip U6 is connected to the gate of the MOSFET Q1 through a nineteenth resistor R19, and a twentieth resistor R20 is connected in parallel between the gate and source of the MOSFET Q1; the source of the MOSFET Q1 is connected to the negative terminal of the main power supply circuit or to ground through a twenty-first resistor R21. Even further, a fourth filter capacitor C4 is connected in parallel with the fifteenth resistor R15; the switching control device is a manual switch, an automatic control switch, or a microcontroller-controlled switching transistor, and the MOSFET Q1 is an N-channel MOSFET.

[0042] like Figure 1 As shown, in practical applications, taking an off-grid inverter as an example, the inverter typically has a power module, which mainly includes a power supply VDC1. The positive terminal of power supply VDC1 is connected to the drain of N-channel MOSFET Q1, and then flows out from the source of N-channel MOSFET Q1, through the 21st resistor R21, and back to the negative terminal of power supply VDC1. The 21st resistor R21 can be other load circuits. The entire circuit mainly involves two modes. The first mode is the normal state as described above, where overcurrent protection is not triggered. The second mode is the overcurrent mode, where either the positive or negative threshold is triggered, causing MOSFET Q1 to disconnect and protecting the main circuit.

[0043] It should be noted that the present invention is not limited to the above-described embodiments. Based on the inventive spirit of the present invention, those skilled in the art can make other changes, and these changes made in accordance with the inventive spirit of the present invention should be included within the scope of protection claimed by the present invention.

Claims

1. A controllable overcurrent protection blocking circuit, characterized in that, The circuit includes a current sampling module, a current limiting threshold setting module, a controllable module, a PWM control module, and a MOS drive module; The current sampling module includes a Hall sensor HCT1 and a first operational amplifier chip U1; the Hall sensor HCT1 is connected to the main power supply circuit to sample the main current; the reference pin vREF of the Hall sensor HCT1 is connected to the out-of-phase input terminal of the first operational amplifier chip U1, and the output pin vOUT of the Hall sensor HCT1 is connected to the non-in-phase input terminal of the first operational amplifier chip U1; the output terminal of the first operational amplifier chip U1 is divided into a first branch and a second branch. The current limiting threshold setting module includes a first comparator chip U2 and a second comparator chip U3. The first branch is connected to the out-of-phase input terminal of the first comparator chip U2, and the second branch is connected to the non-in-phase input terminal of the second comparator chip U3. The non-in-phase input terminal of the first comparator chip U2 is connected to a second voltage input source to provide a positive threshold voltage, and the out-of-phase input terminal of the second comparator chip U3 is connected to a third voltage input source to provide a negative threshold voltage. The controllable module includes a third comparator chip U4, a fourteenth resistor R14, a fifteenth resistor R15, a sixteenth resistor R16, a second diode D2, a third transistor D3, and a switch control unit. The output terminals of the first comparator chip U2 and the second comparator chip U3 are connected in parallel and then connected to the non-inverting input terminal of the third comparator chip U4 through the fourteenth resistor R14. One end of the fifteenth resistor R15 is connected to the connection point between the fourteenth resistor R14 and the non-inverting input terminal of the third comparator chip U4, and the other end is grounded. The switch control unit is connected between a fourth voltage input source and the anode of the second diode D2. The cathode of the second diode D2 is connected to the non-inverting input terminal of the third comparator chip U4, and the non-inverting input terminal of the third comparator chip U4 is connected to a fifth voltage input source to provide a stable reference voltage. The third transistor D3 and the sixteenth resistor R16 are connected in series and in parallel between the non-inverting input terminal and the output terminal of the third comparator chip U4. The PWM control module includes a seventeenth resistor R17 and a logic AND gate chip U5; the output of the third comparator chip U4 is connected to the first input pin of the logic AND gate chip U5 through the seventeenth resistor R17. The first input pin of the logic AND gate chip U5 is also connected to a sixth voltage input source, and the second input pin of the logic AND gate chip U5 is connected to the PWM signal. The MOS driving module includes an optocoupler isolation chip U6 and a MOS transistor Q1; the collector of the secondary side of the optocoupler isolation chip U6 is connected to an eighth voltage input source, the emitter of the secondary side of the optocoupler isolation chip U6 is connected to the gate of the MOS transistor Q1, and the output of the AND gate chip U5 is connected to the primary side of the optocoupler isolation chip U6; the MOS transistor Q1 and the Hall sensor HCT1 are connected in series in the main power supply circuit to control the on / off state of the main power supply circuit through the optocoupler isolation chip U6.

2. The overcurrent protection controllable blocking circuit as described in claim 1, characterized in that, The reference pin vREF of the Hall sensor HCT1 is connected to the out-of-phase input of the first operational amplifier chip U1 via a first input resistor R1. The output pin vOUT of the Hall sensor HCT1 is connected to the non-in-phase input of the first operational amplifier chip U1 via a third input resistor R3. A first voltage input source is also connected at the connection between the non-in-phase input of the first operational amplifier chip U1 and the third input resistor R3. The first voltage input source is connected to the non-in-phase input of the first operational amplifier chip U1 via a fourth resistor R4. A second filter capacitor C2 is connected in parallel with the fourth resistor. A first filter capacitor C1 and a second resistor R2 are connected in parallel to the out-of-phase input terminal and the output terminal of the first operational amplifier chip U1; the voltage of the first voltage input source is equal to the voltage of the sixth voltage input source.

3. The overcurrent protection controllable blocking circuit as described in claim 1, characterized in that, By configuring the resistance ratio of the first input resistor R1 to the third input resistor R3 and the resistance ratio of the feedback resistor R2 to the fourth resistor R4, the first operational amplifier chip U1 outputs a predetermined output voltage to the first comparator U2 and the second comparator U3 as a reference voltage, and compares it with the positive and negative threshold voltages to control whether the output terminals of the first comparator U2 and the second comparator U3 are turned on, which is the signal GND.

4. The overcurrent protection controllable blocking circuit as described in claim 2, characterized in that, The first operational amplifier chip U1 has a fifth resistor R5 on its main output path. The second voltage input source is connected to the non-inverting input of the first comparator chip U2 through a seventh resistor R7. The second voltage input source is connected to the signal GND after passing through the seventh resistor R7, the sixth resistor R6 connected in parallel, and the third capacitor C3. The midpoint of the connection between the sixth resistor R6 and the seventh resistor R7 is connected to the non-inverting input of the first comparator chip U2 to provide a first predetermined voltage division as a positive threshold voltage.

5. The overcurrent protection controllable blocking circuit as described in claim 1, characterized in that, The third voltage input source power supply is also connected to signal GND after passing through the ninth resistor R9, the tenth resistor R10, and the eleventh resistor R11. The midpoint of the ninth resistor R9 and the tenth resistor R10 is connected to the out-of-phase input terminal of the second comparator chip U3 to provide a second predetermined voltage division as a negative threshold voltage. The output terminal of the second comparator chip U3 is connected to the base of the second transistor Q2 through the thirteenth resistor R13. The collector of the second transistor Q2 is connected to the midpoint of the tenth resistor R10 and the eleventh resistor R11, and the emitter of the second transistor Q2 is connected to signal GND. The positive hysteresis voltage of the first comparator chip U2 is obtained by dividing the second voltage input source by the seventh resistor R7 and the eighth resistor R8, which is equal to the voltage drop of the first diode D1. The negative hysteresis voltage of the second comparator chip U3 is obtained by dividing the third voltage input source by the ninth resistor R9 and the tenth resistor R10, which is equal to the voltage drop of the second transistor Q2.

6. The overcurrent protection controllable blocking circuit as described in claim 4, characterized in that, A seventh voltage input source is connected to the base of transistor Q2 after passing through twelfth resistor R12 and thirteenth resistor R13. The midpoint of twelfth resistor R12 and thirteenth resistor R13 is connected to the output of first comparator chip U2, the output of second comparator chip U3, and one end of fourteenth resistor R14. The other end of fourteenth resistor R14 is connected to the non-inverting input of third comparator chip U4. The midpoint of the connection between sixth resistor R6 and seventh resistor R7 is also connected to the anode of first diode D1. The cathode of first diode D1 is connected to the output of first comparator chip U2 and the output of second comparator chip U3 after passing through eighth resistor R8. The voltages of the second voltage input source, the third voltage input source, the fourth voltage input source, the sixth voltage input source, and the seventh voltage input source are all equal.

7. The overcurrent protection controllable blocking circuit as described in claim 1, characterized in that, A seventh voltage input source is connected in parallel to the output of the first comparator chip U2 and the output of the second comparator chip U3. The seventh voltage input source is also connected to the non-inverting input of the third comparator chip U4 after passing through the twelfth resistor R12 and the fourteenth resistor R14. The twelfth resistor R12 plus the fourteenth resistor R14 and the fifteenth resistor R15 form a voltage divider point for the seventh voltage input source between the fourteenth resistor R14 and the fifteenth resistor R15. The voltage at the voltage divider point is less than the voltage of the first voltage input source. The resistance value of the sixteenth resistor R16 in the hysteresis part is less than the resistance value of the fifteenth resistor R15, so that the circuit of the controllable module remains locked.

8. The overcurrent protection controllable blocking circuit as described in claim 7, characterized in that, The overcurrent protection controllable blocking circuit has a non-overcurrent mode and an overcurrent mode; In the non-overcurrent mode, the output voltage of the first operational amplifier chip U1 is lower than the positive threshold of the current limiting threshold setting module and higher than the negative threshold of the current limiting threshold setting module. The comparator voltage obtained at the non-inverting input terminal of the third comparator chip U4 is the voltage division value of the seventh voltage input source by the twelfth resistor R12, the fourteenth resistor R14, and the fifteenth resistor R15, and is higher than the voltage value of the fifth voltage input source. The output terminal of the third comparator chip U4 is in a high impedance state. The sixth voltage input source is not divided. The first input pin of the logic AND gate chip U5 is continuously the voltage value of the sixth voltage input source. At this time, the MOS transistor Q1 will work normally according to the PWM control. In overcurrent mode, the output voltage of the first operational amplifier chip U1 will exceed one of the thresholds of the current limiting threshold setting module. This causes the outputs of the two comparator chips U2 and U3 in the current limiting threshold setting module to conduct with the signal GND, pulling down the voltage at the non-inverting input of the third comparator chip U4. The output of the third comparator chip U4 is also connected to the signal GND, pulling down the voltage at the first input pin of the AND gate chip U5, keeping the output of the AND gate chip U5 continuously low to achieve hardware blocking. At this time, the MOSFET Q1 will turn off due to blocking, and the current will decrease rapidly. The current limiting threshold setting module can be reset based on the voltage output by the real-time current sampling using the hysteresis value. The current limiting threshold setting module functions as follows: After the current limiting threshold setting module is reset, the voltage at the non-inverting input terminal of the third comparator chip U4 is obtained by dividing the voltage of the fourth voltage input source (subtracting the voltage drop of the third diode D3) by the twelfth resistor R12, the fourteenth resistor R14, and the sixteenth resistor R16. By configuring the resistance value of the sixteenth resistor R16, the voltage at the voltage divider point or the input voltage at the non-inverting input terminal of the third comparator chip U4 is made less than the voltage of the first voltage input source. The controllable module controls the fourth voltage input source to be input to the non-inverting input terminal of the third comparator chip U4 through the control of the switch control unit, realizing the long-term lockout and recoverable control of the entire circuit.

9. The overcurrent protection controllable blocking circuit as described in claim 1, characterized in that, The emitter of the secondary side of the optocoupler isolation chip U6 is connected to the gate of the MOS transistor Q1 through a nineteenth resistor R19, and a twentieth resistor R20 is connected between the gate and source of the MOS transistor Q1; the source of the MOS transistor Q1 is connected to the negative terminal or ground terminal of the main power supply circuit through a twenty-first resistor R21.

10. The overcurrent protection controllable blocking circuit as described in claim 6, characterized in that, The fifteenth resistor R15 is connected in parallel with a fourth filter capacitor C4; the switch control device is a manual switch, an automatic control switch, or a microcontroller-controlled switch transistor, and the MOSFET Q1 is an N-channel MOSFET; the voltages of the second voltage input source, the third voltage input source, the fourth voltage input source, the sixth voltage input source, and the seventh voltage input source are all +3.3V; the voltages of the first voltage input source and the sixth voltage input source are both +1.65V; and the voltage of the eighth voltage input source is +15V.

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